1 /* 2 * Copyright (c) 2008-2014 STMicroelectronics Limited 3 * 4 * Author: Angus Clark <Angus.Clark@st.com> 5 * Patrice Chotard <patrice.chotard@st.com> 6 * Lee Jones <lee.jones@linaro.org> 7 * 8 * SPI master mode controller driver, used in STMicroelectronics devices. 9 * 10 * May be copied or modified under the terms of the GNU General Public 11 * License Version 2.0 only. See linux/COPYING for more information. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/of.h> 22 #include <linux/of_gpio.h> 23 #include <linux/of_irq.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/spi/spi.h> 26 #include <linux/spi/spi_bitbang.h> 27 28 /* SSC registers */ 29 #define SSC_BRG 0x000 30 #define SSC_TBUF 0x004 31 #define SSC_RBUF 0x008 32 #define SSC_CTL 0x00C 33 #define SSC_IEN 0x010 34 #define SSC_I2C 0x018 35 36 /* SSC Control */ 37 #define SSC_CTL_DATA_WIDTH_9 0x8 38 #define SSC_CTL_DATA_WIDTH_MSK 0xf 39 #define SSC_CTL_BM 0xf 40 #define SSC_CTL_HB BIT(4) 41 #define SSC_CTL_PH BIT(5) 42 #define SSC_CTL_PO BIT(6) 43 #define SSC_CTL_SR BIT(7) 44 #define SSC_CTL_MS BIT(8) 45 #define SSC_CTL_EN BIT(9) 46 #define SSC_CTL_LPB BIT(10) 47 #define SSC_CTL_EN_TX_FIFO BIT(11) 48 #define SSC_CTL_EN_RX_FIFO BIT(12) 49 #define SSC_CTL_EN_CLST_RX BIT(13) 50 51 /* SSC Interrupt Enable */ 52 #define SSC_IEN_TEEN BIT(2) 53 54 #define FIFO_SIZE 8 55 56 struct spi_st { 57 /* SSC SPI Controller */ 58 void __iomem *base; 59 struct clk *clk; 60 struct device *dev; 61 62 /* SSC SPI current transaction */ 63 const u8 *tx_ptr; 64 u8 *rx_ptr; 65 u16 bytes_per_word; 66 unsigned int words_remaining; 67 unsigned int baud; 68 struct completion done; 69 }; 70 71 static int spi_st_clk_enable(struct spi_st *spi_st) 72 { 73 /* 74 * Current platforms use one of the core clocks for SPI and I2C. 75 * If we attempt to disable the clock, the system will hang. 76 * 77 * TODO: Remove this when platform supports power domains. 78 */ 79 return 0; 80 81 return clk_prepare_enable(spi_st->clk); 82 } 83 84 static void spi_st_clk_disable(struct spi_st *spi_st) 85 { 86 /* 87 * Current platforms use one of the core clocks for SPI and I2C. 88 * If we attempt to disable the clock, the system will hang. 89 * 90 * TODO: Remove this when platform supports power domains. 91 */ 92 return; 93 94 clk_disable_unprepare(spi_st->clk); 95 } 96 97 /* Load the TX FIFO */ 98 static void ssc_write_tx_fifo(struct spi_st *spi_st) 99 { 100 unsigned int count, i; 101 uint32_t word = 0; 102 103 if (spi_st->words_remaining > FIFO_SIZE) 104 count = FIFO_SIZE; 105 else 106 count = spi_st->words_remaining; 107 108 for (i = 0; i < count; i++) { 109 if (spi_st->tx_ptr) { 110 if (spi_st->bytes_per_word == 1) { 111 word = *spi_st->tx_ptr++; 112 } else { 113 word = *spi_st->tx_ptr++; 114 word = *spi_st->tx_ptr++ | (word << 8); 115 } 116 } 117 writel_relaxed(word, spi_st->base + SSC_TBUF); 118 } 119 } 120 121 /* Read the RX FIFO */ 122 static void ssc_read_rx_fifo(struct spi_st *spi_st) 123 { 124 unsigned int count, i; 125 uint32_t word = 0; 126 127 if (spi_st->words_remaining > FIFO_SIZE) 128 count = FIFO_SIZE; 129 else 130 count = spi_st->words_remaining; 131 132 for (i = 0; i < count; i++) { 133 word = readl_relaxed(spi_st->base + SSC_RBUF); 134 135 if (spi_st->rx_ptr) { 136 if (spi_st->bytes_per_word == 1) { 137 *spi_st->rx_ptr++ = (uint8_t)word; 138 } else { 139 *spi_st->rx_ptr++ = (word >> 8); 140 *spi_st->rx_ptr++ = word & 0xff; 141 } 142 } 143 } 144 spi_st->words_remaining -= count; 145 } 146 147 static int spi_st_transfer_one(struct spi_master *master, 148 struct spi_device *spi, struct spi_transfer *t) 149 { 150 struct spi_st *spi_st = spi_master_get_devdata(master); 151 uint32_t ctl = 0; 152 153 /* Setup transfer */ 154 spi_st->tx_ptr = t->tx_buf; 155 spi_st->rx_ptr = t->rx_buf; 156 157 if (spi->bits_per_word > 8) { 158 /* 159 * Anything greater than 8 bits-per-word requires 2 160 * bytes-per-word in the RX/TX buffers 161 */ 162 spi_st->bytes_per_word = 2; 163 spi_st->words_remaining = t->len / 2; 164 165 } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) { 166 /* 167 * If transfer is even-length, and 8 bits-per-word, then 168 * implement as half-length 16 bits-per-word transfer 169 */ 170 spi_st->bytes_per_word = 2; 171 spi_st->words_remaining = t->len / 2; 172 173 /* Set SSC_CTL to 16 bits-per-word */ 174 ctl = readl_relaxed(spi_st->base + SSC_CTL); 175 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL); 176 177 readl_relaxed(spi_st->base + SSC_RBUF); 178 179 } else { 180 spi_st->bytes_per_word = 1; 181 spi_st->words_remaining = t->len; 182 } 183 184 reinit_completion(&spi_st->done); 185 186 /* Start transfer by writing to the TX FIFO */ 187 ssc_write_tx_fifo(spi_st); 188 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN); 189 190 /* Wait for transfer to complete */ 191 wait_for_completion(&spi_st->done); 192 193 /* Restore SSC_CTL if necessary */ 194 if (ctl) 195 writel_relaxed(ctl, spi_st->base + SSC_CTL); 196 197 spi_finalize_current_transfer(spi->master); 198 199 return t->len; 200 } 201 202 static void spi_st_cleanup(struct spi_device *spi) 203 { 204 int cs = spi->cs_gpio; 205 206 if (gpio_is_valid(cs)) 207 devm_gpio_free(&spi->dev, cs); 208 } 209 210 /* the spi->mode bits understood by this driver: */ 211 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH) 212 static int spi_st_setup(struct spi_device *spi) 213 { 214 struct spi_st *spi_st = spi_master_get_devdata(spi->master); 215 u32 spi_st_clk, sscbrg, var; 216 u32 hz = spi->max_speed_hz; 217 int cs = spi->cs_gpio; 218 int ret; 219 220 if (!hz) { 221 dev_err(&spi->dev, "max_speed_hz unspecified\n"); 222 return -EINVAL; 223 } 224 225 if (!gpio_is_valid(cs)) { 226 dev_err(&spi->dev, "%d is not a valid gpio\n", cs); 227 return -EINVAL; 228 } 229 230 if (devm_gpio_request(&spi->dev, cs, dev_name(&spi->dev))) { 231 dev_err(&spi->dev, "could not request gpio:%d\n", cs); 232 return -EINVAL; 233 } 234 235 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH); 236 if (ret) 237 return ret; 238 239 spi_st_clk = clk_get_rate(spi_st->clk); 240 241 /* Set SSC_BRF */ 242 sscbrg = spi_st_clk / (2 * hz); 243 if (sscbrg < 0x07 || sscbrg > BIT(16)) { 244 dev_err(&spi->dev, 245 "baudrate %d outside valid range %d\n", sscbrg, hz); 246 return -EINVAL; 247 } 248 249 spi_st->baud = spi_st_clk / (2 * sscbrg); 250 if (sscbrg == BIT(16)) /* 16-bit counter wraps */ 251 sscbrg = 0x0; 252 253 writel_relaxed(sscbrg, spi_st->base + SSC_BRG); 254 255 dev_dbg(&spi->dev, 256 "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n", 257 hz, spi_st->baud, sscbrg); 258 259 /* Set SSC_CTL and enable SSC */ 260 var = readl_relaxed(spi_st->base + SSC_CTL); 261 var |= SSC_CTL_MS; 262 263 if (spi->mode & SPI_CPOL) 264 var |= SSC_CTL_PO; 265 else 266 var &= ~SSC_CTL_PO; 267 268 if (spi->mode & SPI_CPHA) 269 var |= SSC_CTL_PH; 270 else 271 var &= ~SSC_CTL_PH; 272 273 if ((spi->mode & SPI_LSB_FIRST) == 0) 274 var |= SSC_CTL_HB; 275 else 276 var &= ~SSC_CTL_HB; 277 278 if (spi->mode & SPI_LOOP) 279 var |= SSC_CTL_LPB; 280 else 281 var &= ~SSC_CTL_LPB; 282 283 var &= ~SSC_CTL_DATA_WIDTH_MSK; 284 var |= (spi->bits_per_word - 1); 285 286 var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO; 287 var |= SSC_CTL_EN; 288 289 writel_relaxed(var, spi_st->base + SSC_CTL); 290 291 /* Clear the status register */ 292 readl_relaxed(spi_st->base + SSC_RBUF); 293 294 return 0; 295 } 296 297 /* Interrupt fired when TX shift register becomes empty */ 298 static irqreturn_t spi_st_irq(int irq, void *dev_id) 299 { 300 struct spi_st *spi_st = (struct spi_st *)dev_id; 301 302 /* Read RX FIFO */ 303 ssc_read_rx_fifo(spi_st); 304 305 /* Fill TX FIFO */ 306 if (spi_st->words_remaining) { 307 ssc_write_tx_fifo(spi_st); 308 } else { 309 /* TX/RX complete */ 310 writel_relaxed(0x0, spi_st->base + SSC_IEN); 311 /* 312 * read SSC_IEN to ensure that this bit is set 313 * before re-enabling interrupt 314 */ 315 readl(spi_st->base + SSC_IEN); 316 complete(&spi_st->done); 317 } 318 319 return IRQ_HANDLED; 320 } 321 322 static int spi_st_probe(struct platform_device *pdev) 323 { 324 struct device_node *np = pdev->dev.of_node; 325 struct spi_master *master; 326 struct resource *res; 327 struct spi_st *spi_st; 328 int irq, ret = 0; 329 u32 var; 330 331 master = spi_alloc_master(&pdev->dev, sizeof(*spi_st)); 332 if (!master) 333 return -ENOMEM; 334 335 master->dev.of_node = np; 336 master->mode_bits = MODEBITS; 337 master->setup = spi_st_setup; 338 master->cleanup = spi_st_cleanup; 339 master->transfer_one = spi_st_transfer_one; 340 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 341 master->auto_runtime_pm = true; 342 master->bus_num = pdev->id; 343 spi_st = spi_master_get_devdata(master); 344 345 spi_st->clk = devm_clk_get(&pdev->dev, "ssc"); 346 if (IS_ERR(spi_st->clk)) { 347 dev_err(&pdev->dev, "Unable to request clock\n"); 348 ret = PTR_ERR(spi_st->clk); 349 goto put_master; 350 } 351 352 ret = spi_st_clk_enable(spi_st); 353 if (ret) 354 goto put_master; 355 356 init_completion(&spi_st->done); 357 358 /* Get resources */ 359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 360 spi_st->base = devm_ioremap_resource(&pdev->dev, res); 361 if (IS_ERR(spi_st->base)) { 362 ret = PTR_ERR(spi_st->base); 363 goto clk_disable; 364 } 365 366 /* Disable I2C and Reset SSC */ 367 writel_relaxed(0x0, spi_st->base + SSC_I2C); 368 var = readw_relaxed(spi_st->base + SSC_CTL); 369 var |= SSC_CTL_SR; 370 writel_relaxed(var, spi_st->base + SSC_CTL); 371 372 udelay(1); 373 var = readl_relaxed(spi_st->base + SSC_CTL); 374 var &= ~SSC_CTL_SR; 375 writel_relaxed(var, spi_st->base + SSC_CTL); 376 377 /* Set SSC into slave mode before reconfiguring PIO pins */ 378 var = readl_relaxed(spi_st->base + SSC_CTL); 379 var &= ~SSC_CTL_MS; 380 writel_relaxed(var, spi_st->base + SSC_CTL); 381 382 irq = irq_of_parse_and_map(np, 0); 383 if (!irq) { 384 dev_err(&pdev->dev, "IRQ missing or invalid\n"); 385 ret = -EINVAL; 386 goto clk_disable; 387 } 388 389 ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0, 390 pdev->name, spi_st); 391 if (ret) { 392 dev_err(&pdev->dev, "Failed to request irq %d\n", irq); 393 goto clk_disable; 394 } 395 396 /* by default the device is on */ 397 pm_runtime_set_active(&pdev->dev); 398 pm_runtime_enable(&pdev->dev); 399 400 platform_set_drvdata(pdev, master); 401 402 ret = devm_spi_register_master(&pdev->dev, master); 403 if (ret) { 404 dev_err(&pdev->dev, "Failed to register master\n"); 405 goto clk_disable; 406 } 407 408 return 0; 409 410 clk_disable: 411 spi_st_clk_disable(spi_st); 412 put_master: 413 spi_master_put(master); 414 return ret; 415 } 416 417 static int spi_st_remove(struct platform_device *pdev) 418 { 419 struct spi_master *master = platform_get_drvdata(pdev); 420 struct spi_st *spi_st = spi_master_get_devdata(master); 421 422 spi_st_clk_disable(spi_st); 423 424 pinctrl_pm_select_sleep_state(&pdev->dev); 425 426 return 0; 427 } 428 429 #ifdef CONFIG_PM 430 static int spi_st_runtime_suspend(struct device *dev) 431 { 432 struct spi_master *master = dev_get_drvdata(dev); 433 struct spi_st *spi_st = spi_master_get_devdata(master); 434 435 writel_relaxed(0, spi_st->base + SSC_IEN); 436 pinctrl_pm_select_sleep_state(dev); 437 438 spi_st_clk_disable(spi_st); 439 440 return 0; 441 } 442 443 static int spi_st_runtime_resume(struct device *dev) 444 { 445 struct spi_master *master = dev_get_drvdata(dev); 446 struct spi_st *spi_st = spi_master_get_devdata(master); 447 int ret; 448 449 ret = spi_st_clk_enable(spi_st); 450 pinctrl_pm_select_default_state(dev); 451 452 return ret; 453 } 454 #endif 455 456 #ifdef CONFIG_PM_SLEEP 457 static int spi_st_suspend(struct device *dev) 458 { 459 struct spi_master *master = dev_get_drvdata(dev); 460 int ret; 461 462 ret = spi_master_suspend(master); 463 if (ret) 464 return ret; 465 466 return pm_runtime_force_suspend(dev); 467 } 468 469 static int spi_st_resume(struct device *dev) 470 { 471 struct spi_master *master = dev_get_drvdata(dev); 472 int ret; 473 474 ret = spi_master_resume(master); 475 if (ret) 476 return ret; 477 478 return pm_runtime_force_resume(dev); 479 } 480 #endif 481 482 static const struct dev_pm_ops spi_st_pm = { 483 SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume) 484 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL) 485 }; 486 487 static const struct of_device_id stm_spi_match[] = { 488 { .compatible = "st,comms-ssc4-spi", }, 489 {}, 490 }; 491 MODULE_DEVICE_TABLE(of, stm_spi_match); 492 493 static struct platform_driver spi_st_driver = { 494 .driver = { 495 .name = "spi-st", 496 .pm = &spi_st_pm, 497 .of_match_table = of_match_ptr(stm_spi_match), 498 }, 499 .probe = spi_st_probe, 500 .remove = spi_st_remove, 501 }; 502 module_platform_driver(spi_st_driver); 503 504 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); 505 MODULE_DESCRIPTION("STM SSC SPI driver"); 506 MODULE_LICENSE("GPL v2"); 507