1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2008-2014 STMicroelectronics Limited 4 * 5 * Author: Angus Clark <Angus.Clark@st.com> 6 * Patrice Chotard <patrice.chotard@st.com> 7 * Lee Jones <lee.jones@linaro.org> 8 * 9 * SPI master mode controller driver, used in STMicroelectronics devices. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/of.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_irq.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/spi/spi.h> 24 #include <linux/spi/spi_bitbang.h> 25 26 /* SSC registers */ 27 #define SSC_BRG 0x000 28 #define SSC_TBUF 0x004 29 #define SSC_RBUF 0x008 30 #define SSC_CTL 0x00C 31 #define SSC_IEN 0x010 32 #define SSC_I2C 0x018 33 34 /* SSC Control */ 35 #define SSC_CTL_DATA_WIDTH_9 0x8 36 #define SSC_CTL_DATA_WIDTH_MSK 0xf 37 #define SSC_CTL_BM 0xf 38 #define SSC_CTL_HB BIT(4) 39 #define SSC_CTL_PH BIT(5) 40 #define SSC_CTL_PO BIT(6) 41 #define SSC_CTL_SR BIT(7) 42 #define SSC_CTL_MS BIT(8) 43 #define SSC_CTL_EN BIT(9) 44 #define SSC_CTL_LPB BIT(10) 45 #define SSC_CTL_EN_TX_FIFO BIT(11) 46 #define SSC_CTL_EN_RX_FIFO BIT(12) 47 #define SSC_CTL_EN_CLST_RX BIT(13) 48 49 /* SSC Interrupt Enable */ 50 #define SSC_IEN_TEEN BIT(2) 51 52 #define FIFO_SIZE 8 53 54 struct spi_st { 55 /* SSC SPI Controller */ 56 void __iomem *base; 57 struct clk *clk; 58 struct device *dev; 59 60 /* SSC SPI current transaction */ 61 const u8 *tx_ptr; 62 u8 *rx_ptr; 63 u16 bytes_per_word; 64 unsigned int words_remaining; 65 unsigned int baud; 66 struct completion done; 67 }; 68 69 /* Load the TX FIFO */ 70 static void ssc_write_tx_fifo(struct spi_st *spi_st) 71 { 72 unsigned int count, i; 73 uint32_t word = 0; 74 75 if (spi_st->words_remaining > FIFO_SIZE) 76 count = FIFO_SIZE; 77 else 78 count = spi_st->words_remaining; 79 80 for (i = 0; i < count; i++) { 81 if (spi_st->tx_ptr) { 82 if (spi_st->bytes_per_word == 1) { 83 word = *spi_st->tx_ptr++; 84 } else { 85 word = *spi_st->tx_ptr++; 86 word = *spi_st->tx_ptr++ | (word << 8); 87 } 88 } 89 writel_relaxed(word, spi_st->base + SSC_TBUF); 90 } 91 } 92 93 /* Read the RX FIFO */ 94 static void ssc_read_rx_fifo(struct spi_st *spi_st) 95 { 96 unsigned int count, i; 97 uint32_t word = 0; 98 99 if (spi_st->words_remaining > FIFO_SIZE) 100 count = FIFO_SIZE; 101 else 102 count = spi_st->words_remaining; 103 104 for (i = 0; i < count; i++) { 105 word = readl_relaxed(spi_st->base + SSC_RBUF); 106 107 if (spi_st->rx_ptr) { 108 if (spi_st->bytes_per_word == 1) { 109 *spi_st->rx_ptr++ = (uint8_t)word; 110 } else { 111 *spi_st->rx_ptr++ = (word >> 8); 112 *spi_st->rx_ptr++ = word & 0xff; 113 } 114 } 115 } 116 spi_st->words_remaining -= count; 117 } 118 119 static int spi_st_transfer_one(struct spi_master *master, 120 struct spi_device *spi, struct spi_transfer *t) 121 { 122 struct spi_st *spi_st = spi_master_get_devdata(master); 123 uint32_t ctl = 0; 124 125 /* Setup transfer */ 126 spi_st->tx_ptr = t->tx_buf; 127 spi_st->rx_ptr = t->rx_buf; 128 129 if (spi->bits_per_word > 8) { 130 /* 131 * Anything greater than 8 bits-per-word requires 2 132 * bytes-per-word in the RX/TX buffers 133 */ 134 spi_st->bytes_per_word = 2; 135 spi_st->words_remaining = t->len / 2; 136 137 } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) { 138 /* 139 * If transfer is even-length, and 8 bits-per-word, then 140 * implement as half-length 16 bits-per-word transfer 141 */ 142 spi_st->bytes_per_word = 2; 143 spi_st->words_remaining = t->len / 2; 144 145 /* Set SSC_CTL to 16 bits-per-word */ 146 ctl = readl_relaxed(spi_st->base + SSC_CTL); 147 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL); 148 149 readl_relaxed(spi_st->base + SSC_RBUF); 150 151 } else { 152 spi_st->bytes_per_word = 1; 153 spi_st->words_remaining = t->len; 154 } 155 156 reinit_completion(&spi_st->done); 157 158 /* Start transfer by writing to the TX FIFO */ 159 ssc_write_tx_fifo(spi_st); 160 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN); 161 162 /* Wait for transfer to complete */ 163 wait_for_completion(&spi_st->done); 164 165 /* Restore SSC_CTL if necessary */ 166 if (ctl) 167 writel_relaxed(ctl, spi_st->base + SSC_CTL); 168 169 spi_finalize_current_transfer(spi->master); 170 171 return t->len; 172 } 173 174 static void spi_st_cleanup(struct spi_device *spi) 175 { 176 gpio_free(spi->cs_gpio); 177 } 178 179 /* the spi->mode bits understood by this driver: */ 180 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH) 181 static int spi_st_setup(struct spi_device *spi) 182 { 183 struct spi_st *spi_st = spi_master_get_devdata(spi->master); 184 u32 spi_st_clk, sscbrg, var; 185 u32 hz = spi->max_speed_hz; 186 int cs = spi->cs_gpio; 187 int ret; 188 189 if (!hz) { 190 dev_err(&spi->dev, "max_speed_hz unspecified\n"); 191 return -EINVAL; 192 } 193 194 if (!gpio_is_valid(cs)) { 195 dev_err(&spi->dev, "%d is not a valid gpio\n", cs); 196 return -EINVAL; 197 } 198 199 ret = gpio_request(cs, dev_name(&spi->dev)); 200 if (ret) { 201 dev_err(&spi->dev, "could not request gpio:%d\n", cs); 202 return ret; 203 } 204 205 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH); 206 if (ret) 207 goto out_free_gpio; 208 209 spi_st_clk = clk_get_rate(spi_st->clk); 210 211 /* Set SSC_BRF */ 212 sscbrg = spi_st_clk / (2 * hz); 213 if (sscbrg < 0x07 || sscbrg > BIT(16)) { 214 dev_err(&spi->dev, 215 "baudrate %d outside valid range %d\n", sscbrg, hz); 216 ret = -EINVAL; 217 goto out_free_gpio; 218 } 219 220 spi_st->baud = spi_st_clk / (2 * sscbrg); 221 if (sscbrg == BIT(16)) /* 16-bit counter wraps */ 222 sscbrg = 0x0; 223 224 writel_relaxed(sscbrg, spi_st->base + SSC_BRG); 225 226 dev_dbg(&spi->dev, 227 "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n", 228 hz, spi_st->baud, sscbrg); 229 230 /* Set SSC_CTL and enable SSC */ 231 var = readl_relaxed(spi_st->base + SSC_CTL); 232 var |= SSC_CTL_MS; 233 234 if (spi->mode & SPI_CPOL) 235 var |= SSC_CTL_PO; 236 else 237 var &= ~SSC_CTL_PO; 238 239 if (spi->mode & SPI_CPHA) 240 var |= SSC_CTL_PH; 241 else 242 var &= ~SSC_CTL_PH; 243 244 if ((spi->mode & SPI_LSB_FIRST) == 0) 245 var |= SSC_CTL_HB; 246 else 247 var &= ~SSC_CTL_HB; 248 249 if (spi->mode & SPI_LOOP) 250 var |= SSC_CTL_LPB; 251 else 252 var &= ~SSC_CTL_LPB; 253 254 var &= ~SSC_CTL_DATA_WIDTH_MSK; 255 var |= (spi->bits_per_word - 1); 256 257 var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO; 258 var |= SSC_CTL_EN; 259 260 writel_relaxed(var, spi_st->base + SSC_CTL); 261 262 /* Clear the status register */ 263 readl_relaxed(spi_st->base + SSC_RBUF); 264 265 return 0; 266 267 out_free_gpio: 268 gpio_free(cs); 269 return ret; 270 } 271 272 /* Interrupt fired when TX shift register becomes empty */ 273 static irqreturn_t spi_st_irq(int irq, void *dev_id) 274 { 275 struct spi_st *spi_st = (struct spi_st *)dev_id; 276 277 /* Read RX FIFO */ 278 ssc_read_rx_fifo(spi_st); 279 280 /* Fill TX FIFO */ 281 if (spi_st->words_remaining) { 282 ssc_write_tx_fifo(spi_st); 283 } else { 284 /* TX/RX complete */ 285 writel_relaxed(0x0, spi_st->base + SSC_IEN); 286 /* 287 * read SSC_IEN to ensure that this bit is set 288 * before re-enabling interrupt 289 */ 290 readl(spi_st->base + SSC_IEN); 291 complete(&spi_st->done); 292 } 293 294 return IRQ_HANDLED; 295 } 296 297 static int spi_st_probe(struct platform_device *pdev) 298 { 299 struct device_node *np = pdev->dev.of_node; 300 struct spi_master *master; 301 struct spi_st *spi_st; 302 int irq, ret = 0; 303 u32 var; 304 305 master = spi_alloc_master(&pdev->dev, sizeof(*spi_st)); 306 if (!master) 307 return -ENOMEM; 308 309 master->dev.of_node = np; 310 master->mode_bits = MODEBITS; 311 master->setup = spi_st_setup; 312 master->cleanup = spi_st_cleanup; 313 master->transfer_one = spi_st_transfer_one; 314 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 315 master->auto_runtime_pm = true; 316 master->bus_num = pdev->id; 317 spi_st = spi_master_get_devdata(master); 318 319 spi_st->clk = devm_clk_get(&pdev->dev, "ssc"); 320 if (IS_ERR(spi_st->clk)) { 321 dev_err(&pdev->dev, "Unable to request clock\n"); 322 ret = PTR_ERR(spi_st->clk); 323 goto put_master; 324 } 325 326 ret = clk_prepare_enable(spi_st->clk); 327 if (ret) 328 goto put_master; 329 330 init_completion(&spi_st->done); 331 332 /* Get resources */ 333 spi_st->base = devm_platform_ioremap_resource(pdev, 0); 334 if (IS_ERR(spi_st->base)) { 335 ret = PTR_ERR(spi_st->base); 336 goto clk_disable; 337 } 338 339 /* Disable I2C and Reset SSC */ 340 writel_relaxed(0x0, spi_st->base + SSC_I2C); 341 var = readw_relaxed(spi_st->base + SSC_CTL); 342 var |= SSC_CTL_SR; 343 writel_relaxed(var, spi_st->base + SSC_CTL); 344 345 udelay(1); 346 var = readl_relaxed(spi_st->base + SSC_CTL); 347 var &= ~SSC_CTL_SR; 348 writel_relaxed(var, spi_st->base + SSC_CTL); 349 350 /* Set SSC into slave mode before reconfiguring PIO pins */ 351 var = readl_relaxed(spi_st->base + SSC_CTL); 352 var &= ~SSC_CTL_MS; 353 writel_relaxed(var, spi_st->base + SSC_CTL); 354 355 irq = irq_of_parse_and_map(np, 0); 356 if (!irq) { 357 dev_err(&pdev->dev, "IRQ missing or invalid\n"); 358 ret = -EINVAL; 359 goto clk_disable; 360 } 361 362 ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0, 363 pdev->name, spi_st); 364 if (ret) { 365 dev_err(&pdev->dev, "Failed to request irq %d\n", irq); 366 goto clk_disable; 367 } 368 369 /* by default the device is on */ 370 pm_runtime_set_active(&pdev->dev); 371 pm_runtime_enable(&pdev->dev); 372 373 platform_set_drvdata(pdev, master); 374 375 ret = devm_spi_register_master(&pdev->dev, master); 376 if (ret) { 377 dev_err(&pdev->dev, "Failed to register master\n"); 378 goto clk_disable; 379 } 380 381 return 0; 382 383 clk_disable: 384 clk_disable_unprepare(spi_st->clk); 385 put_master: 386 spi_master_put(master); 387 return ret; 388 } 389 390 static int spi_st_remove(struct platform_device *pdev) 391 { 392 struct spi_master *master = platform_get_drvdata(pdev); 393 struct spi_st *spi_st = spi_master_get_devdata(master); 394 395 clk_disable_unprepare(spi_st->clk); 396 397 pinctrl_pm_select_sleep_state(&pdev->dev); 398 399 return 0; 400 } 401 402 #ifdef CONFIG_PM 403 static int spi_st_runtime_suspend(struct device *dev) 404 { 405 struct spi_master *master = dev_get_drvdata(dev); 406 struct spi_st *spi_st = spi_master_get_devdata(master); 407 408 writel_relaxed(0, spi_st->base + SSC_IEN); 409 pinctrl_pm_select_sleep_state(dev); 410 411 clk_disable_unprepare(spi_st->clk); 412 413 return 0; 414 } 415 416 static int spi_st_runtime_resume(struct device *dev) 417 { 418 struct spi_master *master = dev_get_drvdata(dev); 419 struct spi_st *spi_st = spi_master_get_devdata(master); 420 int ret; 421 422 ret = clk_prepare_enable(spi_st->clk); 423 pinctrl_pm_select_default_state(dev); 424 425 return ret; 426 } 427 #endif 428 429 #ifdef CONFIG_PM_SLEEP 430 static int spi_st_suspend(struct device *dev) 431 { 432 struct spi_master *master = dev_get_drvdata(dev); 433 int ret; 434 435 ret = spi_master_suspend(master); 436 if (ret) 437 return ret; 438 439 return pm_runtime_force_suspend(dev); 440 } 441 442 static int spi_st_resume(struct device *dev) 443 { 444 struct spi_master *master = dev_get_drvdata(dev); 445 int ret; 446 447 ret = spi_master_resume(master); 448 if (ret) 449 return ret; 450 451 return pm_runtime_force_resume(dev); 452 } 453 #endif 454 455 static const struct dev_pm_ops spi_st_pm = { 456 SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume) 457 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL) 458 }; 459 460 static const struct of_device_id stm_spi_match[] = { 461 { .compatible = "st,comms-ssc4-spi", }, 462 {}, 463 }; 464 MODULE_DEVICE_TABLE(of, stm_spi_match); 465 466 static struct platform_driver spi_st_driver = { 467 .driver = { 468 .name = "spi-st", 469 .pm = &spi_st_pm, 470 .of_match_table = of_match_ptr(stm_spi_match), 471 }, 472 .probe = spi_st_probe, 473 .remove = spi_st_remove, 474 }; 475 module_platform_driver(spi_st_driver); 476 477 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); 478 MODULE_DESCRIPTION("STM SSC SPI driver"); 479 MODULE_LICENSE("GPL v2"); 480