1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Spreadtrum Communications Inc. 3 4 #include <linux/clk.h> 5 #include <linux/dmaengine.h> 6 #include <linux/dma-mapping.h> 7 #include <linux/dma/sprd-dma.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/of_dma.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/spi/spi.h> 19 20 #define SPRD_SPI_TXD 0x0 21 #define SPRD_SPI_CLKD 0x4 22 #define SPRD_SPI_CTL0 0x8 23 #define SPRD_SPI_CTL1 0xc 24 #define SPRD_SPI_CTL2 0x10 25 #define SPRD_SPI_CTL3 0x14 26 #define SPRD_SPI_CTL4 0x18 27 #define SPRD_SPI_CTL5 0x1c 28 #define SPRD_SPI_INT_EN 0x20 29 #define SPRD_SPI_INT_CLR 0x24 30 #define SPRD_SPI_INT_RAW_STS 0x28 31 #define SPRD_SPI_INT_MASK_STS 0x2c 32 #define SPRD_SPI_STS1 0x30 33 #define SPRD_SPI_STS2 0x34 34 #define SPRD_SPI_DSP_WAIT 0x38 35 #define SPRD_SPI_STS3 0x3c 36 #define SPRD_SPI_CTL6 0x40 37 #define SPRD_SPI_STS4 0x44 38 #define SPRD_SPI_FIFO_RST 0x48 39 #define SPRD_SPI_CTL7 0x4c 40 #define SPRD_SPI_STS5 0x50 41 #define SPRD_SPI_CTL8 0x54 42 #define SPRD_SPI_CTL9 0x58 43 #define SPRD_SPI_CTL10 0x5c 44 #define SPRD_SPI_CTL11 0x60 45 #define SPRD_SPI_CTL12 0x64 46 #define SPRD_SPI_STS6 0x68 47 #define SPRD_SPI_STS7 0x6c 48 #define SPRD_SPI_STS8 0x70 49 #define SPRD_SPI_STS9 0x74 50 51 /* Bits & mask definition for register CTL0 */ 52 #define SPRD_SPI_SCK_REV BIT(13) 53 #define SPRD_SPI_NG_TX BIT(1) 54 #define SPRD_SPI_NG_RX BIT(0) 55 #define SPRD_SPI_CHNL_LEN_MASK GENMASK(4, 0) 56 #define SPRD_SPI_CSN_MASK GENMASK(11, 8) 57 #define SPRD_SPI_CS0_VALID BIT(8) 58 59 /* Bits & mask definition for register SPI_INT_EN */ 60 #define SPRD_SPI_TX_END_INT_EN BIT(8) 61 #define SPRD_SPI_RX_END_INT_EN BIT(9) 62 63 /* Bits & mask definition for register SPI_INT_RAW_STS */ 64 #define SPRD_SPI_TX_END_RAW BIT(8) 65 #define SPRD_SPI_RX_END_RAW BIT(9) 66 67 /* Bits & mask definition for register SPI_INT_CLR */ 68 #define SPRD_SPI_TX_END_CLR BIT(8) 69 #define SPRD_SPI_RX_END_CLR BIT(9) 70 71 /* Bits & mask definition for register INT_MASK_STS */ 72 #define SPRD_SPI_MASK_RX_END BIT(9) 73 #define SPRD_SPI_MASK_TX_END BIT(8) 74 75 /* Bits & mask definition for register STS2 */ 76 #define SPRD_SPI_TX_BUSY BIT(8) 77 78 /* Bits & mask definition for register CTL1 */ 79 #define SPRD_SPI_RX_MODE BIT(12) 80 #define SPRD_SPI_TX_MODE BIT(13) 81 #define SPRD_SPI_RTX_MD_MASK GENMASK(13, 12) 82 83 /* Bits & mask definition for register CTL2 */ 84 #define SPRD_SPI_DMA_EN BIT(6) 85 86 /* Bits & mask definition for register CTL4 */ 87 #define SPRD_SPI_START_RX BIT(9) 88 #define SPRD_SPI_ONLY_RECV_MASK GENMASK(8, 0) 89 90 /* Bits & mask definition for register SPI_INT_CLR */ 91 #define SPRD_SPI_RX_END_INT_CLR BIT(9) 92 #define SPRD_SPI_TX_END_INT_CLR BIT(8) 93 94 /* Bits & mask definition for register SPI_INT_RAW */ 95 #define SPRD_SPI_RX_END_IRQ BIT(9) 96 #define SPRD_SPI_TX_END_IRQ BIT(8) 97 98 /* Bits & mask definition for register CTL12 */ 99 #define SPRD_SPI_SW_RX_REQ BIT(0) 100 #define SPRD_SPI_SW_TX_REQ BIT(1) 101 102 /* Bits & mask definition for register CTL7 */ 103 #define SPRD_SPI_DATA_LINE2_EN BIT(15) 104 #define SPRD_SPI_MODE_MASK GENMASK(5, 3) 105 #define SPRD_SPI_MODE_OFFSET 3 106 #define SPRD_SPI_3WIRE_MODE 4 107 #define SPRD_SPI_4WIRE_MODE 0 108 109 /* Bits & mask definition for register CTL8 */ 110 #define SPRD_SPI_TX_MAX_LEN_MASK GENMASK(19, 0) 111 #define SPRD_SPI_TX_LEN_H_MASK GENMASK(3, 0) 112 #define SPRD_SPI_TX_LEN_H_OFFSET 16 113 114 /* Bits & mask definition for register CTL9 */ 115 #define SPRD_SPI_TX_LEN_L_MASK GENMASK(15, 0) 116 117 /* Bits & mask definition for register CTL10 */ 118 #define SPRD_SPI_RX_MAX_LEN_MASK GENMASK(19, 0) 119 #define SPRD_SPI_RX_LEN_H_MASK GENMASK(3, 0) 120 #define SPRD_SPI_RX_LEN_H_OFFSET 16 121 122 /* Bits & mask definition for register CTL11 */ 123 #define SPRD_SPI_RX_LEN_L_MASK GENMASK(15, 0) 124 125 /* Default & maximum word delay cycles */ 126 #define SPRD_SPI_MIN_DELAY_CYCLE 14 127 #define SPRD_SPI_MAX_DELAY_CYCLE 130 128 129 #define SPRD_SPI_FIFO_SIZE 32 130 #define SPRD_SPI_CHIP_CS_NUM 0x4 131 #define SPRD_SPI_CHNL_LEN 2 132 #define SPRD_SPI_DEFAULT_SOURCE 26000000 133 #define SPRD_SPI_MAX_SPEED_HZ 48000000 134 #define SPRD_SPI_AUTOSUSPEND_DELAY 100 135 #define SPRD_SPI_DMA_STEP 8 136 137 enum sprd_spi_dma_channel { 138 SPI_RX, 139 SPI_TX, 140 SPI_MAX, 141 }; 142 143 struct sprd_spi_dma { 144 bool enable; 145 struct dma_chan *dma_chan[SPI_MAX]; 146 enum dma_slave_buswidth width; 147 u32 fragmens_len; 148 u32 rx_len; 149 }; 150 151 struct sprd_spi { 152 void __iomem *base; 153 phys_addr_t phy_base; 154 struct device *dev; 155 struct clk *clk; 156 int irq; 157 u32 src_clk; 158 u32 hw_mode; 159 u32 trans_len; 160 u32 trans_mode; 161 u32 word_delay; 162 u32 hw_speed_hz; 163 u32 len; 164 int status; 165 struct sprd_spi_dma dma; 166 struct completion xfer_completion; 167 const void *tx_buf; 168 void *rx_buf; 169 int (*read_bufs)(struct sprd_spi *ss, u32 len); 170 int (*write_bufs)(struct sprd_spi *ss, u32 len); 171 }; 172 173 static u32 sprd_spi_transfer_max_timeout(struct sprd_spi *ss, 174 struct spi_transfer *t) 175 { 176 /* 177 * The time spent on transmission of the full FIFO data is the maximum 178 * SPI transmission time. 179 */ 180 u32 size = t->bits_per_word * SPRD_SPI_FIFO_SIZE; 181 u32 bit_time_us = DIV_ROUND_UP(USEC_PER_SEC, ss->hw_speed_hz); 182 u32 total_time_us = size * bit_time_us; 183 /* 184 * There is an interval between data and the data in our SPI hardware, 185 * so the total transmission time need add the interval time. 186 */ 187 u32 interval_cycle = SPRD_SPI_FIFO_SIZE * ss->word_delay; 188 u32 interval_time_us = DIV_ROUND_UP(interval_cycle * USEC_PER_SEC, 189 ss->src_clk); 190 191 return total_time_us + interval_time_us; 192 } 193 194 static int sprd_spi_wait_for_tx_end(struct sprd_spi *ss, struct spi_transfer *t) 195 { 196 u32 val, us; 197 int ret; 198 199 us = sprd_spi_transfer_max_timeout(ss, t); 200 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, 201 val & SPRD_SPI_TX_END_IRQ, 0, us); 202 if (ret) { 203 dev_err(ss->dev, "SPI error, spi send timeout!\n"); 204 return ret; 205 } 206 207 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val, 208 !(val & SPRD_SPI_TX_BUSY), 0, us); 209 if (ret) { 210 dev_err(ss->dev, "SPI error, spi busy timeout!\n"); 211 return ret; 212 } 213 214 writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR); 215 216 return 0; 217 } 218 219 static int sprd_spi_wait_for_rx_end(struct sprd_spi *ss, struct spi_transfer *t) 220 { 221 u32 val, us; 222 int ret; 223 224 us = sprd_spi_transfer_max_timeout(ss, t); 225 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, 226 val & SPRD_SPI_RX_END_IRQ, 0, us); 227 if (ret) { 228 dev_err(ss->dev, "SPI error, spi rx timeout!\n"); 229 return ret; 230 } 231 232 writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR); 233 234 return 0; 235 } 236 237 static void sprd_spi_tx_req(struct sprd_spi *ss) 238 { 239 writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12); 240 } 241 242 static void sprd_spi_rx_req(struct sprd_spi *ss) 243 { 244 writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12); 245 } 246 247 static void sprd_spi_enter_idle(struct sprd_spi *ss) 248 { 249 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1); 250 251 val &= ~SPRD_SPI_RTX_MD_MASK; 252 writel_relaxed(val, ss->base + SPRD_SPI_CTL1); 253 } 254 255 static void sprd_spi_set_transfer_bits(struct sprd_spi *ss, u32 bits) 256 { 257 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0); 258 259 /* Set the valid bits for every transaction */ 260 val &= ~(SPRD_SPI_CHNL_LEN_MASK << SPRD_SPI_CHNL_LEN); 261 val |= bits << SPRD_SPI_CHNL_LEN; 262 writel_relaxed(val, ss->base + SPRD_SPI_CTL0); 263 } 264 265 static void sprd_spi_set_tx_length(struct sprd_spi *ss, u32 length) 266 { 267 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8); 268 269 length &= SPRD_SPI_TX_MAX_LEN_MASK; 270 val &= ~SPRD_SPI_TX_LEN_H_MASK; 271 val |= length >> SPRD_SPI_TX_LEN_H_OFFSET; 272 writel_relaxed(val, ss->base + SPRD_SPI_CTL8); 273 274 val = length & SPRD_SPI_TX_LEN_L_MASK; 275 writel_relaxed(val, ss->base + SPRD_SPI_CTL9); 276 } 277 278 static void sprd_spi_set_rx_length(struct sprd_spi *ss, u32 length) 279 { 280 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10); 281 282 length &= SPRD_SPI_RX_MAX_LEN_MASK; 283 val &= ~SPRD_SPI_RX_LEN_H_MASK; 284 val |= length >> SPRD_SPI_RX_LEN_H_OFFSET; 285 writel_relaxed(val, ss->base + SPRD_SPI_CTL10); 286 287 val = length & SPRD_SPI_RX_LEN_L_MASK; 288 writel_relaxed(val, ss->base + SPRD_SPI_CTL11); 289 } 290 291 static void sprd_spi_chipselect(struct spi_device *sdev, bool cs) 292 { 293 struct spi_controller *sctlr = sdev->controller; 294 struct sprd_spi *ss = spi_controller_get_devdata(sctlr); 295 u32 val; 296 297 val = readl_relaxed(ss->base + SPRD_SPI_CTL0); 298 /* The SPI controller will pull down CS pin if cs is 0 */ 299 if (!cs) { 300 val &= ~SPRD_SPI_CS0_VALID; 301 writel_relaxed(val, ss->base + SPRD_SPI_CTL0); 302 } else { 303 val |= SPRD_SPI_CSN_MASK; 304 writel_relaxed(val, ss->base + SPRD_SPI_CTL0); 305 } 306 } 307 308 static int sprd_spi_write_only_receive(struct sprd_spi *ss, u32 len) 309 { 310 u32 val; 311 312 /* Clear the start receive bit and reset receive data number */ 313 val = readl_relaxed(ss->base + SPRD_SPI_CTL4); 314 val &= ~(SPRD_SPI_START_RX | SPRD_SPI_ONLY_RECV_MASK); 315 writel_relaxed(val, ss->base + SPRD_SPI_CTL4); 316 317 /* Set the receive data length */ 318 val = readl_relaxed(ss->base + SPRD_SPI_CTL4); 319 val |= len & SPRD_SPI_ONLY_RECV_MASK; 320 writel_relaxed(val, ss->base + SPRD_SPI_CTL4); 321 322 /* Trigger to receive data */ 323 val = readl_relaxed(ss->base + SPRD_SPI_CTL4); 324 val |= SPRD_SPI_START_RX; 325 writel_relaxed(val, ss->base + SPRD_SPI_CTL4); 326 327 return len; 328 } 329 330 static int sprd_spi_write_bufs_u8(struct sprd_spi *ss, u32 len) 331 { 332 u8 *tx_p = (u8 *)ss->tx_buf; 333 int i; 334 335 for (i = 0; i < len; i++) 336 writeb_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD); 337 338 ss->tx_buf += i; 339 return i; 340 } 341 342 static int sprd_spi_write_bufs_u16(struct sprd_spi *ss, u32 len) 343 { 344 u16 *tx_p = (u16 *)ss->tx_buf; 345 int i; 346 347 for (i = 0; i < len; i++) 348 writew_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD); 349 350 ss->tx_buf += i << 1; 351 return i << 1; 352 } 353 354 static int sprd_spi_write_bufs_u32(struct sprd_spi *ss, u32 len) 355 { 356 u32 *tx_p = (u32 *)ss->tx_buf; 357 int i; 358 359 for (i = 0; i < len; i++) 360 writel_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD); 361 362 ss->tx_buf += i << 2; 363 return i << 2; 364 } 365 366 static int sprd_spi_read_bufs_u8(struct sprd_spi *ss, u32 len) 367 { 368 u8 *rx_p = (u8 *)ss->rx_buf; 369 int i; 370 371 for (i = 0; i < len; i++) 372 rx_p[i] = readb_relaxed(ss->base + SPRD_SPI_TXD); 373 374 ss->rx_buf += i; 375 return i; 376 } 377 378 static int sprd_spi_read_bufs_u16(struct sprd_spi *ss, u32 len) 379 { 380 u16 *rx_p = (u16 *)ss->rx_buf; 381 int i; 382 383 for (i = 0; i < len; i++) 384 rx_p[i] = readw_relaxed(ss->base + SPRD_SPI_TXD); 385 386 ss->rx_buf += i << 1; 387 return i << 1; 388 } 389 390 static int sprd_spi_read_bufs_u32(struct sprd_spi *ss, u32 len) 391 { 392 u32 *rx_p = (u32 *)ss->rx_buf; 393 int i; 394 395 for (i = 0; i < len; i++) 396 rx_p[i] = readl_relaxed(ss->base + SPRD_SPI_TXD); 397 398 ss->rx_buf += i << 2; 399 return i << 2; 400 } 401 402 static int sprd_spi_txrx_bufs(struct spi_device *sdev, struct spi_transfer *t) 403 { 404 struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller); 405 u32 trans_len = ss->trans_len, len; 406 int ret, write_size = 0; 407 408 while (trans_len) { 409 len = trans_len > SPRD_SPI_FIFO_SIZE ? SPRD_SPI_FIFO_SIZE : 410 trans_len; 411 if (ss->trans_mode & SPRD_SPI_TX_MODE) { 412 sprd_spi_set_tx_length(ss, len); 413 write_size += ss->write_bufs(ss, len); 414 415 /* 416 * For our 3 wires mode or dual TX line mode, we need 417 * to request the controller to transfer. 418 */ 419 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL) 420 sprd_spi_tx_req(ss); 421 422 ret = sprd_spi_wait_for_tx_end(ss, t); 423 } else { 424 sprd_spi_set_rx_length(ss, len); 425 426 /* 427 * For our 3 wires mode or dual TX line mode, we need 428 * to request the controller to read. 429 */ 430 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL) 431 sprd_spi_rx_req(ss); 432 else 433 write_size += ss->write_bufs(ss, len); 434 435 ret = sprd_spi_wait_for_rx_end(ss, t); 436 } 437 438 if (ret) 439 goto complete; 440 441 if (ss->trans_mode & SPRD_SPI_RX_MODE) 442 ss->read_bufs(ss, len); 443 444 trans_len -= len; 445 } 446 447 ret = write_size; 448 449 complete: 450 sprd_spi_enter_idle(ss); 451 452 return ret; 453 } 454 455 static void sprd_spi_irq_enable(struct sprd_spi *ss) 456 { 457 u32 val; 458 459 /* Clear interrupt status before enabling interrupt. */ 460 writel_relaxed(SPRD_SPI_TX_END_CLR | SPRD_SPI_RX_END_CLR, 461 ss->base + SPRD_SPI_INT_CLR); 462 /* Enable SPI interrupt only in DMA mode. */ 463 val = readl_relaxed(ss->base + SPRD_SPI_INT_EN); 464 writel_relaxed(val | SPRD_SPI_TX_END_INT_EN | 465 SPRD_SPI_RX_END_INT_EN, 466 ss->base + SPRD_SPI_INT_EN); 467 } 468 469 static void sprd_spi_irq_disable(struct sprd_spi *ss) 470 { 471 writel_relaxed(0, ss->base + SPRD_SPI_INT_EN); 472 } 473 474 static void sprd_spi_dma_enable(struct sprd_spi *ss, bool enable) 475 { 476 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL2); 477 478 if (enable) 479 val |= SPRD_SPI_DMA_EN; 480 else 481 val &= ~SPRD_SPI_DMA_EN; 482 483 writel_relaxed(val, ss->base + SPRD_SPI_CTL2); 484 } 485 486 static int sprd_spi_dma_submit(struct dma_chan *dma_chan, 487 struct dma_slave_config *c, 488 struct sg_table *sg, 489 enum dma_transfer_direction dir) 490 { 491 struct dma_async_tx_descriptor *desc; 492 dma_cookie_t cookie; 493 unsigned long flags; 494 int ret; 495 496 ret = dmaengine_slave_config(dma_chan, c); 497 if (ret < 0) 498 return ret; 499 500 flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE, SPRD_DMA_NO_TRG, 501 SPRD_DMA_FRAG_REQ, SPRD_DMA_TRANS_INT); 502 desc = dmaengine_prep_slave_sg(dma_chan, sg->sgl, sg->nents, dir, flags); 503 if (!desc) 504 return -ENODEV; 505 506 cookie = dmaengine_submit(desc); 507 if (dma_submit_error(cookie)) 508 return dma_submit_error(cookie); 509 510 dma_async_issue_pending(dma_chan); 511 512 return 0; 513 } 514 515 static int sprd_spi_dma_rx_config(struct sprd_spi *ss, struct spi_transfer *t) 516 { 517 struct dma_chan *dma_chan = ss->dma.dma_chan[SPI_RX]; 518 struct dma_slave_config config = { 519 .src_addr = ss->phy_base, 520 .src_addr_width = ss->dma.width, 521 .dst_addr_width = ss->dma.width, 522 .dst_maxburst = ss->dma.fragmens_len, 523 }; 524 int ret; 525 526 ret = sprd_spi_dma_submit(dma_chan, &config, &t->rx_sg, DMA_DEV_TO_MEM); 527 if (ret) 528 return ret; 529 530 return ss->dma.rx_len; 531 } 532 533 static int sprd_spi_dma_tx_config(struct sprd_spi *ss, struct spi_transfer *t) 534 { 535 struct dma_chan *dma_chan = ss->dma.dma_chan[SPI_TX]; 536 struct dma_slave_config config = { 537 .dst_addr = ss->phy_base, 538 .src_addr_width = ss->dma.width, 539 .dst_addr_width = ss->dma.width, 540 .src_maxburst = ss->dma.fragmens_len, 541 }; 542 int ret; 543 544 ret = sprd_spi_dma_submit(dma_chan, &config, &t->tx_sg, DMA_MEM_TO_DEV); 545 if (ret) 546 return ret; 547 548 return t->len; 549 } 550 551 static int sprd_spi_dma_request(struct sprd_spi *ss) 552 { 553 ss->dma.dma_chan[SPI_RX] = dma_request_chan(ss->dev, "rx_chn"); 554 if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPI_RX])) { 555 if (PTR_ERR(ss->dma.dma_chan[SPI_RX]) == -EPROBE_DEFER) 556 return PTR_ERR(ss->dma.dma_chan[SPI_RX]); 557 558 dev_err(ss->dev, "request RX DMA channel failed!\n"); 559 return PTR_ERR(ss->dma.dma_chan[SPI_RX]); 560 } 561 562 ss->dma.dma_chan[SPI_TX] = dma_request_chan(ss->dev, "tx_chn"); 563 if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPI_TX])) { 564 if (PTR_ERR(ss->dma.dma_chan[SPI_TX]) == -EPROBE_DEFER) 565 return PTR_ERR(ss->dma.dma_chan[SPI_TX]); 566 567 dev_err(ss->dev, "request TX DMA channel failed!\n"); 568 dma_release_channel(ss->dma.dma_chan[SPI_RX]); 569 return PTR_ERR(ss->dma.dma_chan[SPI_TX]); 570 } 571 572 return 0; 573 } 574 575 static void sprd_spi_dma_release(struct sprd_spi *ss) 576 { 577 if (ss->dma.dma_chan[SPI_RX]) 578 dma_release_channel(ss->dma.dma_chan[SPI_RX]); 579 580 if (ss->dma.dma_chan[SPI_TX]) 581 dma_release_channel(ss->dma.dma_chan[SPI_TX]); 582 } 583 584 static int sprd_spi_dma_txrx_bufs(struct spi_device *sdev, 585 struct spi_transfer *t) 586 { 587 struct sprd_spi *ss = spi_master_get_devdata(sdev->master); 588 u32 trans_len = ss->trans_len; 589 int ret, write_size = 0; 590 591 reinit_completion(&ss->xfer_completion); 592 sprd_spi_irq_enable(ss); 593 if (ss->trans_mode & SPRD_SPI_TX_MODE) { 594 write_size = sprd_spi_dma_tx_config(ss, t); 595 sprd_spi_set_tx_length(ss, trans_len); 596 597 /* 598 * For our 3 wires mode or dual TX line mode, we need 599 * to request the controller to transfer. 600 */ 601 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL) 602 sprd_spi_tx_req(ss); 603 } else { 604 sprd_spi_set_rx_length(ss, trans_len); 605 606 /* 607 * For our 3 wires mode or dual TX line mode, we need 608 * to request the controller to read. 609 */ 610 if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL) 611 sprd_spi_rx_req(ss); 612 else 613 write_size = ss->write_bufs(ss, trans_len); 614 } 615 616 if (write_size < 0) { 617 ret = write_size; 618 dev_err(ss->dev, "failed to write, ret = %d\n", ret); 619 goto trans_complete; 620 } 621 622 if (ss->trans_mode & SPRD_SPI_RX_MODE) { 623 /* 624 * Set up the DMA receive data length, which must be an 625 * integral multiple of fragment length. But when the length 626 * of received data is less than fragment length, DMA can be 627 * configured to receive data according to the actual length 628 * of received data. 629 */ 630 ss->dma.rx_len = t->len > ss->dma.fragmens_len ? 631 (t->len - t->len % ss->dma.fragmens_len) : 632 t->len; 633 ret = sprd_spi_dma_rx_config(ss, t); 634 if (ret < 0) { 635 dev_err(&sdev->dev, 636 "failed to configure rx DMA, ret = %d\n", ret); 637 goto trans_complete; 638 } 639 } 640 641 sprd_spi_dma_enable(ss, true); 642 wait_for_completion(&(ss->xfer_completion)); 643 644 if (ss->trans_mode & SPRD_SPI_TX_MODE) 645 ret = write_size; 646 else 647 ret = ss->dma.rx_len; 648 649 trans_complete: 650 sprd_spi_dma_enable(ss, false); 651 sprd_spi_enter_idle(ss); 652 sprd_spi_irq_disable(ss); 653 654 return ret; 655 } 656 657 static void sprd_spi_set_speed(struct sprd_spi *ss, u32 speed_hz) 658 { 659 /* 660 * From SPI datasheet, the prescale calculation formula: 661 * prescale = SPI source clock / (2 * SPI_freq) - 1; 662 */ 663 u32 clk_div = DIV_ROUND_UP(ss->src_clk, speed_hz << 1) - 1; 664 665 /* Save the real hardware speed */ 666 ss->hw_speed_hz = (ss->src_clk >> 1) / (clk_div + 1); 667 writel_relaxed(clk_div, ss->base + SPRD_SPI_CLKD); 668 } 669 670 static void sprd_spi_init_hw(struct sprd_spi *ss, struct spi_transfer *t) 671 { 672 u16 word_delay, interval; 673 u32 val; 674 675 val = readl_relaxed(ss->base + SPRD_SPI_CTL7); 676 val &= ~(SPRD_SPI_SCK_REV | SPRD_SPI_NG_TX | SPRD_SPI_NG_RX); 677 /* Set default chip selection, clock phase and clock polarity */ 678 val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX; 679 val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0; 680 writel_relaxed(val, ss->base + SPRD_SPI_CTL0); 681 682 /* 683 * Set the intervals of two SPI frames, and the inteval calculation 684 * formula as below per datasheet: 685 * interval time (source clock cycles) = interval * 4 + 10. 686 */ 687 word_delay = clamp_t(u16, t->word_delay, SPRD_SPI_MIN_DELAY_CYCLE, 688 SPRD_SPI_MAX_DELAY_CYCLE); 689 interval = DIV_ROUND_UP(word_delay - 10, 4); 690 ss->word_delay = interval * 4 + 10; 691 writel_relaxed(interval, ss->base + SPRD_SPI_CTL5); 692 693 /* Reset SPI fifo */ 694 writel_relaxed(1, ss->base + SPRD_SPI_FIFO_RST); 695 writel_relaxed(0, ss->base + SPRD_SPI_FIFO_RST); 696 697 /* Set SPI work mode */ 698 val = readl_relaxed(ss->base + SPRD_SPI_CTL7); 699 val &= ~SPRD_SPI_MODE_MASK; 700 701 if (ss->hw_mode & SPI_3WIRE) 702 val |= SPRD_SPI_3WIRE_MODE << SPRD_SPI_MODE_OFFSET; 703 else 704 val |= SPRD_SPI_4WIRE_MODE << SPRD_SPI_MODE_OFFSET; 705 706 if (ss->hw_mode & SPI_TX_DUAL) 707 val |= SPRD_SPI_DATA_LINE2_EN; 708 else 709 val &= ~SPRD_SPI_DATA_LINE2_EN; 710 711 writel_relaxed(val, ss->base + SPRD_SPI_CTL7); 712 } 713 714 static int sprd_spi_setup_transfer(struct spi_device *sdev, 715 struct spi_transfer *t) 716 { 717 struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller); 718 u8 bits_per_word = t->bits_per_word; 719 u32 val, mode = 0; 720 721 ss->len = t->len; 722 ss->tx_buf = t->tx_buf; 723 ss->rx_buf = t->rx_buf; 724 725 ss->hw_mode = sdev->mode; 726 sprd_spi_init_hw(ss, t); 727 728 /* Set tansfer speed and valid bits */ 729 sprd_spi_set_speed(ss, t->speed_hz); 730 sprd_spi_set_transfer_bits(ss, bits_per_word); 731 732 if (bits_per_word > 16) 733 bits_per_word = round_up(bits_per_word, 16); 734 else 735 bits_per_word = round_up(bits_per_word, 8); 736 737 switch (bits_per_word) { 738 case 8: 739 ss->trans_len = t->len; 740 ss->read_bufs = sprd_spi_read_bufs_u8; 741 ss->write_bufs = sprd_spi_write_bufs_u8; 742 ss->dma.width = DMA_SLAVE_BUSWIDTH_1_BYTE; 743 ss->dma.fragmens_len = SPRD_SPI_DMA_STEP; 744 break; 745 case 16: 746 ss->trans_len = t->len >> 1; 747 ss->read_bufs = sprd_spi_read_bufs_u16; 748 ss->write_bufs = sprd_spi_write_bufs_u16; 749 ss->dma.width = DMA_SLAVE_BUSWIDTH_2_BYTES; 750 ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 1; 751 break; 752 case 32: 753 ss->trans_len = t->len >> 2; 754 ss->read_bufs = sprd_spi_read_bufs_u32; 755 ss->write_bufs = sprd_spi_write_bufs_u32; 756 ss->dma.width = DMA_SLAVE_BUSWIDTH_4_BYTES; 757 ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 2; 758 break; 759 default: 760 return -EINVAL; 761 } 762 763 /* Set transfer read or write mode */ 764 val = readl_relaxed(ss->base + SPRD_SPI_CTL1); 765 val &= ~SPRD_SPI_RTX_MD_MASK; 766 if (t->tx_buf) 767 mode |= SPRD_SPI_TX_MODE; 768 if (t->rx_buf) 769 mode |= SPRD_SPI_RX_MODE; 770 771 writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1); 772 773 ss->trans_mode = mode; 774 775 /* 776 * If in only receive mode, we need to trigger the SPI controller to 777 * receive data automatically. 778 */ 779 if (ss->trans_mode == SPRD_SPI_RX_MODE) 780 ss->write_bufs = sprd_spi_write_only_receive; 781 782 return 0; 783 } 784 785 static int sprd_spi_transfer_one(struct spi_controller *sctlr, 786 struct spi_device *sdev, 787 struct spi_transfer *t) 788 { 789 int ret; 790 791 ret = sprd_spi_setup_transfer(sdev, t); 792 if (ret) 793 goto setup_err; 794 795 if (sctlr->can_dma(sctlr, sdev, t)) 796 ret = sprd_spi_dma_txrx_bufs(sdev, t); 797 else 798 ret = sprd_spi_txrx_bufs(sdev, t); 799 800 if (ret == t->len) 801 ret = 0; 802 else if (ret >= 0) 803 ret = -EREMOTEIO; 804 805 setup_err: 806 spi_finalize_current_transfer(sctlr); 807 808 return ret; 809 } 810 811 static irqreturn_t sprd_spi_handle_irq(int irq, void *data) 812 { 813 struct sprd_spi *ss = (struct sprd_spi *)data; 814 u32 val = readl_relaxed(ss->base + SPRD_SPI_INT_MASK_STS); 815 816 if (val & SPRD_SPI_MASK_TX_END) { 817 writel_relaxed(SPRD_SPI_TX_END_CLR, ss->base + SPRD_SPI_INT_CLR); 818 if (!(ss->trans_mode & SPRD_SPI_RX_MODE)) 819 complete(&ss->xfer_completion); 820 821 return IRQ_HANDLED; 822 } 823 824 if (val & SPRD_SPI_MASK_RX_END) { 825 writel_relaxed(SPRD_SPI_RX_END_CLR, ss->base + SPRD_SPI_INT_CLR); 826 if (ss->dma.rx_len < ss->len) { 827 ss->rx_buf += ss->dma.rx_len; 828 ss->dma.rx_len += 829 ss->read_bufs(ss, ss->len - ss->dma.rx_len); 830 } 831 complete(&ss->xfer_completion); 832 833 return IRQ_HANDLED; 834 } 835 836 return IRQ_NONE; 837 } 838 839 static int sprd_spi_irq_init(struct platform_device *pdev, struct sprd_spi *ss) 840 { 841 int ret; 842 843 ss->irq = platform_get_irq(pdev, 0); 844 if (ss->irq < 0) { 845 dev_err(&pdev->dev, "failed to get irq resource\n"); 846 return ss->irq; 847 } 848 849 ret = devm_request_irq(&pdev->dev, ss->irq, sprd_spi_handle_irq, 850 0, pdev->name, ss); 851 if (ret) 852 dev_err(&pdev->dev, "failed to request spi irq %d, ret = %d\n", 853 ss->irq, ret); 854 855 return ret; 856 } 857 858 static int sprd_spi_clk_init(struct platform_device *pdev, struct sprd_spi *ss) 859 { 860 struct clk *clk_spi, *clk_parent; 861 862 clk_spi = devm_clk_get(&pdev->dev, "spi"); 863 if (IS_ERR(clk_spi)) { 864 dev_warn(&pdev->dev, "can't get the spi clock\n"); 865 clk_spi = NULL; 866 } 867 868 clk_parent = devm_clk_get(&pdev->dev, "source"); 869 if (IS_ERR(clk_parent)) { 870 dev_warn(&pdev->dev, "can't get the source clock\n"); 871 clk_parent = NULL; 872 } 873 874 ss->clk = devm_clk_get(&pdev->dev, "enable"); 875 if (IS_ERR(ss->clk)) { 876 dev_err(&pdev->dev, "can't get the enable clock\n"); 877 return PTR_ERR(ss->clk); 878 } 879 880 if (!clk_set_parent(clk_spi, clk_parent)) 881 ss->src_clk = clk_get_rate(clk_spi); 882 else 883 ss->src_clk = SPRD_SPI_DEFAULT_SOURCE; 884 885 return 0; 886 } 887 888 static bool sprd_spi_can_dma(struct spi_controller *sctlr, 889 struct spi_device *spi, struct spi_transfer *t) 890 { 891 struct sprd_spi *ss = spi_controller_get_devdata(sctlr); 892 893 return ss->dma.enable && (t->len > SPRD_SPI_FIFO_SIZE); 894 } 895 896 static int sprd_spi_dma_init(struct platform_device *pdev, struct sprd_spi *ss) 897 { 898 int ret; 899 900 ret = sprd_spi_dma_request(ss); 901 if (ret) { 902 if (ret == -EPROBE_DEFER) 903 return ret; 904 905 dev_warn(&pdev->dev, 906 "failed to request dma, enter no dma mode, ret = %d\n", 907 ret); 908 909 return 0; 910 } 911 912 ss->dma.enable = true; 913 914 return 0; 915 } 916 917 static int sprd_spi_probe(struct platform_device *pdev) 918 { 919 struct spi_controller *sctlr; 920 struct resource *res; 921 struct sprd_spi *ss; 922 int ret; 923 924 pdev->id = of_alias_get_id(pdev->dev.of_node, "spi"); 925 sctlr = spi_alloc_master(&pdev->dev, sizeof(*ss)); 926 if (!sctlr) 927 return -ENOMEM; 928 929 ss = spi_controller_get_devdata(sctlr); 930 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 931 ss->base = devm_ioremap_resource(&pdev->dev, res); 932 if (IS_ERR(ss->base)) { 933 ret = PTR_ERR(ss->base); 934 goto free_controller; 935 } 936 937 ss->phy_base = res->start; 938 ss->dev = &pdev->dev; 939 sctlr->dev.of_node = pdev->dev.of_node; 940 sctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE | SPI_TX_DUAL; 941 sctlr->bus_num = pdev->id; 942 sctlr->set_cs = sprd_spi_chipselect; 943 sctlr->transfer_one = sprd_spi_transfer_one; 944 sctlr->can_dma = sprd_spi_can_dma; 945 sctlr->auto_runtime_pm = true; 946 sctlr->max_speed_hz = min_t(u32, ss->src_clk >> 1, 947 SPRD_SPI_MAX_SPEED_HZ); 948 949 init_completion(&ss->xfer_completion); 950 platform_set_drvdata(pdev, sctlr); 951 ret = sprd_spi_clk_init(pdev, ss); 952 if (ret) 953 goto free_controller; 954 955 ret = sprd_spi_irq_init(pdev, ss); 956 if (ret) 957 goto free_controller; 958 959 ret = sprd_spi_dma_init(pdev, ss); 960 if (ret) 961 goto free_controller; 962 963 ret = clk_prepare_enable(ss->clk); 964 if (ret) 965 goto release_dma; 966 967 ret = pm_runtime_set_active(&pdev->dev); 968 if (ret < 0) 969 goto disable_clk; 970 971 pm_runtime_set_autosuspend_delay(&pdev->dev, 972 SPRD_SPI_AUTOSUSPEND_DELAY); 973 pm_runtime_use_autosuspend(&pdev->dev); 974 pm_runtime_enable(&pdev->dev); 975 ret = pm_runtime_get_sync(&pdev->dev); 976 if (ret < 0) { 977 dev_err(&pdev->dev, "failed to resume SPI controller\n"); 978 goto err_rpm_put; 979 } 980 981 ret = devm_spi_register_controller(&pdev->dev, sctlr); 982 if (ret) 983 goto err_rpm_put; 984 985 pm_runtime_mark_last_busy(&pdev->dev); 986 pm_runtime_put_autosuspend(&pdev->dev); 987 988 return 0; 989 990 err_rpm_put: 991 pm_runtime_put_noidle(&pdev->dev); 992 pm_runtime_disable(&pdev->dev); 993 disable_clk: 994 clk_disable_unprepare(ss->clk); 995 release_dma: 996 sprd_spi_dma_release(ss); 997 free_controller: 998 spi_controller_put(sctlr); 999 1000 return ret; 1001 } 1002 1003 static int sprd_spi_remove(struct platform_device *pdev) 1004 { 1005 struct spi_controller *sctlr = platform_get_drvdata(pdev); 1006 struct sprd_spi *ss = spi_controller_get_devdata(sctlr); 1007 int ret; 1008 1009 ret = pm_runtime_get_sync(ss->dev); 1010 if (ret < 0) { 1011 dev_err(ss->dev, "failed to resume SPI controller\n"); 1012 return ret; 1013 } 1014 1015 spi_controller_suspend(sctlr); 1016 1017 if (ss->dma.enable) 1018 sprd_spi_dma_release(ss); 1019 clk_disable_unprepare(ss->clk); 1020 pm_runtime_put_noidle(&pdev->dev); 1021 pm_runtime_disable(&pdev->dev); 1022 1023 return 0; 1024 } 1025 1026 static int __maybe_unused sprd_spi_runtime_suspend(struct device *dev) 1027 { 1028 struct spi_controller *sctlr = dev_get_drvdata(dev); 1029 struct sprd_spi *ss = spi_controller_get_devdata(sctlr); 1030 1031 if (ss->dma.enable) 1032 sprd_spi_dma_release(ss); 1033 1034 clk_disable_unprepare(ss->clk); 1035 1036 return 0; 1037 } 1038 1039 static int __maybe_unused sprd_spi_runtime_resume(struct device *dev) 1040 { 1041 struct spi_controller *sctlr = dev_get_drvdata(dev); 1042 struct sprd_spi *ss = spi_controller_get_devdata(sctlr); 1043 int ret; 1044 1045 ret = clk_prepare_enable(ss->clk); 1046 if (ret) 1047 return ret; 1048 1049 if (!ss->dma.enable) 1050 return 0; 1051 1052 ret = sprd_spi_dma_request(ss); 1053 if (ret) 1054 clk_disable_unprepare(ss->clk); 1055 1056 return ret; 1057 } 1058 1059 static const struct dev_pm_ops sprd_spi_pm_ops = { 1060 SET_RUNTIME_PM_OPS(sprd_spi_runtime_suspend, 1061 sprd_spi_runtime_resume, NULL) 1062 }; 1063 1064 static const struct of_device_id sprd_spi_of_match[] = { 1065 { .compatible = "sprd,sc9860-spi", }, 1066 { /* sentinel */ } 1067 }; 1068 1069 static struct platform_driver sprd_spi_driver = { 1070 .driver = { 1071 .name = "sprd-spi", 1072 .of_match_table = sprd_spi_of_match, 1073 .pm = &sprd_spi_pm_ops, 1074 }, 1075 .probe = sprd_spi_probe, 1076 .remove = sprd_spi_remove, 1077 }; 1078 1079 module_platform_driver(sprd_spi_driver); 1080 1081 MODULE_DESCRIPTION("Spreadtrum SPI Controller driver"); 1082 MODULE_AUTHOR("Lanqing Liu <lanqing.liu@spreadtrum.com>"); 1083 MODULE_LICENSE("GPL v2"); 1084