19135bac3SWolfram Sang // SPDX-License-Identifier: GPL-2.0
2ca632f55SGrant Likely /*
3ca632f55SGrant Likely * SH SPI bus driver
4ca632f55SGrant Likely *
5ca632f55SGrant Likely * Copyright (C) 2011 Renesas Solutions Corp.
6ca632f55SGrant Likely *
7ca632f55SGrant Likely * Based on pxa2xx_spi.c:
8ca632f55SGrant Likely * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
9ca632f55SGrant Likely */
10ca632f55SGrant Likely
11ca632f55SGrant Likely #include <linux/module.h>
12ca632f55SGrant Likely #include <linux/kernel.h>
13ca632f55SGrant Likely #include <linux/sched.h>
14ca632f55SGrant Likely #include <linux/errno.h>
15ca632f55SGrant Likely #include <linux/timer.h>
16ca632f55SGrant Likely #include <linux/delay.h>
17ca632f55SGrant Likely #include <linux/list.h>
18ca632f55SGrant Likely #include <linux/workqueue.h>
19ca632f55SGrant Likely #include <linux/interrupt.h>
20ca632f55SGrant Likely #include <linux/platform_device.h>
21ca632f55SGrant Likely #include <linux/io.h>
22ca632f55SGrant Likely #include <linux/spi/spi.h>
23ca632f55SGrant Likely
24ca632f55SGrant Likely #define SPI_SH_TBR 0x00
25ca632f55SGrant Likely #define SPI_SH_RBR 0x00
26ca632f55SGrant Likely #define SPI_SH_CR1 0x08
27ca632f55SGrant Likely #define SPI_SH_CR2 0x10
28ca632f55SGrant Likely #define SPI_SH_CR3 0x18
29ca632f55SGrant Likely #define SPI_SH_CR4 0x20
30ca632f55SGrant Likely #define SPI_SH_CR5 0x28
31ca632f55SGrant Likely
32ca632f55SGrant Likely /* CR1 */
33ca632f55SGrant Likely #define SPI_SH_TBE 0x80
34ca632f55SGrant Likely #define SPI_SH_TBF 0x40
35ca632f55SGrant Likely #define SPI_SH_RBE 0x20
36ca632f55SGrant Likely #define SPI_SH_RBF 0x10
37ca632f55SGrant Likely #define SPI_SH_PFONRD 0x08
38ca632f55SGrant Likely #define SPI_SH_SSDB 0x04
39ca632f55SGrant Likely #define SPI_SH_SSD 0x02
40ca632f55SGrant Likely #define SPI_SH_SSA 0x01
41ca632f55SGrant Likely
42ca632f55SGrant Likely /* CR2 */
43ca632f55SGrant Likely #define SPI_SH_RSTF 0x80
44ca632f55SGrant Likely #define SPI_SH_LOOPBK 0x40
45ca632f55SGrant Likely #define SPI_SH_CPOL 0x20
46ca632f55SGrant Likely #define SPI_SH_CPHA 0x10
47ca632f55SGrant Likely #define SPI_SH_L1M0 0x08
48ca632f55SGrant Likely
49ca632f55SGrant Likely /* CR3 */
50ca632f55SGrant Likely #define SPI_SH_MAX_BYTE 0xFF
51ca632f55SGrant Likely
52ca632f55SGrant Likely /* CR4 */
53ca632f55SGrant Likely #define SPI_SH_TBEI 0x80
54ca632f55SGrant Likely #define SPI_SH_TBFI 0x40
55ca632f55SGrant Likely #define SPI_SH_RBEI 0x20
56ca632f55SGrant Likely #define SPI_SH_RBFI 0x10
57ca632f55SGrant Likely #define SPI_SH_WPABRT 0x04
58ca632f55SGrant Likely #define SPI_SH_SSS 0x01
59ca632f55SGrant Likely
60ca632f55SGrant Likely /* CR8 */
61ca632f55SGrant Likely #define SPI_SH_P1L0 0x80
62ca632f55SGrant Likely #define SPI_SH_PP1L0 0x40
63ca632f55SGrant Likely #define SPI_SH_MUXI 0x20
64ca632f55SGrant Likely #define SPI_SH_MUXIRQ 0x10
65ca632f55SGrant Likely
66ca632f55SGrant Likely #define SPI_SH_FIFO_SIZE 32
67ca632f55SGrant Likely #define SPI_SH_SEND_TIMEOUT (3 * HZ)
68ca632f55SGrant Likely #define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3)
69ca632f55SGrant Likely
70ca632f55SGrant Likely #undef DEBUG
71ca632f55SGrant Likely
72ca632f55SGrant Likely struct spi_sh_data {
73ca632f55SGrant Likely void __iomem *addr;
74ca632f55SGrant Likely int irq;
75*0ec6a150SYang Yingliang struct spi_controller *host;
76ca632f55SGrant Likely unsigned long cr1;
77ca632f55SGrant Likely wait_queue_head_t wait;
780eb8880fSShimoda, Yoshihiro int width;
79ca632f55SGrant Likely };
80ca632f55SGrant Likely
spi_sh_write(struct spi_sh_data * ss,unsigned long data,unsigned long offset)81ca632f55SGrant Likely static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
82ca632f55SGrant Likely unsigned long offset)
83ca632f55SGrant Likely {
840eb8880fSShimoda, Yoshihiro if (ss->width == 8)
850eb8880fSShimoda, Yoshihiro iowrite8(data, ss->addr + (offset >> 2));
860eb8880fSShimoda, Yoshihiro else if (ss->width == 32)
870eb8880fSShimoda, Yoshihiro iowrite32(data, ss->addr + offset);
88ca632f55SGrant Likely }
89ca632f55SGrant Likely
spi_sh_read(struct spi_sh_data * ss,unsigned long offset)90ca632f55SGrant Likely static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
91ca632f55SGrant Likely {
920eb8880fSShimoda, Yoshihiro if (ss->width == 8)
930eb8880fSShimoda, Yoshihiro return ioread8(ss->addr + (offset >> 2));
940eb8880fSShimoda, Yoshihiro else if (ss->width == 32)
950eb8880fSShimoda, Yoshihiro return ioread32(ss->addr + offset);
960eb8880fSShimoda, Yoshihiro else
970eb8880fSShimoda, Yoshihiro return 0;
98ca632f55SGrant Likely }
99ca632f55SGrant Likely
spi_sh_set_bit(struct spi_sh_data * ss,unsigned long val,unsigned long offset)100ca632f55SGrant Likely static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
101ca632f55SGrant Likely unsigned long offset)
102ca632f55SGrant Likely {
103ca632f55SGrant Likely unsigned long tmp;
104ca632f55SGrant Likely
105ca632f55SGrant Likely tmp = spi_sh_read(ss, offset);
106ca632f55SGrant Likely tmp |= val;
107ca632f55SGrant Likely spi_sh_write(ss, tmp, offset);
108ca632f55SGrant Likely }
109ca632f55SGrant Likely
spi_sh_clear_bit(struct spi_sh_data * ss,unsigned long val,unsigned long offset)110ca632f55SGrant Likely static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
111ca632f55SGrant Likely unsigned long offset)
112ca632f55SGrant Likely {
113ca632f55SGrant Likely unsigned long tmp;
114ca632f55SGrant Likely
115ca632f55SGrant Likely tmp = spi_sh_read(ss, offset);
116ca632f55SGrant Likely tmp &= ~val;
117ca632f55SGrant Likely spi_sh_write(ss, tmp, offset);
118ca632f55SGrant Likely }
119ca632f55SGrant Likely
clear_fifo(struct spi_sh_data * ss)120ca632f55SGrant Likely static void clear_fifo(struct spi_sh_data *ss)
121ca632f55SGrant Likely {
122ca632f55SGrant Likely spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
123ca632f55SGrant Likely spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
124ca632f55SGrant Likely }
125ca632f55SGrant Likely
spi_sh_wait_receive_buffer(struct spi_sh_data * ss)126ca632f55SGrant Likely static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
127ca632f55SGrant Likely {
128ca632f55SGrant Likely int timeout = 100000;
129ca632f55SGrant Likely
130ca632f55SGrant Likely while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
131ca632f55SGrant Likely udelay(10);
132ca632f55SGrant Likely if (timeout-- < 0)
133ca632f55SGrant Likely return -ETIMEDOUT;
134ca632f55SGrant Likely }
135ca632f55SGrant Likely return 0;
136ca632f55SGrant Likely }
137ca632f55SGrant Likely
spi_sh_wait_write_buffer_empty(struct spi_sh_data * ss)138ca632f55SGrant Likely static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
139ca632f55SGrant Likely {
140ca632f55SGrant Likely int timeout = 100000;
141ca632f55SGrant Likely
142ca632f55SGrant Likely while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
143ca632f55SGrant Likely udelay(10);
144ca632f55SGrant Likely if (timeout-- < 0)
145ca632f55SGrant Likely return -ETIMEDOUT;
146ca632f55SGrant Likely }
147ca632f55SGrant Likely return 0;
148ca632f55SGrant Likely }
149ca632f55SGrant Likely
spi_sh_send(struct spi_sh_data * ss,struct spi_message * mesg,struct spi_transfer * t)150ca632f55SGrant Likely static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
151ca632f55SGrant Likely struct spi_transfer *t)
152ca632f55SGrant Likely {
153ca632f55SGrant Likely int i, retval = 0;
154ca632f55SGrant Likely int remain = t->len;
155ca632f55SGrant Likely int cur_len;
156ca632f55SGrant Likely unsigned char *data;
157ca632f55SGrant Likely long ret;
158ca632f55SGrant Likely
159ca632f55SGrant Likely if (t->len)
160ca632f55SGrant Likely spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
161ca632f55SGrant Likely
162ca632f55SGrant Likely data = (unsigned char *)t->tx_buf;
163ca632f55SGrant Likely while (remain > 0) {
164ca632f55SGrant Likely cur_len = min(SPI_SH_FIFO_SIZE, remain);
165ca632f55SGrant Likely for (i = 0; i < cur_len &&
166ca632f55SGrant Likely !(spi_sh_read(ss, SPI_SH_CR4) &
167ca632f55SGrant Likely SPI_SH_WPABRT) &&
168ca632f55SGrant Likely !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
169ca632f55SGrant Likely i++)
170ca632f55SGrant Likely spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
171ca632f55SGrant Likely
172ca632f55SGrant Likely if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
173ca632f55SGrant Likely /* Abort SPI operation */
174ca632f55SGrant Likely spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
175ca632f55SGrant Likely retval = -EIO;
176ca632f55SGrant Likely break;
177ca632f55SGrant Likely }
178ca632f55SGrant Likely
179ca632f55SGrant Likely cur_len = i;
180ca632f55SGrant Likely
181ca632f55SGrant Likely remain -= cur_len;
182ca632f55SGrant Likely data += cur_len;
183ca632f55SGrant Likely
184ca632f55SGrant Likely if (remain > 0) {
185ca632f55SGrant Likely ss->cr1 &= ~SPI_SH_TBE;
186ca632f55SGrant Likely spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
187ca632f55SGrant Likely ret = wait_event_interruptible_timeout(ss->wait,
188ca632f55SGrant Likely ss->cr1 & SPI_SH_TBE,
189ca632f55SGrant Likely SPI_SH_SEND_TIMEOUT);
190ca632f55SGrant Likely if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
191ca632f55SGrant Likely printk(KERN_ERR "%s: timeout\n", __func__);
192ca632f55SGrant Likely return -ETIMEDOUT;
193ca632f55SGrant Likely }
194ca632f55SGrant Likely }
195ca632f55SGrant Likely }
196ca632f55SGrant Likely
197ca632f55SGrant Likely if (list_is_last(&t->transfer_list, &mesg->transfers)) {
198909e709cSAxel Lin spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
199ca632f55SGrant Likely spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
200ca632f55SGrant Likely
201ca632f55SGrant Likely ss->cr1 &= ~SPI_SH_TBE;
202ca632f55SGrant Likely spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
203ca632f55SGrant Likely ret = wait_event_interruptible_timeout(ss->wait,
204ca632f55SGrant Likely ss->cr1 & SPI_SH_TBE,
205ca632f55SGrant Likely SPI_SH_SEND_TIMEOUT);
206ca632f55SGrant Likely if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
207ca632f55SGrant Likely printk(KERN_ERR "%s: timeout\n", __func__);
208ca632f55SGrant Likely return -ETIMEDOUT;
209ca632f55SGrant Likely }
210ca632f55SGrant Likely }
211ca632f55SGrant Likely
212ca632f55SGrant Likely return retval;
213ca632f55SGrant Likely }
214ca632f55SGrant Likely
spi_sh_receive(struct spi_sh_data * ss,struct spi_message * mesg,struct spi_transfer * t)215ca632f55SGrant Likely static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
216ca632f55SGrant Likely struct spi_transfer *t)
217ca632f55SGrant Likely {
218ca632f55SGrant Likely int i;
219ca632f55SGrant Likely int remain = t->len;
220ca632f55SGrant Likely int cur_len;
221ca632f55SGrant Likely unsigned char *data;
222ca632f55SGrant Likely long ret;
223ca632f55SGrant Likely
224ca632f55SGrant Likely if (t->len > SPI_SH_MAX_BYTE)
225ca632f55SGrant Likely spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
226ca632f55SGrant Likely else
227ca632f55SGrant Likely spi_sh_write(ss, t->len, SPI_SH_CR3);
228ca632f55SGrant Likely
229909e709cSAxel Lin spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
230ca632f55SGrant Likely spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
231ca632f55SGrant Likely
232ca632f55SGrant Likely spi_sh_wait_write_buffer_empty(ss);
233ca632f55SGrant Likely
234ca632f55SGrant Likely data = (unsigned char *)t->rx_buf;
235ca632f55SGrant Likely while (remain > 0) {
236ca632f55SGrant Likely if (remain >= SPI_SH_FIFO_SIZE) {
237ca632f55SGrant Likely ss->cr1 &= ~SPI_SH_RBF;
238ca632f55SGrant Likely spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
239ca632f55SGrant Likely ret = wait_event_interruptible_timeout(ss->wait,
240ca632f55SGrant Likely ss->cr1 & SPI_SH_RBF,
241ca632f55SGrant Likely SPI_SH_RECEIVE_TIMEOUT);
242ca632f55SGrant Likely if (ret == 0 &&
243ca632f55SGrant Likely spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
244ca632f55SGrant Likely printk(KERN_ERR "%s: timeout\n", __func__);
245ca632f55SGrant Likely return -ETIMEDOUT;
246ca632f55SGrant Likely }
247ca632f55SGrant Likely }
248ca632f55SGrant Likely
249ca632f55SGrant Likely cur_len = min(SPI_SH_FIFO_SIZE, remain);
250ca632f55SGrant Likely for (i = 0; i < cur_len; i++) {
251ca632f55SGrant Likely if (spi_sh_wait_receive_buffer(ss))
252ca632f55SGrant Likely break;
253ca632f55SGrant Likely data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
254ca632f55SGrant Likely }
255ca632f55SGrant Likely
256ca632f55SGrant Likely remain -= cur_len;
257ca632f55SGrant Likely data += cur_len;
258ca632f55SGrant Likely }
259ca632f55SGrant Likely
260ca632f55SGrant Likely /* deassert CS when SPI is receiving. */
261ca632f55SGrant Likely if (t->len > SPI_SH_MAX_BYTE) {
262ca632f55SGrant Likely clear_fifo(ss);
263ca632f55SGrant Likely spi_sh_write(ss, 1, SPI_SH_CR3);
264ca632f55SGrant Likely } else {
265ca632f55SGrant Likely spi_sh_write(ss, 0, SPI_SH_CR3);
266ca632f55SGrant Likely }
267ca632f55SGrant Likely
268ca632f55SGrant Likely return 0;
269ca632f55SGrant Likely }
270ca632f55SGrant Likely
spi_sh_transfer_one_message(struct spi_controller * ctlr,struct spi_message * mesg)271e2185072SMark Brown static int spi_sh_transfer_one_message(struct spi_controller *ctlr,
272e2185072SMark Brown struct spi_message *mesg)
273ca632f55SGrant Likely {
274e2185072SMark Brown struct spi_sh_data *ss = spi_controller_get_devdata(ctlr);
275ca632f55SGrant Likely struct spi_transfer *t;
276ca632f55SGrant Likely int ret;
277ca632f55SGrant Likely
278ca632f55SGrant Likely pr_debug("%s: enter\n", __func__);
279ca632f55SGrant Likely
280e2185072SMark Brown spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
281ca632f55SGrant Likely
282ca632f55SGrant Likely list_for_each_entry(t, &mesg->transfers, transfer_list) {
283ca632f55SGrant Likely pr_debug("tx_buf = %p, rx_buf = %p\n",
284ca632f55SGrant Likely t->tx_buf, t->rx_buf);
285506d1a1bSAlexandru Ardelean pr_debug("len = %d, delay.value = %d\n",
286506d1a1bSAlexandru Ardelean t->len, t->delay.value);
287ca632f55SGrant Likely
288ca632f55SGrant Likely if (t->tx_buf) {
289ca632f55SGrant Likely ret = spi_sh_send(ss, mesg, t);
290ca632f55SGrant Likely if (ret < 0)
291ca632f55SGrant Likely goto error;
292ca632f55SGrant Likely }
293ca632f55SGrant Likely if (t->rx_buf) {
294ca632f55SGrant Likely ret = spi_sh_receive(ss, mesg, t);
295ca632f55SGrant Likely if (ret < 0)
296ca632f55SGrant Likely goto error;
297ca632f55SGrant Likely }
298ca632f55SGrant Likely mesg->actual_length += t->len;
299ca632f55SGrant Likely }
300ca632f55SGrant Likely
301ca632f55SGrant Likely mesg->status = 0;
302e2185072SMark Brown spi_finalize_current_message(ctlr);
303ca632f55SGrant Likely
304ca632f55SGrant Likely clear_fifo(ss);
305ca632f55SGrant Likely spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
306ca632f55SGrant Likely udelay(100);
307ca632f55SGrant Likely
308ca632f55SGrant Likely spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
309ca632f55SGrant Likely SPI_SH_CR1);
310ca632f55SGrant Likely
311ca632f55SGrant Likely clear_fifo(ss);
312ca632f55SGrant Likely
313e2185072SMark Brown return 0;
314ca632f55SGrant Likely
315ca632f55SGrant Likely error:
316ca632f55SGrant Likely mesg->status = ret;
317e2185072SMark Brown spi_finalize_current_message(ctlr);
3180a6d3879SAxel Lin if (mesg->complete)
319ca632f55SGrant Likely mesg->complete(mesg->context);
320ca632f55SGrant Likely
321ca632f55SGrant Likely spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
322ca632f55SGrant Likely SPI_SH_CR1);
323ca632f55SGrant Likely clear_fifo(ss);
324ca632f55SGrant Likely
325e2185072SMark Brown return ret;
326ca632f55SGrant Likely }
327ca632f55SGrant Likely
spi_sh_setup(struct spi_device * spi)328ca632f55SGrant Likely static int spi_sh_setup(struct spi_device *spi)
329ca632f55SGrant Likely {
330*0ec6a150SYang Yingliang struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
331ca632f55SGrant Likely
332ca632f55SGrant Likely pr_debug("%s: enter\n", __func__);
333ca632f55SGrant Likely
334ca632f55SGrant Likely spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
335ca632f55SGrant Likely spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
336ca632f55SGrant Likely spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
337ca632f55SGrant Likely
338ca632f55SGrant Likely clear_fifo(ss);
339ca632f55SGrant Likely
340ca632f55SGrant Likely /* 1/8 clock */
341ca632f55SGrant Likely spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
342ca632f55SGrant Likely udelay(10);
343ca632f55SGrant Likely
344ca632f55SGrant Likely return 0;
345ca632f55SGrant Likely }
346ca632f55SGrant Likely
spi_sh_cleanup(struct spi_device * spi)347ca632f55SGrant Likely static void spi_sh_cleanup(struct spi_device *spi)
348ca632f55SGrant Likely {
349*0ec6a150SYang Yingliang struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
350ca632f55SGrant Likely
351ca632f55SGrant Likely pr_debug("%s: enter\n", __func__);
352ca632f55SGrant Likely
353ca632f55SGrant Likely spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
354ca632f55SGrant Likely SPI_SH_CR1);
355ca632f55SGrant Likely }
356ca632f55SGrant Likely
spi_sh_irq(int irq,void * _ss)357ca632f55SGrant Likely static irqreturn_t spi_sh_irq(int irq, void *_ss)
358ca632f55SGrant Likely {
359ca632f55SGrant Likely struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
360ca632f55SGrant Likely unsigned long cr1;
361ca632f55SGrant Likely
362ca632f55SGrant Likely cr1 = spi_sh_read(ss, SPI_SH_CR1);
363ca632f55SGrant Likely if (cr1 & SPI_SH_TBE)
364ca632f55SGrant Likely ss->cr1 |= SPI_SH_TBE;
365ca632f55SGrant Likely if (cr1 & SPI_SH_TBF)
366ca632f55SGrant Likely ss->cr1 |= SPI_SH_TBF;
367ca632f55SGrant Likely if (cr1 & SPI_SH_RBE)
368ca632f55SGrant Likely ss->cr1 |= SPI_SH_RBE;
369ca632f55SGrant Likely if (cr1 & SPI_SH_RBF)
370ca632f55SGrant Likely ss->cr1 |= SPI_SH_RBF;
371ca632f55SGrant Likely
372ca632f55SGrant Likely if (ss->cr1) {
373ca632f55SGrant Likely spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
374ca632f55SGrant Likely wake_up(&ss->wait);
375ca632f55SGrant Likely }
376ca632f55SGrant Likely
377ca632f55SGrant Likely return IRQ_HANDLED;
378ca632f55SGrant Likely }
379ca632f55SGrant Likely
spi_sh_remove(struct platform_device * pdev)380dee2e255SUwe Kleine-König static void spi_sh_remove(struct platform_device *pdev)
381ca632f55SGrant Likely {
38224b5a82cSJingoo Han struct spi_sh_data *ss = platform_get_drvdata(pdev);
383ca632f55SGrant Likely
384*0ec6a150SYang Yingliang spi_unregister_controller(ss->host);
385ca632f55SGrant Likely free_irq(ss->irq, ss);
386ca632f55SGrant Likely }
387ca632f55SGrant Likely
spi_sh_probe(struct platform_device * pdev)388fd4a319bSGrant Likely static int spi_sh_probe(struct platform_device *pdev)
389ca632f55SGrant Likely {
390ca632f55SGrant Likely struct resource *res;
391*0ec6a150SYang Yingliang struct spi_controller *host;
392ca632f55SGrant Likely struct spi_sh_data *ss;
393ca632f55SGrant Likely int ret, irq;
394ca632f55SGrant Likely
395ca632f55SGrant Likely /* get base addr */
396ca632f55SGrant Likely res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
397ca632f55SGrant Likely if (unlikely(res == NULL)) {
398ca632f55SGrant Likely dev_err(&pdev->dev, "invalid resource\n");
399ca632f55SGrant Likely return -EINVAL;
400ca632f55SGrant Likely }
401ca632f55SGrant Likely
402ca632f55SGrant Likely irq = platform_get_irq(pdev, 0);
4036b8ac10eSStephen Boyd if (irq < 0)
404345fef75SGustavo A. R. Silva return irq;
405ca632f55SGrant Likely
406*0ec6a150SYang Yingliang host = devm_spi_alloc_host(&pdev->dev, sizeof(struct spi_sh_data));
407*0ec6a150SYang Yingliang if (host == NULL) {
408*0ec6a150SYang Yingliang dev_err(&pdev->dev, "devm_spi_alloc_host error.\n");
409ca632f55SGrant Likely return -ENOMEM;
410ca632f55SGrant Likely }
411ca632f55SGrant Likely
412*0ec6a150SYang Yingliang ss = spi_controller_get_devdata(host);
41324b5a82cSJingoo Han platform_set_drvdata(pdev, ss);
414ca632f55SGrant Likely
4150eb8880fSShimoda, Yoshihiro switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
4160eb8880fSShimoda, Yoshihiro case IORESOURCE_MEM_8BIT:
4170eb8880fSShimoda, Yoshihiro ss->width = 8;
4180eb8880fSShimoda, Yoshihiro break;
4190eb8880fSShimoda, Yoshihiro case IORESOURCE_MEM_32BIT:
4200eb8880fSShimoda, Yoshihiro ss->width = 32;
4210eb8880fSShimoda, Yoshihiro break;
4220eb8880fSShimoda, Yoshihiro default:
4230eb8880fSShimoda, Yoshihiro dev_err(&pdev->dev, "No support width\n");
424e77df3ecSLukas Wunner return -ENODEV;
4250eb8880fSShimoda, Yoshihiro }
426ca632f55SGrant Likely ss->irq = irq;
427*0ec6a150SYang Yingliang ss->host = host;
428e9d42d15SHimangi Saraogi ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
429ca632f55SGrant Likely if (ss->addr == NULL) {
430ca632f55SGrant Likely dev_err(&pdev->dev, "ioremap error.\n");
431e77df3ecSLukas Wunner return -ENOMEM;
432ca632f55SGrant Likely }
433ca632f55SGrant Likely init_waitqueue_head(&ss->wait);
434ca632f55SGrant Likely
43538ada214SYong Zhang ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
436ca632f55SGrant Likely if (ret < 0) {
437ca632f55SGrant Likely dev_err(&pdev->dev, "request_irq error\n");
438e77df3ecSLukas Wunner return ret;
439ca632f55SGrant Likely }
440ca632f55SGrant Likely
441*0ec6a150SYang Yingliang host->num_chipselect = 2;
442*0ec6a150SYang Yingliang host->bus_num = pdev->id;
443*0ec6a150SYang Yingliang host->setup = spi_sh_setup;
444*0ec6a150SYang Yingliang host->transfer_one_message = spi_sh_transfer_one_message;
445*0ec6a150SYang Yingliang host->cleanup = spi_sh_cleanup;
446ca632f55SGrant Likely
447*0ec6a150SYang Yingliang ret = spi_register_controller(host);
448ca632f55SGrant Likely if (ret < 0) {
449*0ec6a150SYang Yingliang printk(KERN_ERR "spi_register_controller error.\n");
450e9d42d15SHimangi Saraogi goto error3;
451ca632f55SGrant Likely }
452ca632f55SGrant Likely
453ca632f55SGrant Likely return 0;
454ca632f55SGrant Likely
455ca632f55SGrant Likely error3:
456e9d42d15SHimangi Saraogi free_irq(irq, ss);
457ca632f55SGrant Likely return ret;
458ca632f55SGrant Likely }
459ca632f55SGrant Likely
460ca632f55SGrant Likely static struct platform_driver spi_sh_driver = {
461ca632f55SGrant Likely .probe = spi_sh_probe,
462dee2e255SUwe Kleine-König .remove_new = spi_sh_remove,
463ca632f55SGrant Likely .driver = {
464ca632f55SGrant Likely .name = "sh_spi",
465ca632f55SGrant Likely },
466ca632f55SGrant Likely };
467940ab889SGrant Likely module_platform_driver(spi_sh_driver);
468ca632f55SGrant Likely
469ca632f55SGrant Likely MODULE_DESCRIPTION("SH SPI bus driver");
4709135bac3SWolfram Sang MODULE_LICENSE("GPL v2");
471ca632f55SGrant Likely MODULE_AUTHOR("Yoshihiro Shimoda");
472ca632f55SGrant Likely MODULE_ALIAS("platform:sh_spi");
473