xref: /openbmc/linux/drivers/spi/spi-sh-msiof.c (revision e8f6f3b4)
1 /*
2  * SuperH MSIOF SPI Master Interface
3  *
4  * Copyright (c) 2009 Magnus Damm
5  * Copyright (C) 2014 Glider bvba
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  */
12 
13 #include <linux/bitmap.h>
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmaengine.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
30 
31 #include <linux/spi/sh_msiof.h>
32 #include <linux/spi/spi.h>
33 
34 #include <asm/unaligned.h>
35 
36 
37 struct sh_msiof_chipdata {
38 	u16 tx_fifo_size;
39 	u16 rx_fifo_size;
40 	u16 master_flags;
41 };
42 
43 struct sh_msiof_spi_priv {
44 	struct spi_master *master;
45 	void __iomem *mapbase;
46 	struct clk *clk;
47 	struct platform_device *pdev;
48 	const struct sh_msiof_chipdata *chipdata;
49 	struct sh_msiof_spi_info *info;
50 	struct completion done;
51 	int tx_fifo_size;
52 	int rx_fifo_size;
53 	void *tx_dma_page;
54 	void *rx_dma_page;
55 	dma_addr_t tx_dma_addr;
56 	dma_addr_t rx_dma_addr;
57 };
58 
59 #define TMDR1	0x00	/* Transmit Mode Register 1 */
60 #define TMDR2	0x04	/* Transmit Mode Register 2 */
61 #define TMDR3	0x08	/* Transmit Mode Register 3 */
62 #define RMDR1	0x10	/* Receive Mode Register 1 */
63 #define RMDR2	0x14	/* Receive Mode Register 2 */
64 #define RMDR3	0x18	/* Receive Mode Register 3 */
65 #define TSCR	0x20	/* Transmit Clock Select Register */
66 #define RSCR	0x22	/* Receive Clock Select Register (SH, A1, APE6) */
67 #define CTR	0x28	/* Control Register */
68 #define FCTR	0x30	/* FIFO Control Register */
69 #define STR	0x40	/* Status Register */
70 #define IER	0x44	/* Interrupt Enable Register */
71 #define TDR1	0x48	/* Transmit Control Data Register 1 (SH, A1) */
72 #define TDR2	0x4c	/* Transmit Control Data Register 2 (SH, A1) */
73 #define TFDR	0x50	/* Transmit FIFO Data Register */
74 #define RDR1	0x58	/* Receive Control Data Register 1 (SH, A1) */
75 #define RDR2	0x5c	/* Receive Control Data Register 2 (SH, A1) */
76 #define RFDR	0x60	/* Receive FIFO Data Register */
77 
78 /* TMDR1 and RMDR1 */
79 #define MDR1_TRMD	 0x80000000 /* Transfer Mode (1 = Master mode) */
80 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
81 #define MDR1_SYNCMD_SPI	 0x20000000 /*   Level mode/SPI */
82 #define MDR1_SYNCMD_LR	 0x30000000 /*   L/R mode */
83 #define MDR1_SYNCAC_SHIFT	 25 /* Sync Polarity (1 = Active-low) */
84 #define MDR1_BITLSB_SHIFT	 24 /* MSB/LSB First (1 = LSB first) */
85 #define MDR1_FLD_MASK	 0x000000c0 /* Frame Sync Signal Interval (0-3) */
86 #define MDR1_FLD_SHIFT		  2
87 #define MDR1_XXSTP	 0x00000001 /* Transmission/Reception Stop on FIFO */
88 /* TMDR1 */
89 #define TMDR1_PCON	 0x40000000 /* Transfer Signal Connection */
90 
91 /* TMDR2 and RMDR2 */
92 #define MDR2_BITLEN1(i)	(((i) - 1) << 24) /* Data Size (8-32 bits) */
93 #define MDR2_WDLEN1(i)	(((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
94 #define MDR2_GRPMASK1	0x00000001 /* Group Output Mask 1 (SH, A1) */
95 
96 #define MAX_WDLEN	256U
97 
98 /* TSCR and RSCR */
99 #define SCR_BRPS_MASK	    0x1f00 /* Prescaler Setting (1-32) */
100 #define SCR_BRPS(i)	(((i) - 1) << 8)
101 #define SCR_BRDV_MASK	    0x0007 /* Baud Rate Generator's Division Ratio */
102 #define SCR_BRDV_DIV_2	    0x0000
103 #define SCR_BRDV_DIV_4	    0x0001
104 #define SCR_BRDV_DIV_8	    0x0002
105 #define SCR_BRDV_DIV_16	    0x0003
106 #define SCR_BRDV_DIV_32	    0x0004
107 #define SCR_BRDV_DIV_1	    0x0007
108 
109 /* CTR */
110 #define CTR_TSCKIZ_MASK	0xc0000000 /* Transmit Clock I/O Polarity Select */
111 #define CTR_TSCKIZ_SCK	0x80000000 /*   Disable SCK when TX disabled */
112 #define CTR_TSCKIZ_POL_SHIFT	30 /*   Transmit Clock Polarity */
113 #define CTR_RSCKIZ_MASK	0x30000000 /* Receive Clock Polarity Select */
114 #define CTR_RSCKIZ_SCK	0x20000000 /*   Must match CTR_TSCKIZ_SCK */
115 #define CTR_RSCKIZ_POL_SHIFT	28 /*   Receive Clock Polarity */
116 #define CTR_TEDG_SHIFT		27 /* Transmit Timing (1 = falling edge) */
117 #define CTR_REDG_SHIFT		26 /* Receive Timing (1 = falling edge) */
118 #define CTR_TXDIZ_MASK	0x00c00000 /* Pin Output When TX is Disabled */
119 #define CTR_TXDIZ_LOW	0x00000000 /*   0 */
120 #define CTR_TXDIZ_HIGH	0x00400000 /*   1 */
121 #define CTR_TXDIZ_HIZ	0x00800000 /*   High-impedance */
122 #define CTR_TSCKE	0x00008000 /* Transmit Serial Clock Output Enable */
123 #define CTR_TFSE	0x00004000 /* Transmit Frame Sync Signal Output Enable */
124 #define CTR_TXE		0x00000200 /* Transmit Enable */
125 #define CTR_RXE		0x00000100 /* Receive Enable */
126 
127 /* FCTR */
128 #define FCTR_TFWM_MASK	0xe0000000 /* Transmit FIFO Watermark */
129 #define FCTR_TFWM_64	0x00000000 /*  Transfer Request when 64 empty stages */
130 #define FCTR_TFWM_32	0x20000000 /*  Transfer Request when 32 empty stages */
131 #define FCTR_TFWM_24	0x40000000 /*  Transfer Request when 24 empty stages */
132 #define FCTR_TFWM_16	0x60000000 /*  Transfer Request when 16 empty stages */
133 #define FCTR_TFWM_12	0x80000000 /*  Transfer Request when 12 empty stages */
134 #define FCTR_TFWM_8	0xa0000000 /*  Transfer Request when 8 empty stages */
135 #define FCTR_TFWM_4	0xc0000000 /*  Transfer Request when 4 empty stages */
136 #define FCTR_TFWM_1	0xe0000000 /*  Transfer Request when 1 empty stage */
137 #define FCTR_TFUA_MASK	0x07f00000 /* Transmit FIFO Usable Area */
138 #define FCTR_TFUA_SHIFT		20
139 #define FCTR_TFUA(i)	((i) << FCTR_TFUA_SHIFT)
140 #define FCTR_RFWM_MASK	0x0000e000 /* Receive FIFO Watermark */
141 #define FCTR_RFWM_1	0x00000000 /*  Transfer Request when 1 valid stages */
142 #define FCTR_RFWM_4	0x00002000 /*  Transfer Request when 4 valid stages */
143 #define FCTR_RFWM_8	0x00004000 /*  Transfer Request when 8 valid stages */
144 #define FCTR_RFWM_16	0x00006000 /*  Transfer Request when 16 valid stages */
145 #define FCTR_RFWM_32	0x00008000 /*  Transfer Request when 32 valid stages */
146 #define FCTR_RFWM_64	0x0000a000 /*  Transfer Request when 64 valid stages */
147 #define FCTR_RFWM_128	0x0000c000 /*  Transfer Request when 128 valid stages */
148 #define FCTR_RFWM_256	0x0000e000 /*  Transfer Request when 256 valid stages */
149 #define FCTR_RFUA_MASK	0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
150 #define FCTR_RFUA_SHIFT		 4
151 #define FCTR_RFUA(i)	((i) << FCTR_RFUA_SHIFT)
152 
153 /* STR */
154 #define STR_TFEMP	0x20000000 /* Transmit FIFO Empty */
155 #define STR_TDREQ	0x10000000 /* Transmit Data Transfer Request */
156 #define STR_TEOF	0x00800000 /* Frame Transmission End */
157 #define STR_TFSERR	0x00200000 /* Transmit Frame Synchronization Error */
158 #define STR_TFOVF	0x00100000 /* Transmit FIFO Overflow */
159 #define STR_TFUDF	0x00080000 /* Transmit FIFO Underflow */
160 #define STR_RFFUL	0x00002000 /* Receive FIFO Full */
161 #define STR_RDREQ	0x00001000 /* Receive Data Transfer Request */
162 #define STR_REOF	0x00000080 /* Frame Reception End */
163 #define STR_RFSERR	0x00000020 /* Receive Frame Synchronization Error */
164 #define STR_RFUDF	0x00000010 /* Receive FIFO Underflow */
165 #define STR_RFOVF	0x00000008 /* Receive FIFO Overflow */
166 
167 /* IER */
168 #define IER_TDMAE	0x80000000 /* Transmit Data DMA Transfer Req. Enable */
169 #define IER_TFEMPE	0x20000000 /* Transmit FIFO Empty Enable */
170 #define IER_TDREQE	0x10000000 /* Transmit Data Transfer Request Enable */
171 #define IER_TEOFE	0x00800000 /* Frame Transmission End Enable */
172 #define IER_TFSERRE	0x00200000 /* Transmit Frame Sync Error Enable */
173 #define IER_TFOVFE	0x00100000 /* Transmit FIFO Overflow Enable */
174 #define IER_TFUDFE	0x00080000 /* Transmit FIFO Underflow Enable */
175 #define IER_RDMAE	0x00008000 /* Receive Data DMA Transfer Req. Enable */
176 #define IER_RFFULE	0x00002000 /* Receive FIFO Full Enable */
177 #define IER_RDREQE	0x00001000 /* Receive Data Transfer Request Enable */
178 #define IER_REOFE	0x00000080 /* Frame Reception End Enable */
179 #define IER_RFSERRE	0x00000020 /* Receive Frame Sync Error Enable */
180 #define IER_RFUDFE	0x00000010 /* Receive FIFO Underflow Enable */
181 #define IER_RFOVFE	0x00000008 /* Receive FIFO Overflow Enable */
182 
183 
184 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
185 {
186 	switch (reg_offs) {
187 	case TSCR:
188 	case RSCR:
189 		return ioread16(p->mapbase + reg_offs);
190 	default:
191 		return ioread32(p->mapbase + reg_offs);
192 	}
193 }
194 
195 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
196 			   u32 value)
197 {
198 	switch (reg_offs) {
199 	case TSCR:
200 	case RSCR:
201 		iowrite16(value, p->mapbase + reg_offs);
202 		break;
203 	default:
204 		iowrite32(value, p->mapbase + reg_offs);
205 		break;
206 	}
207 }
208 
209 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
210 				    u32 clr, u32 set)
211 {
212 	u32 mask = clr | set;
213 	u32 data;
214 	int k;
215 
216 	data = sh_msiof_read(p, CTR);
217 	data &= ~clr;
218 	data |= set;
219 	sh_msiof_write(p, CTR, data);
220 
221 	for (k = 100; k > 0; k--) {
222 		if ((sh_msiof_read(p, CTR) & mask) == set)
223 			break;
224 
225 		udelay(10);
226 	}
227 
228 	return k > 0 ? 0 : -ETIMEDOUT;
229 }
230 
231 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
232 {
233 	struct sh_msiof_spi_priv *p = data;
234 
235 	/* just disable the interrupt and wake up */
236 	sh_msiof_write(p, IER, 0);
237 	complete(&p->done);
238 
239 	return IRQ_HANDLED;
240 }
241 
242 static struct {
243 	unsigned short div;
244 	unsigned short scr;
245 } const sh_msiof_spi_clk_table[] = {
246 	{ 1,	SCR_BRPS( 1) | SCR_BRDV_DIV_1 },
247 	{ 2,	SCR_BRPS( 1) | SCR_BRDV_DIV_2 },
248 	{ 4,	SCR_BRPS( 1) | SCR_BRDV_DIV_4 },
249 	{ 8,	SCR_BRPS( 1) | SCR_BRDV_DIV_8 },
250 	{ 16,	SCR_BRPS( 1) | SCR_BRDV_DIV_16 },
251 	{ 32,	SCR_BRPS( 1) | SCR_BRDV_DIV_32 },
252 	{ 64,	SCR_BRPS(32) | SCR_BRDV_DIV_2 },
253 	{ 128,	SCR_BRPS(32) | SCR_BRDV_DIV_4 },
254 	{ 256,	SCR_BRPS(32) | SCR_BRDV_DIV_8 },
255 	{ 512,	SCR_BRPS(32) | SCR_BRDV_DIV_16 },
256 	{ 1024,	SCR_BRPS(32) | SCR_BRDV_DIV_32 },
257 };
258 
259 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
260 				      unsigned long parent_rate, u32 spi_hz)
261 {
262 	unsigned long div = 1024;
263 	size_t k;
264 
265 	if (!WARN_ON(!spi_hz || !parent_rate))
266 		div = DIV_ROUND_UP(parent_rate, spi_hz);
267 
268 	/* TODO: make more fine grained */
269 
270 	for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
271 		if (sh_msiof_spi_clk_table[k].div >= div)
272 			break;
273 	}
274 
275 	k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
276 
277 	sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
278 	if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
279 		sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
280 }
281 
282 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
283 				      u32 cpol, u32 cpha,
284 				      u32 tx_hi_z, u32 lsb_first, u32 cs_high)
285 {
286 	u32 tmp;
287 	int edge;
288 
289 	/*
290 	 * CPOL CPHA     TSCKIZ RSCKIZ TEDG REDG
291 	 *    0    0         10     10    1    1
292 	 *    0    1         10     10    0    0
293 	 *    1    0         11     11    0    0
294 	 *    1    1         11     11    1    1
295 	 */
296 	tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
297 	tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
298 	tmp |= lsb_first << MDR1_BITLSB_SHIFT;
299 	sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
300 	if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
301 		/* These bits are reserved if RX needs TX */
302 		tmp &= ~0x0000ffff;
303 	}
304 	sh_msiof_write(p, RMDR1, tmp);
305 
306 	tmp = 0;
307 	tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
308 	tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
309 
310 	edge = cpol ^ !cpha;
311 
312 	tmp |= edge << CTR_TEDG_SHIFT;
313 	tmp |= edge << CTR_REDG_SHIFT;
314 	tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
315 	sh_msiof_write(p, CTR, tmp);
316 }
317 
318 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
319 				       const void *tx_buf, void *rx_buf,
320 				       u32 bits, u32 words)
321 {
322 	u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
323 
324 	if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX))
325 		sh_msiof_write(p, TMDR2, dr2);
326 	else
327 		sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
328 
329 	if (rx_buf)
330 		sh_msiof_write(p, RMDR2, dr2);
331 }
332 
333 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
334 {
335 	sh_msiof_write(p, STR, sh_msiof_read(p, STR));
336 }
337 
338 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
339 				      const void *tx_buf, int words, int fs)
340 {
341 	const u8 *buf_8 = tx_buf;
342 	int k;
343 
344 	for (k = 0; k < words; k++)
345 		sh_msiof_write(p, TFDR, buf_8[k] << fs);
346 }
347 
348 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
349 				       const void *tx_buf, int words, int fs)
350 {
351 	const u16 *buf_16 = tx_buf;
352 	int k;
353 
354 	for (k = 0; k < words; k++)
355 		sh_msiof_write(p, TFDR, buf_16[k] << fs);
356 }
357 
358 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
359 					const void *tx_buf, int words, int fs)
360 {
361 	const u16 *buf_16 = tx_buf;
362 	int k;
363 
364 	for (k = 0; k < words; k++)
365 		sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
366 }
367 
368 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
369 				       const void *tx_buf, int words, int fs)
370 {
371 	const u32 *buf_32 = tx_buf;
372 	int k;
373 
374 	for (k = 0; k < words; k++)
375 		sh_msiof_write(p, TFDR, buf_32[k] << fs);
376 }
377 
378 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
379 					const void *tx_buf, int words, int fs)
380 {
381 	const u32 *buf_32 = tx_buf;
382 	int k;
383 
384 	for (k = 0; k < words; k++)
385 		sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
386 }
387 
388 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
389 					const void *tx_buf, int words, int fs)
390 {
391 	const u32 *buf_32 = tx_buf;
392 	int k;
393 
394 	for (k = 0; k < words; k++)
395 		sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
396 }
397 
398 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
399 					 const void *tx_buf, int words, int fs)
400 {
401 	const u32 *buf_32 = tx_buf;
402 	int k;
403 
404 	for (k = 0; k < words; k++)
405 		sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
406 }
407 
408 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
409 				     void *rx_buf, int words, int fs)
410 {
411 	u8 *buf_8 = rx_buf;
412 	int k;
413 
414 	for (k = 0; k < words; k++)
415 		buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
416 }
417 
418 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
419 				      void *rx_buf, int words, int fs)
420 {
421 	u16 *buf_16 = rx_buf;
422 	int k;
423 
424 	for (k = 0; k < words; k++)
425 		buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
426 }
427 
428 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
429 				       void *rx_buf, int words, int fs)
430 {
431 	u16 *buf_16 = rx_buf;
432 	int k;
433 
434 	for (k = 0; k < words; k++)
435 		put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
436 }
437 
438 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
439 				      void *rx_buf, int words, int fs)
440 {
441 	u32 *buf_32 = rx_buf;
442 	int k;
443 
444 	for (k = 0; k < words; k++)
445 		buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
446 }
447 
448 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
449 				       void *rx_buf, int words, int fs)
450 {
451 	u32 *buf_32 = rx_buf;
452 	int k;
453 
454 	for (k = 0; k < words; k++)
455 		put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
456 }
457 
458 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
459 				       void *rx_buf, int words, int fs)
460 {
461 	u32 *buf_32 = rx_buf;
462 	int k;
463 
464 	for (k = 0; k < words; k++)
465 		buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
466 }
467 
468 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
469 				       void *rx_buf, int words, int fs)
470 {
471 	u32 *buf_32 = rx_buf;
472 	int k;
473 
474 	for (k = 0; k < words; k++)
475 		put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
476 }
477 
478 static int sh_msiof_spi_setup(struct spi_device *spi)
479 {
480 	struct device_node	*np = spi->master->dev.of_node;
481 	struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
482 
483 	pm_runtime_get_sync(&p->pdev->dev);
484 
485 	if (!np) {
486 		/*
487 		 * Use spi->controller_data for CS (same strategy as spi_gpio),
488 		 * if any. otherwise let HW control CS
489 		 */
490 		spi->cs_gpio = (uintptr_t)spi->controller_data;
491 	}
492 
493 	/* Configure pins before deasserting CS */
494 	sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
495 				  !!(spi->mode & SPI_CPHA),
496 				  !!(spi->mode & SPI_3WIRE),
497 				  !!(spi->mode & SPI_LSB_FIRST),
498 				  !!(spi->mode & SPI_CS_HIGH));
499 
500 	if (spi->cs_gpio >= 0)
501 		gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
502 
503 
504 	pm_runtime_put_sync(&p->pdev->dev);
505 
506 	return 0;
507 }
508 
509 static int sh_msiof_prepare_message(struct spi_master *master,
510 				    struct spi_message *msg)
511 {
512 	struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
513 	const struct spi_device *spi = msg->spi;
514 
515 	/* Configure pins before asserting CS */
516 	sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
517 				  !!(spi->mode & SPI_CPHA),
518 				  !!(spi->mode & SPI_3WIRE),
519 				  !!(spi->mode & SPI_LSB_FIRST),
520 				  !!(spi->mode & SPI_CS_HIGH));
521 	return 0;
522 }
523 
524 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
525 {
526 	int ret;
527 
528 	/* setup clock and rx/tx signals */
529 	ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
530 	if (rx_buf && !ret)
531 		ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
532 	if (!ret)
533 		ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
534 
535 	/* start by setting frame bit */
536 	if (!ret)
537 		ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
538 
539 	return ret;
540 }
541 
542 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
543 {
544 	int ret;
545 
546 	/* shut down frame, rx/tx and clock signals */
547 	ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
548 	if (!ret)
549 		ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
550 	if (rx_buf && !ret)
551 		ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
552 	if (!ret)
553 		ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
554 
555 	return ret;
556 }
557 
558 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
559 				  void (*tx_fifo)(struct sh_msiof_spi_priv *,
560 						  const void *, int, int),
561 				  void (*rx_fifo)(struct sh_msiof_spi_priv *,
562 						  void *, int, int),
563 				  const void *tx_buf, void *rx_buf,
564 				  int words, int bits)
565 {
566 	int fifo_shift;
567 	int ret;
568 
569 	/* limit maximum word transfer to rx/tx fifo size */
570 	if (tx_buf)
571 		words = min_t(int, words, p->tx_fifo_size);
572 	if (rx_buf)
573 		words = min_t(int, words, p->rx_fifo_size);
574 
575 	/* the fifo contents need shifting */
576 	fifo_shift = 32 - bits;
577 
578 	/* default FIFO watermarks for PIO */
579 	sh_msiof_write(p, FCTR, 0);
580 
581 	/* setup msiof transfer mode registers */
582 	sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
583 	sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
584 
585 	/* write tx fifo */
586 	if (tx_buf)
587 		tx_fifo(p, tx_buf, words, fifo_shift);
588 
589 	reinit_completion(&p->done);
590 
591 	ret = sh_msiof_spi_start(p, rx_buf);
592 	if (ret) {
593 		dev_err(&p->pdev->dev, "failed to start hardware\n");
594 		goto stop_ier;
595 	}
596 
597 	/* wait for tx fifo to be emptied / rx fifo to be filled */
598 	ret = wait_for_completion_timeout(&p->done, HZ);
599 	if (!ret) {
600 		dev_err(&p->pdev->dev, "PIO timeout\n");
601 		ret = -ETIMEDOUT;
602 		goto stop_reset;
603 	}
604 
605 	/* read rx fifo */
606 	if (rx_buf)
607 		rx_fifo(p, rx_buf, words, fifo_shift);
608 
609 	/* clear status bits */
610 	sh_msiof_reset_str(p);
611 
612 	ret = sh_msiof_spi_stop(p, rx_buf);
613 	if (ret) {
614 		dev_err(&p->pdev->dev, "failed to shut down hardware\n");
615 		return ret;
616 	}
617 
618 	return words;
619 
620 stop_reset:
621 	sh_msiof_reset_str(p);
622 	sh_msiof_spi_stop(p, rx_buf);
623 stop_ier:
624 	sh_msiof_write(p, IER, 0);
625 	return ret;
626 }
627 
628 static void sh_msiof_dma_complete(void *arg)
629 {
630 	struct sh_msiof_spi_priv *p = arg;
631 
632 	sh_msiof_write(p, IER, 0);
633 	complete(&p->done);
634 }
635 
636 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
637 			     void *rx, unsigned int len)
638 {
639 	u32 ier_bits = 0;
640 	struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
641 	dma_cookie_t cookie;
642 	int ret;
643 
644 	/* First prepare and submit the DMA request(s), as this may fail */
645 	if (rx) {
646 		ier_bits |= IER_RDREQE | IER_RDMAE;
647 		desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
648 					p->rx_dma_addr, len, DMA_FROM_DEVICE,
649 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
650 		if (!desc_rx)
651 			return -EAGAIN;
652 
653 		desc_rx->callback = sh_msiof_dma_complete;
654 		desc_rx->callback_param = p;
655 		cookie = dmaengine_submit(desc_rx);
656 		if (dma_submit_error(cookie))
657 			return cookie;
658 	}
659 
660 	if (tx) {
661 		ier_bits |= IER_TDREQE | IER_TDMAE;
662 		dma_sync_single_for_device(p->master->dma_tx->device->dev,
663 					   p->tx_dma_addr, len, DMA_TO_DEVICE);
664 		desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
665 					p->tx_dma_addr, len, DMA_TO_DEVICE,
666 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
667 		if (!desc_tx) {
668 			ret = -EAGAIN;
669 			goto no_dma_tx;
670 		}
671 
672 		if (rx) {
673 			/* No callback */
674 			desc_tx->callback = NULL;
675 		} else {
676 			desc_tx->callback = sh_msiof_dma_complete;
677 			desc_tx->callback_param = p;
678 		}
679 		cookie = dmaengine_submit(desc_tx);
680 		if (dma_submit_error(cookie)) {
681 			ret = cookie;
682 			goto no_dma_tx;
683 		}
684 	}
685 
686 	/* 1 stage FIFO watermarks for DMA */
687 	sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
688 
689 	/* setup msiof transfer mode registers (32-bit words) */
690 	sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
691 
692 	sh_msiof_write(p, IER, ier_bits);
693 
694 	reinit_completion(&p->done);
695 
696 	/* Now start DMA */
697 	if (rx)
698 		dma_async_issue_pending(p->master->dma_rx);
699 	if (tx)
700 		dma_async_issue_pending(p->master->dma_tx);
701 
702 	ret = sh_msiof_spi_start(p, rx);
703 	if (ret) {
704 		dev_err(&p->pdev->dev, "failed to start hardware\n");
705 		goto stop_dma;
706 	}
707 
708 	/* wait for tx fifo to be emptied / rx fifo to be filled */
709 	ret = wait_for_completion_timeout(&p->done, HZ);
710 	if (!ret) {
711 		dev_err(&p->pdev->dev, "DMA timeout\n");
712 		ret = -ETIMEDOUT;
713 		goto stop_reset;
714 	}
715 
716 	/* clear status bits */
717 	sh_msiof_reset_str(p);
718 
719 	ret = sh_msiof_spi_stop(p, rx);
720 	if (ret) {
721 		dev_err(&p->pdev->dev, "failed to shut down hardware\n");
722 		return ret;
723 	}
724 
725 	if (rx)
726 		dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
727 					p->rx_dma_addr, len,
728 					DMA_FROM_DEVICE);
729 
730 	return 0;
731 
732 stop_reset:
733 	sh_msiof_reset_str(p);
734 	sh_msiof_spi_stop(p, rx);
735 stop_dma:
736 	if (tx)
737 		dmaengine_terminate_all(p->master->dma_tx);
738 no_dma_tx:
739 	if (rx)
740 		dmaengine_terminate_all(p->master->dma_rx);
741 	sh_msiof_write(p, IER, 0);
742 	return ret;
743 }
744 
745 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
746 {
747 	/* src or dst can be unaligned, but not both */
748 	if ((unsigned long)src & 3) {
749 		while (words--) {
750 			*dst++ = swab32(get_unaligned(src));
751 			src++;
752 		}
753 	} else if ((unsigned long)dst & 3) {
754 		while (words--) {
755 			put_unaligned(swab32(*src++), dst);
756 			dst++;
757 		}
758 	} else {
759 		while (words--)
760 			*dst++ = swab32(*src++);
761 	}
762 }
763 
764 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
765 {
766 	/* src or dst can be unaligned, but not both */
767 	if ((unsigned long)src & 3) {
768 		while (words--) {
769 			*dst++ = swahw32(get_unaligned(src));
770 			src++;
771 		}
772 	} else if ((unsigned long)dst & 3) {
773 		while (words--) {
774 			put_unaligned(swahw32(*src++), dst);
775 			dst++;
776 		}
777 	} else {
778 		while (words--)
779 			*dst++ = swahw32(*src++);
780 	}
781 }
782 
783 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
784 {
785 	memcpy(dst, src, words * 4);
786 }
787 
788 static int sh_msiof_transfer_one(struct spi_master *master,
789 				 struct spi_device *spi,
790 				 struct spi_transfer *t)
791 {
792 	struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
793 	void (*copy32)(u32 *, const u32 *, unsigned int);
794 	void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
795 	void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
796 	const void *tx_buf = t->tx_buf;
797 	void *rx_buf = t->rx_buf;
798 	unsigned int len = t->len;
799 	unsigned int bits = t->bits_per_word;
800 	unsigned int bytes_per_word;
801 	unsigned int words;
802 	int n;
803 	bool swab;
804 	int ret;
805 
806 	/* setup clocks (clock already enabled in chipselect()) */
807 	sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
808 
809 	while (master->dma_tx && len > 15) {
810 		/*
811 		 *  DMA supports 32-bit words only, hence pack 8-bit and 16-bit
812 		 *  words, with byte resp. word swapping.
813 		 */
814 		unsigned int l = min(len, MAX_WDLEN * 4);
815 
816 		if (bits <= 8) {
817 			if (l & 3)
818 				break;
819 			copy32 = copy_bswap32;
820 		} else if (bits <= 16) {
821 			if (l & 1)
822 				break;
823 			copy32 = copy_wswap32;
824 		} else {
825 			copy32 = copy_plain32;
826 		}
827 
828 		if (tx_buf)
829 			copy32(p->tx_dma_page, tx_buf, l / 4);
830 
831 		ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
832 		if (ret == -EAGAIN) {
833 			pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
834 				     dev_driver_string(&p->pdev->dev),
835 				     dev_name(&p->pdev->dev));
836 			break;
837 		}
838 		if (ret)
839 			return ret;
840 
841 		if (rx_buf) {
842 			copy32(rx_buf, p->rx_dma_page, l / 4);
843 			rx_buf += l;
844 		}
845 		if (tx_buf)
846 			tx_buf += l;
847 
848 		len -= l;
849 		if (!len)
850 			return 0;
851 	}
852 
853 	if (bits <= 8 && len > 15 && !(len & 3)) {
854 		bits = 32;
855 		swab = true;
856 	} else {
857 		swab = false;
858 	}
859 
860 	/* setup bytes per word and fifo read/write functions */
861 	if (bits <= 8) {
862 		bytes_per_word = 1;
863 		tx_fifo = sh_msiof_spi_write_fifo_8;
864 		rx_fifo = sh_msiof_spi_read_fifo_8;
865 	} else if (bits <= 16) {
866 		bytes_per_word = 2;
867 		if ((unsigned long)tx_buf & 0x01)
868 			tx_fifo = sh_msiof_spi_write_fifo_16u;
869 		else
870 			tx_fifo = sh_msiof_spi_write_fifo_16;
871 
872 		if ((unsigned long)rx_buf & 0x01)
873 			rx_fifo = sh_msiof_spi_read_fifo_16u;
874 		else
875 			rx_fifo = sh_msiof_spi_read_fifo_16;
876 	} else if (swab) {
877 		bytes_per_word = 4;
878 		if ((unsigned long)tx_buf & 0x03)
879 			tx_fifo = sh_msiof_spi_write_fifo_s32u;
880 		else
881 			tx_fifo = sh_msiof_spi_write_fifo_s32;
882 
883 		if ((unsigned long)rx_buf & 0x03)
884 			rx_fifo = sh_msiof_spi_read_fifo_s32u;
885 		else
886 			rx_fifo = sh_msiof_spi_read_fifo_s32;
887 	} else {
888 		bytes_per_word = 4;
889 		if ((unsigned long)tx_buf & 0x03)
890 			tx_fifo = sh_msiof_spi_write_fifo_32u;
891 		else
892 			tx_fifo = sh_msiof_spi_write_fifo_32;
893 
894 		if ((unsigned long)rx_buf & 0x03)
895 			rx_fifo = sh_msiof_spi_read_fifo_32u;
896 		else
897 			rx_fifo = sh_msiof_spi_read_fifo_32;
898 	}
899 
900 	/* transfer in fifo sized chunks */
901 	words = len / bytes_per_word;
902 
903 	while (words > 0) {
904 		n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
905 					   words, bits);
906 		if (n < 0)
907 			return n;
908 
909 		if (tx_buf)
910 			tx_buf += n * bytes_per_word;
911 		if (rx_buf)
912 			rx_buf += n * bytes_per_word;
913 		words -= n;
914 	}
915 
916 	return 0;
917 }
918 
919 static const struct sh_msiof_chipdata sh_data = {
920 	.tx_fifo_size = 64,
921 	.rx_fifo_size = 64,
922 	.master_flags = 0,
923 };
924 
925 static const struct sh_msiof_chipdata r8a779x_data = {
926 	.tx_fifo_size = 64,
927 	.rx_fifo_size = 256,
928 	.master_flags = SPI_MASTER_MUST_TX,
929 };
930 
931 static const struct of_device_id sh_msiof_match[] = {
932 	{ .compatible = "renesas,sh-msiof",        .data = &sh_data },
933 	{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
934 	{ .compatible = "renesas,msiof-r8a7790",   .data = &r8a779x_data },
935 	{ .compatible = "renesas,msiof-r8a7791",   .data = &r8a779x_data },
936 	{ .compatible = "renesas,msiof-r8a7792",   .data = &r8a779x_data },
937 	{ .compatible = "renesas,msiof-r8a7793",   .data = &r8a779x_data },
938 	{ .compatible = "renesas,msiof-r8a7794",   .data = &r8a779x_data },
939 	{},
940 };
941 MODULE_DEVICE_TABLE(of, sh_msiof_match);
942 
943 #ifdef CONFIG_OF
944 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
945 {
946 	struct sh_msiof_spi_info *info;
947 	struct device_node *np = dev->of_node;
948 	u32 num_cs = 1;
949 
950 	info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
951 	if (!info)
952 		return NULL;
953 
954 	/* Parse the MSIOF properties */
955 	of_property_read_u32(np, "num-cs", &num_cs);
956 	of_property_read_u32(np, "renesas,tx-fifo-size",
957 					&info->tx_fifo_override);
958 	of_property_read_u32(np, "renesas,rx-fifo-size",
959 					&info->rx_fifo_override);
960 
961 	info->num_chipselect = num_cs;
962 
963 	return info;
964 }
965 #else
966 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
967 {
968 	return NULL;
969 }
970 #endif
971 
972 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
973 	enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
974 {
975 	dma_cap_mask_t mask;
976 	struct dma_chan *chan;
977 	struct dma_slave_config cfg;
978 	int ret;
979 
980 	dma_cap_zero(mask);
981 	dma_cap_set(DMA_SLAVE, mask);
982 
983 	chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
984 				(void *)(unsigned long)id, dev,
985 				dir == DMA_MEM_TO_DEV ? "tx" : "rx");
986 	if (!chan) {
987 		dev_warn(dev, "dma_request_slave_channel_compat failed\n");
988 		return NULL;
989 	}
990 
991 	memset(&cfg, 0, sizeof(cfg));
992 	cfg.slave_id = id;
993 	cfg.direction = dir;
994 	if (dir == DMA_MEM_TO_DEV) {
995 		cfg.dst_addr = port_addr;
996 		cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
997 	} else {
998 		cfg.src_addr = port_addr;
999 		cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1000 	}
1001 
1002 	ret = dmaengine_slave_config(chan, &cfg);
1003 	if (ret) {
1004 		dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1005 		dma_release_channel(chan);
1006 		return NULL;
1007 	}
1008 
1009 	return chan;
1010 }
1011 
1012 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1013 {
1014 	struct platform_device *pdev = p->pdev;
1015 	struct device *dev = &pdev->dev;
1016 	const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1017 	unsigned int dma_tx_id, dma_rx_id;
1018 	const struct resource *res;
1019 	struct spi_master *master;
1020 	struct device *tx_dev, *rx_dev;
1021 
1022 	if (dev->of_node) {
1023 		/* In the OF case we will get the slave IDs from the DT */
1024 		dma_tx_id = 0;
1025 		dma_rx_id = 0;
1026 	} else if (info && info->dma_tx_id && info->dma_rx_id) {
1027 		dma_tx_id = info->dma_tx_id;
1028 		dma_rx_id = info->dma_rx_id;
1029 	} else {
1030 		/* The driver assumes no error */
1031 		return 0;
1032 	}
1033 
1034 	/* The DMA engine uses the second register set, if present */
1035 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1036 	if (!res)
1037 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1038 
1039 	master = p->master;
1040 	master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1041 						   dma_tx_id,
1042 						   res->start + TFDR);
1043 	if (!master->dma_tx)
1044 		return -ENODEV;
1045 
1046 	master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1047 						   dma_rx_id,
1048 						   res->start + RFDR);
1049 	if (!master->dma_rx)
1050 		goto free_tx_chan;
1051 
1052 	p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1053 	if (!p->tx_dma_page)
1054 		goto free_rx_chan;
1055 
1056 	p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1057 	if (!p->rx_dma_page)
1058 		goto free_tx_page;
1059 
1060 	tx_dev = master->dma_tx->device->dev;
1061 	p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1062 					DMA_TO_DEVICE);
1063 	if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1064 		goto free_rx_page;
1065 
1066 	rx_dev = master->dma_rx->device->dev;
1067 	p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1068 					DMA_FROM_DEVICE);
1069 	if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1070 		goto unmap_tx_page;
1071 
1072 	dev_info(dev, "DMA available");
1073 	return 0;
1074 
1075 unmap_tx_page:
1076 	dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1077 free_rx_page:
1078 	free_page((unsigned long)p->rx_dma_page);
1079 free_tx_page:
1080 	free_page((unsigned long)p->tx_dma_page);
1081 free_rx_chan:
1082 	dma_release_channel(master->dma_rx);
1083 free_tx_chan:
1084 	dma_release_channel(master->dma_tx);
1085 	master->dma_tx = NULL;
1086 	return -ENODEV;
1087 }
1088 
1089 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1090 {
1091 	struct spi_master *master = p->master;
1092 	struct device *dev;
1093 
1094 	if (!master->dma_tx)
1095 		return;
1096 
1097 	dev = &p->pdev->dev;
1098 	dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1099 			 PAGE_SIZE, DMA_FROM_DEVICE);
1100 	dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1101 			 PAGE_SIZE, DMA_TO_DEVICE);
1102 	free_page((unsigned long)p->rx_dma_page);
1103 	free_page((unsigned long)p->tx_dma_page);
1104 	dma_release_channel(master->dma_rx);
1105 	dma_release_channel(master->dma_tx);
1106 }
1107 
1108 static int sh_msiof_spi_probe(struct platform_device *pdev)
1109 {
1110 	struct resource	*r;
1111 	struct spi_master *master;
1112 	const struct of_device_id *of_id;
1113 	struct sh_msiof_spi_priv *p;
1114 	int i;
1115 	int ret;
1116 
1117 	master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
1118 	if (master == NULL) {
1119 		dev_err(&pdev->dev, "failed to allocate spi master\n");
1120 		return -ENOMEM;
1121 	}
1122 
1123 	p = spi_master_get_devdata(master);
1124 
1125 	platform_set_drvdata(pdev, p);
1126 	p->master = master;
1127 
1128 	of_id = of_match_device(sh_msiof_match, &pdev->dev);
1129 	if (of_id) {
1130 		p->chipdata = of_id->data;
1131 		p->info = sh_msiof_spi_parse_dt(&pdev->dev);
1132 	} else {
1133 		p->chipdata = (const void *)pdev->id_entry->driver_data;
1134 		p->info = dev_get_platdata(&pdev->dev);
1135 	}
1136 
1137 	if (!p->info) {
1138 		dev_err(&pdev->dev, "failed to obtain device info\n");
1139 		ret = -ENXIO;
1140 		goto err1;
1141 	}
1142 
1143 	init_completion(&p->done);
1144 
1145 	p->clk = devm_clk_get(&pdev->dev, NULL);
1146 	if (IS_ERR(p->clk)) {
1147 		dev_err(&pdev->dev, "cannot get clock\n");
1148 		ret = PTR_ERR(p->clk);
1149 		goto err1;
1150 	}
1151 
1152 	i = platform_get_irq(pdev, 0);
1153 	if (i < 0) {
1154 		dev_err(&pdev->dev, "cannot get platform IRQ\n");
1155 		ret = -ENOENT;
1156 		goto err1;
1157 	}
1158 
1159 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1160 	p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1161 	if (IS_ERR(p->mapbase)) {
1162 		ret = PTR_ERR(p->mapbase);
1163 		goto err1;
1164 	}
1165 
1166 	ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1167 			       dev_name(&pdev->dev), p);
1168 	if (ret) {
1169 		dev_err(&pdev->dev, "unable to request irq\n");
1170 		goto err1;
1171 	}
1172 
1173 	p->pdev = pdev;
1174 	pm_runtime_enable(&pdev->dev);
1175 
1176 	/* Platform data may override FIFO sizes */
1177 	p->tx_fifo_size = p->chipdata->tx_fifo_size;
1178 	p->rx_fifo_size = p->chipdata->rx_fifo_size;
1179 	if (p->info->tx_fifo_override)
1180 		p->tx_fifo_size = p->info->tx_fifo_override;
1181 	if (p->info->rx_fifo_override)
1182 		p->rx_fifo_size = p->info->rx_fifo_override;
1183 
1184 	/* init master code */
1185 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1186 	master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1187 	master->flags = p->chipdata->master_flags;
1188 	master->bus_num = pdev->id;
1189 	master->dev.of_node = pdev->dev.of_node;
1190 	master->num_chipselect = p->info->num_chipselect;
1191 	master->setup = sh_msiof_spi_setup;
1192 	master->prepare_message = sh_msiof_prepare_message;
1193 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1194 	master->auto_runtime_pm = true;
1195 	master->transfer_one = sh_msiof_transfer_one;
1196 
1197 	ret = sh_msiof_request_dma(p);
1198 	if (ret < 0)
1199 		dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1200 
1201 	ret = devm_spi_register_master(&pdev->dev, master);
1202 	if (ret < 0) {
1203 		dev_err(&pdev->dev, "spi_register_master error.\n");
1204 		goto err2;
1205 	}
1206 
1207 	return 0;
1208 
1209  err2:
1210 	sh_msiof_release_dma(p);
1211 	pm_runtime_disable(&pdev->dev);
1212  err1:
1213 	spi_master_put(master);
1214 	return ret;
1215 }
1216 
1217 static int sh_msiof_spi_remove(struct platform_device *pdev)
1218 {
1219 	struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1220 
1221 	sh_msiof_release_dma(p);
1222 	pm_runtime_disable(&pdev->dev);
1223 	return 0;
1224 }
1225 
1226 static struct platform_device_id spi_driver_ids[] = {
1227 	{ "spi_sh_msiof",	(kernel_ulong_t)&sh_data },
1228 	{ "spi_r8a7790_msiof",	(kernel_ulong_t)&r8a779x_data },
1229 	{ "spi_r8a7791_msiof",	(kernel_ulong_t)&r8a779x_data },
1230 	{ "spi_r8a7792_msiof",	(kernel_ulong_t)&r8a779x_data },
1231 	{ "spi_r8a7793_msiof",	(kernel_ulong_t)&r8a779x_data },
1232 	{ "spi_r8a7794_msiof",	(kernel_ulong_t)&r8a779x_data },
1233 	{},
1234 };
1235 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1236 
1237 static struct platform_driver sh_msiof_spi_drv = {
1238 	.probe		= sh_msiof_spi_probe,
1239 	.remove		= sh_msiof_spi_remove,
1240 	.id_table	= spi_driver_ids,
1241 	.driver		= {
1242 		.name		= "spi_sh_msiof",
1243 		.of_match_table = of_match_ptr(sh_msiof_match),
1244 	},
1245 };
1246 module_platform_driver(sh_msiof_spi_drv);
1247 
1248 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1249 MODULE_AUTHOR("Magnus Damm");
1250 MODULE_LICENSE("GPL v2");
1251 MODULE_ALIAS("platform:spi_sh_msiof");
1252