1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH MSIOF SPI Controller Interface 4 * 5 * Copyright (c) 2009 Magnus Damm 6 * Copyright (C) 2014 Renesas Electronics Corporation 7 * Copyright (C) 2014-2017 Glider bvba 8 */ 9 10 #include <linux/bitmap.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/err.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/sh_dma.h> 27 28 #include <linux/spi/sh_msiof.h> 29 #include <linux/spi/spi.h> 30 31 #include <asm/unaligned.h> 32 33 struct sh_msiof_chipdata { 34 u32 bits_per_word_mask; 35 u16 tx_fifo_size; 36 u16 rx_fifo_size; 37 u16 ctlr_flags; 38 u16 min_div_pow; 39 }; 40 41 struct sh_msiof_spi_priv { 42 struct spi_controller *ctlr; 43 void __iomem *mapbase; 44 struct clk *clk; 45 struct platform_device *pdev; 46 struct sh_msiof_spi_info *info; 47 struct completion done; 48 struct completion done_txdma; 49 unsigned int tx_fifo_size; 50 unsigned int rx_fifo_size; 51 unsigned int min_div_pow; 52 void *tx_dma_page; 53 void *rx_dma_page; 54 dma_addr_t tx_dma_addr; 55 dma_addr_t rx_dma_addr; 56 bool native_cs_inited; 57 bool native_cs_high; 58 bool slave_aborted; 59 }; 60 61 #define MAX_SS 3 /* Maximum number of native chip selects */ 62 63 #define SITMDR1 0x00 /* Transmit Mode Register 1 */ 64 #define SITMDR2 0x04 /* Transmit Mode Register 2 */ 65 #define SITMDR3 0x08 /* Transmit Mode Register 3 */ 66 #define SIRMDR1 0x10 /* Receive Mode Register 1 */ 67 #define SIRMDR2 0x14 /* Receive Mode Register 2 */ 68 #define SIRMDR3 0x18 /* Receive Mode Register 3 */ 69 #define SITSCR 0x20 /* Transmit Clock Select Register */ 70 #define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ 71 #define SICTR 0x28 /* Control Register */ 72 #define SIFCTR 0x30 /* FIFO Control Register */ 73 #define SISTR 0x40 /* Status Register */ 74 #define SIIER 0x44 /* Interrupt Enable Register */ 75 #define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ 76 #define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ 77 #define SITFDR 0x50 /* Transmit FIFO Data Register */ 78 #define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ 79 #define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ 80 #define SIRFDR 0x60 /* Receive FIFO Data Register */ 81 82 /* SITMDR1 and SIRMDR1 */ 83 #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */ 84 #define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */ 85 #define SIMDR1_SYNCMD_SPI (2 << 28) /* Level mode/SPI */ 86 #define SIMDR1_SYNCMD_LR (3 << 28) /* L/R mode */ 87 #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ 88 #define SIMDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ 89 #define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */ 90 #define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */ 91 #define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */ 92 #define SIMDR1_FLD_SHIFT 2 93 #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */ 94 /* SITMDR1 */ 95 #define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */ 96 #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */ 97 #define SITMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ 98 99 /* SITMDR2 and SIRMDR2 */ 100 #define SIMDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ 101 #define SIMDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ 102 #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */ 103 104 /* SITSCR and SIRSCR */ 105 #define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */ 106 #define SISCR_BRPS(i) (((i) - 1) << 8) 107 #define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ 108 #define SISCR_BRDV_DIV_2 0 109 #define SISCR_BRDV_DIV_4 1 110 #define SISCR_BRDV_DIV_8 2 111 #define SISCR_BRDV_DIV_16 3 112 #define SISCR_BRDV_DIV_32 4 113 #define SISCR_BRDV_DIV_1 7 114 115 /* SICTR */ 116 #define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */ 117 #define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */ 118 #define SICTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ 119 #define SICTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */ 120 #define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */ 121 #define SICTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ 122 #define SICTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ 123 #define SICTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ 124 #define SICTR_TXDIZ_MASK GENMASK(23, 22) /* Pin Output When TX is Disabled */ 125 #define SICTR_TXDIZ_LOW (0 << 22) /* 0 */ 126 #define SICTR_TXDIZ_HIGH (1 << 22) /* 1 */ 127 #define SICTR_TXDIZ_HIZ (2 << 22) /* High-impedance */ 128 #define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */ 129 #define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */ 130 #define SICTR_TXE BIT(9) /* Transmit Enable */ 131 #define SICTR_RXE BIT(8) /* Receive Enable */ 132 #define SICTR_TXRST BIT(1) /* Transmit Reset */ 133 #define SICTR_RXRST BIT(0) /* Receive Reset */ 134 135 /* SIFCTR */ 136 #define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */ 137 #define SIFCTR_TFWM_64 (0 << 29) /* Transfer Request when 64 empty stages */ 138 #define SIFCTR_TFWM_32 (1 << 29) /* Transfer Request when 32 empty stages */ 139 #define SIFCTR_TFWM_24 (2 << 29) /* Transfer Request when 24 empty stages */ 140 #define SIFCTR_TFWM_16 (3 << 29) /* Transfer Request when 16 empty stages */ 141 #define SIFCTR_TFWM_12 (4 << 29) /* Transfer Request when 12 empty stages */ 142 #define SIFCTR_TFWM_8 (5 << 29) /* Transfer Request when 8 empty stages */ 143 #define SIFCTR_TFWM_4 (6 << 29) /* Transfer Request when 4 empty stages */ 144 #define SIFCTR_TFWM_1 (7 << 29) /* Transfer Request when 1 empty stage */ 145 #define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */ 146 #define SIFCTR_TFUA_SHIFT 20 147 #define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT) 148 #define SIFCTR_RFWM_MASK GENMASK(15, 13) /* Receive FIFO Watermark */ 149 #define SIFCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */ 150 #define SIFCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */ 151 #define SIFCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */ 152 #define SIFCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */ 153 #define SIFCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */ 154 #define SIFCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */ 155 #define SIFCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */ 156 #define SIFCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */ 157 #define SIFCTR_RFUA_MASK GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */ 158 #define SIFCTR_RFUA_SHIFT 4 159 #define SIFCTR_RFUA(i) ((i) << SIFCTR_RFUA_SHIFT) 160 161 /* SISTR */ 162 #define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */ 163 #define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */ 164 #define SISTR_TEOF BIT(23) /* Frame Transmission End */ 165 #define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */ 166 #define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */ 167 #define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */ 168 #define SISTR_RFFUL BIT(13) /* Receive FIFO Full */ 169 #define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */ 170 #define SISTR_REOF BIT(7) /* Frame Reception End */ 171 #define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */ 172 #define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */ 173 #define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */ 174 175 /* SIIER */ 176 #define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */ 177 #define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */ 178 #define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */ 179 #define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */ 180 #define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */ 181 #define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */ 182 #define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */ 183 #define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */ 184 #define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */ 185 #define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */ 186 #define SIIER_REOFE BIT(7) /* Frame Reception End Enable */ 187 #define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */ 188 #define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */ 189 #define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */ 190 191 192 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) 193 { 194 switch (reg_offs) { 195 case SITSCR: 196 case SIRSCR: 197 return ioread16(p->mapbase + reg_offs); 198 default: 199 return ioread32(p->mapbase + reg_offs); 200 } 201 } 202 203 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, 204 u32 value) 205 { 206 switch (reg_offs) { 207 case SITSCR: 208 case SIRSCR: 209 iowrite16(value, p->mapbase + reg_offs); 210 break; 211 default: 212 iowrite32(value, p->mapbase + reg_offs); 213 break; 214 } 215 } 216 217 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, 218 u32 clr, u32 set) 219 { 220 u32 mask = clr | set; 221 u32 data; 222 223 data = sh_msiof_read(p, SICTR); 224 data &= ~clr; 225 data |= set; 226 sh_msiof_write(p, SICTR, data); 227 228 return readl_poll_timeout_atomic(p->mapbase + SICTR, data, 229 (data & mask) == set, 1, 100); 230 } 231 232 static irqreturn_t sh_msiof_spi_irq(int irq, void *data) 233 { 234 struct sh_msiof_spi_priv *p = data; 235 236 /* just disable the interrupt and wake up */ 237 sh_msiof_write(p, SIIER, 0); 238 complete(&p->done); 239 240 return IRQ_HANDLED; 241 } 242 243 static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p) 244 { 245 u32 mask = SICTR_TXRST | SICTR_RXRST; 246 u32 data; 247 248 data = sh_msiof_read(p, SICTR); 249 data |= mask; 250 sh_msiof_write(p, SICTR, data); 251 252 readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1, 253 100); 254 } 255 256 static const u32 sh_msiof_spi_div_array[] = { 257 SISCR_BRDV_DIV_1, SISCR_BRDV_DIV_2, SISCR_BRDV_DIV_4, 258 SISCR_BRDV_DIV_8, SISCR_BRDV_DIV_16, SISCR_BRDV_DIV_32, 259 }; 260 261 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 262 unsigned long parent_rate, u32 spi_hz) 263 { 264 unsigned long div; 265 u32 brps, scr; 266 unsigned int div_pow = p->min_div_pow; 267 268 if (!spi_hz || !parent_rate) { 269 WARN(1, "Invalid clock rate parameters %lu and %u\n", 270 parent_rate, spi_hz); 271 return; 272 } 273 274 div = DIV_ROUND_UP(parent_rate, spi_hz); 275 if (div <= 1024) { 276 /* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */ 277 if (!div_pow && div <= 32 && div > 2) 278 div_pow = 1; 279 280 if (div_pow) 281 brps = (div + 1) >> div_pow; 282 else 283 brps = div; 284 285 for (; brps > 32; div_pow++) 286 brps = (brps + 1) >> 1; 287 } else { 288 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */ 289 dev_err(&p->pdev->dev, 290 "Requested SPI transfer rate %d is too low\n", spi_hz); 291 div_pow = 5; 292 brps = 32; 293 } 294 295 scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps); 296 sh_msiof_write(p, SITSCR, scr); 297 if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) 298 sh_msiof_write(p, SIRSCR, scr); 299 } 300 301 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl) 302 { 303 /* 304 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl 305 * b'000 : 0 306 * b'001 : 100 307 * b'010 : 200 308 * b'011 (SYNCDL only) : 300 309 * b'101 : 50 310 * b'110 : 150 311 */ 312 if (dtdl_or_syncdl % 100) 313 return dtdl_or_syncdl / 100 + 5; 314 else 315 return dtdl_or_syncdl / 100; 316 } 317 318 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) 319 { 320 u32 val; 321 322 if (!p->info) 323 return 0; 324 325 /* check if DTDL and SYNCDL is allowed value */ 326 if (p->info->dtdl > 200 || p->info->syncdl > 300) { 327 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n"); 328 return 0; 329 } 330 331 /* check if the sum of DTDL and SYNCDL becomes an integer value */ 332 if ((p->info->dtdl + p->info->syncdl) % 100) { 333 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n"); 334 return 0; 335 } 336 337 val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT; 338 val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT; 339 340 return val; 341 } 342 343 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, 344 u32 cpol, u32 cpha, 345 u32 tx_hi_z, u32 lsb_first, u32 cs_high) 346 { 347 u32 tmp; 348 int edge; 349 350 /* 351 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG 352 * 0 0 10 10 1 1 353 * 0 1 10 10 0 0 354 * 1 0 11 11 0 0 355 * 1 1 11 11 1 1 356 */ 357 tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP; 358 tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT; 359 tmp |= lsb_first << SIMDR1_BITLSB_SHIFT; 360 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); 361 if (spi_controller_is_slave(p->ctlr)) { 362 sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON); 363 } else { 364 sh_msiof_write(p, SITMDR1, 365 tmp | SIMDR1_TRMD | SITMDR1_PCON | 366 (ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT); 367 } 368 if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) { 369 /* These bits are reserved if RX needs TX */ 370 tmp &= ~0x0000ffff; 371 } 372 sh_msiof_write(p, SIRMDR1, tmp); 373 374 tmp = 0; 375 tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT; 376 tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT; 377 378 edge = cpol ^ !cpha; 379 380 tmp |= edge << SICTR_TEDG_SHIFT; 381 tmp |= edge << SICTR_REDG_SHIFT; 382 tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW; 383 sh_msiof_write(p, SICTR, tmp); 384 } 385 386 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, 387 const void *tx_buf, void *rx_buf, 388 u32 bits, u32 words) 389 { 390 u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words); 391 392 if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) 393 sh_msiof_write(p, SITMDR2, dr2); 394 else 395 sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1); 396 397 if (rx_buf) 398 sh_msiof_write(p, SIRMDR2, dr2); 399 } 400 401 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) 402 { 403 sh_msiof_write(p, SISTR, 404 sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ)); 405 } 406 407 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, 408 const void *tx_buf, int words, int fs) 409 { 410 const u8 *buf_8 = tx_buf; 411 int k; 412 413 for (k = 0; k < words; k++) 414 sh_msiof_write(p, SITFDR, buf_8[k] << fs); 415 } 416 417 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, 418 const void *tx_buf, int words, int fs) 419 { 420 const u16 *buf_16 = tx_buf; 421 int k; 422 423 for (k = 0; k < words; k++) 424 sh_msiof_write(p, SITFDR, buf_16[k] << fs); 425 } 426 427 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, 428 const void *tx_buf, int words, int fs) 429 { 430 const u16 *buf_16 = tx_buf; 431 int k; 432 433 for (k = 0; k < words; k++) 434 sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs); 435 } 436 437 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, 438 const void *tx_buf, int words, int fs) 439 { 440 const u32 *buf_32 = tx_buf; 441 int k; 442 443 for (k = 0; k < words; k++) 444 sh_msiof_write(p, SITFDR, buf_32[k] << fs); 445 } 446 447 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, 448 const void *tx_buf, int words, int fs) 449 { 450 const u32 *buf_32 = tx_buf; 451 int k; 452 453 for (k = 0; k < words; k++) 454 sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs); 455 } 456 457 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, 458 const void *tx_buf, int words, int fs) 459 { 460 const u32 *buf_32 = tx_buf; 461 int k; 462 463 for (k = 0; k < words; k++) 464 sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs)); 465 } 466 467 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, 468 const void *tx_buf, int words, int fs) 469 { 470 const u32 *buf_32 = tx_buf; 471 int k; 472 473 for (k = 0; k < words; k++) 474 sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs)); 475 } 476 477 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, 478 void *rx_buf, int words, int fs) 479 { 480 u8 *buf_8 = rx_buf; 481 int k; 482 483 for (k = 0; k < words; k++) 484 buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs; 485 } 486 487 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, 488 void *rx_buf, int words, int fs) 489 { 490 u16 *buf_16 = rx_buf; 491 int k; 492 493 for (k = 0; k < words; k++) 494 buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs; 495 } 496 497 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, 498 void *rx_buf, int words, int fs) 499 { 500 u16 *buf_16 = rx_buf; 501 int k; 502 503 for (k = 0; k < words; k++) 504 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]); 505 } 506 507 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, 508 void *rx_buf, int words, int fs) 509 { 510 u32 *buf_32 = rx_buf; 511 int k; 512 513 for (k = 0; k < words; k++) 514 buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs; 515 } 516 517 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, 518 void *rx_buf, int words, int fs) 519 { 520 u32 *buf_32 = rx_buf; 521 int k; 522 523 for (k = 0; k < words; k++) 524 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]); 525 } 526 527 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, 528 void *rx_buf, int words, int fs) 529 { 530 u32 *buf_32 = rx_buf; 531 int k; 532 533 for (k = 0; k < words; k++) 534 buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs); 535 } 536 537 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, 538 void *rx_buf, int words, int fs) 539 { 540 u32 *buf_32 = rx_buf; 541 int k; 542 543 for (k = 0; k < words; k++) 544 put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]); 545 } 546 547 static int sh_msiof_spi_setup(struct spi_device *spi) 548 { 549 struct sh_msiof_spi_priv *p = 550 spi_controller_get_devdata(spi->controller); 551 u32 clr, set, tmp; 552 553 if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr)) 554 return 0; 555 556 if (p->native_cs_inited && 557 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH))) 558 return 0; 559 560 /* Configure native chip select mode/polarity early */ 561 clr = SIMDR1_SYNCMD_MASK; 562 set = SIMDR1_SYNCMD_SPI; 563 if (spi->mode & SPI_CS_HIGH) 564 clr |= BIT(SIMDR1_SYNCAC_SHIFT); 565 else 566 set |= BIT(SIMDR1_SYNCAC_SHIFT); 567 pm_runtime_get_sync(&p->pdev->dev); 568 tmp = sh_msiof_read(p, SITMDR1) & ~clr; 569 sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON); 570 tmp = sh_msiof_read(p, SIRMDR1) & ~clr; 571 sh_msiof_write(p, SIRMDR1, tmp | set); 572 pm_runtime_put(&p->pdev->dev); 573 p->native_cs_high = spi->mode & SPI_CS_HIGH; 574 p->native_cs_inited = true; 575 return 0; 576 } 577 578 static int sh_msiof_prepare_message(struct spi_controller *ctlr, 579 struct spi_message *msg) 580 { 581 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); 582 const struct spi_device *spi = msg->spi; 583 u32 ss, cs_high; 584 585 /* Configure pins before asserting CS */ 586 if (spi->cs_gpiod) { 587 ss = ctlr->unused_native_cs; 588 cs_high = p->native_cs_high; 589 } else { 590 ss = spi->chip_select; 591 cs_high = !!(spi->mode & SPI_CS_HIGH); 592 } 593 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL), 594 !!(spi->mode & SPI_CPHA), 595 !!(spi->mode & SPI_3WIRE), 596 !!(spi->mode & SPI_LSB_FIRST), cs_high); 597 return 0; 598 } 599 600 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) 601 { 602 bool slave = spi_controller_is_slave(p->ctlr); 603 int ret = 0; 604 605 /* setup clock and rx/tx signals */ 606 if (!slave) 607 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE); 608 if (rx_buf && !ret) 609 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE); 610 if (!ret) 611 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE); 612 613 /* start by setting frame bit */ 614 if (!ret && !slave) 615 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE); 616 617 return ret; 618 } 619 620 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) 621 { 622 bool slave = spi_controller_is_slave(p->ctlr); 623 int ret = 0; 624 625 /* shut down frame, rx/tx and clock signals */ 626 if (!slave) 627 ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0); 628 if (!ret) 629 ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0); 630 if (rx_buf && !ret) 631 ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0); 632 if (!ret && !slave) 633 ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0); 634 635 return ret; 636 } 637 638 static int sh_msiof_slave_abort(struct spi_controller *ctlr) 639 { 640 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); 641 642 p->slave_aborted = true; 643 complete(&p->done); 644 complete(&p->done_txdma); 645 return 0; 646 } 647 648 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p, 649 struct completion *x) 650 { 651 if (spi_controller_is_slave(p->ctlr)) { 652 if (wait_for_completion_interruptible(x) || 653 p->slave_aborted) { 654 dev_dbg(&p->pdev->dev, "interrupted\n"); 655 return -EINTR; 656 } 657 } else { 658 if (!wait_for_completion_timeout(x, HZ)) { 659 dev_err(&p->pdev->dev, "timeout\n"); 660 return -ETIMEDOUT; 661 } 662 } 663 664 return 0; 665 } 666 667 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, 668 void (*tx_fifo)(struct sh_msiof_spi_priv *, 669 const void *, int, int), 670 void (*rx_fifo)(struct sh_msiof_spi_priv *, 671 void *, int, int), 672 const void *tx_buf, void *rx_buf, 673 int words, int bits) 674 { 675 int fifo_shift; 676 int ret; 677 678 /* limit maximum word transfer to rx/tx fifo size */ 679 if (tx_buf) 680 words = min_t(int, words, p->tx_fifo_size); 681 if (rx_buf) 682 words = min_t(int, words, p->rx_fifo_size); 683 684 /* the fifo contents need shifting */ 685 fifo_shift = 32 - bits; 686 687 /* default FIFO watermarks for PIO */ 688 sh_msiof_write(p, SIFCTR, 0); 689 690 /* setup msiof transfer mode registers */ 691 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); 692 sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE); 693 694 /* write tx fifo */ 695 if (tx_buf) 696 tx_fifo(p, tx_buf, words, fifo_shift); 697 698 reinit_completion(&p->done); 699 p->slave_aborted = false; 700 701 ret = sh_msiof_spi_start(p, rx_buf); 702 if (ret) { 703 dev_err(&p->pdev->dev, "failed to start hardware\n"); 704 goto stop_ier; 705 } 706 707 /* wait for tx fifo to be emptied / rx fifo to be filled */ 708 ret = sh_msiof_wait_for_completion(p, &p->done); 709 if (ret) 710 goto stop_reset; 711 712 /* read rx fifo */ 713 if (rx_buf) 714 rx_fifo(p, rx_buf, words, fifo_shift); 715 716 /* clear status bits */ 717 sh_msiof_reset_str(p); 718 719 ret = sh_msiof_spi_stop(p, rx_buf); 720 if (ret) { 721 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 722 return ret; 723 } 724 725 return words; 726 727 stop_reset: 728 sh_msiof_reset_str(p); 729 sh_msiof_spi_stop(p, rx_buf); 730 stop_ier: 731 sh_msiof_write(p, SIIER, 0); 732 return ret; 733 } 734 735 static void sh_msiof_dma_complete(void *arg) 736 { 737 complete(arg); 738 } 739 740 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, 741 void *rx, unsigned int len) 742 { 743 u32 ier_bits = 0; 744 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 745 dma_cookie_t cookie; 746 int ret; 747 748 /* First prepare and submit the DMA request(s), as this may fail */ 749 if (rx) { 750 ier_bits |= SIIER_RDREQE | SIIER_RDMAE; 751 desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx, 752 p->rx_dma_addr, len, DMA_DEV_TO_MEM, 753 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 754 if (!desc_rx) 755 return -EAGAIN; 756 757 desc_rx->callback = sh_msiof_dma_complete; 758 desc_rx->callback_param = &p->done; 759 cookie = dmaengine_submit(desc_rx); 760 if (dma_submit_error(cookie)) 761 return cookie; 762 } 763 764 if (tx) { 765 ier_bits |= SIIER_TDREQE | SIIER_TDMAE; 766 dma_sync_single_for_device(p->ctlr->dma_tx->device->dev, 767 p->tx_dma_addr, len, DMA_TO_DEVICE); 768 desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx, 769 p->tx_dma_addr, len, DMA_MEM_TO_DEV, 770 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 771 if (!desc_tx) { 772 ret = -EAGAIN; 773 goto no_dma_tx; 774 } 775 776 desc_tx->callback = sh_msiof_dma_complete; 777 desc_tx->callback_param = &p->done_txdma; 778 cookie = dmaengine_submit(desc_tx); 779 if (dma_submit_error(cookie)) { 780 ret = cookie; 781 goto no_dma_tx; 782 } 783 } 784 785 /* 1 stage FIFO watermarks for DMA */ 786 sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1); 787 788 /* setup msiof transfer mode registers (32-bit words) */ 789 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); 790 791 sh_msiof_write(p, SIIER, ier_bits); 792 793 reinit_completion(&p->done); 794 if (tx) 795 reinit_completion(&p->done_txdma); 796 p->slave_aborted = false; 797 798 /* Now start DMA */ 799 if (rx) 800 dma_async_issue_pending(p->ctlr->dma_rx); 801 if (tx) 802 dma_async_issue_pending(p->ctlr->dma_tx); 803 804 ret = sh_msiof_spi_start(p, rx); 805 if (ret) { 806 dev_err(&p->pdev->dev, "failed to start hardware\n"); 807 goto stop_dma; 808 } 809 810 if (tx) { 811 /* wait for tx DMA completion */ 812 ret = sh_msiof_wait_for_completion(p, &p->done_txdma); 813 if (ret) 814 goto stop_reset; 815 } 816 817 if (rx) { 818 /* wait for rx DMA completion */ 819 ret = sh_msiof_wait_for_completion(p, &p->done); 820 if (ret) 821 goto stop_reset; 822 823 sh_msiof_write(p, SIIER, 0); 824 } else { 825 /* wait for tx fifo to be emptied */ 826 sh_msiof_write(p, SIIER, SIIER_TEOFE); 827 ret = sh_msiof_wait_for_completion(p, &p->done); 828 if (ret) 829 goto stop_reset; 830 } 831 832 /* clear status bits */ 833 sh_msiof_reset_str(p); 834 835 ret = sh_msiof_spi_stop(p, rx); 836 if (ret) { 837 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 838 return ret; 839 } 840 841 if (rx) 842 dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev, 843 p->rx_dma_addr, len, DMA_FROM_DEVICE); 844 845 return 0; 846 847 stop_reset: 848 sh_msiof_reset_str(p); 849 sh_msiof_spi_stop(p, rx); 850 stop_dma: 851 if (tx) 852 dmaengine_terminate_all(p->ctlr->dma_tx); 853 no_dma_tx: 854 if (rx) 855 dmaengine_terminate_all(p->ctlr->dma_rx); 856 sh_msiof_write(p, SIIER, 0); 857 return ret; 858 } 859 860 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) 861 { 862 /* src or dst can be unaligned, but not both */ 863 if ((unsigned long)src & 3) { 864 while (words--) { 865 *dst++ = swab32(get_unaligned(src)); 866 src++; 867 } 868 } else if ((unsigned long)dst & 3) { 869 while (words--) { 870 put_unaligned(swab32(*src++), dst); 871 dst++; 872 } 873 } else { 874 while (words--) 875 *dst++ = swab32(*src++); 876 } 877 } 878 879 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) 880 { 881 /* src or dst can be unaligned, but not both */ 882 if ((unsigned long)src & 3) { 883 while (words--) { 884 *dst++ = swahw32(get_unaligned(src)); 885 src++; 886 } 887 } else if ((unsigned long)dst & 3) { 888 while (words--) { 889 put_unaligned(swahw32(*src++), dst); 890 dst++; 891 } 892 } else { 893 while (words--) 894 *dst++ = swahw32(*src++); 895 } 896 } 897 898 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) 899 { 900 memcpy(dst, src, words * 4); 901 } 902 903 static int sh_msiof_transfer_one(struct spi_controller *ctlr, 904 struct spi_device *spi, 905 struct spi_transfer *t) 906 { 907 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); 908 void (*copy32)(u32 *, const u32 *, unsigned int); 909 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); 910 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); 911 const void *tx_buf = t->tx_buf; 912 void *rx_buf = t->rx_buf; 913 unsigned int len = t->len; 914 unsigned int bits = t->bits_per_word; 915 unsigned int bytes_per_word; 916 unsigned int words; 917 int n; 918 bool swab; 919 int ret; 920 921 /* reset registers */ 922 sh_msiof_spi_reset_regs(p); 923 924 /* setup clocks (clock already enabled in chipselect()) */ 925 if (!spi_controller_is_slave(p->ctlr)) 926 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); 927 928 while (ctlr->dma_tx && len > 15) { 929 /* 930 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit 931 * words, with byte resp. word swapping. 932 */ 933 unsigned int l = 0; 934 935 if (tx_buf) 936 l = min(round_down(len, 4), p->tx_fifo_size * 4); 937 if (rx_buf) 938 l = min(round_down(len, 4), p->rx_fifo_size * 4); 939 940 if (bits <= 8) { 941 copy32 = copy_bswap32; 942 } else if (bits <= 16) { 943 copy32 = copy_wswap32; 944 } else { 945 copy32 = copy_plain32; 946 } 947 948 if (tx_buf) 949 copy32(p->tx_dma_page, tx_buf, l / 4); 950 951 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); 952 if (ret == -EAGAIN) { 953 dev_warn_once(&p->pdev->dev, 954 "DMA not available, falling back to PIO\n"); 955 break; 956 } 957 if (ret) 958 return ret; 959 960 if (rx_buf) { 961 copy32(rx_buf, p->rx_dma_page, l / 4); 962 rx_buf += l; 963 } 964 if (tx_buf) 965 tx_buf += l; 966 967 len -= l; 968 if (!len) 969 return 0; 970 } 971 972 if (bits <= 8 && len > 15) { 973 bits = 32; 974 swab = true; 975 } else { 976 swab = false; 977 } 978 979 /* setup bytes per word and fifo read/write functions */ 980 if (bits <= 8) { 981 bytes_per_word = 1; 982 tx_fifo = sh_msiof_spi_write_fifo_8; 983 rx_fifo = sh_msiof_spi_read_fifo_8; 984 } else if (bits <= 16) { 985 bytes_per_word = 2; 986 if ((unsigned long)tx_buf & 0x01) 987 tx_fifo = sh_msiof_spi_write_fifo_16u; 988 else 989 tx_fifo = sh_msiof_spi_write_fifo_16; 990 991 if ((unsigned long)rx_buf & 0x01) 992 rx_fifo = sh_msiof_spi_read_fifo_16u; 993 else 994 rx_fifo = sh_msiof_spi_read_fifo_16; 995 } else if (swab) { 996 bytes_per_word = 4; 997 if ((unsigned long)tx_buf & 0x03) 998 tx_fifo = sh_msiof_spi_write_fifo_s32u; 999 else 1000 tx_fifo = sh_msiof_spi_write_fifo_s32; 1001 1002 if ((unsigned long)rx_buf & 0x03) 1003 rx_fifo = sh_msiof_spi_read_fifo_s32u; 1004 else 1005 rx_fifo = sh_msiof_spi_read_fifo_s32; 1006 } else { 1007 bytes_per_word = 4; 1008 if ((unsigned long)tx_buf & 0x03) 1009 tx_fifo = sh_msiof_spi_write_fifo_32u; 1010 else 1011 tx_fifo = sh_msiof_spi_write_fifo_32; 1012 1013 if ((unsigned long)rx_buf & 0x03) 1014 rx_fifo = sh_msiof_spi_read_fifo_32u; 1015 else 1016 rx_fifo = sh_msiof_spi_read_fifo_32; 1017 } 1018 1019 /* transfer in fifo sized chunks */ 1020 words = len / bytes_per_word; 1021 1022 while (words > 0) { 1023 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, 1024 words, bits); 1025 if (n < 0) 1026 return n; 1027 1028 if (tx_buf) 1029 tx_buf += n * bytes_per_word; 1030 if (rx_buf) 1031 rx_buf += n * bytes_per_word; 1032 words -= n; 1033 1034 if (words == 0 && (len % bytes_per_word)) { 1035 words = len % bytes_per_word; 1036 bits = t->bits_per_word; 1037 bytes_per_word = 1; 1038 tx_fifo = sh_msiof_spi_write_fifo_8; 1039 rx_fifo = sh_msiof_spi_read_fifo_8; 1040 } 1041 } 1042 1043 return 0; 1044 } 1045 1046 static const struct sh_msiof_chipdata sh_data = { 1047 .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32), 1048 .tx_fifo_size = 64, 1049 .rx_fifo_size = 64, 1050 .ctlr_flags = 0, 1051 .min_div_pow = 0, 1052 }; 1053 1054 static const struct sh_msiof_chipdata rcar_gen2_data = { 1055 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 1056 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 1057 .tx_fifo_size = 64, 1058 .rx_fifo_size = 64, 1059 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 1060 .min_div_pow = 0, 1061 }; 1062 1063 static const struct sh_msiof_chipdata rcar_gen3_data = { 1064 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 1065 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 1066 .tx_fifo_size = 64, 1067 .rx_fifo_size = 64, 1068 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 1069 .min_div_pow = 1, 1070 }; 1071 1072 static const struct of_device_id sh_msiof_match[] = { 1073 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, 1074 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data }, 1075 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data }, 1076 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data }, 1077 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data }, 1078 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data }, 1079 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data }, 1080 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data }, 1081 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data }, 1082 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data }, 1083 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data }, 1084 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */ 1085 {}, 1086 }; 1087 MODULE_DEVICE_TABLE(of, sh_msiof_match); 1088 1089 #ifdef CONFIG_OF 1090 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1091 { 1092 struct sh_msiof_spi_info *info; 1093 struct device_node *np = dev->of_node; 1094 u32 num_cs = 1; 1095 1096 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); 1097 if (!info) 1098 return NULL; 1099 1100 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE 1101 : MSIOF_SPI_MASTER; 1102 1103 /* Parse the MSIOF properties */ 1104 if (info->mode == MSIOF_SPI_MASTER) 1105 of_property_read_u32(np, "num-cs", &num_cs); 1106 of_property_read_u32(np, "renesas,tx-fifo-size", 1107 &info->tx_fifo_override); 1108 of_property_read_u32(np, "renesas,rx-fifo-size", 1109 &info->rx_fifo_override); 1110 of_property_read_u32(np, "renesas,dtdl", &info->dtdl); 1111 of_property_read_u32(np, "renesas,syncdl", &info->syncdl); 1112 1113 info->num_chipselect = num_cs; 1114 1115 return info; 1116 } 1117 #else 1118 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1119 { 1120 return NULL; 1121 } 1122 #endif 1123 1124 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, 1125 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) 1126 { 1127 dma_cap_mask_t mask; 1128 struct dma_chan *chan; 1129 struct dma_slave_config cfg; 1130 int ret; 1131 1132 dma_cap_zero(mask); 1133 dma_cap_set(DMA_SLAVE, mask); 1134 1135 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 1136 (void *)(unsigned long)id, dev, 1137 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1138 if (!chan) { 1139 dev_warn(dev, "dma_request_slave_channel_compat failed\n"); 1140 return NULL; 1141 } 1142 1143 memset(&cfg, 0, sizeof(cfg)); 1144 cfg.direction = dir; 1145 if (dir == DMA_MEM_TO_DEV) { 1146 cfg.dst_addr = port_addr; 1147 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1148 } else { 1149 cfg.src_addr = port_addr; 1150 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1151 } 1152 1153 ret = dmaengine_slave_config(chan, &cfg); 1154 if (ret) { 1155 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 1156 dma_release_channel(chan); 1157 return NULL; 1158 } 1159 1160 return chan; 1161 } 1162 1163 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) 1164 { 1165 struct platform_device *pdev = p->pdev; 1166 struct device *dev = &pdev->dev; 1167 const struct sh_msiof_spi_info *info = p->info; 1168 unsigned int dma_tx_id, dma_rx_id; 1169 const struct resource *res; 1170 struct spi_controller *ctlr; 1171 struct device *tx_dev, *rx_dev; 1172 1173 if (dev->of_node) { 1174 /* In the OF case we will get the slave IDs from the DT */ 1175 dma_tx_id = 0; 1176 dma_rx_id = 0; 1177 } else if (info && info->dma_tx_id && info->dma_rx_id) { 1178 dma_tx_id = info->dma_tx_id; 1179 dma_rx_id = info->dma_rx_id; 1180 } else { 1181 /* The driver assumes no error */ 1182 return 0; 1183 } 1184 1185 /* The DMA engine uses the second register set, if present */ 1186 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1187 if (!res) 1188 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1189 1190 ctlr = p->ctlr; 1191 ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, 1192 dma_tx_id, res->start + SITFDR); 1193 if (!ctlr->dma_tx) 1194 return -ENODEV; 1195 1196 ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, 1197 dma_rx_id, res->start + SIRFDR); 1198 if (!ctlr->dma_rx) 1199 goto free_tx_chan; 1200 1201 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1202 if (!p->tx_dma_page) 1203 goto free_rx_chan; 1204 1205 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1206 if (!p->rx_dma_page) 1207 goto free_tx_page; 1208 1209 tx_dev = ctlr->dma_tx->device->dev; 1210 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, 1211 DMA_TO_DEVICE); 1212 if (dma_mapping_error(tx_dev, p->tx_dma_addr)) 1213 goto free_rx_page; 1214 1215 rx_dev = ctlr->dma_rx->device->dev; 1216 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, 1217 DMA_FROM_DEVICE); 1218 if (dma_mapping_error(rx_dev, p->rx_dma_addr)) 1219 goto unmap_tx_page; 1220 1221 dev_info(dev, "DMA available"); 1222 return 0; 1223 1224 unmap_tx_page: 1225 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); 1226 free_rx_page: 1227 free_page((unsigned long)p->rx_dma_page); 1228 free_tx_page: 1229 free_page((unsigned long)p->tx_dma_page); 1230 free_rx_chan: 1231 dma_release_channel(ctlr->dma_rx); 1232 free_tx_chan: 1233 dma_release_channel(ctlr->dma_tx); 1234 ctlr->dma_tx = NULL; 1235 return -ENODEV; 1236 } 1237 1238 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) 1239 { 1240 struct spi_controller *ctlr = p->ctlr; 1241 1242 if (!ctlr->dma_tx) 1243 return; 1244 1245 dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE, 1246 DMA_FROM_DEVICE); 1247 dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE, 1248 DMA_TO_DEVICE); 1249 free_page((unsigned long)p->rx_dma_page); 1250 free_page((unsigned long)p->tx_dma_page); 1251 dma_release_channel(ctlr->dma_rx); 1252 dma_release_channel(ctlr->dma_tx); 1253 } 1254 1255 static int sh_msiof_spi_probe(struct platform_device *pdev) 1256 { 1257 struct spi_controller *ctlr; 1258 const struct sh_msiof_chipdata *chipdata; 1259 struct sh_msiof_spi_info *info; 1260 struct sh_msiof_spi_priv *p; 1261 int i; 1262 int ret; 1263 1264 chipdata = of_device_get_match_data(&pdev->dev); 1265 if (chipdata) { 1266 info = sh_msiof_spi_parse_dt(&pdev->dev); 1267 } else { 1268 chipdata = (const void *)pdev->id_entry->driver_data; 1269 info = dev_get_platdata(&pdev->dev); 1270 } 1271 1272 if (!info) { 1273 dev_err(&pdev->dev, "failed to obtain device info\n"); 1274 return -ENXIO; 1275 } 1276 1277 if (info->mode == MSIOF_SPI_SLAVE) 1278 ctlr = spi_alloc_slave(&pdev->dev, 1279 sizeof(struct sh_msiof_spi_priv)); 1280 else 1281 ctlr = spi_alloc_master(&pdev->dev, 1282 sizeof(struct sh_msiof_spi_priv)); 1283 if (ctlr == NULL) 1284 return -ENOMEM; 1285 1286 p = spi_controller_get_devdata(ctlr); 1287 1288 platform_set_drvdata(pdev, p); 1289 p->ctlr = ctlr; 1290 p->info = info; 1291 p->min_div_pow = chipdata->min_div_pow; 1292 1293 init_completion(&p->done); 1294 init_completion(&p->done_txdma); 1295 1296 p->clk = devm_clk_get(&pdev->dev, NULL); 1297 if (IS_ERR(p->clk)) { 1298 dev_err(&pdev->dev, "cannot get clock\n"); 1299 ret = PTR_ERR(p->clk); 1300 goto err1; 1301 } 1302 1303 i = platform_get_irq(pdev, 0); 1304 if (i < 0) { 1305 ret = i; 1306 goto err1; 1307 } 1308 1309 p->mapbase = devm_platform_ioremap_resource(pdev, 0); 1310 if (IS_ERR(p->mapbase)) { 1311 ret = PTR_ERR(p->mapbase); 1312 goto err1; 1313 } 1314 1315 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, 1316 dev_name(&pdev->dev), p); 1317 if (ret) { 1318 dev_err(&pdev->dev, "unable to request irq\n"); 1319 goto err1; 1320 } 1321 1322 p->pdev = pdev; 1323 pm_runtime_enable(&pdev->dev); 1324 1325 /* Platform data may override FIFO sizes */ 1326 p->tx_fifo_size = chipdata->tx_fifo_size; 1327 p->rx_fifo_size = chipdata->rx_fifo_size; 1328 if (p->info->tx_fifo_override) 1329 p->tx_fifo_size = p->info->tx_fifo_override; 1330 if (p->info->rx_fifo_override) 1331 p->rx_fifo_size = p->info->rx_fifo_override; 1332 1333 /* init controller code */ 1334 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1335 ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; 1336 ctlr->flags = chipdata->ctlr_flags; 1337 ctlr->bus_num = pdev->id; 1338 ctlr->num_chipselect = p->info->num_chipselect; 1339 ctlr->dev.of_node = pdev->dev.of_node; 1340 ctlr->setup = sh_msiof_spi_setup; 1341 ctlr->prepare_message = sh_msiof_prepare_message; 1342 ctlr->slave_abort = sh_msiof_slave_abort; 1343 ctlr->bits_per_word_mask = chipdata->bits_per_word_mask; 1344 ctlr->auto_runtime_pm = true; 1345 ctlr->transfer_one = sh_msiof_transfer_one; 1346 ctlr->use_gpio_descriptors = true; 1347 ctlr->max_native_cs = MAX_SS; 1348 1349 ret = sh_msiof_request_dma(p); 1350 if (ret < 0) 1351 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1352 1353 ret = devm_spi_register_controller(&pdev->dev, ctlr); 1354 if (ret < 0) { 1355 dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); 1356 goto err2; 1357 } 1358 1359 return 0; 1360 1361 err2: 1362 sh_msiof_release_dma(p); 1363 pm_runtime_disable(&pdev->dev); 1364 err1: 1365 spi_controller_put(ctlr); 1366 return ret; 1367 } 1368 1369 static int sh_msiof_spi_remove(struct platform_device *pdev) 1370 { 1371 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); 1372 1373 sh_msiof_release_dma(p); 1374 pm_runtime_disable(&pdev->dev); 1375 return 0; 1376 } 1377 1378 static const struct platform_device_id spi_driver_ids[] = { 1379 { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, 1380 {}, 1381 }; 1382 MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1383 1384 #ifdef CONFIG_PM_SLEEP 1385 static int sh_msiof_spi_suspend(struct device *dev) 1386 { 1387 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev); 1388 1389 return spi_controller_suspend(p->ctlr); 1390 } 1391 1392 static int sh_msiof_spi_resume(struct device *dev) 1393 { 1394 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev); 1395 1396 return spi_controller_resume(p->ctlr); 1397 } 1398 1399 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend, 1400 sh_msiof_spi_resume); 1401 #define DEV_PM_OPS &sh_msiof_spi_pm_ops 1402 #else 1403 #define DEV_PM_OPS NULL 1404 #endif /* CONFIG_PM_SLEEP */ 1405 1406 static struct platform_driver sh_msiof_spi_drv = { 1407 .probe = sh_msiof_spi_probe, 1408 .remove = sh_msiof_spi_remove, 1409 .id_table = spi_driver_ids, 1410 .driver = { 1411 .name = "spi_sh_msiof", 1412 .pm = DEV_PM_OPS, 1413 .of_match_table = of_match_ptr(sh_msiof_match), 1414 }, 1415 }; 1416 module_platform_driver(sh_msiof_spi_drv); 1417 1418 MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver"); 1419 MODULE_AUTHOR("Magnus Damm"); 1420 MODULE_LICENSE("GPL v2"); 1421 MODULE_ALIAS("platform:spi_sh_msiof"); 1422