1 /* 2 * SuperH MSIOF SPI Master Interface 3 * 4 * Copyright (c) 2009 Magnus Damm 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 * Copyright (C) 2014-2017 Glider bvba 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 */ 13 14 #include <linux/bitmap.h> 15 #include <linux/clk.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/dmaengine.h> 20 #include <linux/err.h> 21 #include <linux/gpio.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/sh_dma.h> 31 32 #include <linux/spi/sh_msiof.h> 33 #include <linux/spi/spi.h> 34 35 #include <asm/unaligned.h> 36 37 struct sh_msiof_chipdata { 38 u16 tx_fifo_size; 39 u16 rx_fifo_size; 40 u16 master_flags; 41 u16 min_div; 42 }; 43 44 struct sh_msiof_spi_priv { 45 struct spi_master *master; 46 void __iomem *mapbase; 47 struct clk *clk; 48 struct platform_device *pdev; 49 struct sh_msiof_spi_info *info; 50 struct completion done; 51 unsigned int tx_fifo_size; 52 unsigned int rx_fifo_size; 53 unsigned int min_div; 54 void *tx_dma_page; 55 void *rx_dma_page; 56 dma_addr_t tx_dma_addr; 57 dma_addr_t rx_dma_addr; 58 bool slave_aborted; 59 }; 60 61 #define TMDR1 0x00 /* Transmit Mode Register 1 */ 62 #define TMDR2 0x04 /* Transmit Mode Register 2 */ 63 #define TMDR3 0x08 /* Transmit Mode Register 3 */ 64 #define RMDR1 0x10 /* Receive Mode Register 1 */ 65 #define RMDR2 0x14 /* Receive Mode Register 2 */ 66 #define RMDR3 0x18 /* Receive Mode Register 3 */ 67 #define TSCR 0x20 /* Transmit Clock Select Register */ 68 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ 69 #define CTR 0x28 /* Control Register */ 70 #define FCTR 0x30 /* FIFO Control Register */ 71 #define STR 0x40 /* Status Register */ 72 #define IER 0x44 /* Interrupt Enable Register */ 73 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ 74 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ 75 #define TFDR 0x50 /* Transmit FIFO Data Register */ 76 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ 77 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ 78 #define RFDR 0x60 /* Receive FIFO Data Register */ 79 80 /* TMDR1 and RMDR1 */ 81 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ 82 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ 83 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ 84 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ 85 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ 86 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ 87 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */ 88 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */ 89 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */ 90 #define MDR1_FLD_SHIFT 2 91 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ 92 /* TMDR1 */ 93 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ 94 95 /* TMDR2 and RMDR2 */ 96 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ 97 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ 98 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ 99 100 /* TSCR and RSCR */ 101 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ 102 #define SCR_BRPS(i) (((i) - 1) << 8) 103 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ 104 #define SCR_BRDV_DIV_2 0x0000 105 #define SCR_BRDV_DIV_4 0x0001 106 #define SCR_BRDV_DIV_8 0x0002 107 #define SCR_BRDV_DIV_16 0x0003 108 #define SCR_BRDV_DIV_32 0x0004 109 #define SCR_BRDV_DIV_1 0x0007 110 111 /* CTR */ 112 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ 113 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ 114 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ 115 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ 116 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ 117 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ 118 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ 119 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ 120 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ 121 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ 122 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ 123 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ 124 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ 125 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ 126 #define CTR_TXE 0x00000200 /* Transmit Enable */ 127 #define CTR_RXE 0x00000100 /* Receive Enable */ 128 129 /* FCTR */ 130 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ 131 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */ 132 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */ 133 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */ 134 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */ 135 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */ 136 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */ 137 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */ 138 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */ 139 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */ 140 #define FCTR_TFUA_SHIFT 20 141 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT) 142 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */ 143 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */ 144 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */ 145 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */ 146 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */ 147 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */ 148 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */ 149 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */ 150 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */ 151 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */ 152 #define FCTR_RFUA_SHIFT 4 153 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT) 154 155 /* STR */ 156 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */ 157 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */ 158 #define STR_TEOF 0x00800000 /* Frame Transmission End */ 159 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */ 160 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */ 161 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */ 162 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */ 163 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */ 164 #define STR_REOF 0x00000080 /* Frame Reception End */ 165 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */ 166 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */ 167 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */ 168 169 /* IER */ 170 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */ 171 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */ 172 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */ 173 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */ 174 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */ 175 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */ 176 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */ 177 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */ 178 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */ 179 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */ 180 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */ 181 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */ 182 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */ 183 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */ 184 185 186 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) 187 { 188 switch (reg_offs) { 189 case TSCR: 190 case RSCR: 191 return ioread16(p->mapbase + reg_offs); 192 default: 193 return ioread32(p->mapbase + reg_offs); 194 } 195 } 196 197 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, 198 u32 value) 199 { 200 switch (reg_offs) { 201 case TSCR: 202 case RSCR: 203 iowrite16(value, p->mapbase + reg_offs); 204 break; 205 default: 206 iowrite32(value, p->mapbase + reg_offs); 207 break; 208 } 209 } 210 211 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, 212 u32 clr, u32 set) 213 { 214 u32 mask = clr | set; 215 u32 data; 216 int k; 217 218 data = sh_msiof_read(p, CTR); 219 data &= ~clr; 220 data |= set; 221 sh_msiof_write(p, CTR, data); 222 223 for (k = 100; k > 0; k--) { 224 if ((sh_msiof_read(p, CTR) & mask) == set) 225 break; 226 227 udelay(10); 228 } 229 230 return k > 0 ? 0 : -ETIMEDOUT; 231 } 232 233 static irqreturn_t sh_msiof_spi_irq(int irq, void *data) 234 { 235 struct sh_msiof_spi_priv *p = data; 236 237 /* just disable the interrupt and wake up */ 238 sh_msiof_write(p, IER, 0); 239 complete(&p->done); 240 241 return IRQ_HANDLED; 242 } 243 244 static struct { 245 unsigned short div; 246 unsigned short brdv; 247 } const sh_msiof_spi_div_table[] = { 248 { 1, SCR_BRDV_DIV_1 }, 249 { 2, SCR_BRDV_DIV_2 }, 250 { 4, SCR_BRDV_DIV_4 }, 251 { 8, SCR_BRDV_DIV_8 }, 252 { 16, SCR_BRDV_DIV_16 }, 253 { 32, SCR_BRDV_DIV_32 }, 254 }; 255 256 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 257 unsigned long parent_rate, u32 spi_hz) 258 { 259 unsigned long div = 1024; 260 u32 brps, scr; 261 size_t k; 262 263 if (!WARN_ON(!spi_hz || !parent_rate)) 264 div = DIV_ROUND_UP(parent_rate, spi_hz); 265 266 div = max_t(unsigned long, div, p->min_div); 267 268 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) { 269 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div); 270 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */ 271 if (sh_msiof_spi_div_table[k].div == 1 && brps > 2) 272 continue; 273 if (brps <= 32) /* max of brdv is 32 */ 274 break; 275 } 276 277 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1); 278 279 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps); 280 sh_msiof_write(p, TSCR, scr); 281 if (!(p->master->flags & SPI_MASTER_MUST_TX)) 282 sh_msiof_write(p, RSCR, scr); 283 } 284 285 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl) 286 { 287 /* 288 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl 289 * b'000 : 0 290 * b'001 : 100 291 * b'010 : 200 292 * b'011 (SYNCDL only) : 300 293 * b'101 : 50 294 * b'110 : 150 295 */ 296 if (dtdl_or_syncdl % 100) 297 return dtdl_or_syncdl / 100 + 5; 298 else 299 return dtdl_or_syncdl / 100; 300 } 301 302 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) 303 { 304 u32 val; 305 306 if (!p->info) 307 return 0; 308 309 /* check if DTDL and SYNCDL is allowed value */ 310 if (p->info->dtdl > 200 || p->info->syncdl > 300) { 311 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n"); 312 return 0; 313 } 314 315 /* check if the sum of DTDL and SYNCDL becomes an integer value */ 316 if ((p->info->dtdl + p->info->syncdl) % 100) { 317 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n"); 318 return 0; 319 } 320 321 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT; 322 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT; 323 324 return val; 325 } 326 327 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, 328 u32 cpol, u32 cpha, 329 u32 tx_hi_z, u32 lsb_first, u32 cs_high) 330 { 331 u32 tmp; 332 int edge; 333 334 /* 335 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG 336 * 0 0 10 10 1 1 337 * 0 1 10 10 0 0 338 * 1 0 11 11 0 0 339 * 1 1 11 11 1 1 340 */ 341 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; 342 tmp |= !cs_high << MDR1_SYNCAC_SHIFT; 343 tmp |= lsb_first << MDR1_BITLSB_SHIFT; 344 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); 345 if (spi_controller_is_slave(p->master)) 346 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON); 347 else 348 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); 349 if (p->master->flags & SPI_MASTER_MUST_TX) { 350 /* These bits are reserved if RX needs TX */ 351 tmp &= ~0x0000ffff; 352 } 353 sh_msiof_write(p, RMDR1, tmp); 354 355 tmp = 0; 356 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; 357 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; 358 359 edge = cpol ^ !cpha; 360 361 tmp |= edge << CTR_TEDG_SHIFT; 362 tmp |= edge << CTR_REDG_SHIFT; 363 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; 364 sh_msiof_write(p, CTR, tmp); 365 } 366 367 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, 368 const void *tx_buf, void *rx_buf, 369 u32 bits, u32 words) 370 { 371 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); 372 373 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX)) 374 sh_msiof_write(p, TMDR2, dr2); 375 else 376 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); 377 378 if (rx_buf) 379 sh_msiof_write(p, RMDR2, dr2); 380 } 381 382 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) 383 { 384 sh_msiof_write(p, STR, sh_msiof_read(p, STR)); 385 } 386 387 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, 388 const void *tx_buf, int words, int fs) 389 { 390 const u8 *buf_8 = tx_buf; 391 int k; 392 393 for (k = 0; k < words; k++) 394 sh_msiof_write(p, TFDR, buf_8[k] << fs); 395 } 396 397 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, 398 const void *tx_buf, int words, int fs) 399 { 400 const u16 *buf_16 = tx_buf; 401 int k; 402 403 for (k = 0; k < words; k++) 404 sh_msiof_write(p, TFDR, buf_16[k] << fs); 405 } 406 407 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, 408 const void *tx_buf, int words, int fs) 409 { 410 const u16 *buf_16 = tx_buf; 411 int k; 412 413 for (k = 0; k < words; k++) 414 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); 415 } 416 417 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, 418 const void *tx_buf, int words, int fs) 419 { 420 const u32 *buf_32 = tx_buf; 421 int k; 422 423 for (k = 0; k < words; k++) 424 sh_msiof_write(p, TFDR, buf_32[k] << fs); 425 } 426 427 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, 428 const void *tx_buf, int words, int fs) 429 { 430 const u32 *buf_32 = tx_buf; 431 int k; 432 433 for (k = 0; k < words; k++) 434 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); 435 } 436 437 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, 438 const void *tx_buf, int words, int fs) 439 { 440 const u32 *buf_32 = tx_buf; 441 int k; 442 443 for (k = 0; k < words; k++) 444 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); 445 } 446 447 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, 448 const void *tx_buf, int words, int fs) 449 { 450 const u32 *buf_32 = tx_buf; 451 int k; 452 453 for (k = 0; k < words; k++) 454 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); 455 } 456 457 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, 458 void *rx_buf, int words, int fs) 459 { 460 u8 *buf_8 = rx_buf; 461 int k; 462 463 for (k = 0; k < words; k++) 464 buf_8[k] = sh_msiof_read(p, RFDR) >> fs; 465 } 466 467 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, 468 void *rx_buf, int words, int fs) 469 { 470 u16 *buf_16 = rx_buf; 471 int k; 472 473 for (k = 0; k < words; k++) 474 buf_16[k] = sh_msiof_read(p, RFDR) >> fs; 475 } 476 477 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, 478 void *rx_buf, int words, int fs) 479 { 480 u16 *buf_16 = rx_buf; 481 int k; 482 483 for (k = 0; k < words; k++) 484 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); 485 } 486 487 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, 488 void *rx_buf, int words, int fs) 489 { 490 u32 *buf_32 = rx_buf; 491 int k; 492 493 for (k = 0; k < words; k++) 494 buf_32[k] = sh_msiof_read(p, RFDR) >> fs; 495 } 496 497 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, 498 void *rx_buf, int words, int fs) 499 { 500 u32 *buf_32 = rx_buf; 501 int k; 502 503 for (k = 0; k < words; k++) 504 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); 505 } 506 507 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, 508 void *rx_buf, int words, int fs) 509 { 510 u32 *buf_32 = rx_buf; 511 int k; 512 513 for (k = 0; k < words; k++) 514 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); 515 } 516 517 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, 518 void *rx_buf, int words, int fs) 519 { 520 u32 *buf_32 = rx_buf; 521 int k; 522 523 for (k = 0; k < words; k++) 524 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); 525 } 526 527 static int sh_msiof_spi_setup(struct spi_device *spi) 528 { 529 struct device_node *np = spi->master->dev.of_node; 530 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); 531 532 pm_runtime_get_sync(&p->pdev->dev); 533 534 if (!np) { 535 /* 536 * Use spi->controller_data for CS (same strategy as spi_gpio), 537 * if any. otherwise let HW control CS 538 */ 539 spi->cs_gpio = (uintptr_t)spi->controller_data; 540 } 541 542 /* Configure pins before deasserting CS */ 543 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), 544 !!(spi->mode & SPI_CPHA), 545 !!(spi->mode & SPI_3WIRE), 546 !!(spi->mode & SPI_LSB_FIRST), 547 !!(spi->mode & SPI_CS_HIGH)); 548 549 if (spi->cs_gpio >= 0) 550 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 551 552 553 pm_runtime_put(&p->pdev->dev); 554 555 return 0; 556 } 557 558 static int sh_msiof_prepare_message(struct spi_master *master, 559 struct spi_message *msg) 560 { 561 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 562 const struct spi_device *spi = msg->spi; 563 564 /* Configure pins before asserting CS */ 565 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), 566 !!(spi->mode & SPI_CPHA), 567 !!(spi->mode & SPI_3WIRE), 568 !!(spi->mode & SPI_LSB_FIRST), 569 !!(spi->mode & SPI_CS_HIGH)); 570 return 0; 571 } 572 573 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) 574 { 575 bool slave = spi_controller_is_slave(p->master); 576 int ret = 0; 577 578 /* setup clock and rx/tx signals */ 579 if (!slave) 580 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); 581 if (rx_buf && !ret) 582 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); 583 if (!ret) 584 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); 585 586 /* start by setting frame bit */ 587 if (!ret && !slave) 588 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); 589 590 return ret; 591 } 592 593 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) 594 { 595 bool slave = spi_controller_is_slave(p->master); 596 int ret = 0; 597 598 /* shut down frame, rx/tx and clock signals */ 599 if (!slave) 600 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); 601 if (!ret) 602 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); 603 if (rx_buf && !ret) 604 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); 605 if (!ret && !slave) 606 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); 607 608 return ret; 609 } 610 611 static int sh_msiof_slave_abort(struct spi_master *master) 612 { 613 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 614 615 p->slave_aborted = true; 616 complete(&p->done); 617 return 0; 618 } 619 620 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p) 621 { 622 if (spi_controller_is_slave(p->master)) { 623 if (wait_for_completion_interruptible(&p->done) || 624 p->slave_aborted) { 625 dev_dbg(&p->pdev->dev, "interrupted\n"); 626 return -EINTR; 627 } 628 } else { 629 if (!wait_for_completion_timeout(&p->done, HZ)) { 630 dev_err(&p->pdev->dev, "timeout\n"); 631 return -ETIMEDOUT; 632 } 633 } 634 635 return 0; 636 } 637 638 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, 639 void (*tx_fifo)(struct sh_msiof_spi_priv *, 640 const void *, int, int), 641 void (*rx_fifo)(struct sh_msiof_spi_priv *, 642 void *, int, int), 643 const void *tx_buf, void *rx_buf, 644 int words, int bits) 645 { 646 int fifo_shift; 647 int ret; 648 649 /* limit maximum word transfer to rx/tx fifo size */ 650 if (tx_buf) 651 words = min_t(int, words, p->tx_fifo_size); 652 if (rx_buf) 653 words = min_t(int, words, p->rx_fifo_size); 654 655 /* the fifo contents need shifting */ 656 fifo_shift = 32 - bits; 657 658 /* default FIFO watermarks for PIO */ 659 sh_msiof_write(p, FCTR, 0); 660 661 /* setup msiof transfer mode registers */ 662 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); 663 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE); 664 665 /* write tx fifo */ 666 if (tx_buf) 667 tx_fifo(p, tx_buf, words, fifo_shift); 668 669 reinit_completion(&p->done); 670 p->slave_aborted = false; 671 672 ret = sh_msiof_spi_start(p, rx_buf); 673 if (ret) { 674 dev_err(&p->pdev->dev, "failed to start hardware\n"); 675 goto stop_ier; 676 } 677 678 /* wait for tx fifo to be emptied / rx fifo to be filled */ 679 ret = sh_msiof_wait_for_completion(p); 680 if (ret) 681 goto stop_reset; 682 683 /* read rx fifo */ 684 if (rx_buf) 685 rx_fifo(p, rx_buf, words, fifo_shift); 686 687 /* clear status bits */ 688 sh_msiof_reset_str(p); 689 690 ret = sh_msiof_spi_stop(p, rx_buf); 691 if (ret) { 692 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 693 return ret; 694 } 695 696 return words; 697 698 stop_reset: 699 sh_msiof_reset_str(p); 700 sh_msiof_spi_stop(p, rx_buf); 701 stop_ier: 702 sh_msiof_write(p, IER, 0); 703 return ret; 704 } 705 706 static void sh_msiof_dma_complete(void *arg) 707 { 708 struct sh_msiof_spi_priv *p = arg; 709 710 sh_msiof_write(p, IER, 0); 711 complete(&p->done); 712 } 713 714 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, 715 void *rx, unsigned int len) 716 { 717 u32 ier_bits = 0; 718 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 719 dma_cookie_t cookie; 720 int ret; 721 722 /* First prepare and submit the DMA request(s), as this may fail */ 723 if (rx) { 724 ier_bits |= IER_RDREQE | IER_RDMAE; 725 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, 726 p->rx_dma_addr, len, DMA_FROM_DEVICE, 727 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 728 if (!desc_rx) 729 return -EAGAIN; 730 731 desc_rx->callback = sh_msiof_dma_complete; 732 desc_rx->callback_param = p; 733 cookie = dmaengine_submit(desc_rx); 734 if (dma_submit_error(cookie)) 735 return cookie; 736 } 737 738 if (tx) { 739 ier_bits |= IER_TDREQE | IER_TDMAE; 740 dma_sync_single_for_device(p->master->dma_tx->device->dev, 741 p->tx_dma_addr, len, DMA_TO_DEVICE); 742 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx, 743 p->tx_dma_addr, len, DMA_TO_DEVICE, 744 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 745 if (!desc_tx) { 746 ret = -EAGAIN; 747 goto no_dma_tx; 748 } 749 750 if (rx) { 751 /* No callback */ 752 desc_tx->callback = NULL; 753 } else { 754 desc_tx->callback = sh_msiof_dma_complete; 755 desc_tx->callback_param = p; 756 } 757 cookie = dmaengine_submit(desc_tx); 758 if (dma_submit_error(cookie)) { 759 ret = cookie; 760 goto no_dma_tx; 761 } 762 } 763 764 /* 1 stage FIFO watermarks for DMA */ 765 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1); 766 767 /* setup msiof transfer mode registers (32-bit words) */ 768 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); 769 770 sh_msiof_write(p, IER, ier_bits); 771 772 reinit_completion(&p->done); 773 p->slave_aborted = false; 774 775 /* Now start DMA */ 776 if (rx) 777 dma_async_issue_pending(p->master->dma_rx); 778 if (tx) 779 dma_async_issue_pending(p->master->dma_tx); 780 781 ret = sh_msiof_spi_start(p, rx); 782 if (ret) { 783 dev_err(&p->pdev->dev, "failed to start hardware\n"); 784 goto stop_dma; 785 } 786 787 /* wait for tx fifo to be emptied / rx fifo to be filled */ 788 ret = sh_msiof_wait_for_completion(p); 789 if (ret) 790 goto stop_reset; 791 792 /* clear status bits */ 793 sh_msiof_reset_str(p); 794 795 ret = sh_msiof_spi_stop(p, rx); 796 if (ret) { 797 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 798 return ret; 799 } 800 801 if (rx) 802 dma_sync_single_for_cpu(p->master->dma_rx->device->dev, 803 p->rx_dma_addr, len, 804 DMA_FROM_DEVICE); 805 806 return 0; 807 808 stop_reset: 809 sh_msiof_reset_str(p); 810 sh_msiof_spi_stop(p, rx); 811 stop_dma: 812 if (tx) 813 dmaengine_terminate_all(p->master->dma_tx); 814 no_dma_tx: 815 if (rx) 816 dmaengine_terminate_all(p->master->dma_rx); 817 sh_msiof_write(p, IER, 0); 818 return ret; 819 } 820 821 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) 822 { 823 /* src or dst can be unaligned, but not both */ 824 if ((unsigned long)src & 3) { 825 while (words--) { 826 *dst++ = swab32(get_unaligned(src)); 827 src++; 828 } 829 } else if ((unsigned long)dst & 3) { 830 while (words--) { 831 put_unaligned(swab32(*src++), dst); 832 dst++; 833 } 834 } else { 835 while (words--) 836 *dst++ = swab32(*src++); 837 } 838 } 839 840 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) 841 { 842 /* src or dst can be unaligned, but not both */ 843 if ((unsigned long)src & 3) { 844 while (words--) { 845 *dst++ = swahw32(get_unaligned(src)); 846 src++; 847 } 848 } else if ((unsigned long)dst & 3) { 849 while (words--) { 850 put_unaligned(swahw32(*src++), dst); 851 dst++; 852 } 853 } else { 854 while (words--) 855 *dst++ = swahw32(*src++); 856 } 857 } 858 859 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) 860 { 861 memcpy(dst, src, words * 4); 862 } 863 864 static int sh_msiof_transfer_one(struct spi_master *master, 865 struct spi_device *spi, 866 struct spi_transfer *t) 867 { 868 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 869 void (*copy32)(u32 *, const u32 *, unsigned int); 870 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); 871 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); 872 const void *tx_buf = t->tx_buf; 873 void *rx_buf = t->rx_buf; 874 unsigned int len = t->len; 875 unsigned int bits = t->bits_per_word; 876 unsigned int bytes_per_word; 877 unsigned int words; 878 int n; 879 bool swab; 880 int ret; 881 882 /* setup clocks (clock already enabled in chipselect()) */ 883 if (!spi_controller_is_slave(p->master)) 884 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); 885 886 while (master->dma_tx && len > 15) { 887 /* 888 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit 889 * words, with byte resp. word swapping. 890 */ 891 unsigned int l = 0; 892 893 if (tx_buf) 894 l = min(len, p->tx_fifo_size * 4); 895 if (rx_buf) 896 l = min(len, p->rx_fifo_size * 4); 897 898 if (bits <= 8) { 899 if (l & 3) 900 break; 901 copy32 = copy_bswap32; 902 } else if (bits <= 16) { 903 if (l & 3) 904 break; 905 copy32 = copy_wswap32; 906 } else { 907 copy32 = copy_plain32; 908 } 909 910 if (tx_buf) 911 copy32(p->tx_dma_page, tx_buf, l / 4); 912 913 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); 914 if (ret == -EAGAIN) { 915 pr_warn_once("%s %s: DMA not available, falling back to PIO\n", 916 dev_driver_string(&p->pdev->dev), 917 dev_name(&p->pdev->dev)); 918 break; 919 } 920 if (ret) 921 return ret; 922 923 if (rx_buf) { 924 copy32(rx_buf, p->rx_dma_page, l / 4); 925 rx_buf += l; 926 } 927 if (tx_buf) 928 tx_buf += l; 929 930 len -= l; 931 if (!len) 932 return 0; 933 } 934 935 if (bits <= 8 && len > 15 && !(len & 3)) { 936 bits = 32; 937 swab = true; 938 } else { 939 swab = false; 940 } 941 942 /* setup bytes per word and fifo read/write functions */ 943 if (bits <= 8) { 944 bytes_per_word = 1; 945 tx_fifo = sh_msiof_spi_write_fifo_8; 946 rx_fifo = sh_msiof_spi_read_fifo_8; 947 } else if (bits <= 16) { 948 bytes_per_word = 2; 949 if ((unsigned long)tx_buf & 0x01) 950 tx_fifo = sh_msiof_spi_write_fifo_16u; 951 else 952 tx_fifo = sh_msiof_spi_write_fifo_16; 953 954 if ((unsigned long)rx_buf & 0x01) 955 rx_fifo = sh_msiof_spi_read_fifo_16u; 956 else 957 rx_fifo = sh_msiof_spi_read_fifo_16; 958 } else if (swab) { 959 bytes_per_word = 4; 960 if ((unsigned long)tx_buf & 0x03) 961 tx_fifo = sh_msiof_spi_write_fifo_s32u; 962 else 963 tx_fifo = sh_msiof_spi_write_fifo_s32; 964 965 if ((unsigned long)rx_buf & 0x03) 966 rx_fifo = sh_msiof_spi_read_fifo_s32u; 967 else 968 rx_fifo = sh_msiof_spi_read_fifo_s32; 969 } else { 970 bytes_per_word = 4; 971 if ((unsigned long)tx_buf & 0x03) 972 tx_fifo = sh_msiof_spi_write_fifo_32u; 973 else 974 tx_fifo = sh_msiof_spi_write_fifo_32; 975 976 if ((unsigned long)rx_buf & 0x03) 977 rx_fifo = sh_msiof_spi_read_fifo_32u; 978 else 979 rx_fifo = sh_msiof_spi_read_fifo_32; 980 } 981 982 /* transfer in fifo sized chunks */ 983 words = len / bytes_per_word; 984 985 while (words > 0) { 986 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, 987 words, bits); 988 if (n < 0) 989 return n; 990 991 if (tx_buf) 992 tx_buf += n * bytes_per_word; 993 if (rx_buf) 994 rx_buf += n * bytes_per_word; 995 words -= n; 996 } 997 998 return 0; 999 } 1000 1001 static const struct sh_msiof_chipdata sh_data = { 1002 .tx_fifo_size = 64, 1003 .rx_fifo_size = 64, 1004 .master_flags = 0, 1005 .min_div = 1, 1006 }; 1007 1008 static const struct sh_msiof_chipdata rcar_gen2_data = { 1009 .tx_fifo_size = 64, 1010 .rx_fifo_size = 64, 1011 .master_flags = SPI_MASTER_MUST_TX, 1012 .min_div = 1, 1013 }; 1014 1015 static const struct sh_msiof_chipdata rcar_gen3_data = { 1016 .tx_fifo_size = 64, 1017 .rx_fifo_size = 64, 1018 .master_flags = SPI_MASTER_MUST_TX, 1019 .min_div = 2, 1020 }; 1021 1022 static const struct of_device_id sh_msiof_match[] = { 1023 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, 1024 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data }, 1025 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data }, 1026 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data }, 1027 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data }, 1028 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data }, 1029 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data }, 1030 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data }, 1031 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data }, 1032 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data }, 1033 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data }, 1034 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */ 1035 {}, 1036 }; 1037 MODULE_DEVICE_TABLE(of, sh_msiof_match); 1038 1039 #ifdef CONFIG_OF 1040 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1041 { 1042 struct sh_msiof_spi_info *info; 1043 struct device_node *np = dev->of_node; 1044 u32 num_cs = 1; 1045 1046 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); 1047 if (!info) 1048 return NULL; 1049 1050 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE 1051 : MSIOF_SPI_MASTER; 1052 1053 /* Parse the MSIOF properties */ 1054 if (info->mode == MSIOF_SPI_MASTER) 1055 of_property_read_u32(np, "num-cs", &num_cs); 1056 of_property_read_u32(np, "renesas,tx-fifo-size", 1057 &info->tx_fifo_override); 1058 of_property_read_u32(np, "renesas,rx-fifo-size", 1059 &info->rx_fifo_override); 1060 of_property_read_u32(np, "renesas,dtdl", &info->dtdl); 1061 of_property_read_u32(np, "renesas,syncdl", &info->syncdl); 1062 1063 info->num_chipselect = num_cs; 1064 1065 return info; 1066 } 1067 #else 1068 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1069 { 1070 return NULL; 1071 } 1072 #endif 1073 1074 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, 1075 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) 1076 { 1077 dma_cap_mask_t mask; 1078 struct dma_chan *chan; 1079 struct dma_slave_config cfg; 1080 int ret; 1081 1082 dma_cap_zero(mask); 1083 dma_cap_set(DMA_SLAVE, mask); 1084 1085 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 1086 (void *)(unsigned long)id, dev, 1087 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1088 if (!chan) { 1089 dev_warn(dev, "dma_request_slave_channel_compat failed\n"); 1090 return NULL; 1091 } 1092 1093 memset(&cfg, 0, sizeof(cfg)); 1094 cfg.direction = dir; 1095 if (dir == DMA_MEM_TO_DEV) { 1096 cfg.dst_addr = port_addr; 1097 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1098 } else { 1099 cfg.src_addr = port_addr; 1100 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1101 } 1102 1103 ret = dmaengine_slave_config(chan, &cfg); 1104 if (ret) { 1105 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 1106 dma_release_channel(chan); 1107 return NULL; 1108 } 1109 1110 return chan; 1111 } 1112 1113 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) 1114 { 1115 struct platform_device *pdev = p->pdev; 1116 struct device *dev = &pdev->dev; 1117 const struct sh_msiof_spi_info *info = dev_get_platdata(dev); 1118 unsigned int dma_tx_id, dma_rx_id; 1119 const struct resource *res; 1120 struct spi_master *master; 1121 struct device *tx_dev, *rx_dev; 1122 1123 if (dev->of_node) { 1124 /* In the OF case we will get the slave IDs from the DT */ 1125 dma_tx_id = 0; 1126 dma_rx_id = 0; 1127 } else if (info && info->dma_tx_id && info->dma_rx_id) { 1128 dma_tx_id = info->dma_tx_id; 1129 dma_rx_id = info->dma_rx_id; 1130 } else { 1131 /* The driver assumes no error */ 1132 return 0; 1133 } 1134 1135 /* The DMA engine uses the second register set, if present */ 1136 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1137 if (!res) 1138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1139 1140 master = p->master; 1141 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, 1142 dma_tx_id, 1143 res->start + TFDR); 1144 if (!master->dma_tx) 1145 return -ENODEV; 1146 1147 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, 1148 dma_rx_id, 1149 res->start + RFDR); 1150 if (!master->dma_rx) 1151 goto free_tx_chan; 1152 1153 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1154 if (!p->tx_dma_page) 1155 goto free_rx_chan; 1156 1157 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1158 if (!p->rx_dma_page) 1159 goto free_tx_page; 1160 1161 tx_dev = master->dma_tx->device->dev; 1162 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, 1163 DMA_TO_DEVICE); 1164 if (dma_mapping_error(tx_dev, p->tx_dma_addr)) 1165 goto free_rx_page; 1166 1167 rx_dev = master->dma_rx->device->dev; 1168 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, 1169 DMA_FROM_DEVICE); 1170 if (dma_mapping_error(rx_dev, p->rx_dma_addr)) 1171 goto unmap_tx_page; 1172 1173 dev_info(dev, "DMA available"); 1174 return 0; 1175 1176 unmap_tx_page: 1177 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); 1178 free_rx_page: 1179 free_page((unsigned long)p->rx_dma_page); 1180 free_tx_page: 1181 free_page((unsigned long)p->tx_dma_page); 1182 free_rx_chan: 1183 dma_release_channel(master->dma_rx); 1184 free_tx_chan: 1185 dma_release_channel(master->dma_tx); 1186 master->dma_tx = NULL; 1187 return -ENODEV; 1188 } 1189 1190 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) 1191 { 1192 struct spi_master *master = p->master; 1193 1194 if (!master->dma_tx) 1195 return; 1196 1197 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr, 1198 PAGE_SIZE, DMA_FROM_DEVICE); 1199 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr, 1200 PAGE_SIZE, DMA_TO_DEVICE); 1201 free_page((unsigned long)p->rx_dma_page); 1202 free_page((unsigned long)p->tx_dma_page); 1203 dma_release_channel(master->dma_rx); 1204 dma_release_channel(master->dma_tx); 1205 } 1206 1207 static int sh_msiof_spi_probe(struct platform_device *pdev) 1208 { 1209 struct resource *r; 1210 struct spi_master *master; 1211 const struct sh_msiof_chipdata *chipdata; 1212 struct sh_msiof_spi_info *info; 1213 struct sh_msiof_spi_priv *p; 1214 int i; 1215 int ret; 1216 1217 chipdata = of_device_get_match_data(&pdev->dev); 1218 if (chipdata) { 1219 info = sh_msiof_spi_parse_dt(&pdev->dev); 1220 } else { 1221 chipdata = (const void *)pdev->id_entry->driver_data; 1222 info = dev_get_platdata(&pdev->dev); 1223 } 1224 1225 if (!info) { 1226 dev_err(&pdev->dev, "failed to obtain device info\n"); 1227 return -ENXIO; 1228 } 1229 1230 if (info->mode == MSIOF_SPI_SLAVE) 1231 master = spi_alloc_slave(&pdev->dev, 1232 sizeof(struct sh_msiof_spi_priv)); 1233 else 1234 master = spi_alloc_master(&pdev->dev, 1235 sizeof(struct sh_msiof_spi_priv)); 1236 if (master == NULL) 1237 return -ENOMEM; 1238 1239 p = spi_master_get_devdata(master); 1240 1241 platform_set_drvdata(pdev, p); 1242 p->master = master; 1243 p->info = info; 1244 p->min_div = chipdata->min_div; 1245 1246 init_completion(&p->done); 1247 1248 p->clk = devm_clk_get(&pdev->dev, NULL); 1249 if (IS_ERR(p->clk)) { 1250 dev_err(&pdev->dev, "cannot get clock\n"); 1251 ret = PTR_ERR(p->clk); 1252 goto err1; 1253 } 1254 1255 i = platform_get_irq(pdev, 0); 1256 if (i < 0) { 1257 dev_err(&pdev->dev, "cannot get platform IRQ\n"); 1258 ret = -ENOENT; 1259 goto err1; 1260 } 1261 1262 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1263 p->mapbase = devm_ioremap_resource(&pdev->dev, r); 1264 if (IS_ERR(p->mapbase)) { 1265 ret = PTR_ERR(p->mapbase); 1266 goto err1; 1267 } 1268 1269 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, 1270 dev_name(&pdev->dev), p); 1271 if (ret) { 1272 dev_err(&pdev->dev, "unable to request irq\n"); 1273 goto err1; 1274 } 1275 1276 p->pdev = pdev; 1277 pm_runtime_enable(&pdev->dev); 1278 1279 /* Platform data may override FIFO sizes */ 1280 p->tx_fifo_size = chipdata->tx_fifo_size; 1281 p->rx_fifo_size = chipdata->rx_fifo_size; 1282 if (p->info->tx_fifo_override) 1283 p->tx_fifo_size = p->info->tx_fifo_override; 1284 if (p->info->rx_fifo_override) 1285 p->rx_fifo_size = p->info->rx_fifo_override; 1286 1287 /* init master code */ 1288 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1289 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; 1290 master->flags = chipdata->master_flags; 1291 master->bus_num = pdev->id; 1292 master->dev.of_node = pdev->dev.of_node; 1293 master->num_chipselect = p->info->num_chipselect; 1294 master->setup = sh_msiof_spi_setup; 1295 master->prepare_message = sh_msiof_prepare_message; 1296 master->slave_abort = sh_msiof_slave_abort; 1297 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 1298 master->auto_runtime_pm = true; 1299 master->transfer_one = sh_msiof_transfer_one; 1300 1301 ret = sh_msiof_request_dma(p); 1302 if (ret < 0) 1303 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1304 1305 ret = devm_spi_register_master(&pdev->dev, master); 1306 if (ret < 0) { 1307 dev_err(&pdev->dev, "spi_register_master error.\n"); 1308 goto err2; 1309 } 1310 1311 return 0; 1312 1313 err2: 1314 sh_msiof_release_dma(p); 1315 pm_runtime_disable(&pdev->dev); 1316 err1: 1317 spi_master_put(master); 1318 return ret; 1319 } 1320 1321 static int sh_msiof_spi_remove(struct platform_device *pdev) 1322 { 1323 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); 1324 1325 sh_msiof_release_dma(p); 1326 pm_runtime_disable(&pdev->dev); 1327 return 0; 1328 } 1329 1330 static const struct platform_device_id spi_driver_ids[] = { 1331 { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, 1332 {}, 1333 }; 1334 MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1335 1336 static struct platform_driver sh_msiof_spi_drv = { 1337 .probe = sh_msiof_spi_probe, 1338 .remove = sh_msiof_spi_remove, 1339 .id_table = spi_driver_ids, 1340 .driver = { 1341 .name = "spi_sh_msiof", 1342 .of_match_table = of_match_ptr(sh_msiof_match), 1343 }, 1344 }; 1345 module_platform_driver(sh_msiof_spi_drv); 1346 1347 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); 1348 MODULE_AUTHOR("Magnus Damm"); 1349 MODULE_LICENSE("GPL v2"); 1350 MODULE_ALIAS("platform:spi_sh_msiof"); 1351