1 /* 2 * SuperH MSIOF SPI Master Interface 3 * 4 * Copyright (c) 2009 Magnus Damm 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 * Copyright (C) 2014-2017 Glider bvba 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 */ 13 14 #include <linux/bitmap.h> 15 #include <linux/clk.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/dmaengine.h> 20 #include <linux/err.h> 21 #include <linux/gpio.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/sh_dma.h> 32 33 #include <linux/spi/sh_msiof.h> 34 #include <linux/spi/spi.h> 35 36 #include <asm/unaligned.h> 37 38 struct sh_msiof_chipdata { 39 u16 tx_fifo_size; 40 u16 rx_fifo_size; 41 u16 master_flags; 42 u16 min_div; 43 }; 44 45 struct sh_msiof_spi_priv { 46 struct spi_master *master; 47 void __iomem *mapbase; 48 struct clk *clk; 49 struct platform_device *pdev; 50 struct sh_msiof_spi_info *info; 51 struct completion done; 52 unsigned int tx_fifo_size; 53 unsigned int rx_fifo_size; 54 unsigned int min_div; 55 void *tx_dma_page; 56 void *rx_dma_page; 57 dma_addr_t tx_dma_addr; 58 dma_addr_t rx_dma_addr; 59 unsigned short unused_ss; 60 bool native_cs_inited; 61 bool native_cs_high; 62 bool slave_aborted; 63 }; 64 65 #define MAX_SS 3 /* Maximum number of native chip selects */ 66 67 #define TMDR1 0x00 /* Transmit Mode Register 1 */ 68 #define TMDR2 0x04 /* Transmit Mode Register 2 */ 69 #define TMDR3 0x08 /* Transmit Mode Register 3 */ 70 #define RMDR1 0x10 /* Receive Mode Register 1 */ 71 #define RMDR2 0x14 /* Receive Mode Register 2 */ 72 #define RMDR3 0x18 /* Receive Mode Register 3 */ 73 #define TSCR 0x20 /* Transmit Clock Select Register */ 74 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ 75 #define CTR 0x28 /* Control Register */ 76 #define FCTR 0x30 /* FIFO Control Register */ 77 #define STR 0x40 /* Status Register */ 78 #define IER 0x44 /* Interrupt Enable Register */ 79 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ 80 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ 81 #define TFDR 0x50 /* Transmit FIFO Data Register */ 82 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ 83 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ 84 #define RFDR 0x60 /* Receive FIFO Data Register */ 85 86 /* TMDR1 and RMDR1 */ 87 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ 88 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ 89 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ 90 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ 91 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ 92 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ 93 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */ 94 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */ 95 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */ 96 #define MDR1_FLD_SHIFT 2 97 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ 98 /* TMDR1 */ 99 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ 100 #define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */ 101 #define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ 102 103 /* TMDR2 and RMDR2 */ 104 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ 105 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ 106 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ 107 108 /* TSCR and RSCR */ 109 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ 110 #define SCR_BRPS(i) (((i) - 1) << 8) 111 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ 112 #define SCR_BRDV_DIV_2 0x0000 113 #define SCR_BRDV_DIV_4 0x0001 114 #define SCR_BRDV_DIV_8 0x0002 115 #define SCR_BRDV_DIV_16 0x0003 116 #define SCR_BRDV_DIV_32 0x0004 117 #define SCR_BRDV_DIV_1 0x0007 118 119 /* CTR */ 120 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ 121 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ 122 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ 123 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ 124 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ 125 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ 126 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ 127 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ 128 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ 129 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ 130 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ 131 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ 132 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ 133 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ 134 #define CTR_TXE 0x00000200 /* Transmit Enable */ 135 #define CTR_RXE 0x00000100 /* Receive Enable */ 136 137 /* FCTR */ 138 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ 139 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */ 140 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */ 141 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */ 142 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */ 143 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */ 144 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */ 145 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */ 146 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */ 147 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */ 148 #define FCTR_TFUA_SHIFT 20 149 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT) 150 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */ 151 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */ 152 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */ 153 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */ 154 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */ 155 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */ 156 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */ 157 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */ 158 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */ 159 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */ 160 #define FCTR_RFUA_SHIFT 4 161 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT) 162 163 /* STR */ 164 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */ 165 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */ 166 #define STR_TEOF 0x00800000 /* Frame Transmission End */ 167 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */ 168 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */ 169 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */ 170 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */ 171 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */ 172 #define STR_REOF 0x00000080 /* Frame Reception End */ 173 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */ 174 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */ 175 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */ 176 177 /* IER */ 178 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */ 179 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */ 180 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */ 181 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */ 182 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */ 183 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */ 184 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */ 185 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */ 186 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */ 187 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */ 188 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */ 189 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */ 190 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */ 191 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */ 192 193 194 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) 195 { 196 switch (reg_offs) { 197 case TSCR: 198 case RSCR: 199 return ioread16(p->mapbase + reg_offs); 200 default: 201 return ioread32(p->mapbase + reg_offs); 202 } 203 } 204 205 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, 206 u32 value) 207 { 208 switch (reg_offs) { 209 case TSCR: 210 case RSCR: 211 iowrite16(value, p->mapbase + reg_offs); 212 break; 213 default: 214 iowrite32(value, p->mapbase + reg_offs); 215 break; 216 } 217 } 218 219 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, 220 u32 clr, u32 set) 221 { 222 u32 mask = clr | set; 223 u32 data; 224 int k; 225 226 data = sh_msiof_read(p, CTR); 227 data &= ~clr; 228 data |= set; 229 sh_msiof_write(p, CTR, data); 230 231 for (k = 100; k > 0; k--) { 232 if ((sh_msiof_read(p, CTR) & mask) == set) 233 break; 234 235 udelay(10); 236 } 237 238 return k > 0 ? 0 : -ETIMEDOUT; 239 } 240 241 static irqreturn_t sh_msiof_spi_irq(int irq, void *data) 242 { 243 struct sh_msiof_spi_priv *p = data; 244 245 /* just disable the interrupt and wake up */ 246 sh_msiof_write(p, IER, 0); 247 complete(&p->done); 248 249 return IRQ_HANDLED; 250 } 251 252 static struct { 253 unsigned short div; 254 unsigned short brdv; 255 } const sh_msiof_spi_div_table[] = { 256 { 1, SCR_BRDV_DIV_1 }, 257 { 2, SCR_BRDV_DIV_2 }, 258 { 4, SCR_BRDV_DIV_4 }, 259 { 8, SCR_BRDV_DIV_8 }, 260 { 16, SCR_BRDV_DIV_16 }, 261 { 32, SCR_BRDV_DIV_32 }, 262 }; 263 264 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 265 unsigned long parent_rate, u32 spi_hz) 266 { 267 unsigned long div = 1024; 268 u32 brps, scr; 269 size_t k; 270 271 if (!WARN_ON(!spi_hz || !parent_rate)) 272 div = DIV_ROUND_UP(parent_rate, spi_hz); 273 274 div = max_t(unsigned long, div, p->min_div); 275 276 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) { 277 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div); 278 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */ 279 if (sh_msiof_spi_div_table[k].div == 1 && brps > 2) 280 continue; 281 if (brps <= 32) /* max of brdv is 32 */ 282 break; 283 } 284 285 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1); 286 287 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps); 288 sh_msiof_write(p, TSCR, scr); 289 if (!(p->master->flags & SPI_MASTER_MUST_TX)) 290 sh_msiof_write(p, RSCR, scr); 291 } 292 293 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl) 294 { 295 /* 296 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl 297 * b'000 : 0 298 * b'001 : 100 299 * b'010 : 200 300 * b'011 (SYNCDL only) : 300 301 * b'101 : 50 302 * b'110 : 150 303 */ 304 if (dtdl_or_syncdl % 100) 305 return dtdl_or_syncdl / 100 + 5; 306 else 307 return dtdl_or_syncdl / 100; 308 } 309 310 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) 311 { 312 u32 val; 313 314 if (!p->info) 315 return 0; 316 317 /* check if DTDL and SYNCDL is allowed value */ 318 if (p->info->dtdl > 200 || p->info->syncdl > 300) { 319 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n"); 320 return 0; 321 } 322 323 /* check if the sum of DTDL and SYNCDL becomes an integer value */ 324 if ((p->info->dtdl + p->info->syncdl) % 100) { 325 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n"); 326 return 0; 327 } 328 329 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT; 330 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT; 331 332 return val; 333 } 334 335 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, 336 u32 cpol, u32 cpha, 337 u32 tx_hi_z, u32 lsb_first, u32 cs_high) 338 { 339 u32 tmp; 340 int edge; 341 342 /* 343 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG 344 * 0 0 10 10 1 1 345 * 0 1 10 10 0 0 346 * 1 0 11 11 0 0 347 * 1 1 11 11 1 1 348 */ 349 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; 350 tmp |= !cs_high << MDR1_SYNCAC_SHIFT; 351 tmp |= lsb_first << MDR1_BITLSB_SHIFT; 352 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); 353 if (spi_controller_is_slave(p->master)) { 354 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON); 355 } else { 356 sh_msiof_write(p, TMDR1, 357 tmp | MDR1_TRMD | TMDR1_PCON | 358 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT); 359 } 360 if (p->master->flags & SPI_MASTER_MUST_TX) { 361 /* These bits are reserved if RX needs TX */ 362 tmp &= ~0x0000ffff; 363 } 364 sh_msiof_write(p, RMDR1, tmp); 365 366 tmp = 0; 367 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; 368 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; 369 370 edge = cpol ^ !cpha; 371 372 tmp |= edge << CTR_TEDG_SHIFT; 373 tmp |= edge << CTR_REDG_SHIFT; 374 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; 375 sh_msiof_write(p, CTR, tmp); 376 } 377 378 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, 379 const void *tx_buf, void *rx_buf, 380 u32 bits, u32 words) 381 { 382 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); 383 384 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX)) 385 sh_msiof_write(p, TMDR2, dr2); 386 else 387 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); 388 389 if (rx_buf) 390 sh_msiof_write(p, RMDR2, dr2); 391 } 392 393 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) 394 { 395 sh_msiof_write(p, STR, sh_msiof_read(p, STR)); 396 } 397 398 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, 399 const void *tx_buf, int words, int fs) 400 { 401 const u8 *buf_8 = tx_buf; 402 int k; 403 404 for (k = 0; k < words; k++) 405 sh_msiof_write(p, TFDR, buf_8[k] << fs); 406 } 407 408 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, 409 const void *tx_buf, int words, int fs) 410 { 411 const u16 *buf_16 = tx_buf; 412 int k; 413 414 for (k = 0; k < words; k++) 415 sh_msiof_write(p, TFDR, buf_16[k] << fs); 416 } 417 418 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, 419 const void *tx_buf, int words, int fs) 420 { 421 const u16 *buf_16 = tx_buf; 422 int k; 423 424 for (k = 0; k < words; k++) 425 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); 426 } 427 428 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, 429 const void *tx_buf, int words, int fs) 430 { 431 const u32 *buf_32 = tx_buf; 432 int k; 433 434 for (k = 0; k < words; k++) 435 sh_msiof_write(p, TFDR, buf_32[k] << fs); 436 } 437 438 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, 439 const void *tx_buf, int words, int fs) 440 { 441 const u32 *buf_32 = tx_buf; 442 int k; 443 444 for (k = 0; k < words; k++) 445 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); 446 } 447 448 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, 449 const void *tx_buf, int words, int fs) 450 { 451 const u32 *buf_32 = tx_buf; 452 int k; 453 454 for (k = 0; k < words; k++) 455 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); 456 } 457 458 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, 459 const void *tx_buf, int words, int fs) 460 { 461 const u32 *buf_32 = tx_buf; 462 int k; 463 464 for (k = 0; k < words; k++) 465 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); 466 } 467 468 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, 469 void *rx_buf, int words, int fs) 470 { 471 u8 *buf_8 = rx_buf; 472 int k; 473 474 for (k = 0; k < words; k++) 475 buf_8[k] = sh_msiof_read(p, RFDR) >> fs; 476 } 477 478 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, 479 void *rx_buf, int words, int fs) 480 { 481 u16 *buf_16 = rx_buf; 482 int k; 483 484 for (k = 0; k < words; k++) 485 buf_16[k] = sh_msiof_read(p, RFDR) >> fs; 486 } 487 488 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, 489 void *rx_buf, int words, int fs) 490 { 491 u16 *buf_16 = rx_buf; 492 int k; 493 494 for (k = 0; k < words; k++) 495 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); 496 } 497 498 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, 499 void *rx_buf, int words, int fs) 500 { 501 u32 *buf_32 = rx_buf; 502 int k; 503 504 for (k = 0; k < words; k++) 505 buf_32[k] = sh_msiof_read(p, RFDR) >> fs; 506 } 507 508 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, 509 void *rx_buf, int words, int fs) 510 { 511 u32 *buf_32 = rx_buf; 512 int k; 513 514 for (k = 0; k < words; k++) 515 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); 516 } 517 518 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, 519 void *rx_buf, int words, int fs) 520 { 521 u32 *buf_32 = rx_buf; 522 int k; 523 524 for (k = 0; k < words; k++) 525 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); 526 } 527 528 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, 529 void *rx_buf, int words, int fs) 530 { 531 u32 *buf_32 = rx_buf; 532 int k; 533 534 for (k = 0; k < words; k++) 535 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); 536 } 537 538 static int sh_msiof_spi_setup(struct spi_device *spi) 539 { 540 struct device_node *np = spi->master->dev.of_node; 541 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); 542 u32 clr, set, tmp; 543 544 if (!np) { 545 /* 546 * Use spi->controller_data for CS (same strategy as spi_gpio), 547 * if any. otherwise let HW control CS 548 */ 549 spi->cs_gpio = (uintptr_t)spi->controller_data; 550 } 551 552 if (gpio_is_valid(spi->cs_gpio)) { 553 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 554 return 0; 555 } 556 557 if (spi_controller_is_slave(p->master)) 558 return 0; 559 560 if (p->native_cs_inited && 561 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH))) 562 return 0; 563 564 /* Configure native chip select mode/polarity early */ 565 clr = MDR1_SYNCMD_MASK; 566 set = MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI; 567 if (spi->mode & SPI_CS_HIGH) 568 clr |= BIT(MDR1_SYNCAC_SHIFT); 569 else 570 set |= BIT(MDR1_SYNCAC_SHIFT); 571 pm_runtime_get_sync(&p->pdev->dev); 572 tmp = sh_msiof_read(p, TMDR1) & ~clr; 573 sh_msiof_write(p, TMDR1, tmp | set); 574 pm_runtime_put(&p->pdev->dev); 575 p->native_cs_high = spi->mode & SPI_CS_HIGH; 576 p->native_cs_inited = true; 577 return 0; 578 } 579 580 static int sh_msiof_prepare_message(struct spi_master *master, 581 struct spi_message *msg) 582 { 583 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 584 const struct spi_device *spi = msg->spi; 585 u32 ss, cs_high; 586 587 /* Configure pins before asserting CS */ 588 if (gpio_is_valid(spi->cs_gpio)) { 589 ss = p->unused_ss; 590 cs_high = p->native_cs_high; 591 } else { 592 ss = spi->chip_select; 593 cs_high = !!(spi->mode & SPI_CS_HIGH); 594 } 595 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL), 596 !!(spi->mode & SPI_CPHA), 597 !!(spi->mode & SPI_3WIRE), 598 !!(spi->mode & SPI_LSB_FIRST), cs_high); 599 return 0; 600 } 601 602 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) 603 { 604 bool slave = spi_controller_is_slave(p->master); 605 int ret = 0; 606 607 /* setup clock and rx/tx signals */ 608 if (!slave) 609 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); 610 if (rx_buf && !ret) 611 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); 612 if (!ret) 613 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); 614 615 /* start by setting frame bit */ 616 if (!ret && !slave) 617 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); 618 619 return ret; 620 } 621 622 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) 623 { 624 bool slave = spi_controller_is_slave(p->master); 625 int ret = 0; 626 627 /* shut down frame, rx/tx and clock signals */ 628 if (!slave) 629 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); 630 if (!ret) 631 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); 632 if (rx_buf && !ret) 633 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); 634 if (!ret && !slave) 635 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); 636 637 return ret; 638 } 639 640 static int sh_msiof_slave_abort(struct spi_master *master) 641 { 642 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 643 644 p->slave_aborted = true; 645 complete(&p->done); 646 return 0; 647 } 648 649 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p) 650 { 651 if (spi_controller_is_slave(p->master)) { 652 if (wait_for_completion_interruptible(&p->done) || 653 p->slave_aborted) { 654 dev_dbg(&p->pdev->dev, "interrupted\n"); 655 return -EINTR; 656 } 657 } else { 658 if (!wait_for_completion_timeout(&p->done, HZ)) { 659 dev_err(&p->pdev->dev, "timeout\n"); 660 return -ETIMEDOUT; 661 } 662 } 663 664 return 0; 665 } 666 667 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, 668 void (*tx_fifo)(struct sh_msiof_spi_priv *, 669 const void *, int, int), 670 void (*rx_fifo)(struct sh_msiof_spi_priv *, 671 void *, int, int), 672 const void *tx_buf, void *rx_buf, 673 int words, int bits) 674 { 675 int fifo_shift; 676 int ret; 677 678 /* limit maximum word transfer to rx/tx fifo size */ 679 if (tx_buf) 680 words = min_t(int, words, p->tx_fifo_size); 681 if (rx_buf) 682 words = min_t(int, words, p->rx_fifo_size); 683 684 /* the fifo contents need shifting */ 685 fifo_shift = 32 - bits; 686 687 /* default FIFO watermarks for PIO */ 688 sh_msiof_write(p, FCTR, 0); 689 690 /* setup msiof transfer mode registers */ 691 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); 692 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE); 693 694 /* write tx fifo */ 695 if (tx_buf) 696 tx_fifo(p, tx_buf, words, fifo_shift); 697 698 reinit_completion(&p->done); 699 p->slave_aborted = false; 700 701 ret = sh_msiof_spi_start(p, rx_buf); 702 if (ret) { 703 dev_err(&p->pdev->dev, "failed to start hardware\n"); 704 goto stop_ier; 705 } 706 707 /* wait for tx fifo to be emptied / rx fifo to be filled */ 708 ret = sh_msiof_wait_for_completion(p); 709 if (ret) 710 goto stop_reset; 711 712 /* read rx fifo */ 713 if (rx_buf) 714 rx_fifo(p, rx_buf, words, fifo_shift); 715 716 /* clear status bits */ 717 sh_msiof_reset_str(p); 718 719 ret = sh_msiof_spi_stop(p, rx_buf); 720 if (ret) { 721 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 722 return ret; 723 } 724 725 return words; 726 727 stop_reset: 728 sh_msiof_reset_str(p); 729 sh_msiof_spi_stop(p, rx_buf); 730 stop_ier: 731 sh_msiof_write(p, IER, 0); 732 return ret; 733 } 734 735 static void sh_msiof_dma_complete(void *arg) 736 { 737 struct sh_msiof_spi_priv *p = arg; 738 739 sh_msiof_write(p, IER, 0); 740 complete(&p->done); 741 } 742 743 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, 744 void *rx, unsigned int len) 745 { 746 u32 ier_bits = 0; 747 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 748 dma_cookie_t cookie; 749 int ret; 750 751 /* First prepare and submit the DMA request(s), as this may fail */ 752 if (rx) { 753 ier_bits |= IER_RDREQE | IER_RDMAE; 754 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, 755 p->rx_dma_addr, len, DMA_FROM_DEVICE, 756 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 757 if (!desc_rx) 758 return -EAGAIN; 759 760 desc_rx->callback = sh_msiof_dma_complete; 761 desc_rx->callback_param = p; 762 cookie = dmaengine_submit(desc_rx); 763 if (dma_submit_error(cookie)) 764 return cookie; 765 } 766 767 if (tx) { 768 ier_bits |= IER_TDREQE | IER_TDMAE; 769 dma_sync_single_for_device(p->master->dma_tx->device->dev, 770 p->tx_dma_addr, len, DMA_TO_DEVICE); 771 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx, 772 p->tx_dma_addr, len, DMA_TO_DEVICE, 773 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 774 if (!desc_tx) { 775 ret = -EAGAIN; 776 goto no_dma_tx; 777 } 778 779 if (rx) { 780 /* No callback */ 781 desc_tx->callback = NULL; 782 } else { 783 desc_tx->callback = sh_msiof_dma_complete; 784 desc_tx->callback_param = p; 785 } 786 cookie = dmaengine_submit(desc_tx); 787 if (dma_submit_error(cookie)) { 788 ret = cookie; 789 goto no_dma_tx; 790 } 791 } 792 793 /* 1 stage FIFO watermarks for DMA */ 794 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1); 795 796 /* setup msiof transfer mode registers (32-bit words) */ 797 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); 798 799 sh_msiof_write(p, IER, ier_bits); 800 801 reinit_completion(&p->done); 802 p->slave_aborted = false; 803 804 /* Now start DMA */ 805 if (rx) 806 dma_async_issue_pending(p->master->dma_rx); 807 if (tx) 808 dma_async_issue_pending(p->master->dma_tx); 809 810 ret = sh_msiof_spi_start(p, rx); 811 if (ret) { 812 dev_err(&p->pdev->dev, "failed to start hardware\n"); 813 goto stop_dma; 814 } 815 816 /* wait for tx/rx DMA completion */ 817 ret = sh_msiof_wait_for_completion(p); 818 if (ret) 819 goto stop_reset; 820 821 if (!rx) { 822 reinit_completion(&p->done); 823 sh_msiof_write(p, IER, IER_TEOFE); 824 825 /* wait for tx fifo to be emptied */ 826 ret = sh_msiof_wait_for_completion(p); 827 if (ret) 828 goto stop_reset; 829 } 830 831 /* clear status bits */ 832 sh_msiof_reset_str(p); 833 834 ret = sh_msiof_spi_stop(p, rx); 835 if (ret) { 836 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 837 return ret; 838 } 839 840 if (rx) 841 dma_sync_single_for_cpu(p->master->dma_rx->device->dev, 842 p->rx_dma_addr, len, 843 DMA_FROM_DEVICE); 844 845 return 0; 846 847 stop_reset: 848 sh_msiof_reset_str(p); 849 sh_msiof_spi_stop(p, rx); 850 stop_dma: 851 if (tx) 852 dmaengine_terminate_all(p->master->dma_tx); 853 no_dma_tx: 854 if (rx) 855 dmaengine_terminate_all(p->master->dma_rx); 856 sh_msiof_write(p, IER, 0); 857 return ret; 858 } 859 860 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) 861 { 862 /* src or dst can be unaligned, but not both */ 863 if ((unsigned long)src & 3) { 864 while (words--) { 865 *dst++ = swab32(get_unaligned(src)); 866 src++; 867 } 868 } else if ((unsigned long)dst & 3) { 869 while (words--) { 870 put_unaligned(swab32(*src++), dst); 871 dst++; 872 } 873 } else { 874 while (words--) 875 *dst++ = swab32(*src++); 876 } 877 } 878 879 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) 880 { 881 /* src or dst can be unaligned, but not both */ 882 if ((unsigned long)src & 3) { 883 while (words--) { 884 *dst++ = swahw32(get_unaligned(src)); 885 src++; 886 } 887 } else if ((unsigned long)dst & 3) { 888 while (words--) { 889 put_unaligned(swahw32(*src++), dst); 890 dst++; 891 } 892 } else { 893 while (words--) 894 *dst++ = swahw32(*src++); 895 } 896 } 897 898 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) 899 { 900 memcpy(dst, src, words * 4); 901 } 902 903 static int sh_msiof_transfer_one(struct spi_master *master, 904 struct spi_device *spi, 905 struct spi_transfer *t) 906 { 907 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 908 void (*copy32)(u32 *, const u32 *, unsigned int); 909 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); 910 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); 911 const void *tx_buf = t->tx_buf; 912 void *rx_buf = t->rx_buf; 913 unsigned int len = t->len; 914 unsigned int bits = t->bits_per_word; 915 unsigned int bytes_per_word; 916 unsigned int words; 917 int n; 918 bool swab; 919 int ret; 920 921 /* setup clocks (clock already enabled in chipselect()) */ 922 if (!spi_controller_is_slave(p->master)) 923 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); 924 925 while (master->dma_tx && len > 15) { 926 /* 927 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit 928 * words, with byte resp. word swapping. 929 */ 930 unsigned int l = 0; 931 932 if (tx_buf) 933 l = min(len, p->tx_fifo_size * 4); 934 if (rx_buf) 935 l = min(len, p->rx_fifo_size * 4); 936 937 if (bits <= 8) { 938 if (l & 3) 939 break; 940 copy32 = copy_bswap32; 941 } else if (bits <= 16) { 942 if (l & 3) 943 break; 944 copy32 = copy_wswap32; 945 } else { 946 copy32 = copy_plain32; 947 } 948 949 if (tx_buf) 950 copy32(p->tx_dma_page, tx_buf, l / 4); 951 952 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); 953 if (ret == -EAGAIN) { 954 dev_warn_once(&p->pdev->dev, 955 "DMA not available, falling back to PIO\n"); 956 break; 957 } 958 if (ret) 959 return ret; 960 961 if (rx_buf) { 962 copy32(rx_buf, p->rx_dma_page, l / 4); 963 rx_buf += l; 964 } 965 if (tx_buf) 966 tx_buf += l; 967 968 len -= l; 969 if (!len) 970 return 0; 971 } 972 973 if (bits <= 8 && len > 15 && !(len & 3)) { 974 bits = 32; 975 swab = true; 976 } else { 977 swab = false; 978 } 979 980 /* setup bytes per word and fifo read/write functions */ 981 if (bits <= 8) { 982 bytes_per_word = 1; 983 tx_fifo = sh_msiof_spi_write_fifo_8; 984 rx_fifo = sh_msiof_spi_read_fifo_8; 985 } else if (bits <= 16) { 986 bytes_per_word = 2; 987 if ((unsigned long)tx_buf & 0x01) 988 tx_fifo = sh_msiof_spi_write_fifo_16u; 989 else 990 tx_fifo = sh_msiof_spi_write_fifo_16; 991 992 if ((unsigned long)rx_buf & 0x01) 993 rx_fifo = sh_msiof_spi_read_fifo_16u; 994 else 995 rx_fifo = sh_msiof_spi_read_fifo_16; 996 } else if (swab) { 997 bytes_per_word = 4; 998 if ((unsigned long)tx_buf & 0x03) 999 tx_fifo = sh_msiof_spi_write_fifo_s32u; 1000 else 1001 tx_fifo = sh_msiof_spi_write_fifo_s32; 1002 1003 if ((unsigned long)rx_buf & 0x03) 1004 rx_fifo = sh_msiof_spi_read_fifo_s32u; 1005 else 1006 rx_fifo = sh_msiof_spi_read_fifo_s32; 1007 } else { 1008 bytes_per_word = 4; 1009 if ((unsigned long)tx_buf & 0x03) 1010 tx_fifo = sh_msiof_spi_write_fifo_32u; 1011 else 1012 tx_fifo = sh_msiof_spi_write_fifo_32; 1013 1014 if ((unsigned long)rx_buf & 0x03) 1015 rx_fifo = sh_msiof_spi_read_fifo_32u; 1016 else 1017 rx_fifo = sh_msiof_spi_read_fifo_32; 1018 } 1019 1020 /* transfer in fifo sized chunks */ 1021 words = len / bytes_per_word; 1022 1023 while (words > 0) { 1024 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, 1025 words, bits); 1026 if (n < 0) 1027 return n; 1028 1029 if (tx_buf) 1030 tx_buf += n * bytes_per_word; 1031 if (rx_buf) 1032 rx_buf += n * bytes_per_word; 1033 words -= n; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static const struct sh_msiof_chipdata sh_data = { 1040 .tx_fifo_size = 64, 1041 .rx_fifo_size = 64, 1042 .master_flags = 0, 1043 .min_div = 1, 1044 }; 1045 1046 static const struct sh_msiof_chipdata rcar_gen2_data = { 1047 .tx_fifo_size = 64, 1048 .rx_fifo_size = 64, 1049 .master_flags = SPI_MASTER_MUST_TX, 1050 .min_div = 1, 1051 }; 1052 1053 static const struct sh_msiof_chipdata rcar_gen3_data = { 1054 .tx_fifo_size = 64, 1055 .rx_fifo_size = 64, 1056 .master_flags = SPI_MASTER_MUST_TX, 1057 .min_div = 2, 1058 }; 1059 1060 static const struct of_device_id sh_msiof_match[] = { 1061 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, 1062 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data }, 1063 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data }, 1064 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data }, 1065 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data }, 1066 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data }, 1067 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data }, 1068 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data }, 1069 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data }, 1070 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data }, 1071 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data }, 1072 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */ 1073 {}, 1074 }; 1075 MODULE_DEVICE_TABLE(of, sh_msiof_match); 1076 1077 #ifdef CONFIG_OF 1078 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1079 { 1080 struct sh_msiof_spi_info *info; 1081 struct device_node *np = dev->of_node; 1082 u32 num_cs = 1; 1083 1084 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); 1085 if (!info) 1086 return NULL; 1087 1088 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE 1089 : MSIOF_SPI_MASTER; 1090 1091 /* Parse the MSIOF properties */ 1092 if (info->mode == MSIOF_SPI_MASTER) 1093 of_property_read_u32(np, "num-cs", &num_cs); 1094 of_property_read_u32(np, "renesas,tx-fifo-size", 1095 &info->tx_fifo_override); 1096 of_property_read_u32(np, "renesas,rx-fifo-size", 1097 &info->rx_fifo_override); 1098 of_property_read_u32(np, "renesas,dtdl", &info->dtdl); 1099 of_property_read_u32(np, "renesas,syncdl", &info->syncdl); 1100 1101 info->num_chipselect = num_cs; 1102 1103 return info; 1104 } 1105 #else 1106 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1107 { 1108 return NULL; 1109 } 1110 #endif 1111 1112 static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p) 1113 { 1114 struct device *dev = &p->pdev->dev; 1115 unsigned int used_ss_mask = 0; 1116 unsigned int cs_gpios = 0; 1117 unsigned int num_cs, i; 1118 int ret; 1119 1120 ret = gpiod_count(dev, "cs"); 1121 if (ret <= 0) 1122 return 0; 1123 1124 num_cs = max_t(unsigned int, ret, p->master->num_chipselect); 1125 for (i = 0; i < num_cs; i++) { 1126 struct gpio_desc *gpiod; 1127 1128 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS); 1129 if (!IS_ERR(gpiod)) { 1130 cs_gpios++; 1131 continue; 1132 } 1133 1134 if (PTR_ERR(gpiod) != -ENOENT) 1135 return PTR_ERR(gpiod); 1136 1137 if (i >= MAX_SS) { 1138 dev_err(dev, "Invalid native chip select %d\n", i); 1139 return -EINVAL; 1140 } 1141 used_ss_mask |= BIT(i); 1142 } 1143 p->unused_ss = ffz(used_ss_mask); 1144 if (cs_gpios && p->unused_ss >= MAX_SS) { 1145 dev_err(dev, "No unused native chip select available\n"); 1146 return -EINVAL; 1147 } 1148 return 0; 1149 } 1150 1151 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, 1152 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) 1153 { 1154 dma_cap_mask_t mask; 1155 struct dma_chan *chan; 1156 struct dma_slave_config cfg; 1157 int ret; 1158 1159 dma_cap_zero(mask); 1160 dma_cap_set(DMA_SLAVE, mask); 1161 1162 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 1163 (void *)(unsigned long)id, dev, 1164 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1165 if (!chan) { 1166 dev_warn(dev, "dma_request_slave_channel_compat failed\n"); 1167 return NULL; 1168 } 1169 1170 memset(&cfg, 0, sizeof(cfg)); 1171 cfg.direction = dir; 1172 if (dir == DMA_MEM_TO_DEV) { 1173 cfg.dst_addr = port_addr; 1174 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1175 } else { 1176 cfg.src_addr = port_addr; 1177 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1178 } 1179 1180 ret = dmaengine_slave_config(chan, &cfg); 1181 if (ret) { 1182 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 1183 dma_release_channel(chan); 1184 return NULL; 1185 } 1186 1187 return chan; 1188 } 1189 1190 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) 1191 { 1192 struct platform_device *pdev = p->pdev; 1193 struct device *dev = &pdev->dev; 1194 const struct sh_msiof_spi_info *info = dev_get_platdata(dev); 1195 unsigned int dma_tx_id, dma_rx_id; 1196 const struct resource *res; 1197 struct spi_master *master; 1198 struct device *tx_dev, *rx_dev; 1199 1200 if (dev->of_node) { 1201 /* In the OF case we will get the slave IDs from the DT */ 1202 dma_tx_id = 0; 1203 dma_rx_id = 0; 1204 } else if (info && info->dma_tx_id && info->dma_rx_id) { 1205 dma_tx_id = info->dma_tx_id; 1206 dma_rx_id = info->dma_rx_id; 1207 } else { 1208 /* The driver assumes no error */ 1209 return 0; 1210 } 1211 1212 /* The DMA engine uses the second register set, if present */ 1213 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1214 if (!res) 1215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1216 1217 master = p->master; 1218 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, 1219 dma_tx_id, 1220 res->start + TFDR); 1221 if (!master->dma_tx) 1222 return -ENODEV; 1223 1224 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, 1225 dma_rx_id, 1226 res->start + RFDR); 1227 if (!master->dma_rx) 1228 goto free_tx_chan; 1229 1230 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1231 if (!p->tx_dma_page) 1232 goto free_rx_chan; 1233 1234 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1235 if (!p->rx_dma_page) 1236 goto free_tx_page; 1237 1238 tx_dev = master->dma_tx->device->dev; 1239 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, 1240 DMA_TO_DEVICE); 1241 if (dma_mapping_error(tx_dev, p->tx_dma_addr)) 1242 goto free_rx_page; 1243 1244 rx_dev = master->dma_rx->device->dev; 1245 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, 1246 DMA_FROM_DEVICE); 1247 if (dma_mapping_error(rx_dev, p->rx_dma_addr)) 1248 goto unmap_tx_page; 1249 1250 dev_info(dev, "DMA available"); 1251 return 0; 1252 1253 unmap_tx_page: 1254 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); 1255 free_rx_page: 1256 free_page((unsigned long)p->rx_dma_page); 1257 free_tx_page: 1258 free_page((unsigned long)p->tx_dma_page); 1259 free_rx_chan: 1260 dma_release_channel(master->dma_rx); 1261 free_tx_chan: 1262 dma_release_channel(master->dma_tx); 1263 master->dma_tx = NULL; 1264 return -ENODEV; 1265 } 1266 1267 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) 1268 { 1269 struct spi_master *master = p->master; 1270 1271 if (!master->dma_tx) 1272 return; 1273 1274 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr, 1275 PAGE_SIZE, DMA_FROM_DEVICE); 1276 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr, 1277 PAGE_SIZE, DMA_TO_DEVICE); 1278 free_page((unsigned long)p->rx_dma_page); 1279 free_page((unsigned long)p->tx_dma_page); 1280 dma_release_channel(master->dma_rx); 1281 dma_release_channel(master->dma_tx); 1282 } 1283 1284 static int sh_msiof_spi_probe(struct platform_device *pdev) 1285 { 1286 struct resource *r; 1287 struct spi_master *master; 1288 const struct sh_msiof_chipdata *chipdata; 1289 struct sh_msiof_spi_info *info; 1290 struct sh_msiof_spi_priv *p; 1291 int i; 1292 int ret; 1293 1294 chipdata = of_device_get_match_data(&pdev->dev); 1295 if (chipdata) { 1296 info = sh_msiof_spi_parse_dt(&pdev->dev); 1297 } else { 1298 chipdata = (const void *)pdev->id_entry->driver_data; 1299 info = dev_get_platdata(&pdev->dev); 1300 } 1301 1302 if (!info) { 1303 dev_err(&pdev->dev, "failed to obtain device info\n"); 1304 return -ENXIO; 1305 } 1306 1307 if (info->mode == MSIOF_SPI_SLAVE) 1308 master = spi_alloc_slave(&pdev->dev, 1309 sizeof(struct sh_msiof_spi_priv)); 1310 else 1311 master = spi_alloc_master(&pdev->dev, 1312 sizeof(struct sh_msiof_spi_priv)); 1313 if (master == NULL) 1314 return -ENOMEM; 1315 1316 p = spi_master_get_devdata(master); 1317 1318 platform_set_drvdata(pdev, p); 1319 p->master = master; 1320 p->info = info; 1321 p->min_div = chipdata->min_div; 1322 1323 init_completion(&p->done); 1324 1325 p->clk = devm_clk_get(&pdev->dev, NULL); 1326 if (IS_ERR(p->clk)) { 1327 dev_err(&pdev->dev, "cannot get clock\n"); 1328 ret = PTR_ERR(p->clk); 1329 goto err1; 1330 } 1331 1332 i = platform_get_irq(pdev, 0); 1333 if (i < 0) { 1334 dev_err(&pdev->dev, "cannot get platform IRQ\n"); 1335 ret = -ENOENT; 1336 goto err1; 1337 } 1338 1339 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1340 p->mapbase = devm_ioremap_resource(&pdev->dev, r); 1341 if (IS_ERR(p->mapbase)) { 1342 ret = PTR_ERR(p->mapbase); 1343 goto err1; 1344 } 1345 1346 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, 1347 dev_name(&pdev->dev), p); 1348 if (ret) { 1349 dev_err(&pdev->dev, "unable to request irq\n"); 1350 goto err1; 1351 } 1352 1353 p->pdev = pdev; 1354 pm_runtime_enable(&pdev->dev); 1355 1356 /* Platform data may override FIFO sizes */ 1357 p->tx_fifo_size = chipdata->tx_fifo_size; 1358 p->rx_fifo_size = chipdata->rx_fifo_size; 1359 if (p->info->tx_fifo_override) 1360 p->tx_fifo_size = p->info->tx_fifo_override; 1361 if (p->info->rx_fifo_override) 1362 p->rx_fifo_size = p->info->rx_fifo_override; 1363 1364 /* Setup GPIO chip selects */ 1365 master->num_chipselect = p->info->num_chipselect; 1366 ret = sh_msiof_get_cs_gpios(p); 1367 if (ret) 1368 goto err1; 1369 1370 /* init master code */ 1371 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1372 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; 1373 master->flags = chipdata->master_flags; 1374 master->bus_num = pdev->id; 1375 master->dev.of_node = pdev->dev.of_node; 1376 master->setup = sh_msiof_spi_setup; 1377 master->prepare_message = sh_msiof_prepare_message; 1378 master->slave_abort = sh_msiof_slave_abort; 1379 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 1380 master->auto_runtime_pm = true; 1381 master->transfer_one = sh_msiof_transfer_one; 1382 1383 ret = sh_msiof_request_dma(p); 1384 if (ret < 0) 1385 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1386 1387 ret = devm_spi_register_master(&pdev->dev, master); 1388 if (ret < 0) { 1389 dev_err(&pdev->dev, "spi_register_master error.\n"); 1390 goto err2; 1391 } 1392 1393 return 0; 1394 1395 err2: 1396 sh_msiof_release_dma(p); 1397 pm_runtime_disable(&pdev->dev); 1398 err1: 1399 spi_master_put(master); 1400 return ret; 1401 } 1402 1403 static int sh_msiof_spi_remove(struct platform_device *pdev) 1404 { 1405 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); 1406 1407 sh_msiof_release_dma(p); 1408 pm_runtime_disable(&pdev->dev); 1409 return 0; 1410 } 1411 1412 static const struct platform_device_id spi_driver_ids[] = { 1413 { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, 1414 {}, 1415 }; 1416 MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1417 1418 static struct platform_driver sh_msiof_spi_drv = { 1419 .probe = sh_msiof_spi_probe, 1420 .remove = sh_msiof_spi_remove, 1421 .id_table = spi_driver_ids, 1422 .driver = { 1423 .name = "spi_sh_msiof", 1424 .of_match_table = of_match_ptr(sh_msiof_match), 1425 }, 1426 }; 1427 module_platform_driver(sh_msiof_spi_drv); 1428 1429 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); 1430 MODULE_AUTHOR("Magnus Damm"); 1431 MODULE_LICENSE("GPL v2"); 1432 MODULE_ALIAS("platform:spi_sh_msiof"); 1433