1 /* 2 * SuperH MSIOF SPI Master Interface 3 * 4 * Copyright (c) 2009 Magnus Damm 5 * Copyright (C) 2014 Glider bvba 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 */ 12 13 #include <linux/bitmap.h> 14 #include <linux/clk.h> 15 #include <linux/completion.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/dmaengine.h> 19 #include <linux/err.h> 20 #include <linux/gpio.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/sh_dma.h> 30 31 #include <linux/spi/sh_msiof.h> 32 #include <linux/spi/spi.h> 33 34 #include <asm/unaligned.h> 35 36 37 struct sh_msiof_chipdata { 38 u16 tx_fifo_size; 39 u16 rx_fifo_size; 40 u16 master_flags; 41 }; 42 43 struct sh_msiof_spi_priv { 44 struct spi_master *master; 45 void __iomem *mapbase; 46 struct clk *clk; 47 struct platform_device *pdev; 48 const struct sh_msiof_chipdata *chipdata; 49 struct sh_msiof_spi_info *info; 50 struct completion done; 51 int tx_fifo_size; 52 int rx_fifo_size; 53 void *tx_dma_page; 54 void *rx_dma_page; 55 dma_addr_t tx_dma_addr; 56 dma_addr_t rx_dma_addr; 57 }; 58 59 #define TMDR1 0x00 /* Transmit Mode Register 1 */ 60 #define TMDR2 0x04 /* Transmit Mode Register 2 */ 61 #define TMDR3 0x08 /* Transmit Mode Register 3 */ 62 #define RMDR1 0x10 /* Receive Mode Register 1 */ 63 #define RMDR2 0x14 /* Receive Mode Register 2 */ 64 #define RMDR3 0x18 /* Receive Mode Register 3 */ 65 #define TSCR 0x20 /* Transmit Clock Select Register */ 66 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ 67 #define CTR 0x28 /* Control Register */ 68 #define FCTR 0x30 /* FIFO Control Register */ 69 #define STR 0x40 /* Status Register */ 70 #define IER 0x44 /* Interrupt Enable Register */ 71 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ 72 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ 73 #define TFDR 0x50 /* Transmit FIFO Data Register */ 74 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ 75 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ 76 #define RFDR 0x60 /* Receive FIFO Data Register */ 77 78 /* TMDR1 and RMDR1 */ 79 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ 80 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ 81 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ 82 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ 83 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ 84 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ 85 #define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ 86 #define MDR1_FLD_SHIFT 2 87 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ 88 /* TMDR1 */ 89 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ 90 91 /* TMDR2 and RMDR2 */ 92 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ 93 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ 94 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ 95 96 #define MAX_WDLEN 256U 97 98 /* TSCR and RSCR */ 99 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ 100 #define SCR_BRPS(i) (((i) - 1) << 8) 101 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ 102 #define SCR_BRDV_DIV_2 0x0000 103 #define SCR_BRDV_DIV_4 0x0001 104 #define SCR_BRDV_DIV_8 0x0002 105 #define SCR_BRDV_DIV_16 0x0003 106 #define SCR_BRDV_DIV_32 0x0004 107 #define SCR_BRDV_DIV_1 0x0007 108 109 /* CTR */ 110 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ 111 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ 112 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ 113 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ 114 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ 115 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ 116 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ 117 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ 118 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ 119 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ 120 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ 121 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ 122 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ 123 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ 124 #define CTR_TXE 0x00000200 /* Transmit Enable */ 125 #define CTR_RXE 0x00000100 /* Receive Enable */ 126 127 /* FCTR */ 128 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ 129 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */ 130 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */ 131 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */ 132 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */ 133 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */ 134 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */ 135 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */ 136 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */ 137 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */ 138 #define FCTR_TFUA_SHIFT 20 139 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT) 140 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */ 141 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */ 142 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */ 143 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */ 144 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */ 145 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */ 146 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */ 147 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */ 148 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */ 149 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */ 150 #define FCTR_RFUA_SHIFT 4 151 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT) 152 153 /* STR */ 154 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */ 155 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */ 156 #define STR_TEOF 0x00800000 /* Frame Transmission End */ 157 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */ 158 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */ 159 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */ 160 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */ 161 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */ 162 #define STR_REOF 0x00000080 /* Frame Reception End */ 163 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */ 164 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */ 165 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */ 166 167 /* IER */ 168 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */ 169 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */ 170 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */ 171 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */ 172 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */ 173 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */ 174 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */ 175 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */ 176 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */ 177 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */ 178 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */ 179 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */ 180 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */ 181 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */ 182 183 184 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) 185 { 186 switch (reg_offs) { 187 case TSCR: 188 case RSCR: 189 return ioread16(p->mapbase + reg_offs); 190 default: 191 return ioread32(p->mapbase + reg_offs); 192 } 193 } 194 195 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, 196 u32 value) 197 { 198 switch (reg_offs) { 199 case TSCR: 200 case RSCR: 201 iowrite16(value, p->mapbase + reg_offs); 202 break; 203 default: 204 iowrite32(value, p->mapbase + reg_offs); 205 break; 206 } 207 } 208 209 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, 210 u32 clr, u32 set) 211 { 212 u32 mask = clr | set; 213 u32 data; 214 int k; 215 216 data = sh_msiof_read(p, CTR); 217 data &= ~clr; 218 data |= set; 219 sh_msiof_write(p, CTR, data); 220 221 for (k = 100; k > 0; k--) { 222 if ((sh_msiof_read(p, CTR) & mask) == set) 223 break; 224 225 udelay(10); 226 } 227 228 return k > 0 ? 0 : -ETIMEDOUT; 229 } 230 231 static irqreturn_t sh_msiof_spi_irq(int irq, void *data) 232 { 233 struct sh_msiof_spi_priv *p = data; 234 235 /* just disable the interrupt and wake up */ 236 sh_msiof_write(p, IER, 0); 237 complete(&p->done); 238 239 return IRQ_HANDLED; 240 } 241 242 static struct { 243 unsigned short div; 244 unsigned short scr; 245 } const sh_msiof_spi_clk_table[] = { 246 { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, 247 { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, 248 { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, 249 { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, 250 { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, 251 { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, 252 { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, 253 { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, 254 { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, 255 { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, 256 { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, 257 }; 258 259 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 260 unsigned long parent_rate, u32 spi_hz) 261 { 262 unsigned long div = 1024; 263 size_t k; 264 265 if (!WARN_ON(!spi_hz || !parent_rate)) 266 div = DIV_ROUND_UP(parent_rate, spi_hz); 267 268 /* TODO: make more fine grained */ 269 270 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { 271 if (sh_msiof_spi_clk_table[k].div >= div) 272 break; 273 } 274 275 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); 276 277 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); 278 if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) 279 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); 280 } 281 282 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, 283 u32 cpol, u32 cpha, 284 u32 tx_hi_z, u32 lsb_first, u32 cs_high) 285 { 286 u32 tmp; 287 int edge; 288 289 /* 290 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG 291 * 0 0 10 10 1 1 292 * 0 1 10 10 0 0 293 * 1 0 11 11 0 0 294 * 1 1 11 11 1 1 295 */ 296 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; 297 tmp |= !cs_high << MDR1_SYNCAC_SHIFT; 298 tmp |= lsb_first << MDR1_BITLSB_SHIFT; 299 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); 300 if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { 301 /* These bits are reserved if RX needs TX */ 302 tmp &= ~0x0000ffff; 303 } 304 sh_msiof_write(p, RMDR1, tmp); 305 306 tmp = 0; 307 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; 308 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; 309 310 edge = cpol ^ !cpha; 311 312 tmp |= edge << CTR_TEDG_SHIFT; 313 tmp |= edge << CTR_REDG_SHIFT; 314 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; 315 sh_msiof_write(p, CTR, tmp); 316 } 317 318 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, 319 const void *tx_buf, void *rx_buf, 320 u32 bits, u32 words) 321 { 322 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); 323 324 if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) 325 sh_msiof_write(p, TMDR2, dr2); 326 else 327 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); 328 329 if (rx_buf) 330 sh_msiof_write(p, RMDR2, dr2); 331 } 332 333 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) 334 { 335 sh_msiof_write(p, STR, sh_msiof_read(p, STR)); 336 } 337 338 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, 339 const void *tx_buf, int words, int fs) 340 { 341 const u8 *buf_8 = tx_buf; 342 int k; 343 344 for (k = 0; k < words; k++) 345 sh_msiof_write(p, TFDR, buf_8[k] << fs); 346 } 347 348 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, 349 const void *tx_buf, int words, int fs) 350 { 351 const u16 *buf_16 = tx_buf; 352 int k; 353 354 for (k = 0; k < words; k++) 355 sh_msiof_write(p, TFDR, buf_16[k] << fs); 356 } 357 358 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, 359 const void *tx_buf, int words, int fs) 360 { 361 const u16 *buf_16 = tx_buf; 362 int k; 363 364 for (k = 0; k < words; k++) 365 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); 366 } 367 368 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, 369 const void *tx_buf, int words, int fs) 370 { 371 const u32 *buf_32 = tx_buf; 372 int k; 373 374 for (k = 0; k < words; k++) 375 sh_msiof_write(p, TFDR, buf_32[k] << fs); 376 } 377 378 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, 379 const void *tx_buf, int words, int fs) 380 { 381 const u32 *buf_32 = tx_buf; 382 int k; 383 384 for (k = 0; k < words; k++) 385 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); 386 } 387 388 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, 389 const void *tx_buf, int words, int fs) 390 { 391 const u32 *buf_32 = tx_buf; 392 int k; 393 394 for (k = 0; k < words; k++) 395 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); 396 } 397 398 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, 399 const void *tx_buf, int words, int fs) 400 { 401 const u32 *buf_32 = tx_buf; 402 int k; 403 404 for (k = 0; k < words; k++) 405 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); 406 } 407 408 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, 409 void *rx_buf, int words, int fs) 410 { 411 u8 *buf_8 = rx_buf; 412 int k; 413 414 for (k = 0; k < words; k++) 415 buf_8[k] = sh_msiof_read(p, RFDR) >> fs; 416 } 417 418 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, 419 void *rx_buf, int words, int fs) 420 { 421 u16 *buf_16 = rx_buf; 422 int k; 423 424 for (k = 0; k < words; k++) 425 buf_16[k] = sh_msiof_read(p, RFDR) >> fs; 426 } 427 428 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, 429 void *rx_buf, int words, int fs) 430 { 431 u16 *buf_16 = rx_buf; 432 int k; 433 434 for (k = 0; k < words; k++) 435 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); 436 } 437 438 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, 439 void *rx_buf, int words, int fs) 440 { 441 u32 *buf_32 = rx_buf; 442 int k; 443 444 for (k = 0; k < words; k++) 445 buf_32[k] = sh_msiof_read(p, RFDR) >> fs; 446 } 447 448 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, 449 void *rx_buf, int words, int fs) 450 { 451 u32 *buf_32 = rx_buf; 452 int k; 453 454 for (k = 0; k < words; k++) 455 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); 456 } 457 458 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, 459 void *rx_buf, int words, int fs) 460 { 461 u32 *buf_32 = rx_buf; 462 int k; 463 464 for (k = 0; k < words; k++) 465 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); 466 } 467 468 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, 469 void *rx_buf, int words, int fs) 470 { 471 u32 *buf_32 = rx_buf; 472 int k; 473 474 for (k = 0; k < words; k++) 475 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); 476 } 477 478 static int sh_msiof_spi_setup(struct spi_device *spi) 479 { 480 struct device_node *np = spi->master->dev.of_node; 481 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); 482 483 if (!np) { 484 /* 485 * Use spi->controller_data for CS (same strategy as spi_gpio), 486 * if any. otherwise let HW control CS 487 */ 488 spi->cs_gpio = (uintptr_t)spi->controller_data; 489 } 490 491 /* Configure pins before deasserting CS */ 492 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), 493 !!(spi->mode & SPI_CPHA), 494 !!(spi->mode & SPI_3WIRE), 495 !!(spi->mode & SPI_LSB_FIRST), 496 !!(spi->mode & SPI_CS_HIGH)); 497 498 if (spi->cs_gpio >= 0) 499 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 500 501 return 0; 502 } 503 504 static int sh_msiof_prepare_message(struct spi_master *master, 505 struct spi_message *msg) 506 { 507 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 508 const struct spi_device *spi = msg->spi; 509 510 /* Configure pins before asserting CS */ 511 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), 512 !!(spi->mode & SPI_CPHA), 513 !!(spi->mode & SPI_3WIRE), 514 !!(spi->mode & SPI_LSB_FIRST), 515 !!(spi->mode & SPI_CS_HIGH)); 516 return 0; 517 } 518 519 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) 520 { 521 int ret; 522 523 /* setup clock and rx/tx signals */ 524 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); 525 if (rx_buf && !ret) 526 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); 527 if (!ret) 528 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); 529 530 /* start by setting frame bit */ 531 if (!ret) 532 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); 533 534 return ret; 535 } 536 537 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) 538 { 539 int ret; 540 541 /* shut down frame, rx/tx and clock signals */ 542 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); 543 if (!ret) 544 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); 545 if (rx_buf && !ret) 546 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); 547 if (!ret) 548 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); 549 550 return ret; 551 } 552 553 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, 554 void (*tx_fifo)(struct sh_msiof_spi_priv *, 555 const void *, int, int), 556 void (*rx_fifo)(struct sh_msiof_spi_priv *, 557 void *, int, int), 558 const void *tx_buf, void *rx_buf, 559 int words, int bits) 560 { 561 int fifo_shift; 562 int ret; 563 564 /* limit maximum word transfer to rx/tx fifo size */ 565 if (tx_buf) 566 words = min_t(int, words, p->tx_fifo_size); 567 if (rx_buf) 568 words = min_t(int, words, p->rx_fifo_size); 569 570 /* the fifo contents need shifting */ 571 fifo_shift = 32 - bits; 572 573 /* default FIFO watermarks for PIO */ 574 sh_msiof_write(p, FCTR, 0); 575 576 /* setup msiof transfer mode registers */ 577 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); 578 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE); 579 580 /* write tx fifo */ 581 if (tx_buf) 582 tx_fifo(p, tx_buf, words, fifo_shift); 583 584 reinit_completion(&p->done); 585 586 ret = sh_msiof_spi_start(p, rx_buf); 587 if (ret) { 588 dev_err(&p->pdev->dev, "failed to start hardware\n"); 589 goto stop_ier; 590 } 591 592 /* wait for tx fifo to be emptied / rx fifo to be filled */ 593 ret = wait_for_completion_timeout(&p->done, HZ); 594 if (!ret) { 595 dev_err(&p->pdev->dev, "PIO timeout\n"); 596 ret = -ETIMEDOUT; 597 goto stop_reset; 598 } 599 600 /* read rx fifo */ 601 if (rx_buf) 602 rx_fifo(p, rx_buf, words, fifo_shift); 603 604 /* clear status bits */ 605 sh_msiof_reset_str(p); 606 607 ret = sh_msiof_spi_stop(p, rx_buf); 608 if (ret) { 609 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 610 return ret; 611 } 612 613 return words; 614 615 stop_reset: 616 sh_msiof_reset_str(p); 617 sh_msiof_spi_stop(p, rx_buf); 618 stop_ier: 619 sh_msiof_write(p, IER, 0); 620 return ret; 621 } 622 623 static void sh_msiof_dma_complete(void *arg) 624 { 625 struct sh_msiof_spi_priv *p = arg; 626 627 sh_msiof_write(p, IER, 0); 628 complete(&p->done); 629 } 630 631 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, 632 void *rx, unsigned int len) 633 { 634 u32 ier_bits = 0; 635 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 636 dma_cookie_t cookie; 637 int ret; 638 639 /* First prepare and submit the DMA request(s), as this may fail */ 640 if (rx) { 641 ier_bits |= IER_RDREQE | IER_RDMAE; 642 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, 643 p->rx_dma_addr, len, DMA_FROM_DEVICE, 644 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 645 if (!desc_rx) { 646 ret = -EAGAIN; 647 goto no_dma_rx; 648 } 649 650 desc_rx->callback = sh_msiof_dma_complete; 651 desc_rx->callback_param = p; 652 cookie = dmaengine_submit(desc_rx); 653 if (dma_submit_error(cookie)) { 654 ret = cookie; 655 goto no_dma_rx; 656 } 657 } 658 659 if (tx) { 660 ier_bits |= IER_TDREQE | IER_TDMAE; 661 dma_sync_single_for_device(p->master->dma_tx->device->dev, 662 p->tx_dma_addr, len, DMA_TO_DEVICE); 663 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx, 664 p->tx_dma_addr, len, DMA_TO_DEVICE, 665 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 666 if (!desc_tx) { 667 ret = -EAGAIN; 668 goto no_dma_tx; 669 } 670 671 if (rx) { 672 /* No callback */ 673 desc_tx->callback = NULL; 674 } else { 675 desc_tx->callback = sh_msiof_dma_complete; 676 desc_tx->callback_param = p; 677 } 678 cookie = dmaengine_submit(desc_tx); 679 if (dma_submit_error(cookie)) { 680 ret = cookie; 681 goto no_dma_tx; 682 } 683 } 684 685 /* 1 stage FIFO watermarks for DMA */ 686 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1); 687 688 /* setup msiof transfer mode registers (32-bit words) */ 689 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); 690 691 sh_msiof_write(p, IER, ier_bits); 692 693 reinit_completion(&p->done); 694 695 /* Now start DMA */ 696 if (rx) 697 dma_async_issue_pending(p->master->dma_rx); 698 if (tx) 699 dma_async_issue_pending(p->master->dma_tx); 700 701 ret = sh_msiof_spi_start(p, rx); 702 if (ret) { 703 dev_err(&p->pdev->dev, "failed to start hardware\n"); 704 goto stop_dma; 705 } 706 707 /* wait for tx fifo to be emptied / rx fifo to be filled */ 708 ret = wait_for_completion_timeout(&p->done, HZ); 709 if (!ret) { 710 dev_err(&p->pdev->dev, "DMA timeout\n"); 711 ret = -ETIMEDOUT; 712 goto stop_reset; 713 } 714 715 /* clear status bits */ 716 sh_msiof_reset_str(p); 717 718 ret = sh_msiof_spi_stop(p, rx); 719 if (ret) { 720 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 721 return ret; 722 } 723 724 if (rx) 725 dma_sync_single_for_cpu(p->master->dma_rx->device->dev, 726 p->rx_dma_addr, len, 727 DMA_FROM_DEVICE); 728 729 return 0; 730 731 stop_reset: 732 sh_msiof_reset_str(p); 733 sh_msiof_spi_stop(p, rx); 734 stop_dma: 735 if (tx) 736 dmaengine_terminate_all(p->master->dma_tx); 737 no_dma_tx: 738 if (rx) 739 dmaengine_terminate_all(p->master->dma_rx); 740 sh_msiof_write(p, IER, 0); 741 no_dma_rx: 742 return ret; 743 } 744 745 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) 746 { 747 /* src or dst can be unaligned, but not both */ 748 if ((unsigned long)src & 3) { 749 while (words--) { 750 *dst++ = swab32(get_unaligned(src)); 751 src++; 752 } 753 } else if ((unsigned long)dst & 3) { 754 while (words--) { 755 put_unaligned(swab32(*src++), dst); 756 dst++; 757 } 758 } else { 759 while (words--) 760 *dst++ = swab32(*src++); 761 } 762 } 763 764 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) 765 { 766 /* src or dst can be unaligned, but not both */ 767 if ((unsigned long)src & 3) { 768 while (words--) { 769 *dst++ = swahw32(get_unaligned(src)); 770 src++; 771 } 772 } else if ((unsigned long)dst & 3) { 773 while (words--) { 774 put_unaligned(swahw32(*src++), dst); 775 dst++; 776 } 777 } else { 778 while (words--) 779 *dst++ = swahw32(*src++); 780 } 781 } 782 783 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) 784 { 785 memcpy(dst, src, words * 4); 786 } 787 788 static int sh_msiof_transfer_one(struct spi_master *master, 789 struct spi_device *spi, 790 struct spi_transfer *t) 791 { 792 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 793 void (*copy32)(u32 *, const u32 *, unsigned int); 794 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); 795 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); 796 const void *tx_buf = t->tx_buf; 797 void *rx_buf = t->rx_buf; 798 unsigned int len = t->len; 799 unsigned int bits = t->bits_per_word; 800 unsigned int bytes_per_word; 801 unsigned int words; 802 int n; 803 bool swab; 804 int ret; 805 806 /* setup clocks (clock already enabled in chipselect()) */ 807 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); 808 809 while (master->dma_tx && len > 15) { 810 /* 811 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit 812 * words, with byte resp. word swapping. 813 */ 814 unsigned int l = min(len, MAX_WDLEN * 4); 815 816 if (bits <= 8) { 817 if (l & 3) 818 break; 819 copy32 = copy_bswap32; 820 } else if (bits <= 16) { 821 if (l & 1) 822 break; 823 copy32 = copy_wswap32; 824 } else { 825 copy32 = copy_plain32; 826 } 827 828 if (tx_buf) 829 copy32(p->tx_dma_page, tx_buf, l / 4); 830 831 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); 832 if (ret == -EAGAIN) { 833 pr_warn_once("%s %s: DMA not available, falling back to PIO\n", 834 dev_driver_string(&p->pdev->dev), 835 dev_name(&p->pdev->dev)); 836 break; 837 } 838 if (ret) 839 return ret; 840 841 if (rx_buf) { 842 copy32(rx_buf, p->rx_dma_page, l / 4); 843 rx_buf += l; 844 } 845 if (tx_buf) 846 tx_buf += l; 847 848 len -= l; 849 if (!len) 850 return 0; 851 } 852 853 if (bits <= 8 && len > 15 && !(len & 3)) { 854 bits = 32; 855 swab = true; 856 } else { 857 swab = false; 858 } 859 860 /* setup bytes per word and fifo read/write functions */ 861 if (bits <= 8) { 862 bytes_per_word = 1; 863 tx_fifo = sh_msiof_spi_write_fifo_8; 864 rx_fifo = sh_msiof_spi_read_fifo_8; 865 } else if (bits <= 16) { 866 bytes_per_word = 2; 867 if ((unsigned long)tx_buf & 0x01) 868 tx_fifo = sh_msiof_spi_write_fifo_16u; 869 else 870 tx_fifo = sh_msiof_spi_write_fifo_16; 871 872 if ((unsigned long)rx_buf & 0x01) 873 rx_fifo = sh_msiof_spi_read_fifo_16u; 874 else 875 rx_fifo = sh_msiof_spi_read_fifo_16; 876 } else if (swab) { 877 bytes_per_word = 4; 878 if ((unsigned long)tx_buf & 0x03) 879 tx_fifo = sh_msiof_spi_write_fifo_s32u; 880 else 881 tx_fifo = sh_msiof_spi_write_fifo_s32; 882 883 if ((unsigned long)rx_buf & 0x03) 884 rx_fifo = sh_msiof_spi_read_fifo_s32u; 885 else 886 rx_fifo = sh_msiof_spi_read_fifo_s32; 887 } else { 888 bytes_per_word = 4; 889 if ((unsigned long)tx_buf & 0x03) 890 tx_fifo = sh_msiof_spi_write_fifo_32u; 891 else 892 tx_fifo = sh_msiof_spi_write_fifo_32; 893 894 if ((unsigned long)rx_buf & 0x03) 895 rx_fifo = sh_msiof_spi_read_fifo_32u; 896 else 897 rx_fifo = sh_msiof_spi_read_fifo_32; 898 } 899 900 /* transfer in fifo sized chunks */ 901 words = len / bytes_per_word; 902 903 while (words > 0) { 904 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, 905 words, bits); 906 if (n < 0) 907 return n; 908 909 if (tx_buf) 910 tx_buf += n * bytes_per_word; 911 if (rx_buf) 912 rx_buf += n * bytes_per_word; 913 words -= n; 914 } 915 916 return 0; 917 } 918 919 static const struct sh_msiof_chipdata sh_data = { 920 .tx_fifo_size = 64, 921 .rx_fifo_size = 64, 922 .master_flags = 0, 923 }; 924 925 static const struct sh_msiof_chipdata r8a779x_data = { 926 .tx_fifo_size = 64, 927 .rx_fifo_size = 256, 928 .master_flags = SPI_MASTER_MUST_TX, 929 }; 930 931 static const struct of_device_id sh_msiof_match[] = { 932 { .compatible = "renesas,sh-msiof", .data = &sh_data }, 933 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, 934 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, 935 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, 936 {}, 937 }; 938 MODULE_DEVICE_TABLE(of, sh_msiof_match); 939 940 #ifdef CONFIG_OF 941 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 942 { 943 struct sh_msiof_spi_info *info; 944 struct device_node *np = dev->of_node; 945 u32 num_cs = 1; 946 947 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); 948 if (!info) 949 return NULL; 950 951 /* Parse the MSIOF properties */ 952 of_property_read_u32(np, "num-cs", &num_cs); 953 of_property_read_u32(np, "renesas,tx-fifo-size", 954 &info->tx_fifo_override); 955 of_property_read_u32(np, "renesas,rx-fifo-size", 956 &info->rx_fifo_override); 957 958 info->num_chipselect = num_cs; 959 960 return info; 961 } 962 #else 963 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 964 { 965 return NULL; 966 } 967 #endif 968 969 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, 970 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) 971 { 972 dma_cap_mask_t mask; 973 struct dma_chan *chan; 974 struct dma_slave_config cfg; 975 int ret; 976 977 dma_cap_zero(mask); 978 dma_cap_set(DMA_SLAVE, mask); 979 980 chan = dma_request_channel(mask, shdma_chan_filter, 981 (void *)(unsigned long)id); 982 if (!chan) { 983 dev_warn(dev, "dma_request_channel failed\n"); 984 return NULL; 985 } 986 987 memset(&cfg, 0, sizeof(cfg)); 988 cfg.slave_id = id; 989 cfg.direction = dir; 990 if (dir == DMA_MEM_TO_DEV) 991 cfg.dst_addr = port_addr; 992 else 993 cfg.src_addr = port_addr; 994 995 ret = dmaengine_slave_config(chan, &cfg); 996 if (ret) { 997 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 998 dma_release_channel(chan); 999 return NULL; 1000 } 1001 1002 return chan; 1003 } 1004 1005 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) 1006 { 1007 struct platform_device *pdev = p->pdev; 1008 struct device *dev = &pdev->dev; 1009 const struct sh_msiof_spi_info *info = dev_get_platdata(dev); 1010 const struct resource *res; 1011 struct spi_master *master; 1012 struct device *tx_dev, *rx_dev; 1013 1014 if (!info || !info->dma_tx_id || !info->dma_rx_id) 1015 return 0; /* The driver assumes no error */ 1016 1017 /* The DMA engine uses the second register set, if present */ 1018 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1019 if (!res) 1020 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1021 1022 master = p->master; 1023 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, 1024 info->dma_tx_id, 1025 res->start + TFDR); 1026 if (!master->dma_tx) 1027 return -ENODEV; 1028 1029 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, 1030 info->dma_rx_id, 1031 res->start + RFDR); 1032 if (!master->dma_rx) 1033 goto free_tx_chan; 1034 1035 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1036 if (!p->tx_dma_page) 1037 goto free_rx_chan; 1038 1039 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1040 if (!p->rx_dma_page) 1041 goto free_tx_page; 1042 1043 tx_dev = master->dma_tx->device->dev; 1044 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, 1045 DMA_TO_DEVICE); 1046 if (dma_mapping_error(tx_dev, p->tx_dma_addr)) 1047 goto free_rx_page; 1048 1049 rx_dev = master->dma_rx->device->dev; 1050 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, 1051 DMA_FROM_DEVICE); 1052 if (dma_mapping_error(rx_dev, p->rx_dma_addr)) 1053 goto unmap_tx_page; 1054 1055 dev_info(dev, "DMA available"); 1056 return 0; 1057 1058 unmap_tx_page: 1059 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); 1060 free_rx_page: 1061 free_page((unsigned long)p->rx_dma_page); 1062 free_tx_page: 1063 free_page((unsigned long)p->tx_dma_page); 1064 free_rx_chan: 1065 dma_release_channel(master->dma_rx); 1066 free_tx_chan: 1067 dma_release_channel(master->dma_tx); 1068 master->dma_tx = NULL; 1069 return -ENODEV; 1070 } 1071 1072 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) 1073 { 1074 struct spi_master *master = p->master; 1075 struct device *dev; 1076 1077 if (!master->dma_tx) 1078 return; 1079 1080 dev = &p->pdev->dev; 1081 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr, 1082 PAGE_SIZE, DMA_FROM_DEVICE); 1083 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr, 1084 PAGE_SIZE, DMA_TO_DEVICE); 1085 free_page((unsigned long)p->rx_dma_page); 1086 free_page((unsigned long)p->tx_dma_page); 1087 dma_release_channel(master->dma_rx); 1088 dma_release_channel(master->dma_tx); 1089 } 1090 1091 static int sh_msiof_spi_probe(struct platform_device *pdev) 1092 { 1093 struct resource *r; 1094 struct spi_master *master; 1095 const struct of_device_id *of_id; 1096 struct sh_msiof_spi_priv *p; 1097 int i; 1098 int ret; 1099 1100 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); 1101 if (master == NULL) { 1102 dev_err(&pdev->dev, "failed to allocate spi master\n"); 1103 return -ENOMEM; 1104 } 1105 1106 p = spi_master_get_devdata(master); 1107 1108 platform_set_drvdata(pdev, p); 1109 p->master = master; 1110 1111 of_id = of_match_device(sh_msiof_match, &pdev->dev); 1112 if (of_id) { 1113 p->chipdata = of_id->data; 1114 p->info = sh_msiof_spi_parse_dt(&pdev->dev); 1115 } else { 1116 p->chipdata = (const void *)pdev->id_entry->driver_data; 1117 p->info = dev_get_platdata(&pdev->dev); 1118 } 1119 1120 if (!p->info) { 1121 dev_err(&pdev->dev, "failed to obtain device info\n"); 1122 ret = -ENXIO; 1123 goto err1; 1124 } 1125 1126 init_completion(&p->done); 1127 1128 p->clk = devm_clk_get(&pdev->dev, NULL); 1129 if (IS_ERR(p->clk)) { 1130 dev_err(&pdev->dev, "cannot get clock\n"); 1131 ret = PTR_ERR(p->clk); 1132 goto err1; 1133 } 1134 1135 i = platform_get_irq(pdev, 0); 1136 if (i < 0) { 1137 dev_err(&pdev->dev, "cannot get platform IRQ\n"); 1138 ret = -ENOENT; 1139 goto err1; 1140 } 1141 1142 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1143 p->mapbase = devm_ioremap_resource(&pdev->dev, r); 1144 if (IS_ERR(p->mapbase)) { 1145 ret = PTR_ERR(p->mapbase); 1146 goto err1; 1147 } 1148 1149 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, 1150 dev_name(&pdev->dev), p); 1151 if (ret) { 1152 dev_err(&pdev->dev, "unable to request irq\n"); 1153 goto err1; 1154 } 1155 1156 p->pdev = pdev; 1157 pm_runtime_enable(&pdev->dev); 1158 1159 /* Platform data may override FIFO sizes */ 1160 p->tx_fifo_size = p->chipdata->tx_fifo_size; 1161 p->rx_fifo_size = p->chipdata->rx_fifo_size; 1162 if (p->info->tx_fifo_override) 1163 p->tx_fifo_size = p->info->tx_fifo_override; 1164 if (p->info->rx_fifo_override) 1165 p->rx_fifo_size = p->info->rx_fifo_override; 1166 1167 /* init master code */ 1168 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1169 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; 1170 master->flags = p->chipdata->master_flags; 1171 master->bus_num = pdev->id; 1172 master->dev.of_node = pdev->dev.of_node; 1173 master->num_chipselect = p->info->num_chipselect; 1174 master->setup = sh_msiof_spi_setup; 1175 master->prepare_message = sh_msiof_prepare_message; 1176 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 1177 master->auto_runtime_pm = true; 1178 master->transfer_one = sh_msiof_transfer_one; 1179 1180 ret = sh_msiof_request_dma(p); 1181 if (ret < 0) 1182 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1183 1184 ret = devm_spi_register_master(&pdev->dev, master); 1185 if (ret < 0) { 1186 dev_err(&pdev->dev, "spi_register_master error.\n"); 1187 goto err2; 1188 } 1189 1190 return 0; 1191 1192 err2: 1193 sh_msiof_release_dma(p); 1194 pm_runtime_disable(&pdev->dev); 1195 err1: 1196 spi_master_put(master); 1197 return ret; 1198 } 1199 1200 static int sh_msiof_spi_remove(struct platform_device *pdev) 1201 { 1202 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); 1203 1204 sh_msiof_release_dma(p); 1205 pm_runtime_disable(&pdev->dev); 1206 return 0; 1207 } 1208 1209 static struct platform_device_id spi_driver_ids[] = { 1210 { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, 1211 { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, 1212 { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, 1213 {}, 1214 }; 1215 MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1216 1217 static struct platform_driver sh_msiof_spi_drv = { 1218 .probe = sh_msiof_spi_probe, 1219 .remove = sh_msiof_spi_remove, 1220 .id_table = spi_driver_ids, 1221 .driver = { 1222 .name = "spi_sh_msiof", 1223 .owner = THIS_MODULE, 1224 .of_match_table = of_match_ptr(sh_msiof_match), 1225 }, 1226 }; 1227 module_platform_driver(sh_msiof_spi_drv); 1228 1229 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); 1230 MODULE_AUTHOR("Magnus Damm"); 1231 MODULE_LICENSE("GPL v2"); 1232 MODULE_ALIAS("platform:spi_sh_msiof"); 1233