1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2009 Samsung Electronics Co., Ltd. 4 // Jaswinder Singh <jassi.brar@samsung.com> 5 6 #include <linux/init.h> 7 #include <linux/module.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/spi/spi.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 19 #include <linux/platform_data/spi-s3c64xx.h> 20 21 #define MAX_SPI_PORTS 12 22 #define S3C64XX_SPI_QUIRK_POLL (1 << 0) 23 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) 24 #define AUTOSUSPEND_TIMEOUT 2000 25 26 /* Registers and bit-fields */ 27 28 #define S3C64XX_SPI_CH_CFG 0x00 29 #define S3C64XX_SPI_CLK_CFG 0x04 30 #define S3C64XX_SPI_MODE_CFG 0x08 31 #define S3C64XX_SPI_CS_REG 0x0C 32 #define S3C64XX_SPI_INT_EN 0x10 33 #define S3C64XX_SPI_STATUS 0x14 34 #define S3C64XX_SPI_TX_DATA 0x18 35 #define S3C64XX_SPI_RX_DATA 0x1C 36 #define S3C64XX_SPI_PACKET_CNT 0x20 37 #define S3C64XX_SPI_PENDING_CLR 0x24 38 #define S3C64XX_SPI_SWAP_CFG 0x28 39 #define S3C64XX_SPI_FB_CLK 0x2C 40 41 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 42 #define S3C64XX_SPI_CH_SW_RST (1<<5) 43 #define S3C64XX_SPI_CH_SLAVE (1<<4) 44 #define S3C64XX_SPI_CPOL_L (1<<3) 45 #define S3C64XX_SPI_CPHA_B (1<<2) 46 #define S3C64XX_SPI_CH_RXCH_ON (1<<1) 47 #define S3C64XX_SPI_CH_TXCH_ON (1<<0) 48 49 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 50 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 51 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 52 #define S3C64XX_SPI_PSR_MASK 0xff 53 54 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 55 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 56 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 57 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 58 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 59 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 60 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 61 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 62 #define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) 63 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 64 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 65 #define S3C64XX_SPI_MODE_4BURST (1<<0) 66 67 #define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) 68 #define S3C64XX_SPI_CS_AUTO (1<<1) 69 #define S3C64XX_SPI_CS_SIG_INACT (1<<0) 70 71 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 72 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 73 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 74 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 75 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 76 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 77 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 78 79 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 80 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 81 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 82 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 83 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 84 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 85 86 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 87 88 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 89 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 90 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 91 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 92 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 93 94 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 95 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 96 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 97 #define S3C64XX_SPI_SWAP_RX_EN (1<<4) 98 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 99 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 100 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 101 #define S3C64XX_SPI_SWAP_TX_EN (1<<0) 102 103 #define S3C64XX_SPI_FBCLK_MSK (3<<0) 104 105 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) 106 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ 107 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) 108 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) 109 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ 110 FIFO_LVL_MASK(i)) 111 112 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 113 #define S3C64XX_SPI_TRAILCNT_OFF 19 114 115 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT 116 117 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 118 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) 119 120 #define RXBUSY (1<<2) 121 #define TXBUSY (1<<3) 122 123 struct s3c64xx_spi_dma_data { 124 struct dma_chan *ch; 125 dma_cookie_t cookie; 126 enum dma_transfer_direction direction; 127 }; 128 129 /** 130 * struct s3c64xx_spi_port_config - SPI Controller hardware info 131 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. 132 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. 133 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. 134 * @clk_div: Internal clock divider 135 * @quirks: Bitmask of known quirks 136 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. 137 * @clk_from_cmu: True, if the controller does not include a clock mux and 138 * prescaler unit. 139 * @clk_ioclk: True if clock is present on this device 140 * @has_loopback: True if loopback mode can be supported 141 * 142 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but 143 * differ in some aspects such as the size of the fifo and spi bus clock 144 * setup. Such differences are specified to the driver using this structure 145 * which is provided as driver data to the driver. 146 */ 147 struct s3c64xx_spi_port_config { 148 int fifo_lvl_mask[MAX_SPI_PORTS]; 149 int rx_lvl_offset; 150 int tx_st_done; 151 int quirks; 152 int clk_div; 153 bool high_speed; 154 bool clk_from_cmu; 155 bool clk_ioclk; 156 bool has_loopback; 157 }; 158 159 /** 160 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 161 * @clk: Pointer to the spi clock. 162 * @src_clk: Pointer to the clock used to generate SPI signals. 163 * @ioclk: Pointer to the i/o clock between master and slave 164 * @pdev: Pointer to device's platform device data 165 * @master: Pointer to the SPI Protocol master. 166 * @cntrlr_info: Platform specific data for the controller this driver manages. 167 * @lock: Controller specific lock. 168 * @state: Set of FLAGS to indicate status. 169 * @sfr_start: BUS address of SPI controller regs. 170 * @regs: Pointer to ioremap'ed controller registers. 171 * @xfer_completion: To indicate completion of xfer task. 172 * @cur_mode: Stores the active configuration of the controller. 173 * @cur_bpw: Stores the active bits per word settings. 174 * @cur_speed: Current clock speed 175 * @rx_dma: Local receive DMA data (e.g. chan and direction) 176 * @tx_dma: Local transmit DMA data (e.g. chan and direction) 177 * @port_conf: Local SPI port configuartion data 178 * @port_id: Port identification number 179 */ 180 struct s3c64xx_spi_driver_data { 181 void __iomem *regs; 182 struct clk *clk; 183 struct clk *src_clk; 184 struct clk *ioclk; 185 struct platform_device *pdev; 186 struct spi_master *master; 187 struct s3c64xx_spi_info *cntrlr_info; 188 spinlock_t lock; 189 unsigned long sfr_start; 190 struct completion xfer_completion; 191 unsigned state; 192 unsigned cur_mode, cur_bpw; 193 unsigned cur_speed; 194 struct s3c64xx_spi_dma_data rx_dma; 195 struct s3c64xx_spi_dma_data tx_dma; 196 const struct s3c64xx_spi_port_config *port_conf; 197 unsigned int port_id; 198 }; 199 200 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) 201 { 202 void __iomem *regs = sdd->regs; 203 unsigned long loops; 204 u32 val; 205 206 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 207 208 val = readl(regs + S3C64XX_SPI_CH_CFG); 209 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 210 writel(val, regs + S3C64XX_SPI_CH_CFG); 211 212 val = readl(regs + S3C64XX_SPI_CH_CFG); 213 val |= S3C64XX_SPI_CH_SW_RST; 214 val &= ~S3C64XX_SPI_CH_HS_EN; 215 writel(val, regs + S3C64XX_SPI_CH_CFG); 216 217 /* Flush TxFIFO*/ 218 loops = msecs_to_loops(1); 219 do { 220 val = readl(regs + S3C64XX_SPI_STATUS); 221 } while (TX_FIFO_LVL(val, sdd) && loops--); 222 223 if (loops == 0) 224 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 225 226 /* Flush RxFIFO*/ 227 loops = msecs_to_loops(1); 228 do { 229 val = readl(regs + S3C64XX_SPI_STATUS); 230 if (RX_FIFO_LVL(val, sdd)) 231 readl(regs + S3C64XX_SPI_RX_DATA); 232 else 233 break; 234 } while (loops--); 235 236 if (loops == 0) 237 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 238 239 val = readl(regs + S3C64XX_SPI_CH_CFG); 240 val &= ~S3C64XX_SPI_CH_SW_RST; 241 writel(val, regs + S3C64XX_SPI_CH_CFG); 242 243 val = readl(regs + S3C64XX_SPI_MODE_CFG); 244 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 245 writel(val, regs + S3C64XX_SPI_MODE_CFG); 246 } 247 248 static void s3c64xx_spi_dmacb(void *data) 249 { 250 struct s3c64xx_spi_driver_data *sdd; 251 struct s3c64xx_spi_dma_data *dma = data; 252 unsigned long flags; 253 254 if (dma->direction == DMA_DEV_TO_MEM) 255 sdd = container_of(data, 256 struct s3c64xx_spi_driver_data, rx_dma); 257 else 258 sdd = container_of(data, 259 struct s3c64xx_spi_driver_data, tx_dma); 260 261 spin_lock_irqsave(&sdd->lock, flags); 262 263 if (dma->direction == DMA_DEV_TO_MEM) { 264 sdd->state &= ~RXBUSY; 265 if (!(sdd->state & TXBUSY)) 266 complete(&sdd->xfer_completion); 267 } else { 268 sdd->state &= ~TXBUSY; 269 if (!(sdd->state & RXBUSY)) 270 complete(&sdd->xfer_completion); 271 } 272 273 spin_unlock_irqrestore(&sdd->lock, flags); 274 } 275 276 static int prepare_dma(struct s3c64xx_spi_dma_data *dma, 277 struct sg_table *sgt) 278 { 279 struct s3c64xx_spi_driver_data *sdd; 280 struct dma_slave_config config; 281 struct dma_async_tx_descriptor *desc; 282 int ret; 283 284 memset(&config, 0, sizeof(config)); 285 286 if (dma->direction == DMA_DEV_TO_MEM) { 287 sdd = container_of((void *)dma, 288 struct s3c64xx_spi_driver_data, rx_dma); 289 config.direction = dma->direction; 290 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 291 config.src_addr_width = sdd->cur_bpw / 8; 292 config.src_maxburst = 1; 293 dmaengine_slave_config(dma->ch, &config); 294 } else { 295 sdd = container_of((void *)dma, 296 struct s3c64xx_spi_driver_data, tx_dma); 297 config.direction = dma->direction; 298 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 299 config.dst_addr_width = sdd->cur_bpw / 8; 300 config.dst_maxburst = 1; 301 dmaengine_slave_config(dma->ch, &config); 302 } 303 304 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, 305 dma->direction, DMA_PREP_INTERRUPT); 306 if (!desc) { 307 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", 308 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx"); 309 return -ENOMEM; 310 } 311 312 desc->callback = s3c64xx_spi_dmacb; 313 desc->callback_param = dma; 314 315 dma->cookie = dmaengine_submit(desc); 316 ret = dma_submit_error(dma->cookie); 317 if (ret) { 318 dev_err(&sdd->pdev->dev, "DMA submission failed"); 319 return -EIO; 320 } 321 322 dma_async_issue_pending(dma->ch); 323 return 0; 324 } 325 326 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) 327 { 328 struct s3c64xx_spi_driver_data *sdd = 329 spi_master_get_devdata(spi->master); 330 331 if (sdd->cntrlr_info->no_cs) 332 return; 333 334 if (enable) { 335 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { 336 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 337 } else { 338 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); 339 340 ssel |= (S3C64XX_SPI_CS_AUTO | 341 S3C64XX_SPI_CS_NSC_CNT_2); 342 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); 343 } 344 } else { 345 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 346 writel(S3C64XX_SPI_CS_SIG_INACT, 347 sdd->regs + S3C64XX_SPI_CS_REG); 348 } 349 } 350 351 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) 352 { 353 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 354 355 if (is_polling(sdd)) 356 return 0; 357 358 /* Requests DMA channels */ 359 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx"); 360 if (IS_ERR(sdd->rx_dma.ch)) { 361 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n"); 362 sdd->rx_dma.ch = NULL; 363 return 0; 364 } 365 366 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx"); 367 if (IS_ERR(sdd->tx_dma.ch)) { 368 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n"); 369 dma_release_channel(sdd->rx_dma.ch); 370 sdd->tx_dma.ch = NULL; 371 sdd->rx_dma.ch = NULL; 372 return 0; 373 } 374 375 spi->dma_rx = sdd->rx_dma.ch; 376 spi->dma_tx = sdd->tx_dma.ch; 377 378 return 0; 379 } 380 381 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) 382 { 383 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 384 385 if (is_polling(sdd)) 386 return 0; 387 388 /* Releases DMA channels if they are allocated */ 389 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { 390 dma_release_channel(sdd->rx_dma.ch); 391 dma_release_channel(sdd->tx_dma.ch); 392 sdd->rx_dma.ch = 0; 393 sdd->tx_dma.ch = 0; 394 } 395 396 return 0; 397 } 398 399 static bool s3c64xx_spi_can_dma(struct spi_master *master, 400 struct spi_device *spi, 401 struct spi_transfer *xfer) 402 { 403 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 404 405 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { 406 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; 407 } else { 408 return false; 409 } 410 411 } 412 413 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, 414 struct spi_transfer *xfer, int dma_mode) 415 { 416 void __iomem *regs = sdd->regs; 417 u32 modecfg, chcfg; 418 int ret = 0; 419 420 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 421 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 422 423 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 424 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 425 426 if (dma_mode) { 427 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 428 } else { 429 /* Always shift in data in FIFO, even if xfer is Tx only, 430 * this helps setting PCKT_CNT value for generating clocks 431 * as exactly needed. 432 */ 433 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 434 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 435 | S3C64XX_SPI_PACKET_CNT_EN, 436 regs + S3C64XX_SPI_PACKET_CNT); 437 } 438 439 if (xfer->tx_buf != NULL) { 440 sdd->state |= TXBUSY; 441 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 442 if (dma_mode) { 443 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 444 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); 445 } else { 446 switch (sdd->cur_bpw) { 447 case 32: 448 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, 449 xfer->tx_buf, xfer->len / 4); 450 break; 451 case 16: 452 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, 453 xfer->tx_buf, xfer->len / 2); 454 break; 455 default: 456 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, 457 xfer->tx_buf, xfer->len); 458 break; 459 } 460 } 461 } 462 463 if (xfer->rx_buf != NULL) { 464 sdd->state |= RXBUSY; 465 466 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL 467 && !(sdd->cur_mode & SPI_CPHA)) 468 chcfg |= S3C64XX_SPI_CH_HS_EN; 469 470 if (dma_mode) { 471 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 472 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 473 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 474 | S3C64XX_SPI_PACKET_CNT_EN, 475 regs + S3C64XX_SPI_PACKET_CNT); 476 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg); 477 } 478 } 479 480 if (ret) 481 return ret; 482 483 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 484 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 485 486 return 0; 487 } 488 489 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 490 int timeout_ms) 491 { 492 void __iomem *regs = sdd->regs; 493 unsigned long val = 1; 494 u32 status; 495 496 /* max fifo depth available */ 497 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; 498 499 if (timeout_ms) 500 val = msecs_to_loops(timeout_ms); 501 502 do { 503 status = readl(regs + S3C64XX_SPI_STATUS); 504 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); 505 506 /* return the actual received data length */ 507 return RX_FIFO_LVL(status, sdd); 508 } 509 510 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, 511 struct spi_transfer *xfer) 512 { 513 void __iomem *regs = sdd->regs; 514 unsigned long val; 515 u32 status; 516 int ms; 517 518 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 519 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 520 ms += 30; /* some tolerance */ 521 ms = max(ms, 100); /* minimum timeout */ 522 523 val = msecs_to_jiffies(ms) + 10; 524 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 525 526 /* 527 * If the previous xfer was completed within timeout, then 528 * proceed further else return -EIO. 529 * DmaTx returns after simply writing data in the FIFO, 530 * w/o waiting for real transmission on the bus to finish. 531 * DmaRx returns only after Dma read data from FIFO which 532 * needs bus transmission to finish, so we don't worry if 533 * Xfer involved Rx(with or without Tx). 534 */ 535 if (val && !xfer->rx_buf) { 536 val = msecs_to_loops(10); 537 status = readl(regs + S3C64XX_SPI_STATUS); 538 while ((TX_FIFO_LVL(status, sdd) 539 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) 540 && --val) { 541 cpu_relax(); 542 status = readl(regs + S3C64XX_SPI_STATUS); 543 } 544 545 } 546 547 /* If timed out while checking rx/tx status return error */ 548 if (!val) 549 return -EIO; 550 551 return 0; 552 } 553 554 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, 555 struct spi_transfer *xfer) 556 { 557 void __iomem *regs = sdd->regs; 558 unsigned long val; 559 u32 status; 560 int loops; 561 u32 cpy_len; 562 u8 *buf; 563 int ms; 564 565 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 566 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 567 ms += 10; /* some tolerance */ 568 569 val = msecs_to_loops(ms); 570 do { 571 status = readl(regs + S3C64XX_SPI_STATUS); 572 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 573 574 if (!val) 575 return -EIO; 576 577 /* If it was only Tx */ 578 if (!xfer->rx_buf) { 579 sdd->state &= ~TXBUSY; 580 return 0; 581 } 582 583 /* 584 * If the receive length is bigger than the controller fifo 585 * size, calculate the loops and read the fifo as many times. 586 * loops = length / max fifo size (calculated by using the 587 * fifo mask). 588 * For any size less than the fifo size the below code is 589 * executed atleast once. 590 */ 591 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); 592 buf = xfer->rx_buf; 593 do { 594 /* wait for data to be received in the fifo */ 595 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, 596 (loops ? ms : 0)); 597 598 switch (sdd->cur_bpw) { 599 case 32: 600 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 601 buf, cpy_len / 4); 602 break; 603 case 16: 604 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 605 buf, cpy_len / 2); 606 break; 607 default: 608 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 609 buf, cpy_len); 610 break; 611 } 612 613 buf = buf + cpy_len; 614 } while (loops--); 615 sdd->state &= ~RXBUSY; 616 617 return 0; 618 } 619 620 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 621 { 622 void __iomem *regs = sdd->regs; 623 int ret; 624 u32 val; 625 int div = sdd->port_conf->clk_div; 626 627 /* Disable Clock */ 628 if (!sdd->port_conf->clk_from_cmu) { 629 val = readl(regs + S3C64XX_SPI_CLK_CFG); 630 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 631 writel(val, regs + S3C64XX_SPI_CLK_CFG); 632 } 633 634 /* Set Polarity and Phase */ 635 val = readl(regs + S3C64XX_SPI_CH_CFG); 636 val &= ~(S3C64XX_SPI_CH_SLAVE | 637 S3C64XX_SPI_CPOL_L | 638 S3C64XX_SPI_CPHA_B); 639 640 if (sdd->cur_mode & SPI_CPOL) 641 val |= S3C64XX_SPI_CPOL_L; 642 643 if (sdd->cur_mode & SPI_CPHA) 644 val |= S3C64XX_SPI_CPHA_B; 645 646 writel(val, regs + S3C64XX_SPI_CH_CFG); 647 648 /* Set Channel & DMA Mode */ 649 val = readl(regs + S3C64XX_SPI_MODE_CFG); 650 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 651 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 652 653 switch (sdd->cur_bpw) { 654 case 32: 655 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 656 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 657 break; 658 case 16: 659 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 660 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 661 break; 662 default: 663 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 664 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 665 break; 666 } 667 668 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) 669 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK; 670 671 writel(val, regs + S3C64XX_SPI_MODE_CFG); 672 673 if (sdd->port_conf->clk_from_cmu) { 674 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); 675 if (ret) 676 return ret; 677 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; 678 } else { 679 /* Configure Clock */ 680 val = readl(regs + S3C64XX_SPI_CLK_CFG); 681 val &= ~S3C64XX_SPI_PSR_MASK; 682 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) 683 & S3C64XX_SPI_PSR_MASK); 684 writel(val, regs + S3C64XX_SPI_CLK_CFG); 685 686 /* Enable Clock */ 687 val = readl(regs + S3C64XX_SPI_CLK_CFG); 688 val |= S3C64XX_SPI_ENCLK_ENABLE; 689 writel(val, regs + S3C64XX_SPI_CLK_CFG); 690 } 691 692 return 0; 693 } 694 695 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 696 697 static int s3c64xx_spi_prepare_message(struct spi_master *master, 698 struct spi_message *msg) 699 { 700 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 701 struct spi_device *spi = msg->spi; 702 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 703 704 /* Configure feedback delay */ 705 if (!cs) 706 /* No delay if not defined */ 707 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK); 708 else 709 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 710 711 return 0; 712 } 713 714 static int s3c64xx_spi_transfer_one(struct spi_master *master, 715 struct spi_device *spi, 716 struct spi_transfer *xfer) 717 { 718 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 719 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1; 720 const void *tx_buf = NULL; 721 void *rx_buf = NULL; 722 int target_len = 0, origin_len = 0; 723 int use_dma = 0; 724 int status; 725 u32 speed; 726 u8 bpw; 727 unsigned long flags; 728 729 reinit_completion(&sdd->xfer_completion); 730 731 /* Only BPW and Speed may change across transfers */ 732 bpw = xfer->bits_per_word; 733 speed = xfer->speed_hz; 734 735 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 736 sdd->cur_bpw = bpw; 737 sdd->cur_speed = speed; 738 sdd->cur_mode = spi->mode; 739 status = s3c64xx_spi_config(sdd); 740 if (status) 741 return status; 742 } 743 744 if (!is_polling(sdd) && (xfer->len > fifo_len) && 745 sdd->rx_dma.ch && sdd->tx_dma.ch) { 746 use_dma = 1; 747 748 } else if (xfer->len > fifo_len) { 749 tx_buf = xfer->tx_buf; 750 rx_buf = xfer->rx_buf; 751 origin_len = xfer->len; 752 753 target_len = xfer->len; 754 if (xfer->len > fifo_len) 755 xfer->len = fifo_len; 756 } 757 758 do { 759 spin_lock_irqsave(&sdd->lock, flags); 760 761 /* Pending only which is to be done */ 762 sdd->state &= ~RXBUSY; 763 sdd->state &= ~TXBUSY; 764 765 /* Start the signals */ 766 s3c64xx_spi_set_cs(spi, true); 767 768 status = s3c64xx_enable_datapath(sdd, xfer, use_dma); 769 770 spin_unlock_irqrestore(&sdd->lock, flags); 771 772 if (status) { 773 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status); 774 break; 775 } 776 777 if (use_dma) 778 status = s3c64xx_wait_for_dma(sdd, xfer); 779 else 780 status = s3c64xx_wait_for_pio(sdd, xfer); 781 782 if (status) { 783 dev_err(&spi->dev, 784 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n", 785 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 786 (sdd->state & RXBUSY) ? 'f' : 'p', 787 (sdd->state & TXBUSY) ? 'f' : 'p', 788 xfer->len, use_dma ? 1 : 0, status); 789 790 if (use_dma) { 791 struct dma_tx_state s; 792 793 if (xfer->tx_buf && (sdd->state & TXBUSY)) { 794 dmaengine_pause(sdd->tx_dma.ch); 795 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); 796 dmaengine_terminate_all(sdd->tx_dma.ch); 797 dev_err(&spi->dev, "TX residue: %d\n", s.residue); 798 799 } 800 if (xfer->rx_buf && (sdd->state & RXBUSY)) { 801 dmaengine_pause(sdd->rx_dma.ch); 802 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); 803 dmaengine_terminate_all(sdd->rx_dma.ch); 804 dev_err(&spi->dev, "RX residue: %d\n", s.residue); 805 } 806 } 807 } else { 808 s3c64xx_flush_fifo(sdd); 809 } 810 if (target_len > 0) { 811 target_len -= xfer->len; 812 813 if (xfer->tx_buf) 814 xfer->tx_buf += xfer->len; 815 816 if (xfer->rx_buf) 817 xfer->rx_buf += xfer->len; 818 819 if (target_len > fifo_len) 820 xfer->len = fifo_len; 821 else 822 xfer->len = target_len; 823 } 824 } while (target_len > 0); 825 826 if (origin_len) { 827 /* Restore original xfer buffers and length */ 828 xfer->tx_buf = tx_buf; 829 xfer->rx_buf = rx_buf; 830 xfer->len = origin_len; 831 } 832 833 return status; 834 } 835 836 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( 837 struct spi_device *spi) 838 { 839 struct s3c64xx_spi_csinfo *cs; 840 struct device_node *slave_np, *data_np = NULL; 841 u32 fb_delay = 0; 842 843 slave_np = spi->dev.of_node; 844 if (!slave_np) { 845 dev_err(&spi->dev, "device node not found\n"); 846 return ERR_PTR(-EINVAL); 847 } 848 849 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 850 if (!cs) 851 return ERR_PTR(-ENOMEM); 852 853 data_np = of_get_child_by_name(slave_np, "controller-data"); 854 if (!data_np) { 855 dev_info(&spi->dev, "feedback delay set to default (0)\n"); 856 return cs; 857 } 858 859 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 860 cs->fb_delay = fb_delay; 861 of_node_put(data_np); 862 return cs; 863 } 864 865 /* 866 * Here we only check the validity of requested configuration 867 * and save the configuration in a local data-structure. 868 * The controller is actually configured only just before we 869 * get a message to transfer. 870 */ 871 static int s3c64xx_spi_setup(struct spi_device *spi) 872 { 873 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 874 struct s3c64xx_spi_driver_data *sdd; 875 int err; 876 int div; 877 878 sdd = spi_master_get_devdata(spi->master); 879 if (spi->dev.of_node) { 880 cs = s3c64xx_get_slave_ctrldata(spi); 881 spi->controller_data = cs; 882 } 883 884 /* NULL is fine, we just avoid using the FB delay (=0) */ 885 if (IS_ERR(cs)) { 886 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); 887 return -ENODEV; 888 } 889 890 if (!spi_get_ctldata(spi)) 891 spi_set_ctldata(spi, cs); 892 893 pm_runtime_get_sync(&sdd->pdev->dev); 894 895 div = sdd->port_conf->clk_div; 896 897 /* Check if we can provide the requested rate */ 898 if (!sdd->port_conf->clk_from_cmu) { 899 u32 psr, speed; 900 901 /* Max possible */ 902 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); 903 904 if (spi->max_speed_hz > speed) 905 spi->max_speed_hz = speed; 906 907 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; 908 psr &= S3C64XX_SPI_PSR_MASK; 909 if (psr == S3C64XX_SPI_PSR_MASK) 910 psr--; 911 912 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 913 if (spi->max_speed_hz < speed) { 914 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 915 psr++; 916 } else { 917 err = -EINVAL; 918 goto setup_exit; 919 } 920 } 921 922 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 923 if (spi->max_speed_hz >= speed) { 924 spi->max_speed_hz = speed; 925 } else { 926 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", 927 spi->max_speed_hz); 928 err = -EINVAL; 929 goto setup_exit; 930 } 931 } 932 933 pm_runtime_mark_last_busy(&sdd->pdev->dev); 934 pm_runtime_put_autosuspend(&sdd->pdev->dev); 935 s3c64xx_spi_set_cs(spi, false); 936 937 return 0; 938 939 setup_exit: 940 pm_runtime_mark_last_busy(&sdd->pdev->dev); 941 pm_runtime_put_autosuspend(&sdd->pdev->dev); 942 /* setup() returns with device de-selected */ 943 s3c64xx_spi_set_cs(spi, false); 944 945 spi_set_ctldata(spi, NULL); 946 947 /* This was dynamically allocated on the DT path */ 948 if (spi->dev.of_node) 949 kfree(cs); 950 951 return err; 952 } 953 954 static void s3c64xx_spi_cleanup(struct spi_device *spi) 955 { 956 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 957 958 /* This was dynamically allocated on the DT path */ 959 if (spi->dev.of_node) 960 kfree(cs); 961 962 spi_set_ctldata(spi, NULL); 963 } 964 965 static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 966 { 967 struct s3c64xx_spi_driver_data *sdd = data; 968 struct spi_master *spi = sdd->master; 969 unsigned int val, clr = 0; 970 971 val = readl(sdd->regs + S3C64XX_SPI_STATUS); 972 973 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { 974 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; 975 dev_err(&spi->dev, "RX overrun\n"); 976 } 977 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { 978 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; 979 dev_err(&spi->dev, "RX underrun\n"); 980 } 981 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { 982 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; 983 dev_err(&spi->dev, "TX overrun\n"); 984 } 985 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { 986 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 987 dev_err(&spi->dev, "TX underrun\n"); 988 } 989 990 /* Clear the pending irq by setting and then clearing it */ 991 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); 992 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); 993 994 return IRQ_HANDLED; 995 } 996 997 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) 998 { 999 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1000 void __iomem *regs = sdd->regs; 1001 unsigned int val; 1002 1003 sdd->cur_speed = 0; 1004 1005 if (sci->no_cs) 1006 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 1007 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 1008 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); 1009 1010 /* Disable Interrupts - we use Polling if not DMA mode */ 1011 writel(0, regs + S3C64XX_SPI_INT_EN); 1012 1013 if (!sdd->port_conf->clk_from_cmu) 1014 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 1015 regs + S3C64XX_SPI_CLK_CFG); 1016 writel(0, regs + S3C64XX_SPI_MODE_CFG); 1017 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 1018 1019 /* Clear any irq pending bits, should set and clear the bits */ 1020 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | 1021 S3C64XX_SPI_PND_RX_UNDERRUN_CLR | 1022 S3C64XX_SPI_PND_TX_OVERRUN_CLR | 1023 S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 1024 writel(val, regs + S3C64XX_SPI_PENDING_CLR); 1025 writel(0, regs + S3C64XX_SPI_PENDING_CLR); 1026 1027 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 1028 1029 val = readl(regs + S3C64XX_SPI_MODE_CFG); 1030 val &= ~S3C64XX_SPI_MODE_4BURST; 1031 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1032 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1033 writel(val, regs + S3C64XX_SPI_MODE_CFG); 1034 1035 s3c64xx_flush_fifo(sdd); 1036 } 1037 1038 #ifdef CONFIG_OF 1039 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1040 { 1041 struct s3c64xx_spi_info *sci; 1042 u32 temp; 1043 1044 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); 1045 if (!sci) 1046 return ERR_PTR(-ENOMEM); 1047 1048 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { 1049 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); 1050 sci->src_clk_nr = 0; 1051 } else { 1052 sci->src_clk_nr = temp; 1053 } 1054 1055 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { 1056 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); 1057 sci->num_cs = 1; 1058 } else { 1059 sci->num_cs = temp; 1060 } 1061 1062 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); 1063 1064 return sci; 1065 } 1066 #else 1067 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1068 { 1069 return dev_get_platdata(dev); 1070 } 1071 #endif 1072 1073 static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( 1074 struct platform_device *pdev) 1075 { 1076 #ifdef CONFIG_OF 1077 if (pdev->dev.of_node) 1078 return of_device_get_match_data(&pdev->dev); 1079 #endif 1080 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; 1081 } 1082 1083 static int s3c64xx_spi_probe(struct platform_device *pdev) 1084 { 1085 struct resource *mem_res; 1086 struct s3c64xx_spi_driver_data *sdd; 1087 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); 1088 struct spi_master *master; 1089 int ret, irq; 1090 char clk_name[16]; 1091 1092 if (!sci && pdev->dev.of_node) { 1093 sci = s3c64xx_spi_parse_dt(&pdev->dev); 1094 if (IS_ERR(sci)) 1095 return PTR_ERR(sci); 1096 } 1097 1098 if (!sci) { 1099 dev_err(&pdev->dev, "platform_data missing!\n"); 1100 return -ENODEV; 1101 } 1102 1103 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1104 if (mem_res == NULL) { 1105 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); 1106 return -ENXIO; 1107 } 1108 1109 irq = platform_get_irq(pdev, 0); 1110 if (irq < 0) { 1111 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); 1112 return irq; 1113 } 1114 1115 master = spi_alloc_master(&pdev->dev, 1116 sizeof(struct s3c64xx_spi_driver_data)); 1117 if (master == NULL) { 1118 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 1119 return -ENOMEM; 1120 } 1121 1122 platform_set_drvdata(pdev, master); 1123 1124 sdd = spi_master_get_devdata(master); 1125 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); 1126 sdd->master = master; 1127 sdd->cntrlr_info = sci; 1128 sdd->pdev = pdev; 1129 sdd->sfr_start = mem_res->start; 1130 if (pdev->dev.of_node) { 1131 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1132 if (ret < 0) { 1133 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 1134 ret); 1135 goto err_deref_master; 1136 } 1137 sdd->port_id = ret; 1138 } else { 1139 sdd->port_id = pdev->id; 1140 } 1141 1142 sdd->cur_bpw = 8; 1143 1144 sdd->tx_dma.direction = DMA_MEM_TO_DEV; 1145 sdd->rx_dma.direction = DMA_DEV_TO_MEM; 1146 1147 master->dev.of_node = pdev->dev.of_node; 1148 master->bus_num = sdd->port_id; 1149 master->setup = s3c64xx_spi_setup; 1150 master->cleanup = s3c64xx_spi_cleanup; 1151 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1152 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; 1153 master->prepare_message = s3c64xx_spi_prepare_message; 1154 master->transfer_one = s3c64xx_spi_transfer_one; 1155 master->num_chipselect = sci->num_cs; 1156 master->use_gpio_descriptors = true; 1157 master->dma_alignment = 8; 1158 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1159 SPI_BPW_MASK(8); 1160 /* the spi->mode bits understood by this driver: */ 1161 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1162 if (sdd->port_conf->has_loopback) 1163 master->mode_bits |= SPI_LOOP; 1164 master->auto_runtime_pm = true; 1165 if (!is_polling(sdd)) 1166 master->can_dma = s3c64xx_spi_can_dma; 1167 1168 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); 1169 if (IS_ERR(sdd->regs)) { 1170 ret = PTR_ERR(sdd->regs); 1171 goto err_deref_master; 1172 } 1173 1174 if (sci->cfg_gpio && sci->cfg_gpio()) { 1175 dev_err(&pdev->dev, "Unable to config gpio\n"); 1176 ret = -EBUSY; 1177 goto err_deref_master; 1178 } 1179 1180 /* Setup clocks */ 1181 sdd->clk = devm_clk_get(&pdev->dev, "spi"); 1182 if (IS_ERR(sdd->clk)) { 1183 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); 1184 ret = PTR_ERR(sdd->clk); 1185 goto err_deref_master; 1186 } 1187 1188 ret = clk_prepare_enable(sdd->clk); 1189 if (ret) { 1190 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); 1191 goto err_deref_master; 1192 } 1193 1194 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1195 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); 1196 if (IS_ERR(sdd->src_clk)) { 1197 dev_err(&pdev->dev, 1198 "Unable to acquire clock '%s'\n", clk_name); 1199 ret = PTR_ERR(sdd->src_clk); 1200 goto err_disable_clk; 1201 } 1202 1203 ret = clk_prepare_enable(sdd->src_clk); 1204 if (ret) { 1205 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); 1206 goto err_disable_clk; 1207 } 1208 1209 if (sdd->port_conf->clk_ioclk) { 1210 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk"); 1211 if (IS_ERR(sdd->ioclk)) { 1212 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n"); 1213 ret = PTR_ERR(sdd->ioclk); 1214 goto err_disable_src_clk; 1215 } 1216 1217 ret = clk_prepare_enable(sdd->ioclk); 1218 if (ret) { 1219 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n"); 1220 goto err_disable_src_clk; 1221 } 1222 } 1223 1224 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1225 pm_runtime_use_autosuspend(&pdev->dev); 1226 pm_runtime_set_active(&pdev->dev); 1227 pm_runtime_enable(&pdev->dev); 1228 pm_runtime_get_sync(&pdev->dev); 1229 1230 /* Setup Deufult Mode */ 1231 s3c64xx_spi_hwinit(sdd); 1232 1233 spin_lock_init(&sdd->lock); 1234 init_completion(&sdd->xfer_completion); 1235 1236 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, 1237 "spi-s3c64xx", sdd); 1238 if (ret != 0) { 1239 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", 1240 irq, ret); 1241 goto err_pm_put; 1242 } 1243 1244 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1245 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1246 sdd->regs + S3C64XX_SPI_INT_EN); 1247 1248 ret = devm_spi_register_master(&pdev->dev, master); 1249 if (ret != 0) { 1250 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); 1251 goto err_pm_put; 1252 } 1253 1254 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", 1255 sdd->port_id, master->num_chipselect); 1256 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", 1257 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1); 1258 1259 pm_runtime_mark_last_busy(&pdev->dev); 1260 pm_runtime_put_autosuspend(&pdev->dev); 1261 1262 return 0; 1263 1264 err_pm_put: 1265 pm_runtime_put_noidle(&pdev->dev); 1266 pm_runtime_disable(&pdev->dev); 1267 pm_runtime_set_suspended(&pdev->dev); 1268 1269 clk_disable_unprepare(sdd->ioclk); 1270 err_disable_src_clk: 1271 clk_disable_unprepare(sdd->src_clk); 1272 err_disable_clk: 1273 clk_disable_unprepare(sdd->clk); 1274 err_deref_master: 1275 spi_master_put(master); 1276 1277 return ret; 1278 } 1279 1280 static int s3c64xx_spi_remove(struct platform_device *pdev) 1281 { 1282 struct spi_master *master = platform_get_drvdata(pdev); 1283 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1284 1285 pm_runtime_get_sync(&pdev->dev); 1286 1287 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1288 1289 if (!is_polling(sdd)) { 1290 dma_release_channel(sdd->rx_dma.ch); 1291 dma_release_channel(sdd->tx_dma.ch); 1292 } 1293 1294 clk_disable_unprepare(sdd->ioclk); 1295 1296 clk_disable_unprepare(sdd->src_clk); 1297 1298 clk_disable_unprepare(sdd->clk); 1299 1300 pm_runtime_put_noidle(&pdev->dev); 1301 pm_runtime_disable(&pdev->dev); 1302 pm_runtime_set_suspended(&pdev->dev); 1303 1304 return 0; 1305 } 1306 1307 #ifdef CONFIG_PM_SLEEP 1308 static int s3c64xx_spi_suspend(struct device *dev) 1309 { 1310 struct spi_master *master = dev_get_drvdata(dev); 1311 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1312 1313 int ret = spi_master_suspend(master); 1314 if (ret) 1315 return ret; 1316 1317 ret = pm_runtime_force_suspend(dev); 1318 if (ret < 0) 1319 return ret; 1320 1321 sdd->cur_speed = 0; /* Output Clock is stopped */ 1322 1323 return 0; 1324 } 1325 1326 static int s3c64xx_spi_resume(struct device *dev) 1327 { 1328 struct spi_master *master = dev_get_drvdata(dev); 1329 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1330 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1331 int ret; 1332 1333 if (sci->cfg_gpio) 1334 sci->cfg_gpio(); 1335 1336 ret = pm_runtime_force_resume(dev); 1337 if (ret < 0) 1338 return ret; 1339 1340 return spi_master_resume(master); 1341 } 1342 #endif /* CONFIG_PM_SLEEP */ 1343 1344 #ifdef CONFIG_PM 1345 static int s3c64xx_spi_runtime_suspend(struct device *dev) 1346 { 1347 struct spi_master *master = dev_get_drvdata(dev); 1348 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1349 1350 clk_disable_unprepare(sdd->clk); 1351 clk_disable_unprepare(sdd->src_clk); 1352 clk_disable_unprepare(sdd->ioclk); 1353 1354 return 0; 1355 } 1356 1357 static int s3c64xx_spi_runtime_resume(struct device *dev) 1358 { 1359 struct spi_master *master = dev_get_drvdata(dev); 1360 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1361 int ret; 1362 1363 if (sdd->port_conf->clk_ioclk) { 1364 ret = clk_prepare_enable(sdd->ioclk); 1365 if (ret != 0) 1366 return ret; 1367 } 1368 1369 ret = clk_prepare_enable(sdd->src_clk); 1370 if (ret != 0) 1371 goto err_disable_ioclk; 1372 1373 ret = clk_prepare_enable(sdd->clk); 1374 if (ret != 0) 1375 goto err_disable_src_clk; 1376 1377 s3c64xx_spi_hwinit(sdd); 1378 1379 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1380 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1381 sdd->regs + S3C64XX_SPI_INT_EN); 1382 1383 return 0; 1384 1385 err_disable_src_clk: 1386 clk_disable_unprepare(sdd->src_clk); 1387 err_disable_ioclk: 1388 clk_disable_unprepare(sdd->ioclk); 1389 1390 return ret; 1391 } 1392 #endif /* CONFIG_PM */ 1393 1394 static const struct dev_pm_ops s3c64xx_spi_pm = { 1395 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) 1396 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, 1397 s3c64xx_spi_runtime_resume, NULL) 1398 }; 1399 1400 static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1401 .fifo_lvl_mask = { 0x7f }, 1402 .rx_lvl_offset = 13, 1403 .tx_st_done = 21, 1404 .clk_div = 2, 1405 .high_speed = true, 1406 }; 1407 1408 static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1409 .fifo_lvl_mask = { 0x7f, 0x7F }, 1410 .rx_lvl_offset = 13, 1411 .tx_st_done = 21, 1412 .clk_div = 2, 1413 }; 1414 1415 static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1416 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1417 .rx_lvl_offset = 15, 1418 .tx_st_done = 25, 1419 .clk_div = 2, 1420 .high_speed = true, 1421 }; 1422 1423 static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1424 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1425 .rx_lvl_offset = 15, 1426 .tx_st_done = 25, 1427 .clk_div = 2, 1428 .high_speed = true, 1429 .clk_from_cmu = true, 1430 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1431 }; 1432 1433 static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { 1434 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, 1435 .rx_lvl_offset = 15, 1436 .tx_st_done = 25, 1437 .clk_div = 2, 1438 .high_speed = true, 1439 .clk_from_cmu = true, 1440 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1441 }; 1442 1443 static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { 1444 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, 1445 .rx_lvl_offset = 15, 1446 .tx_st_done = 25, 1447 .clk_div = 2, 1448 .high_speed = true, 1449 .clk_from_cmu = true, 1450 .clk_ioclk = true, 1451 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1452 }; 1453 1454 static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { 1455 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 1456 0x7f, 0x7f, 0x7f, 0x7f}, 1457 .rx_lvl_offset = 15, 1458 .tx_st_done = 25, 1459 .clk_div = 4, 1460 .high_speed = true, 1461 .clk_from_cmu = true, 1462 .clk_ioclk = true, 1463 .has_loopback = true, 1464 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1465 }; 1466 1467 static const struct s3c64xx_spi_port_config fsd_spi_port_config = { 1468 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, 1469 .rx_lvl_offset = 15, 1470 .tx_st_done = 25, 1471 .clk_div = 2, 1472 .high_speed = true, 1473 .clk_from_cmu = true, 1474 .clk_ioclk = false, 1475 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1476 }; 1477 1478 static const struct platform_device_id s3c64xx_spi_driver_ids[] = { 1479 { 1480 .name = "s3c2443-spi", 1481 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, 1482 }, { 1483 .name = "s3c6410-spi", 1484 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1485 }, 1486 { }, 1487 }; 1488 1489 static const struct of_device_id s3c64xx_spi_dt_match[] = { 1490 { .compatible = "samsung,s3c2443-spi", 1491 .data = (void *)&s3c2443_spi_port_config, 1492 }, 1493 { .compatible = "samsung,s3c6410-spi", 1494 .data = (void *)&s3c6410_spi_port_config, 1495 }, 1496 { .compatible = "samsung,s5pv210-spi", 1497 .data = (void *)&s5pv210_spi_port_config, 1498 }, 1499 { .compatible = "samsung,exynos4210-spi", 1500 .data = (void *)&exynos4_spi_port_config, 1501 }, 1502 { .compatible = "samsung,exynos7-spi", 1503 .data = (void *)&exynos7_spi_port_config, 1504 }, 1505 { .compatible = "samsung,exynos5433-spi", 1506 .data = (void *)&exynos5433_spi_port_config, 1507 }, 1508 { .compatible = "samsung,exynosautov9-spi", 1509 .data = (void *)&exynosautov9_spi_port_config, 1510 }, 1511 { .compatible = "tesla,fsd-spi", 1512 .data = (void *)&fsd_spi_port_config, 1513 }, 1514 { }, 1515 }; 1516 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1517 1518 static struct platform_driver s3c64xx_spi_driver = { 1519 .driver = { 1520 .name = "s3c64xx-spi", 1521 .pm = &s3c64xx_spi_pm, 1522 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), 1523 }, 1524 .probe = s3c64xx_spi_probe, 1525 .remove = s3c64xx_spi_remove, 1526 .id_table = s3c64xx_spi_driver_ids, 1527 }; 1528 MODULE_ALIAS("platform:s3c64xx-spi"); 1529 1530 module_platform_driver(s3c64xx_spi_driver); 1531 1532 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1533 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1534 MODULE_LICENSE("GPL"); 1535