1 /* 2 * Copyright (C) 2009 Samsung Electronics Ltd. 3 * Jaswinder Singh <jassi.brar@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/workqueue.h> 23 #include <linux/interrupt.h> 24 #include <linux/delay.h> 25 #include <linux/clk.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/dmaengine.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/spi/spi.h> 31 #include <linux/gpio.h> 32 #include <linux/of.h> 33 #include <linux/of_gpio.h> 34 35 #include <linux/platform_data/spi-s3c64xx.h> 36 37 #define MAX_SPI_PORTS 3 38 #define S3C64XX_SPI_QUIRK_POLL (1 << 0) 39 40 /* Registers and bit-fields */ 41 42 #define S3C64XX_SPI_CH_CFG 0x00 43 #define S3C64XX_SPI_CLK_CFG 0x04 44 #define S3C64XX_SPI_MODE_CFG 0x08 45 #define S3C64XX_SPI_SLAVE_SEL 0x0C 46 #define S3C64XX_SPI_INT_EN 0x10 47 #define S3C64XX_SPI_STATUS 0x14 48 #define S3C64XX_SPI_TX_DATA 0x18 49 #define S3C64XX_SPI_RX_DATA 0x1C 50 #define S3C64XX_SPI_PACKET_CNT 0x20 51 #define S3C64XX_SPI_PENDING_CLR 0x24 52 #define S3C64XX_SPI_SWAP_CFG 0x28 53 #define S3C64XX_SPI_FB_CLK 0x2C 54 55 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 56 #define S3C64XX_SPI_CH_SW_RST (1<<5) 57 #define S3C64XX_SPI_CH_SLAVE (1<<4) 58 #define S3C64XX_SPI_CPOL_L (1<<3) 59 #define S3C64XX_SPI_CPHA_B (1<<2) 60 #define S3C64XX_SPI_CH_RXCH_ON (1<<1) 61 #define S3C64XX_SPI_CH_TXCH_ON (1<<0) 62 63 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 64 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 65 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 66 #define S3C64XX_SPI_PSR_MASK 0xff 67 68 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 69 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 70 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 71 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 72 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 73 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 74 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 75 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 76 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 77 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 78 #define S3C64XX_SPI_MODE_4BURST (1<<0) 79 80 #define S3C64XX_SPI_SLAVE_AUTO (1<<1) 81 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) 82 83 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 84 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 85 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 86 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 87 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 88 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 89 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 90 91 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 92 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 93 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 94 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 95 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 96 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 97 98 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 99 100 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 101 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 102 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 103 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 104 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 105 106 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 107 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 108 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 109 #define S3C64XX_SPI_SWAP_RX_EN (1<<4) 110 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 111 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 112 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 113 #define S3C64XX_SPI_SWAP_TX_EN (1<<0) 114 115 #define S3C64XX_SPI_FBCLK_MSK (3<<0) 116 117 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) 118 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ 119 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) 120 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) 121 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ 122 FIFO_LVL_MASK(i)) 123 124 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 125 #define S3C64XX_SPI_TRAILCNT_OFF 19 126 127 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT 128 129 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 130 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) 131 132 #define RXBUSY (1<<2) 133 #define TXBUSY (1<<3) 134 135 struct s3c64xx_spi_dma_data { 136 struct dma_chan *ch; 137 enum dma_transfer_direction direction; 138 unsigned int dmach; 139 }; 140 141 /** 142 * struct s3c64xx_spi_info - SPI Controller hardware info 143 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. 144 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. 145 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. 146 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. 147 * @clk_from_cmu: True, if the controller does not include a clock mux and 148 * prescaler unit. 149 * 150 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but 151 * differ in some aspects such as the size of the fifo and spi bus clock 152 * setup. Such differences are specified to the driver using this structure 153 * which is provided as driver data to the driver. 154 */ 155 struct s3c64xx_spi_port_config { 156 int fifo_lvl_mask[MAX_SPI_PORTS]; 157 int rx_lvl_offset; 158 int tx_st_done; 159 int quirks; 160 bool high_speed; 161 bool clk_from_cmu; 162 }; 163 164 /** 165 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 166 * @clk: Pointer to the spi clock. 167 * @src_clk: Pointer to the clock used to generate SPI signals. 168 * @master: Pointer to the SPI Protocol master. 169 * @cntrlr_info: Platform specific data for the controller this driver manages. 170 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. 171 * @lock: Controller specific lock. 172 * @state: Set of FLAGS to indicate status. 173 * @rx_dmach: Controller's DMA channel for Rx. 174 * @tx_dmach: Controller's DMA channel for Tx. 175 * @sfr_start: BUS address of SPI controller regs. 176 * @regs: Pointer to ioremap'ed controller registers. 177 * @irq: interrupt 178 * @xfer_completion: To indicate completion of xfer task. 179 * @cur_mode: Stores the active configuration of the controller. 180 * @cur_bpw: Stores the active bits per word settings. 181 * @cur_speed: Stores the active xfer clock speed. 182 */ 183 struct s3c64xx_spi_driver_data { 184 void __iomem *regs; 185 struct clk *clk; 186 struct clk *src_clk; 187 struct platform_device *pdev; 188 struct spi_master *master; 189 struct s3c64xx_spi_info *cntrlr_info; 190 struct spi_device *tgl_spi; 191 spinlock_t lock; 192 unsigned long sfr_start; 193 struct completion xfer_completion; 194 unsigned state; 195 unsigned cur_mode, cur_bpw; 196 unsigned cur_speed; 197 struct s3c64xx_spi_dma_data rx_dma; 198 struct s3c64xx_spi_dma_data tx_dma; 199 struct s3c64xx_spi_port_config *port_conf; 200 unsigned int port_id; 201 bool cs_gpio; 202 }; 203 204 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) 205 { 206 void __iomem *regs = sdd->regs; 207 unsigned long loops; 208 u32 val; 209 210 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 211 212 val = readl(regs + S3C64XX_SPI_CH_CFG); 213 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 214 writel(val, regs + S3C64XX_SPI_CH_CFG); 215 216 val = readl(regs + S3C64XX_SPI_CH_CFG); 217 val |= S3C64XX_SPI_CH_SW_RST; 218 val &= ~S3C64XX_SPI_CH_HS_EN; 219 writel(val, regs + S3C64XX_SPI_CH_CFG); 220 221 /* Flush TxFIFO*/ 222 loops = msecs_to_loops(1); 223 do { 224 val = readl(regs + S3C64XX_SPI_STATUS); 225 } while (TX_FIFO_LVL(val, sdd) && loops--); 226 227 if (loops == 0) 228 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 229 230 /* Flush RxFIFO*/ 231 loops = msecs_to_loops(1); 232 do { 233 val = readl(regs + S3C64XX_SPI_STATUS); 234 if (RX_FIFO_LVL(val, sdd)) 235 readl(regs + S3C64XX_SPI_RX_DATA); 236 else 237 break; 238 } while (loops--); 239 240 if (loops == 0) 241 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 242 243 val = readl(regs + S3C64XX_SPI_CH_CFG); 244 val &= ~S3C64XX_SPI_CH_SW_RST; 245 writel(val, regs + S3C64XX_SPI_CH_CFG); 246 247 val = readl(regs + S3C64XX_SPI_MODE_CFG); 248 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 249 writel(val, regs + S3C64XX_SPI_MODE_CFG); 250 } 251 252 static void s3c64xx_spi_dmacb(void *data) 253 { 254 struct s3c64xx_spi_driver_data *sdd; 255 struct s3c64xx_spi_dma_data *dma = data; 256 unsigned long flags; 257 258 if (dma->direction == DMA_DEV_TO_MEM) 259 sdd = container_of(data, 260 struct s3c64xx_spi_driver_data, rx_dma); 261 else 262 sdd = container_of(data, 263 struct s3c64xx_spi_driver_data, tx_dma); 264 265 spin_lock_irqsave(&sdd->lock, flags); 266 267 if (dma->direction == DMA_DEV_TO_MEM) { 268 sdd->state &= ~RXBUSY; 269 if (!(sdd->state & TXBUSY)) 270 complete(&sdd->xfer_completion); 271 } else { 272 sdd->state &= ~TXBUSY; 273 if (!(sdd->state & RXBUSY)) 274 complete(&sdd->xfer_completion); 275 } 276 277 spin_unlock_irqrestore(&sdd->lock, flags); 278 } 279 280 static void prepare_dma(struct s3c64xx_spi_dma_data *dma, 281 struct sg_table *sgt) 282 { 283 struct s3c64xx_spi_driver_data *sdd; 284 struct dma_slave_config config; 285 struct dma_async_tx_descriptor *desc; 286 287 memset(&config, 0, sizeof(config)); 288 289 if (dma->direction == DMA_DEV_TO_MEM) { 290 sdd = container_of((void *)dma, 291 struct s3c64xx_spi_driver_data, rx_dma); 292 config.direction = dma->direction; 293 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 294 config.src_addr_width = sdd->cur_bpw / 8; 295 config.src_maxburst = 1; 296 dmaengine_slave_config(dma->ch, &config); 297 } else { 298 sdd = container_of((void *)dma, 299 struct s3c64xx_spi_driver_data, tx_dma); 300 config.direction = dma->direction; 301 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 302 config.dst_addr_width = sdd->cur_bpw / 8; 303 config.dst_maxburst = 1; 304 dmaengine_slave_config(dma->ch, &config); 305 } 306 307 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, 308 dma->direction, DMA_PREP_INTERRUPT); 309 310 desc->callback = s3c64xx_spi_dmacb; 311 desc->callback_param = dma; 312 313 dmaengine_submit(desc); 314 dma_async_issue_pending(dma->ch); 315 } 316 317 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) 318 { 319 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 320 dma_filter_fn filter = sdd->cntrlr_info->filter; 321 struct device *dev = &sdd->pdev->dev; 322 dma_cap_mask_t mask; 323 int ret; 324 325 if (!is_polling(sdd)) { 326 dma_cap_zero(mask); 327 dma_cap_set(DMA_SLAVE, mask); 328 329 /* Acquire DMA channels */ 330 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter, 331 (void *)sdd->rx_dma.dmach, dev, "rx"); 332 if (!sdd->rx_dma.ch) { 333 dev_err(dev, "Failed to get RX DMA channel\n"); 334 ret = -EBUSY; 335 goto out; 336 } 337 spi->dma_rx = sdd->rx_dma.ch; 338 339 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, 340 (void *)sdd->tx_dma.dmach, dev, "tx"); 341 if (!sdd->tx_dma.ch) { 342 dev_err(dev, "Failed to get TX DMA channel\n"); 343 ret = -EBUSY; 344 goto out_rx; 345 } 346 spi->dma_tx = sdd->tx_dma.ch; 347 } 348 349 ret = pm_runtime_get_sync(&sdd->pdev->dev); 350 if (ret < 0) { 351 dev_err(dev, "Failed to enable device: %d\n", ret); 352 goto out_tx; 353 } 354 355 return 0; 356 357 out_tx: 358 dma_release_channel(sdd->tx_dma.ch); 359 out_rx: 360 dma_release_channel(sdd->rx_dma.ch); 361 out: 362 return ret; 363 } 364 365 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) 366 { 367 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 368 369 /* Free DMA channels */ 370 if (!is_polling(sdd)) { 371 dma_release_channel(sdd->rx_dma.ch); 372 dma_release_channel(sdd->tx_dma.ch); 373 } 374 375 pm_runtime_put(&sdd->pdev->dev); 376 return 0; 377 } 378 379 static bool s3c64xx_spi_can_dma(struct spi_master *master, 380 struct spi_device *spi, 381 struct spi_transfer *xfer) 382 { 383 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 384 385 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; 386 } 387 388 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, 389 struct spi_device *spi, 390 struct spi_transfer *xfer, int dma_mode) 391 { 392 void __iomem *regs = sdd->regs; 393 u32 modecfg, chcfg; 394 395 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 396 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 397 398 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 399 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 400 401 if (dma_mode) { 402 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 403 } else { 404 /* Always shift in data in FIFO, even if xfer is Tx only, 405 * this helps setting PCKT_CNT value for generating clocks 406 * as exactly needed. 407 */ 408 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 409 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 410 | S3C64XX_SPI_PACKET_CNT_EN, 411 regs + S3C64XX_SPI_PACKET_CNT); 412 } 413 414 if (xfer->tx_buf != NULL) { 415 sdd->state |= TXBUSY; 416 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 417 if (dma_mode) { 418 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 419 prepare_dma(&sdd->tx_dma, &xfer->tx_sg); 420 } else { 421 switch (sdd->cur_bpw) { 422 case 32: 423 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, 424 xfer->tx_buf, xfer->len / 4); 425 break; 426 case 16: 427 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, 428 xfer->tx_buf, xfer->len / 2); 429 break; 430 default: 431 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, 432 xfer->tx_buf, xfer->len); 433 break; 434 } 435 } 436 } 437 438 if (xfer->rx_buf != NULL) { 439 sdd->state |= RXBUSY; 440 441 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL 442 && !(sdd->cur_mode & SPI_CPHA)) 443 chcfg |= S3C64XX_SPI_CH_HS_EN; 444 445 if (dma_mode) { 446 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 447 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 448 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 449 | S3C64XX_SPI_PACKET_CNT_EN, 450 regs + S3C64XX_SPI_PACKET_CNT); 451 prepare_dma(&sdd->rx_dma, &xfer->rx_sg); 452 } 453 } 454 455 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 456 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 457 } 458 459 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 460 int timeout_ms) 461 { 462 void __iomem *regs = sdd->regs; 463 unsigned long val = 1; 464 u32 status; 465 466 /* max fifo depth available */ 467 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; 468 469 if (timeout_ms) 470 val = msecs_to_loops(timeout_ms); 471 472 do { 473 status = readl(regs + S3C64XX_SPI_STATUS); 474 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); 475 476 /* return the actual received data length */ 477 return RX_FIFO_LVL(status, sdd); 478 } 479 480 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd, 481 struct spi_transfer *xfer) 482 { 483 void __iomem *regs = sdd->regs; 484 unsigned long val; 485 u32 status; 486 int ms; 487 488 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 489 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 490 ms += 10; /* some tolerance */ 491 492 val = msecs_to_jiffies(ms) + 10; 493 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 494 495 /* 496 * If the previous xfer was completed within timeout, then 497 * proceed further else return -EIO. 498 * DmaTx returns after simply writing data in the FIFO, 499 * w/o waiting for real transmission on the bus to finish. 500 * DmaRx returns only after Dma read data from FIFO which 501 * needs bus transmission to finish, so we don't worry if 502 * Xfer involved Rx(with or without Tx). 503 */ 504 if (val && !xfer->rx_buf) { 505 val = msecs_to_loops(10); 506 status = readl(regs + S3C64XX_SPI_STATUS); 507 while ((TX_FIFO_LVL(status, sdd) 508 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) 509 && --val) { 510 cpu_relax(); 511 status = readl(regs + S3C64XX_SPI_STATUS); 512 } 513 514 } 515 516 /* If timed out while checking rx/tx status return error */ 517 if (!val) 518 return -EIO; 519 520 return 0; 521 } 522 523 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd, 524 struct spi_transfer *xfer) 525 { 526 void __iomem *regs = sdd->regs; 527 unsigned long val; 528 u32 status; 529 int loops; 530 u32 cpy_len; 531 u8 *buf; 532 int ms; 533 534 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 535 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 536 ms += 10; /* some tolerance */ 537 538 val = msecs_to_loops(ms); 539 do { 540 status = readl(regs + S3C64XX_SPI_STATUS); 541 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 542 543 544 /* If it was only Tx */ 545 if (!xfer->rx_buf) { 546 sdd->state &= ~TXBUSY; 547 return 0; 548 } 549 550 /* 551 * If the receive length is bigger than the controller fifo 552 * size, calculate the loops and read the fifo as many times. 553 * loops = length / max fifo size (calculated by using the 554 * fifo mask). 555 * For any size less than the fifo size the below code is 556 * executed atleast once. 557 */ 558 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); 559 buf = xfer->rx_buf; 560 do { 561 /* wait for data to be received in the fifo */ 562 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, 563 (loops ? ms : 0)); 564 565 switch (sdd->cur_bpw) { 566 case 32: 567 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 568 buf, cpy_len / 4); 569 break; 570 case 16: 571 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 572 buf, cpy_len / 2); 573 break; 574 default: 575 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 576 buf, cpy_len); 577 break; 578 } 579 580 buf = buf + cpy_len; 581 } while (loops--); 582 sdd->state &= ~RXBUSY; 583 584 return 0; 585 } 586 587 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 588 { 589 void __iomem *regs = sdd->regs; 590 u32 val; 591 592 /* Disable Clock */ 593 if (sdd->port_conf->clk_from_cmu) { 594 clk_disable_unprepare(sdd->src_clk); 595 } else { 596 val = readl(regs + S3C64XX_SPI_CLK_CFG); 597 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 598 writel(val, regs + S3C64XX_SPI_CLK_CFG); 599 } 600 601 /* Set Polarity and Phase */ 602 val = readl(regs + S3C64XX_SPI_CH_CFG); 603 val &= ~(S3C64XX_SPI_CH_SLAVE | 604 S3C64XX_SPI_CPOL_L | 605 S3C64XX_SPI_CPHA_B); 606 607 if (sdd->cur_mode & SPI_CPOL) 608 val |= S3C64XX_SPI_CPOL_L; 609 610 if (sdd->cur_mode & SPI_CPHA) 611 val |= S3C64XX_SPI_CPHA_B; 612 613 writel(val, regs + S3C64XX_SPI_CH_CFG); 614 615 /* Set Channel & DMA Mode */ 616 val = readl(regs + S3C64XX_SPI_MODE_CFG); 617 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 618 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 619 620 switch (sdd->cur_bpw) { 621 case 32: 622 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 623 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 624 break; 625 case 16: 626 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 627 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 628 break; 629 default: 630 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 631 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 632 break; 633 } 634 635 writel(val, regs + S3C64XX_SPI_MODE_CFG); 636 637 if (sdd->port_conf->clk_from_cmu) { 638 /* Configure Clock */ 639 /* There is half-multiplier before the SPI */ 640 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); 641 /* Enable Clock */ 642 clk_prepare_enable(sdd->src_clk); 643 } else { 644 /* Configure Clock */ 645 val = readl(regs + S3C64XX_SPI_CLK_CFG); 646 val &= ~S3C64XX_SPI_PSR_MASK; 647 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) 648 & S3C64XX_SPI_PSR_MASK); 649 writel(val, regs + S3C64XX_SPI_CLK_CFG); 650 651 /* Enable Clock */ 652 val = readl(regs + S3C64XX_SPI_CLK_CFG); 653 val |= S3C64XX_SPI_ENCLK_ENABLE; 654 writel(val, regs + S3C64XX_SPI_CLK_CFG); 655 } 656 } 657 658 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 659 660 static int s3c64xx_spi_prepare_message(struct spi_master *master, 661 struct spi_message *msg) 662 { 663 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 664 struct spi_device *spi = msg->spi; 665 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 666 667 /* If Master's(controller) state differs from that needed by Slave */ 668 if (sdd->cur_speed != spi->max_speed_hz 669 || sdd->cur_mode != spi->mode 670 || sdd->cur_bpw != spi->bits_per_word) { 671 sdd->cur_bpw = spi->bits_per_word; 672 sdd->cur_speed = spi->max_speed_hz; 673 sdd->cur_mode = spi->mode; 674 s3c64xx_spi_config(sdd); 675 } 676 677 /* Configure feedback delay */ 678 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 679 680 return 0; 681 } 682 683 static int s3c64xx_spi_transfer_one(struct spi_master *master, 684 struct spi_device *spi, 685 struct spi_transfer *xfer) 686 { 687 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 688 int status; 689 u32 speed; 690 u8 bpw; 691 unsigned long flags; 692 int use_dma; 693 694 reinit_completion(&sdd->xfer_completion); 695 696 /* Only BPW and Speed may change across transfers */ 697 bpw = xfer->bits_per_word; 698 speed = xfer->speed_hz ? : spi->max_speed_hz; 699 700 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 701 sdd->cur_bpw = bpw; 702 sdd->cur_speed = speed; 703 s3c64xx_spi_config(sdd); 704 } 705 706 /* Polling method for xfers not bigger than FIFO capacity */ 707 use_dma = 0; 708 if (!is_polling(sdd) && 709 (sdd->rx_dma.ch && sdd->tx_dma.ch && 710 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))) 711 use_dma = 1; 712 713 spin_lock_irqsave(&sdd->lock, flags); 714 715 /* Pending only which is to be done */ 716 sdd->state &= ~RXBUSY; 717 sdd->state &= ~TXBUSY; 718 719 enable_datapath(sdd, spi, xfer, use_dma); 720 721 /* Start the signals */ 722 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 723 724 spin_unlock_irqrestore(&sdd->lock, flags); 725 726 if (use_dma) 727 status = wait_for_dma(sdd, xfer); 728 else 729 status = wait_for_pio(sdd, xfer); 730 731 if (status) { 732 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", 733 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 734 (sdd->state & RXBUSY) ? 'f' : 'p', 735 (sdd->state & TXBUSY) ? 'f' : 'p', 736 xfer->len); 737 738 if (use_dma) { 739 if (xfer->tx_buf != NULL 740 && (sdd->state & TXBUSY)) 741 dmaengine_terminate_all(sdd->tx_dma.ch); 742 if (xfer->rx_buf != NULL 743 && (sdd->state & RXBUSY)) 744 dmaengine_terminate_all(sdd->rx_dma.ch); 745 } 746 } else { 747 flush_fifo(sdd); 748 } 749 750 return status; 751 } 752 753 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( 754 struct spi_device *spi) 755 { 756 struct s3c64xx_spi_csinfo *cs; 757 struct device_node *slave_np, *data_np = NULL; 758 struct s3c64xx_spi_driver_data *sdd; 759 u32 fb_delay = 0; 760 761 sdd = spi_master_get_devdata(spi->master); 762 slave_np = spi->dev.of_node; 763 if (!slave_np) { 764 dev_err(&spi->dev, "device node not found\n"); 765 return ERR_PTR(-EINVAL); 766 } 767 768 data_np = of_get_child_by_name(slave_np, "controller-data"); 769 if (!data_np) { 770 dev_err(&spi->dev, "child node 'controller-data' not found\n"); 771 return ERR_PTR(-EINVAL); 772 } 773 774 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 775 if (!cs) { 776 dev_err(&spi->dev, "could not allocate memory for controller data\n"); 777 of_node_put(data_np); 778 return ERR_PTR(-ENOMEM); 779 } 780 781 /* The CS line is asserted/deasserted by the gpio pin */ 782 if (sdd->cs_gpio) 783 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); 784 785 if (!gpio_is_valid(cs->line)) { 786 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n"); 787 kfree(cs); 788 of_node_put(data_np); 789 return ERR_PTR(-EINVAL); 790 } 791 792 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 793 cs->fb_delay = fb_delay; 794 of_node_put(data_np); 795 return cs; 796 } 797 798 /* 799 * Here we only check the validity of requested configuration 800 * and save the configuration in a local data-structure. 801 * The controller is actually configured only just before we 802 * get a message to transfer. 803 */ 804 static int s3c64xx_spi_setup(struct spi_device *spi) 805 { 806 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 807 struct s3c64xx_spi_driver_data *sdd; 808 struct s3c64xx_spi_info *sci; 809 int err; 810 811 sdd = spi_master_get_devdata(spi->master); 812 if (!cs && spi->dev.of_node) { 813 cs = s3c64xx_get_slave_ctrldata(spi); 814 spi->controller_data = cs; 815 } 816 817 if (IS_ERR_OR_NULL(cs)) { 818 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); 819 return -ENODEV; 820 } 821 822 if (!spi_get_ctldata(spi)) { 823 /* Request gpio only if cs line is asserted by gpio pins */ 824 if (sdd->cs_gpio) { 825 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH, 826 dev_name(&spi->dev)); 827 if (err) { 828 dev_err(&spi->dev, 829 "Failed to get /CS gpio [%d]: %d\n", 830 cs->line, err); 831 goto err_gpio_req; 832 } 833 834 spi->cs_gpio = cs->line; 835 } 836 837 spi_set_ctldata(spi, cs); 838 } 839 840 sci = sdd->cntrlr_info; 841 842 pm_runtime_get_sync(&sdd->pdev->dev); 843 844 /* Check if we can provide the requested rate */ 845 if (!sdd->port_conf->clk_from_cmu) { 846 u32 psr, speed; 847 848 /* Max possible */ 849 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); 850 851 if (spi->max_speed_hz > speed) 852 spi->max_speed_hz = speed; 853 854 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; 855 psr &= S3C64XX_SPI_PSR_MASK; 856 if (psr == S3C64XX_SPI_PSR_MASK) 857 psr--; 858 859 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 860 if (spi->max_speed_hz < speed) { 861 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 862 psr++; 863 } else { 864 err = -EINVAL; 865 goto setup_exit; 866 } 867 } 868 869 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 870 if (spi->max_speed_hz >= speed) { 871 spi->max_speed_hz = speed; 872 } else { 873 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", 874 spi->max_speed_hz); 875 err = -EINVAL; 876 goto setup_exit; 877 } 878 } 879 880 pm_runtime_put(&sdd->pdev->dev); 881 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 882 return 0; 883 884 setup_exit: 885 pm_runtime_put(&sdd->pdev->dev); 886 /* setup() returns with device de-selected */ 887 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 888 889 gpio_free(cs->line); 890 spi_set_ctldata(spi, NULL); 891 892 err_gpio_req: 893 if (spi->dev.of_node) 894 kfree(cs); 895 896 return err; 897 } 898 899 static void s3c64xx_spi_cleanup(struct spi_device *spi) 900 { 901 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 902 struct s3c64xx_spi_driver_data *sdd; 903 904 sdd = spi_master_get_devdata(spi->master); 905 if (spi->cs_gpio) { 906 gpio_free(spi->cs_gpio); 907 if (spi->dev.of_node) 908 kfree(cs); 909 } 910 spi_set_ctldata(spi, NULL); 911 } 912 913 static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 914 { 915 struct s3c64xx_spi_driver_data *sdd = data; 916 struct spi_master *spi = sdd->master; 917 unsigned int val, clr = 0; 918 919 val = readl(sdd->regs + S3C64XX_SPI_STATUS); 920 921 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { 922 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; 923 dev_err(&spi->dev, "RX overrun\n"); 924 } 925 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { 926 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; 927 dev_err(&spi->dev, "RX underrun\n"); 928 } 929 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { 930 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; 931 dev_err(&spi->dev, "TX overrun\n"); 932 } 933 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { 934 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 935 dev_err(&spi->dev, "TX underrun\n"); 936 } 937 938 /* Clear the pending irq by setting and then clearing it */ 939 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); 940 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); 941 942 return IRQ_HANDLED; 943 } 944 945 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) 946 { 947 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 948 void __iomem *regs = sdd->regs; 949 unsigned int val; 950 951 sdd->cur_speed = 0; 952 953 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 954 955 /* Disable Interrupts - we use Polling if not DMA mode */ 956 writel(0, regs + S3C64XX_SPI_INT_EN); 957 958 if (!sdd->port_conf->clk_from_cmu) 959 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 960 regs + S3C64XX_SPI_CLK_CFG); 961 writel(0, regs + S3C64XX_SPI_MODE_CFG); 962 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 963 964 /* Clear any irq pending bits, should set and clear the bits */ 965 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | 966 S3C64XX_SPI_PND_RX_UNDERRUN_CLR | 967 S3C64XX_SPI_PND_TX_OVERRUN_CLR | 968 S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 969 writel(val, regs + S3C64XX_SPI_PENDING_CLR); 970 writel(0, regs + S3C64XX_SPI_PENDING_CLR); 971 972 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 973 974 val = readl(regs + S3C64XX_SPI_MODE_CFG); 975 val &= ~S3C64XX_SPI_MODE_4BURST; 976 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 977 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 978 writel(val, regs + S3C64XX_SPI_MODE_CFG); 979 980 flush_fifo(sdd); 981 } 982 983 #ifdef CONFIG_OF 984 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 985 { 986 struct s3c64xx_spi_info *sci; 987 u32 temp; 988 989 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); 990 if (!sci) { 991 dev_err(dev, "memory allocation for spi_info failed\n"); 992 return ERR_PTR(-ENOMEM); 993 } 994 995 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { 996 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); 997 sci->src_clk_nr = 0; 998 } else { 999 sci->src_clk_nr = temp; 1000 } 1001 1002 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { 1003 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); 1004 sci->num_cs = 1; 1005 } else { 1006 sci->num_cs = temp; 1007 } 1008 1009 return sci; 1010 } 1011 #else 1012 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1013 { 1014 return dev_get_platdata(dev); 1015 } 1016 #endif 1017 1018 static const struct of_device_id s3c64xx_spi_dt_match[]; 1019 1020 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( 1021 struct platform_device *pdev) 1022 { 1023 #ifdef CONFIG_OF 1024 if (pdev->dev.of_node) { 1025 const struct of_device_id *match; 1026 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); 1027 return (struct s3c64xx_spi_port_config *)match->data; 1028 } 1029 #endif 1030 return (struct s3c64xx_spi_port_config *) 1031 platform_get_device_id(pdev)->driver_data; 1032 } 1033 1034 static int s3c64xx_spi_probe(struct platform_device *pdev) 1035 { 1036 struct resource *mem_res; 1037 struct resource *res; 1038 struct s3c64xx_spi_driver_data *sdd; 1039 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); 1040 struct spi_master *master; 1041 int ret, irq; 1042 char clk_name[16]; 1043 1044 if (!sci && pdev->dev.of_node) { 1045 sci = s3c64xx_spi_parse_dt(&pdev->dev); 1046 if (IS_ERR(sci)) 1047 return PTR_ERR(sci); 1048 } 1049 1050 if (!sci) { 1051 dev_err(&pdev->dev, "platform_data missing!\n"); 1052 return -ENODEV; 1053 } 1054 1055 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1056 if (mem_res == NULL) { 1057 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); 1058 return -ENXIO; 1059 } 1060 1061 irq = platform_get_irq(pdev, 0); 1062 if (irq < 0) { 1063 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); 1064 return irq; 1065 } 1066 1067 master = spi_alloc_master(&pdev->dev, 1068 sizeof(struct s3c64xx_spi_driver_data)); 1069 if (master == NULL) { 1070 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 1071 return -ENOMEM; 1072 } 1073 1074 platform_set_drvdata(pdev, master); 1075 1076 sdd = spi_master_get_devdata(master); 1077 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); 1078 sdd->master = master; 1079 sdd->cntrlr_info = sci; 1080 sdd->pdev = pdev; 1081 sdd->sfr_start = mem_res->start; 1082 sdd->cs_gpio = true; 1083 if (pdev->dev.of_node) { 1084 if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL)) 1085 sdd->cs_gpio = false; 1086 1087 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1088 if (ret < 0) { 1089 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 1090 ret); 1091 goto err0; 1092 } 1093 sdd->port_id = ret; 1094 } else { 1095 sdd->port_id = pdev->id; 1096 } 1097 1098 sdd->cur_bpw = 8; 1099 1100 if (!sdd->pdev->dev.of_node) { 1101 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1102 if (!res) { 1103 dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n"); 1104 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; 1105 } else 1106 sdd->tx_dma.dmach = res->start; 1107 1108 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1109 if (!res) { 1110 dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n"); 1111 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; 1112 } else 1113 sdd->rx_dma.dmach = res->start; 1114 } 1115 1116 sdd->tx_dma.direction = DMA_MEM_TO_DEV; 1117 sdd->rx_dma.direction = DMA_DEV_TO_MEM; 1118 1119 master->dev.of_node = pdev->dev.of_node; 1120 master->bus_num = sdd->port_id; 1121 master->setup = s3c64xx_spi_setup; 1122 master->cleanup = s3c64xx_spi_cleanup; 1123 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1124 master->prepare_message = s3c64xx_spi_prepare_message; 1125 master->transfer_one = s3c64xx_spi_transfer_one; 1126 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; 1127 master->num_chipselect = sci->num_cs; 1128 master->dma_alignment = 8; 1129 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1130 SPI_BPW_MASK(8); 1131 /* the spi->mode bits understood by this driver: */ 1132 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1133 master->auto_runtime_pm = true; 1134 if (!is_polling(sdd)) 1135 master->can_dma = s3c64xx_spi_can_dma; 1136 1137 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); 1138 if (IS_ERR(sdd->regs)) { 1139 ret = PTR_ERR(sdd->regs); 1140 goto err0; 1141 } 1142 1143 if (sci->cfg_gpio && sci->cfg_gpio()) { 1144 dev_err(&pdev->dev, "Unable to config gpio\n"); 1145 ret = -EBUSY; 1146 goto err0; 1147 } 1148 1149 /* Setup clocks */ 1150 sdd->clk = devm_clk_get(&pdev->dev, "spi"); 1151 if (IS_ERR(sdd->clk)) { 1152 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); 1153 ret = PTR_ERR(sdd->clk); 1154 goto err0; 1155 } 1156 1157 if (clk_prepare_enable(sdd->clk)) { 1158 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); 1159 ret = -EBUSY; 1160 goto err0; 1161 } 1162 1163 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1164 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); 1165 if (IS_ERR(sdd->src_clk)) { 1166 dev_err(&pdev->dev, 1167 "Unable to acquire clock '%s'\n", clk_name); 1168 ret = PTR_ERR(sdd->src_clk); 1169 goto err2; 1170 } 1171 1172 if (clk_prepare_enable(sdd->src_clk)) { 1173 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); 1174 ret = -EBUSY; 1175 goto err2; 1176 } 1177 1178 /* Setup Deufult Mode */ 1179 s3c64xx_spi_hwinit(sdd, sdd->port_id); 1180 1181 spin_lock_init(&sdd->lock); 1182 init_completion(&sdd->xfer_completion); 1183 1184 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, 1185 "spi-s3c64xx", sdd); 1186 if (ret != 0) { 1187 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", 1188 irq, ret); 1189 goto err3; 1190 } 1191 1192 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1193 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1194 sdd->regs + S3C64XX_SPI_INT_EN); 1195 1196 pm_runtime_set_active(&pdev->dev); 1197 pm_runtime_enable(&pdev->dev); 1198 1199 ret = devm_spi_register_master(&pdev->dev, master); 1200 if (ret != 0) { 1201 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); 1202 goto err3; 1203 } 1204 1205 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", 1206 sdd->port_id, master->num_chipselect); 1207 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n", 1208 mem_res, 1209 sdd->rx_dma.dmach, sdd->tx_dma.dmach); 1210 1211 return 0; 1212 1213 err3: 1214 clk_disable_unprepare(sdd->src_clk); 1215 err2: 1216 clk_disable_unprepare(sdd->clk); 1217 err0: 1218 spi_master_put(master); 1219 1220 return ret; 1221 } 1222 1223 static int s3c64xx_spi_remove(struct platform_device *pdev) 1224 { 1225 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 1226 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1227 1228 pm_runtime_disable(&pdev->dev); 1229 1230 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1231 1232 clk_disable_unprepare(sdd->src_clk); 1233 1234 clk_disable_unprepare(sdd->clk); 1235 1236 return 0; 1237 } 1238 1239 #ifdef CONFIG_PM_SLEEP 1240 static int s3c64xx_spi_suspend(struct device *dev) 1241 { 1242 struct spi_master *master = dev_get_drvdata(dev); 1243 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1244 1245 int ret = spi_master_suspend(master); 1246 if (ret) 1247 return ret; 1248 1249 if (!pm_runtime_suspended(dev)) { 1250 clk_disable_unprepare(sdd->clk); 1251 clk_disable_unprepare(sdd->src_clk); 1252 } 1253 1254 sdd->cur_speed = 0; /* Output Clock is stopped */ 1255 1256 return 0; 1257 } 1258 1259 static int s3c64xx_spi_resume(struct device *dev) 1260 { 1261 struct spi_master *master = dev_get_drvdata(dev); 1262 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1263 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1264 1265 if (sci->cfg_gpio) 1266 sci->cfg_gpio(); 1267 1268 if (!pm_runtime_suspended(dev)) { 1269 clk_prepare_enable(sdd->src_clk); 1270 clk_prepare_enable(sdd->clk); 1271 } 1272 1273 s3c64xx_spi_hwinit(sdd, sdd->port_id); 1274 1275 return spi_master_resume(master); 1276 } 1277 #endif /* CONFIG_PM_SLEEP */ 1278 1279 #ifdef CONFIG_PM_RUNTIME 1280 static int s3c64xx_spi_runtime_suspend(struct device *dev) 1281 { 1282 struct spi_master *master = dev_get_drvdata(dev); 1283 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1284 1285 clk_disable_unprepare(sdd->clk); 1286 clk_disable_unprepare(sdd->src_clk); 1287 1288 return 0; 1289 } 1290 1291 static int s3c64xx_spi_runtime_resume(struct device *dev) 1292 { 1293 struct spi_master *master = dev_get_drvdata(dev); 1294 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1295 int ret; 1296 1297 ret = clk_prepare_enable(sdd->src_clk); 1298 if (ret != 0) 1299 return ret; 1300 1301 ret = clk_prepare_enable(sdd->clk); 1302 if (ret != 0) { 1303 clk_disable_unprepare(sdd->src_clk); 1304 return ret; 1305 } 1306 1307 return 0; 1308 } 1309 #endif /* CONFIG_PM_RUNTIME */ 1310 1311 static const struct dev_pm_ops s3c64xx_spi_pm = { 1312 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) 1313 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, 1314 s3c64xx_spi_runtime_resume, NULL) 1315 }; 1316 1317 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1318 .fifo_lvl_mask = { 0x7f }, 1319 .rx_lvl_offset = 13, 1320 .tx_st_done = 21, 1321 .high_speed = true, 1322 }; 1323 1324 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1325 .fifo_lvl_mask = { 0x7f, 0x7F }, 1326 .rx_lvl_offset = 13, 1327 .tx_st_done = 21, 1328 }; 1329 1330 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { 1331 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1332 .rx_lvl_offset = 15, 1333 .tx_st_done = 25, 1334 }; 1335 1336 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = { 1337 .fifo_lvl_mask = { 0x7f, 0x7F }, 1338 .rx_lvl_offset = 13, 1339 .tx_st_done = 21, 1340 .high_speed = true, 1341 }; 1342 1343 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1344 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1345 .rx_lvl_offset = 15, 1346 .tx_st_done = 25, 1347 .high_speed = true, 1348 }; 1349 1350 static struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1351 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1352 .rx_lvl_offset = 15, 1353 .tx_st_done = 25, 1354 .high_speed = true, 1355 .clk_from_cmu = true, 1356 }; 1357 1358 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = { 1359 .fifo_lvl_mask = { 0x1ff }, 1360 .rx_lvl_offset = 15, 1361 .tx_st_done = 25, 1362 .high_speed = true, 1363 .clk_from_cmu = true, 1364 .quirks = S3C64XX_SPI_QUIRK_POLL, 1365 }; 1366 1367 static struct platform_device_id s3c64xx_spi_driver_ids[] = { 1368 { 1369 .name = "s3c2443-spi", 1370 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, 1371 }, { 1372 .name = "s3c6410-spi", 1373 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1374 }, { 1375 .name = "s5p64x0-spi", 1376 .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config, 1377 }, { 1378 .name = "s5pc100-spi", 1379 .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config, 1380 }, { 1381 .name = "s5pv210-spi", 1382 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, 1383 }, { 1384 .name = "exynos4210-spi", 1385 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, 1386 }, 1387 { }, 1388 }; 1389 1390 static const struct of_device_id s3c64xx_spi_dt_match[] = { 1391 { .compatible = "samsung,s3c2443-spi", 1392 .data = (void *)&s3c2443_spi_port_config, 1393 }, 1394 { .compatible = "samsung,s3c6410-spi", 1395 .data = (void *)&s3c6410_spi_port_config, 1396 }, 1397 { .compatible = "samsung,s5pc100-spi", 1398 .data = (void *)&s5pc100_spi_port_config, 1399 }, 1400 { .compatible = "samsung,s5pv210-spi", 1401 .data = (void *)&s5pv210_spi_port_config, 1402 }, 1403 { .compatible = "samsung,exynos4210-spi", 1404 .data = (void *)&exynos4_spi_port_config, 1405 }, 1406 { .compatible = "samsung,exynos5440-spi", 1407 .data = (void *)&exynos5440_spi_port_config, 1408 }, 1409 { }, 1410 }; 1411 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1412 1413 static struct platform_driver s3c64xx_spi_driver = { 1414 .driver = { 1415 .name = "s3c64xx-spi", 1416 .owner = THIS_MODULE, 1417 .pm = &s3c64xx_spi_pm, 1418 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), 1419 }, 1420 .probe = s3c64xx_spi_probe, 1421 .remove = s3c64xx_spi_remove, 1422 .id_table = s3c64xx_spi_driver_ids, 1423 }; 1424 MODULE_ALIAS("platform:s3c64xx-spi"); 1425 1426 module_platform_driver(s3c64xx_spi_driver); 1427 1428 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1429 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1430 MODULE_LICENSE("GPL"); 1431