1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2009 Samsung Electronics Co., Ltd. 4 // Jaswinder Singh <jassi.brar@samsung.com> 5 6 #include <linux/init.h> 7 #include <linux/module.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/spi/spi.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 19 #include <linux/platform_data/spi-s3c64xx.h> 20 21 #define MAX_SPI_PORTS 12 22 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) 23 #define AUTOSUSPEND_TIMEOUT 2000 24 25 /* Registers and bit-fields */ 26 27 #define S3C64XX_SPI_CH_CFG 0x00 28 #define S3C64XX_SPI_CLK_CFG 0x04 29 #define S3C64XX_SPI_MODE_CFG 0x08 30 #define S3C64XX_SPI_CS_REG 0x0C 31 #define S3C64XX_SPI_INT_EN 0x10 32 #define S3C64XX_SPI_STATUS 0x14 33 #define S3C64XX_SPI_TX_DATA 0x18 34 #define S3C64XX_SPI_RX_DATA 0x1C 35 #define S3C64XX_SPI_PACKET_CNT 0x20 36 #define S3C64XX_SPI_PENDING_CLR 0x24 37 #define S3C64XX_SPI_SWAP_CFG 0x28 38 #define S3C64XX_SPI_FB_CLK 0x2C 39 40 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 41 #define S3C64XX_SPI_CH_SW_RST (1<<5) 42 #define S3C64XX_SPI_CH_SLAVE (1<<4) 43 #define S3C64XX_SPI_CPOL_L (1<<3) 44 #define S3C64XX_SPI_CPHA_B (1<<2) 45 #define S3C64XX_SPI_CH_RXCH_ON (1<<1) 46 #define S3C64XX_SPI_CH_TXCH_ON (1<<0) 47 48 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 49 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 50 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 51 #define S3C64XX_SPI_PSR_MASK 0xff 52 53 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 54 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 55 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 56 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 57 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 58 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 59 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 60 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 61 #define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11) 62 #define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11 63 #define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) 64 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 65 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 66 #define S3C64XX_SPI_MODE_4BURST (1<<0) 67 68 #define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) 69 #define S3C64XX_SPI_CS_AUTO (1<<1) 70 #define S3C64XX_SPI_CS_SIG_INACT (1<<0) 71 72 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 73 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 74 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 75 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 76 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 77 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 78 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 79 80 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 81 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 82 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 83 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 84 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 85 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 86 87 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 88 #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) 89 90 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 91 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 92 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 93 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 94 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 95 96 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 97 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 98 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 99 #define S3C64XX_SPI_SWAP_RX_EN (1<<4) 100 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 101 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 102 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 103 #define S3C64XX_SPI_SWAP_TX_EN (1<<0) 104 105 #define S3C64XX_SPI_FBCLK_MSK (3<<0) 106 107 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) 108 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ 109 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) 110 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) 111 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ 112 FIFO_LVL_MASK(i)) 113 114 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 115 #define S3C64XX_SPI_TRAILCNT_OFF 19 116 117 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT 118 119 #define S3C64XX_SPI_POLLING_SIZE 32 120 121 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 122 #define is_polling(x) (x->cntrlr_info->polling) 123 124 #define RXBUSY (1<<2) 125 #define TXBUSY (1<<3) 126 127 struct s3c64xx_spi_dma_data { 128 struct dma_chan *ch; 129 dma_cookie_t cookie; 130 enum dma_transfer_direction direction; 131 }; 132 133 /** 134 * struct s3c64xx_spi_port_config - SPI Controller hardware info 135 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. 136 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. 137 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. 138 * @clk_div: Internal clock divider 139 * @quirks: Bitmask of known quirks 140 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. 141 * @clk_from_cmu: True, if the controller does not include a clock mux and 142 * prescaler unit. 143 * @clk_ioclk: True if clock is present on this device 144 * @has_loopback: True if loopback mode can be supported 145 * 146 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but 147 * differ in some aspects such as the size of the fifo and spi bus clock 148 * setup. Such differences are specified to the driver using this structure 149 * which is provided as driver data to the driver. 150 */ 151 struct s3c64xx_spi_port_config { 152 int fifo_lvl_mask[MAX_SPI_PORTS]; 153 int rx_lvl_offset; 154 int tx_st_done; 155 int quirks; 156 int clk_div; 157 bool high_speed; 158 bool clk_from_cmu; 159 bool clk_ioclk; 160 bool has_loopback; 161 }; 162 163 /** 164 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 165 * @clk: Pointer to the spi clock. 166 * @src_clk: Pointer to the clock used to generate SPI signals. 167 * @ioclk: Pointer to the i/o clock between master and slave 168 * @pdev: Pointer to device's platform device data 169 * @master: Pointer to the SPI Protocol master. 170 * @cntrlr_info: Platform specific data for the controller this driver manages. 171 * @lock: Controller specific lock. 172 * @state: Set of FLAGS to indicate status. 173 * @sfr_start: BUS address of SPI controller regs. 174 * @regs: Pointer to ioremap'ed controller registers. 175 * @xfer_completion: To indicate completion of xfer task. 176 * @cur_mode: Stores the active configuration of the controller. 177 * @cur_bpw: Stores the active bits per word settings. 178 * @cur_speed: Current clock speed 179 * @rx_dma: Local receive DMA data (e.g. chan and direction) 180 * @tx_dma: Local transmit DMA data (e.g. chan and direction) 181 * @port_conf: Local SPI port configuartion data 182 * @port_id: Port identification number 183 */ 184 struct s3c64xx_spi_driver_data { 185 void __iomem *regs; 186 struct clk *clk; 187 struct clk *src_clk; 188 struct clk *ioclk; 189 struct platform_device *pdev; 190 struct spi_master *master; 191 struct s3c64xx_spi_info *cntrlr_info; 192 spinlock_t lock; 193 unsigned long sfr_start; 194 struct completion xfer_completion; 195 unsigned state; 196 unsigned cur_mode, cur_bpw; 197 unsigned cur_speed; 198 struct s3c64xx_spi_dma_data rx_dma; 199 struct s3c64xx_spi_dma_data tx_dma; 200 const struct s3c64xx_spi_port_config *port_conf; 201 unsigned int port_id; 202 }; 203 204 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) 205 { 206 void __iomem *regs = sdd->regs; 207 unsigned long loops; 208 u32 val; 209 210 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 211 212 val = readl(regs + S3C64XX_SPI_CH_CFG); 213 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 214 writel(val, regs + S3C64XX_SPI_CH_CFG); 215 216 val = readl(regs + S3C64XX_SPI_CH_CFG); 217 val |= S3C64XX_SPI_CH_SW_RST; 218 val &= ~S3C64XX_SPI_CH_HS_EN; 219 writel(val, regs + S3C64XX_SPI_CH_CFG); 220 221 /* Flush TxFIFO*/ 222 loops = msecs_to_loops(1); 223 do { 224 val = readl(regs + S3C64XX_SPI_STATUS); 225 } while (TX_FIFO_LVL(val, sdd) && loops--); 226 227 if (loops == 0) 228 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 229 230 /* Flush RxFIFO*/ 231 loops = msecs_to_loops(1); 232 do { 233 val = readl(regs + S3C64XX_SPI_STATUS); 234 if (RX_FIFO_LVL(val, sdd)) 235 readl(regs + S3C64XX_SPI_RX_DATA); 236 else 237 break; 238 } while (loops--); 239 240 if (loops == 0) 241 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 242 243 val = readl(regs + S3C64XX_SPI_CH_CFG); 244 val &= ~S3C64XX_SPI_CH_SW_RST; 245 writel(val, regs + S3C64XX_SPI_CH_CFG); 246 247 val = readl(regs + S3C64XX_SPI_MODE_CFG); 248 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 249 writel(val, regs + S3C64XX_SPI_MODE_CFG); 250 } 251 252 static void s3c64xx_spi_dmacb(void *data) 253 { 254 struct s3c64xx_spi_driver_data *sdd; 255 struct s3c64xx_spi_dma_data *dma = data; 256 unsigned long flags; 257 258 if (dma->direction == DMA_DEV_TO_MEM) 259 sdd = container_of(data, 260 struct s3c64xx_spi_driver_data, rx_dma); 261 else 262 sdd = container_of(data, 263 struct s3c64xx_spi_driver_data, tx_dma); 264 265 spin_lock_irqsave(&sdd->lock, flags); 266 267 if (dma->direction == DMA_DEV_TO_MEM) { 268 sdd->state &= ~RXBUSY; 269 if (!(sdd->state & TXBUSY)) 270 complete(&sdd->xfer_completion); 271 } else { 272 sdd->state &= ~TXBUSY; 273 if (!(sdd->state & RXBUSY)) 274 complete(&sdd->xfer_completion); 275 } 276 277 spin_unlock_irqrestore(&sdd->lock, flags); 278 } 279 280 static int prepare_dma(struct s3c64xx_spi_dma_data *dma, 281 struct sg_table *sgt) 282 { 283 struct s3c64xx_spi_driver_data *sdd; 284 struct dma_slave_config config; 285 struct dma_async_tx_descriptor *desc; 286 int ret; 287 288 memset(&config, 0, sizeof(config)); 289 290 if (dma->direction == DMA_DEV_TO_MEM) { 291 sdd = container_of((void *)dma, 292 struct s3c64xx_spi_driver_data, rx_dma); 293 config.direction = dma->direction; 294 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 295 config.src_addr_width = sdd->cur_bpw / 8; 296 config.src_maxburst = 1; 297 dmaengine_slave_config(dma->ch, &config); 298 } else { 299 sdd = container_of((void *)dma, 300 struct s3c64xx_spi_driver_data, tx_dma); 301 config.direction = dma->direction; 302 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 303 config.dst_addr_width = sdd->cur_bpw / 8; 304 config.dst_maxburst = 1; 305 dmaengine_slave_config(dma->ch, &config); 306 } 307 308 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, 309 dma->direction, DMA_PREP_INTERRUPT); 310 if (!desc) { 311 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", 312 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx"); 313 return -ENOMEM; 314 } 315 316 desc->callback = s3c64xx_spi_dmacb; 317 desc->callback_param = dma; 318 319 dma->cookie = dmaengine_submit(desc); 320 ret = dma_submit_error(dma->cookie); 321 if (ret) { 322 dev_err(&sdd->pdev->dev, "DMA submission failed"); 323 return -EIO; 324 } 325 326 dma_async_issue_pending(dma->ch); 327 return 0; 328 } 329 330 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) 331 { 332 struct s3c64xx_spi_driver_data *sdd = 333 spi_master_get_devdata(spi->master); 334 335 if (sdd->cntrlr_info->no_cs) 336 return; 337 338 if (enable) { 339 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { 340 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 341 } else { 342 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); 343 344 ssel |= (S3C64XX_SPI_CS_AUTO | 345 S3C64XX_SPI_CS_NSC_CNT_2); 346 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); 347 } 348 } else { 349 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 350 writel(S3C64XX_SPI_CS_SIG_INACT, 351 sdd->regs + S3C64XX_SPI_CS_REG); 352 } 353 } 354 355 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) 356 { 357 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 358 359 if (is_polling(sdd)) 360 return 0; 361 362 /* Requests DMA channels */ 363 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx"); 364 if (IS_ERR(sdd->rx_dma.ch)) { 365 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n"); 366 sdd->rx_dma.ch = NULL; 367 return 0; 368 } 369 370 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx"); 371 if (IS_ERR(sdd->tx_dma.ch)) { 372 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n"); 373 dma_release_channel(sdd->rx_dma.ch); 374 sdd->tx_dma.ch = NULL; 375 sdd->rx_dma.ch = NULL; 376 return 0; 377 } 378 379 spi->dma_rx = sdd->rx_dma.ch; 380 spi->dma_tx = sdd->tx_dma.ch; 381 382 return 0; 383 } 384 385 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) 386 { 387 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 388 389 if (is_polling(sdd)) 390 return 0; 391 392 /* Releases DMA channels if they are allocated */ 393 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { 394 dma_release_channel(sdd->rx_dma.ch); 395 dma_release_channel(sdd->tx_dma.ch); 396 sdd->rx_dma.ch = NULL; 397 sdd->tx_dma.ch = NULL; 398 } 399 400 return 0; 401 } 402 403 static bool s3c64xx_spi_can_dma(struct spi_master *master, 404 struct spi_device *spi, 405 struct spi_transfer *xfer) 406 { 407 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 408 409 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { 410 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; 411 } else { 412 return false; 413 } 414 415 } 416 417 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, 418 struct spi_transfer *xfer, int dma_mode) 419 { 420 void __iomem *regs = sdd->regs; 421 u32 modecfg, chcfg; 422 int ret = 0; 423 424 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 425 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 426 427 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 428 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 429 430 if (dma_mode) { 431 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 432 } else { 433 /* Always shift in data in FIFO, even if xfer is Tx only, 434 * this helps setting PCKT_CNT value for generating clocks 435 * as exactly needed. 436 */ 437 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 438 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 439 | S3C64XX_SPI_PACKET_CNT_EN, 440 regs + S3C64XX_SPI_PACKET_CNT); 441 } 442 443 if (xfer->tx_buf != NULL) { 444 sdd->state |= TXBUSY; 445 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 446 if (dma_mode) { 447 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 448 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); 449 } else { 450 switch (sdd->cur_bpw) { 451 case 32: 452 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, 453 xfer->tx_buf, xfer->len / 4); 454 break; 455 case 16: 456 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, 457 xfer->tx_buf, xfer->len / 2); 458 break; 459 default: 460 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, 461 xfer->tx_buf, xfer->len); 462 break; 463 } 464 } 465 } 466 467 if (xfer->rx_buf != NULL) { 468 sdd->state |= RXBUSY; 469 470 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL 471 && !(sdd->cur_mode & SPI_CPHA)) 472 chcfg |= S3C64XX_SPI_CH_HS_EN; 473 474 if (dma_mode) { 475 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 476 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 477 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 478 | S3C64XX_SPI_PACKET_CNT_EN, 479 regs + S3C64XX_SPI_PACKET_CNT); 480 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg); 481 } 482 } 483 484 if (ret) 485 return ret; 486 487 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 488 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 489 490 return 0; 491 } 492 493 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 494 int timeout_ms) 495 { 496 void __iomem *regs = sdd->regs; 497 unsigned long val = 1; 498 u32 status; 499 500 /* max fifo depth available */ 501 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; 502 503 if (timeout_ms) 504 val = msecs_to_loops(timeout_ms); 505 506 do { 507 status = readl(regs + S3C64XX_SPI_STATUS); 508 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); 509 510 /* return the actual received data length */ 511 return RX_FIFO_LVL(status, sdd); 512 } 513 514 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, 515 struct spi_transfer *xfer) 516 { 517 void __iomem *regs = sdd->regs; 518 unsigned long val; 519 u32 status; 520 int ms; 521 522 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 523 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 524 ms += 30; /* some tolerance */ 525 ms = max(ms, 100); /* minimum timeout */ 526 527 val = msecs_to_jiffies(ms) + 10; 528 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 529 530 /* 531 * If the previous xfer was completed within timeout, then 532 * proceed further else return -EIO. 533 * DmaTx returns after simply writing data in the FIFO, 534 * w/o waiting for real transmission on the bus to finish. 535 * DmaRx returns only after Dma read data from FIFO which 536 * needs bus transmission to finish, so we don't worry if 537 * Xfer involved Rx(with or without Tx). 538 */ 539 if (val && !xfer->rx_buf) { 540 val = msecs_to_loops(10); 541 status = readl(regs + S3C64XX_SPI_STATUS); 542 while ((TX_FIFO_LVL(status, sdd) 543 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) 544 && --val) { 545 cpu_relax(); 546 status = readl(regs + S3C64XX_SPI_STATUS); 547 } 548 549 } 550 551 /* If timed out while checking rx/tx status return error */ 552 if (!val) 553 return -EIO; 554 555 return 0; 556 } 557 558 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, 559 struct spi_transfer *xfer, bool use_irq) 560 { 561 void __iomem *regs = sdd->regs; 562 unsigned long val; 563 u32 status; 564 int loops; 565 u32 cpy_len; 566 u8 *buf; 567 int ms; 568 unsigned long time_us; 569 570 /* microsecs to xfer 'len' bytes @ 'cur_speed' */ 571 time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; 572 ms = (time_us / 1000); 573 ms += 10; /* some tolerance */ 574 575 /* sleep during signal transfer time */ 576 status = readl(regs + S3C64XX_SPI_STATUS); 577 if (RX_FIFO_LVL(status, sdd) < xfer->len) 578 usleep_range(time_us / 2, time_us); 579 580 if (use_irq) { 581 val = msecs_to_jiffies(ms); 582 if (!wait_for_completion_timeout(&sdd->xfer_completion, val)) 583 return -EIO; 584 } 585 586 val = msecs_to_loops(ms); 587 do { 588 status = readl(regs + S3C64XX_SPI_STATUS); 589 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 590 591 if (!val) 592 return -EIO; 593 594 /* If it was only Tx */ 595 if (!xfer->rx_buf) { 596 sdd->state &= ~TXBUSY; 597 return 0; 598 } 599 600 /* 601 * If the receive length is bigger than the controller fifo 602 * size, calculate the loops and read the fifo as many times. 603 * loops = length / max fifo size (calculated by using the 604 * fifo mask). 605 * For any size less than the fifo size the below code is 606 * executed atleast once. 607 */ 608 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); 609 buf = xfer->rx_buf; 610 do { 611 /* wait for data to be received in the fifo */ 612 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, 613 (loops ? ms : 0)); 614 615 switch (sdd->cur_bpw) { 616 case 32: 617 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 618 buf, cpy_len / 4); 619 break; 620 case 16: 621 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 622 buf, cpy_len / 2); 623 break; 624 default: 625 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 626 buf, cpy_len); 627 break; 628 } 629 630 buf = buf + cpy_len; 631 } while (loops--); 632 sdd->state &= ~RXBUSY; 633 634 return 0; 635 } 636 637 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 638 { 639 void __iomem *regs = sdd->regs; 640 int ret; 641 u32 val; 642 int div = sdd->port_conf->clk_div; 643 644 /* Disable Clock */ 645 if (!sdd->port_conf->clk_from_cmu) { 646 val = readl(regs + S3C64XX_SPI_CLK_CFG); 647 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 648 writel(val, regs + S3C64XX_SPI_CLK_CFG); 649 } 650 651 /* Set Polarity and Phase */ 652 val = readl(regs + S3C64XX_SPI_CH_CFG); 653 val &= ~(S3C64XX_SPI_CH_SLAVE | 654 S3C64XX_SPI_CPOL_L | 655 S3C64XX_SPI_CPHA_B); 656 657 if (sdd->cur_mode & SPI_CPOL) 658 val |= S3C64XX_SPI_CPOL_L; 659 660 if (sdd->cur_mode & SPI_CPHA) 661 val |= S3C64XX_SPI_CPHA_B; 662 663 writel(val, regs + S3C64XX_SPI_CH_CFG); 664 665 /* Set Channel & DMA Mode */ 666 val = readl(regs + S3C64XX_SPI_MODE_CFG); 667 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 668 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 669 670 switch (sdd->cur_bpw) { 671 case 32: 672 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 673 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 674 break; 675 case 16: 676 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 677 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 678 break; 679 default: 680 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 681 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 682 break; 683 } 684 685 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) 686 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK; 687 688 writel(val, regs + S3C64XX_SPI_MODE_CFG); 689 690 if (sdd->port_conf->clk_from_cmu) { 691 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); 692 if (ret) 693 return ret; 694 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; 695 } else { 696 /* Configure Clock */ 697 val = readl(regs + S3C64XX_SPI_CLK_CFG); 698 val &= ~S3C64XX_SPI_PSR_MASK; 699 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) 700 & S3C64XX_SPI_PSR_MASK); 701 writel(val, regs + S3C64XX_SPI_CLK_CFG); 702 703 /* Enable Clock */ 704 val = readl(regs + S3C64XX_SPI_CLK_CFG); 705 val |= S3C64XX_SPI_ENCLK_ENABLE; 706 writel(val, regs + S3C64XX_SPI_CLK_CFG); 707 } 708 709 return 0; 710 } 711 712 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 713 714 static int s3c64xx_spi_prepare_message(struct spi_master *master, 715 struct spi_message *msg) 716 { 717 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 718 struct spi_device *spi = msg->spi; 719 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 720 721 /* Configure feedback delay */ 722 if (!cs) 723 /* No delay if not defined */ 724 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK); 725 else 726 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 727 728 return 0; 729 } 730 731 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi) 732 { 733 struct spi_controller *ctlr = spi->controller; 734 735 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX; 736 } 737 738 static int s3c64xx_spi_transfer_one(struct spi_master *master, 739 struct spi_device *spi, 740 struct spi_transfer *xfer) 741 { 742 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 743 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1; 744 const void *tx_buf = NULL; 745 void *rx_buf = NULL; 746 int target_len = 0, origin_len = 0; 747 int use_dma = 0; 748 bool use_irq = false; 749 int status; 750 u32 speed; 751 u8 bpw; 752 unsigned long flags; 753 u32 rdy_lv; 754 u32 val; 755 756 reinit_completion(&sdd->xfer_completion); 757 758 /* Only BPW and Speed may change across transfers */ 759 bpw = xfer->bits_per_word; 760 speed = xfer->speed_hz; 761 762 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 763 sdd->cur_bpw = bpw; 764 sdd->cur_speed = speed; 765 sdd->cur_mode = spi->mode; 766 status = s3c64xx_spi_config(sdd); 767 if (status) 768 return status; 769 } 770 771 if (!is_polling(sdd) && (xfer->len > fifo_len) && 772 sdd->rx_dma.ch && sdd->tx_dma.ch) { 773 use_dma = 1; 774 775 } else if (xfer->len >= fifo_len) { 776 tx_buf = xfer->tx_buf; 777 rx_buf = xfer->rx_buf; 778 origin_len = xfer->len; 779 target_len = xfer->len; 780 xfer->len = fifo_len - 1; 781 } 782 783 do { 784 /* transfer size is greater than 32, change to IRQ mode */ 785 if (!use_dma && xfer->len > S3C64XX_SPI_POLLING_SIZE) 786 use_irq = true; 787 788 if (use_irq) { 789 reinit_completion(&sdd->xfer_completion); 790 791 rdy_lv = xfer->len; 792 /* Setup RDY_FIFO trigger Level 793 * RDY_LVL = 794 * fifo_lvl up to 64 byte -> N bytes 795 * 128 byte -> RDY_LVL * 2 bytes 796 * 256 byte -> RDY_LVL * 4 bytes 797 */ 798 if (fifo_len == 128) 799 rdy_lv /= 2; 800 else if (fifo_len == 256) 801 rdy_lv /= 4; 802 803 val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG); 804 val &= ~S3C64XX_SPI_MODE_RX_RDY_LVL; 805 val |= (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT); 806 writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG); 807 808 /* Enable FIFO_RDY_EN IRQ */ 809 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); 810 writel((val | S3C64XX_SPI_INT_RX_FIFORDY_EN), 811 sdd->regs + S3C64XX_SPI_INT_EN); 812 813 } 814 815 spin_lock_irqsave(&sdd->lock, flags); 816 817 /* Pending only which is to be done */ 818 sdd->state &= ~RXBUSY; 819 sdd->state &= ~TXBUSY; 820 821 /* Start the signals */ 822 s3c64xx_spi_set_cs(spi, true); 823 824 status = s3c64xx_enable_datapath(sdd, xfer, use_dma); 825 826 spin_unlock_irqrestore(&sdd->lock, flags); 827 828 if (status) { 829 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status); 830 break; 831 } 832 833 if (use_dma) 834 status = s3c64xx_wait_for_dma(sdd, xfer); 835 else 836 status = s3c64xx_wait_for_pio(sdd, xfer, use_irq); 837 838 if (status) { 839 dev_err(&spi->dev, 840 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n", 841 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 842 (sdd->state & RXBUSY) ? 'f' : 'p', 843 (sdd->state & TXBUSY) ? 'f' : 'p', 844 xfer->len, use_dma ? 1 : 0, status); 845 846 if (use_dma) { 847 struct dma_tx_state s; 848 849 if (xfer->tx_buf && (sdd->state & TXBUSY)) { 850 dmaengine_pause(sdd->tx_dma.ch); 851 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); 852 dmaengine_terminate_all(sdd->tx_dma.ch); 853 dev_err(&spi->dev, "TX residue: %d\n", s.residue); 854 855 } 856 if (xfer->rx_buf && (sdd->state & RXBUSY)) { 857 dmaengine_pause(sdd->rx_dma.ch); 858 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); 859 dmaengine_terminate_all(sdd->rx_dma.ch); 860 dev_err(&spi->dev, "RX residue: %d\n", s.residue); 861 } 862 } 863 } else { 864 s3c64xx_flush_fifo(sdd); 865 } 866 if (target_len > 0) { 867 target_len -= xfer->len; 868 869 if (xfer->tx_buf) 870 xfer->tx_buf += xfer->len; 871 872 if (xfer->rx_buf) 873 xfer->rx_buf += xfer->len; 874 875 if (target_len >= fifo_len) 876 xfer->len = fifo_len - 1; 877 else 878 xfer->len = target_len; 879 } 880 } while (target_len > 0); 881 882 if (origin_len) { 883 /* Restore original xfer buffers and length */ 884 xfer->tx_buf = tx_buf; 885 xfer->rx_buf = rx_buf; 886 xfer->len = origin_len; 887 } 888 889 return status; 890 } 891 892 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( 893 struct spi_device *spi) 894 { 895 struct s3c64xx_spi_csinfo *cs; 896 struct device_node *slave_np, *data_np = NULL; 897 u32 fb_delay = 0; 898 899 slave_np = spi->dev.of_node; 900 if (!slave_np) { 901 dev_err(&spi->dev, "device node not found\n"); 902 return ERR_PTR(-EINVAL); 903 } 904 905 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 906 if (!cs) 907 return ERR_PTR(-ENOMEM); 908 909 data_np = of_get_child_by_name(slave_np, "controller-data"); 910 if (!data_np) { 911 dev_info(&spi->dev, "feedback delay set to default (0)\n"); 912 return cs; 913 } 914 915 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 916 cs->fb_delay = fb_delay; 917 of_node_put(data_np); 918 return cs; 919 } 920 921 /* 922 * Here we only check the validity of requested configuration 923 * and save the configuration in a local data-structure. 924 * The controller is actually configured only just before we 925 * get a message to transfer. 926 */ 927 static int s3c64xx_spi_setup(struct spi_device *spi) 928 { 929 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 930 struct s3c64xx_spi_driver_data *sdd; 931 int err; 932 int div; 933 934 sdd = spi_master_get_devdata(spi->master); 935 if (spi->dev.of_node) { 936 cs = s3c64xx_get_slave_ctrldata(spi); 937 spi->controller_data = cs; 938 } 939 940 /* NULL is fine, we just avoid using the FB delay (=0) */ 941 if (IS_ERR(cs)) { 942 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0)); 943 return -ENODEV; 944 } 945 946 if (!spi_get_ctldata(spi)) 947 spi_set_ctldata(spi, cs); 948 949 pm_runtime_get_sync(&sdd->pdev->dev); 950 951 div = sdd->port_conf->clk_div; 952 953 /* Check if we can provide the requested rate */ 954 if (!sdd->port_conf->clk_from_cmu) { 955 u32 psr, speed; 956 957 /* Max possible */ 958 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); 959 960 if (spi->max_speed_hz > speed) 961 spi->max_speed_hz = speed; 962 963 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; 964 psr &= S3C64XX_SPI_PSR_MASK; 965 if (psr == S3C64XX_SPI_PSR_MASK) 966 psr--; 967 968 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 969 if (spi->max_speed_hz < speed) { 970 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 971 psr++; 972 } else { 973 err = -EINVAL; 974 goto setup_exit; 975 } 976 } 977 978 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 979 if (spi->max_speed_hz >= speed) { 980 spi->max_speed_hz = speed; 981 } else { 982 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", 983 spi->max_speed_hz); 984 err = -EINVAL; 985 goto setup_exit; 986 } 987 } 988 989 pm_runtime_mark_last_busy(&sdd->pdev->dev); 990 pm_runtime_put_autosuspend(&sdd->pdev->dev); 991 s3c64xx_spi_set_cs(spi, false); 992 993 return 0; 994 995 setup_exit: 996 pm_runtime_mark_last_busy(&sdd->pdev->dev); 997 pm_runtime_put_autosuspend(&sdd->pdev->dev); 998 /* setup() returns with device de-selected */ 999 s3c64xx_spi_set_cs(spi, false); 1000 1001 spi_set_ctldata(spi, NULL); 1002 1003 /* This was dynamically allocated on the DT path */ 1004 if (spi->dev.of_node) 1005 kfree(cs); 1006 1007 return err; 1008 } 1009 1010 static void s3c64xx_spi_cleanup(struct spi_device *spi) 1011 { 1012 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 1013 1014 /* This was dynamically allocated on the DT path */ 1015 if (spi->dev.of_node) 1016 kfree(cs); 1017 1018 spi_set_ctldata(spi, NULL); 1019 } 1020 1021 static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 1022 { 1023 struct s3c64xx_spi_driver_data *sdd = data; 1024 struct spi_master *spi = sdd->master; 1025 unsigned int val, clr = 0; 1026 1027 val = readl(sdd->regs + S3C64XX_SPI_STATUS); 1028 1029 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { 1030 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; 1031 dev_err(&spi->dev, "RX overrun\n"); 1032 } 1033 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { 1034 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; 1035 dev_err(&spi->dev, "RX underrun\n"); 1036 } 1037 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { 1038 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; 1039 dev_err(&spi->dev, "TX overrun\n"); 1040 } 1041 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { 1042 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 1043 dev_err(&spi->dev, "TX underrun\n"); 1044 } 1045 1046 if (val & S3C64XX_SPI_ST_RX_FIFORDY) { 1047 complete(&sdd->xfer_completion); 1048 /* No pending clear irq, turn-off INT_EN_RX_FIFO_RDY */ 1049 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); 1050 writel((val & ~S3C64XX_SPI_INT_RX_FIFORDY_EN), 1051 sdd->regs + S3C64XX_SPI_INT_EN); 1052 } 1053 1054 /* Clear the pending irq by setting and then clearing it */ 1055 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); 1056 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); 1057 1058 return IRQ_HANDLED; 1059 } 1060 1061 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) 1062 { 1063 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1064 void __iomem *regs = sdd->regs; 1065 unsigned int val; 1066 1067 sdd->cur_speed = 0; 1068 1069 if (sci->no_cs) 1070 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 1071 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 1072 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); 1073 1074 /* Disable Interrupts - we use Polling if not DMA mode */ 1075 writel(0, regs + S3C64XX_SPI_INT_EN); 1076 1077 if (!sdd->port_conf->clk_from_cmu) 1078 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 1079 regs + S3C64XX_SPI_CLK_CFG); 1080 writel(0, regs + S3C64XX_SPI_MODE_CFG); 1081 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 1082 1083 /* Clear any irq pending bits, should set and clear the bits */ 1084 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | 1085 S3C64XX_SPI_PND_RX_UNDERRUN_CLR | 1086 S3C64XX_SPI_PND_TX_OVERRUN_CLR | 1087 S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 1088 writel(val, regs + S3C64XX_SPI_PENDING_CLR); 1089 writel(0, regs + S3C64XX_SPI_PENDING_CLR); 1090 1091 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 1092 1093 val = readl(regs + S3C64XX_SPI_MODE_CFG); 1094 val &= ~S3C64XX_SPI_MODE_4BURST; 1095 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1096 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1097 writel(val, regs + S3C64XX_SPI_MODE_CFG); 1098 1099 s3c64xx_flush_fifo(sdd); 1100 } 1101 1102 #ifdef CONFIG_OF 1103 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1104 { 1105 struct s3c64xx_spi_info *sci; 1106 u32 temp; 1107 1108 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); 1109 if (!sci) 1110 return ERR_PTR(-ENOMEM); 1111 1112 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { 1113 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); 1114 sci->src_clk_nr = 0; 1115 } else { 1116 sci->src_clk_nr = temp; 1117 } 1118 1119 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { 1120 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); 1121 sci->num_cs = 1; 1122 } else { 1123 sci->num_cs = temp; 1124 } 1125 1126 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); 1127 sci->polling = !of_property_present(dev->of_node, "dmas"); 1128 1129 return sci; 1130 } 1131 #else 1132 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1133 { 1134 return dev_get_platdata(dev); 1135 } 1136 #endif 1137 1138 static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( 1139 struct platform_device *pdev) 1140 { 1141 #ifdef CONFIG_OF 1142 if (pdev->dev.of_node) 1143 return of_device_get_match_data(&pdev->dev); 1144 #endif 1145 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; 1146 } 1147 1148 static int s3c64xx_spi_probe(struct platform_device *pdev) 1149 { 1150 struct resource *mem_res; 1151 struct s3c64xx_spi_driver_data *sdd; 1152 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); 1153 struct spi_master *master; 1154 int ret, irq; 1155 char clk_name[16]; 1156 1157 if (!sci && pdev->dev.of_node) { 1158 sci = s3c64xx_spi_parse_dt(&pdev->dev); 1159 if (IS_ERR(sci)) 1160 return PTR_ERR(sci); 1161 } 1162 1163 if (!sci) 1164 return dev_err_probe(&pdev->dev, -ENODEV, 1165 "Platform_data missing!\n"); 1166 1167 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1168 if (!mem_res) 1169 return dev_err_probe(&pdev->dev, -ENXIO, 1170 "Unable to get SPI MEM resource\n"); 1171 1172 irq = platform_get_irq(pdev, 0); 1173 if (irq < 0) 1174 return dev_err_probe(&pdev->dev, irq, "Failed to get IRQ\n"); 1175 1176 master = devm_spi_alloc_master(&pdev->dev, sizeof(*sdd)); 1177 if (!master) 1178 return dev_err_probe(&pdev->dev, -ENOMEM, 1179 "Unable to allocate SPI Master\n"); 1180 1181 platform_set_drvdata(pdev, master); 1182 1183 sdd = spi_master_get_devdata(master); 1184 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); 1185 sdd->master = master; 1186 sdd->cntrlr_info = sci; 1187 sdd->pdev = pdev; 1188 sdd->sfr_start = mem_res->start; 1189 if (pdev->dev.of_node) { 1190 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1191 if (ret < 0) 1192 return dev_err_probe(&pdev->dev, ret, 1193 "Failed to get alias id\n"); 1194 sdd->port_id = ret; 1195 } else { 1196 sdd->port_id = pdev->id; 1197 } 1198 1199 sdd->cur_bpw = 8; 1200 1201 sdd->tx_dma.direction = DMA_MEM_TO_DEV; 1202 sdd->rx_dma.direction = DMA_DEV_TO_MEM; 1203 1204 master->dev.of_node = pdev->dev.of_node; 1205 master->bus_num = sdd->port_id; 1206 master->setup = s3c64xx_spi_setup; 1207 master->cleanup = s3c64xx_spi_cleanup; 1208 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1209 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; 1210 master->prepare_message = s3c64xx_spi_prepare_message; 1211 master->transfer_one = s3c64xx_spi_transfer_one; 1212 master->max_transfer_size = s3c64xx_spi_max_transfer_size; 1213 master->num_chipselect = sci->num_cs; 1214 master->use_gpio_descriptors = true; 1215 master->dma_alignment = 8; 1216 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1217 SPI_BPW_MASK(8); 1218 /* the spi->mode bits understood by this driver: */ 1219 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1220 if (sdd->port_conf->has_loopback) 1221 master->mode_bits |= SPI_LOOP; 1222 master->auto_runtime_pm = true; 1223 if (!is_polling(sdd)) 1224 master->can_dma = s3c64xx_spi_can_dma; 1225 1226 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); 1227 if (IS_ERR(sdd->regs)) 1228 return PTR_ERR(sdd->regs); 1229 1230 if (sci->cfg_gpio && sci->cfg_gpio()) 1231 return dev_err_probe(&pdev->dev, -EBUSY, 1232 "Unable to config gpio\n"); 1233 1234 /* Setup clocks */ 1235 sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi"); 1236 if (IS_ERR(sdd->clk)) 1237 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->clk), 1238 "Unable to acquire clock 'spi'\n"); 1239 1240 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1241 sdd->src_clk = devm_clk_get_enabled(&pdev->dev, clk_name); 1242 if (IS_ERR(sdd->src_clk)) 1243 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk), 1244 "Unable to acquire clock '%s'\n", 1245 clk_name); 1246 1247 if (sdd->port_conf->clk_ioclk) { 1248 sdd->ioclk = devm_clk_get_enabled(&pdev->dev, "spi_ioclk"); 1249 if (IS_ERR(sdd->ioclk)) 1250 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->ioclk), 1251 "Unable to acquire 'ioclk'\n"); 1252 } 1253 1254 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1255 pm_runtime_use_autosuspend(&pdev->dev); 1256 pm_runtime_set_active(&pdev->dev); 1257 pm_runtime_enable(&pdev->dev); 1258 pm_runtime_get_sync(&pdev->dev); 1259 1260 /* Setup Deufult Mode */ 1261 s3c64xx_spi_hwinit(sdd); 1262 1263 spin_lock_init(&sdd->lock); 1264 init_completion(&sdd->xfer_completion); 1265 1266 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, 1267 "spi-s3c64xx", sdd); 1268 if (ret != 0) { 1269 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", 1270 irq, ret); 1271 goto err_pm_put; 1272 } 1273 1274 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1275 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1276 sdd->regs + S3C64XX_SPI_INT_EN); 1277 1278 ret = devm_spi_register_master(&pdev->dev, master); 1279 if (ret != 0) { 1280 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); 1281 goto err_pm_put; 1282 } 1283 1284 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", 1285 sdd->port_id, master->num_chipselect); 1286 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", 1287 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1); 1288 1289 pm_runtime_mark_last_busy(&pdev->dev); 1290 pm_runtime_put_autosuspend(&pdev->dev); 1291 1292 return 0; 1293 1294 err_pm_put: 1295 pm_runtime_put_noidle(&pdev->dev); 1296 pm_runtime_disable(&pdev->dev); 1297 pm_runtime_set_suspended(&pdev->dev); 1298 1299 return ret; 1300 } 1301 1302 static void s3c64xx_spi_remove(struct platform_device *pdev) 1303 { 1304 struct spi_master *master = platform_get_drvdata(pdev); 1305 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1306 1307 pm_runtime_get_sync(&pdev->dev); 1308 1309 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1310 1311 if (!is_polling(sdd)) { 1312 dma_release_channel(sdd->rx_dma.ch); 1313 dma_release_channel(sdd->tx_dma.ch); 1314 } 1315 1316 pm_runtime_put_noidle(&pdev->dev); 1317 pm_runtime_disable(&pdev->dev); 1318 pm_runtime_set_suspended(&pdev->dev); 1319 } 1320 1321 #ifdef CONFIG_PM_SLEEP 1322 static int s3c64xx_spi_suspend(struct device *dev) 1323 { 1324 struct spi_master *master = dev_get_drvdata(dev); 1325 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1326 1327 int ret = spi_master_suspend(master); 1328 if (ret) 1329 return ret; 1330 1331 ret = pm_runtime_force_suspend(dev); 1332 if (ret < 0) 1333 return ret; 1334 1335 sdd->cur_speed = 0; /* Output Clock is stopped */ 1336 1337 return 0; 1338 } 1339 1340 static int s3c64xx_spi_resume(struct device *dev) 1341 { 1342 struct spi_master *master = dev_get_drvdata(dev); 1343 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1344 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1345 int ret; 1346 1347 if (sci->cfg_gpio) 1348 sci->cfg_gpio(); 1349 1350 ret = pm_runtime_force_resume(dev); 1351 if (ret < 0) 1352 return ret; 1353 1354 return spi_master_resume(master); 1355 } 1356 #endif /* CONFIG_PM_SLEEP */ 1357 1358 #ifdef CONFIG_PM 1359 static int s3c64xx_spi_runtime_suspend(struct device *dev) 1360 { 1361 struct spi_master *master = dev_get_drvdata(dev); 1362 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1363 1364 clk_disable_unprepare(sdd->clk); 1365 clk_disable_unprepare(sdd->src_clk); 1366 clk_disable_unprepare(sdd->ioclk); 1367 1368 return 0; 1369 } 1370 1371 static int s3c64xx_spi_runtime_resume(struct device *dev) 1372 { 1373 struct spi_master *master = dev_get_drvdata(dev); 1374 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1375 int ret; 1376 1377 if (sdd->port_conf->clk_ioclk) { 1378 ret = clk_prepare_enable(sdd->ioclk); 1379 if (ret != 0) 1380 return ret; 1381 } 1382 1383 ret = clk_prepare_enable(sdd->src_clk); 1384 if (ret != 0) 1385 goto err_disable_ioclk; 1386 1387 ret = clk_prepare_enable(sdd->clk); 1388 if (ret != 0) 1389 goto err_disable_src_clk; 1390 1391 s3c64xx_spi_hwinit(sdd); 1392 1393 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1394 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1395 sdd->regs + S3C64XX_SPI_INT_EN); 1396 1397 return 0; 1398 1399 err_disable_src_clk: 1400 clk_disable_unprepare(sdd->src_clk); 1401 err_disable_ioclk: 1402 clk_disable_unprepare(sdd->ioclk); 1403 1404 return ret; 1405 } 1406 #endif /* CONFIG_PM */ 1407 1408 static const struct dev_pm_ops s3c64xx_spi_pm = { 1409 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) 1410 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, 1411 s3c64xx_spi_runtime_resume, NULL) 1412 }; 1413 1414 static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1415 .fifo_lvl_mask = { 0x7f }, 1416 .rx_lvl_offset = 13, 1417 .tx_st_done = 21, 1418 .clk_div = 2, 1419 .high_speed = true, 1420 }; 1421 1422 static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1423 .fifo_lvl_mask = { 0x7f, 0x7F }, 1424 .rx_lvl_offset = 13, 1425 .tx_st_done = 21, 1426 .clk_div = 2, 1427 }; 1428 1429 static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1430 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1431 .rx_lvl_offset = 15, 1432 .tx_st_done = 25, 1433 .clk_div = 2, 1434 .high_speed = true, 1435 }; 1436 1437 static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1438 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1439 .rx_lvl_offset = 15, 1440 .tx_st_done = 25, 1441 .clk_div = 2, 1442 .high_speed = true, 1443 .clk_from_cmu = true, 1444 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1445 }; 1446 1447 static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { 1448 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, 1449 .rx_lvl_offset = 15, 1450 .tx_st_done = 25, 1451 .clk_div = 2, 1452 .high_speed = true, 1453 .clk_from_cmu = true, 1454 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1455 }; 1456 1457 static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { 1458 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, 1459 .rx_lvl_offset = 15, 1460 .tx_st_done = 25, 1461 .clk_div = 2, 1462 .high_speed = true, 1463 .clk_from_cmu = true, 1464 .clk_ioclk = true, 1465 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1466 }; 1467 1468 static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { 1469 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 1470 0x7f, 0x7f, 0x7f, 0x7f}, 1471 .rx_lvl_offset = 15, 1472 .tx_st_done = 25, 1473 .clk_div = 4, 1474 .high_speed = true, 1475 .clk_from_cmu = true, 1476 .clk_ioclk = true, 1477 .has_loopback = true, 1478 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1479 }; 1480 1481 static const struct s3c64xx_spi_port_config fsd_spi_port_config = { 1482 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, 1483 .rx_lvl_offset = 15, 1484 .tx_st_done = 25, 1485 .clk_div = 2, 1486 .high_speed = true, 1487 .clk_from_cmu = true, 1488 .clk_ioclk = false, 1489 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1490 }; 1491 1492 static const struct platform_device_id s3c64xx_spi_driver_ids[] = { 1493 { 1494 .name = "s3c2443-spi", 1495 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, 1496 }, { 1497 .name = "s3c6410-spi", 1498 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1499 }, 1500 { }, 1501 }; 1502 1503 static const struct of_device_id s3c64xx_spi_dt_match[] = { 1504 { .compatible = "samsung,s3c2443-spi", 1505 .data = (void *)&s3c2443_spi_port_config, 1506 }, 1507 { .compatible = "samsung,s3c6410-spi", 1508 .data = (void *)&s3c6410_spi_port_config, 1509 }, 1510 { .compatible = "samsung,s5pv210-spi", 1511 .data = (void *)&s5pv210_spi_port_config, 1512 }, 1513 { .compatible = "samsung,exynos4210-spi", 1514 .data = (void *)&exynos4_spi_port_config, 1515 }, 1516 { .compatible = "samsung,exynos7-spi", 1517 .data = (void *)&exynos7_spi_port_config, 1518 }, 1519 { .compatible = "samsung,exynos5433-spi", 1520 .data = (void *)&exynos5433_spi_port_config, 1521 }, 1522 { .compatible = "samsung,exynosautov9-spi", 1523 .data = (void *)&exynosautov9_spi_port_config, 1524 }, 1525 { .compatible = "tesla,fsd-spi", 1526 .data = (void *)&fsd_spi_port_config, 1527 }, 1528 { }, 1529 }; 1530 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1531 1532 static struct platform_driver s3c64xx_spi_driver = { 1533 .driver = { 1534 .name = "s3c64xx-spi", 1535 .pm = &s3c64xx_spi_pm, 1536 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), 1537 }, 1538 .probe = s3c64xx_spi_probe, 1539 .remove_new = s3c64xx_spi_remove, 1540 .id_table = s3c64xx_spi_driver_ids, 1541 }; 1542 MODULE_ALIAS("platform:s3c64xx-spi"); 1543 1544 module_platform_driver(s3c64xx_spi_driver); 1545 1546 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1547 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1548 MODULE_LICENSE("GPL"); 1549