1 /* 2 * Copyright (C) 2009 Samsung Electronics Ltd. 3 * Jaswinder Singh <jassi.brar@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/workqueue.h> 23 #include <linux/delay.h> 24 #include <linux/clk.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/platform_device.h> 27 #include <linux/spi/spi.h> 28 29 #include <mach/dma.h> 30 #include <plat/s3c64xx-spi.h> 31 32 /* Registers and bit-fields */ 33 34 #define S3C64XX_SPI_CH_CFG 0x00 35 #define S3C64XX_SPI_CLK_CFG 0x04 36 #define S3C64XX_SPI_MODE_CFG 0x08 37 #define S3C64XX_SPI_SLAVE_SEL 0x0C 38 #define S3C64XX_SPI_INT_EN 0x10 39 #define S3C64XX_SPI_STATUS 0x14 40 #define S3C64XX_SPI_TX_DATA 0x18 41 #define S3C64XX_SPI_RX_DATA 0x1C 42 #define S3C64XX_SPI_PACKET_CNT 0x20 43 #define S3C64XX_SPI_PENDING_CLR 0x24 44 #define S3C64XX_SPI_SWAP_CFG 0x28 45 #define S3C64XX_SPI_FB_CLK 0x2C 46 47 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 48 #define S3C64XX_SPI_CH_SW_RST (1<<5) 49 #define S3C64XX_SPI_CH_SLAVE (1<<4) 50 #define S3C64XX_SPI_CPOL_L (1<<3) 51 #define S3C64XX_SPI_CPHA_B (1<<2) 52 #define S3C64XX_SPI_CH_RXCH_ON (1<<1) 53 #define S3C64XX_SPI_CH_TXCH_ON (1<<0) 54 55 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 56 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 57 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 58 #define S3C64XX_SPI_PSR_MASK 0xff 59 60 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 61 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 62 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 63 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 64 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 65 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 66 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 67 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 68 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 69 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 70 #define S3C64XX_SPI_MODE_4BURST (1<<0) 71 72 #define S3C64XX_SPI_SLAVE_AUTO (1<<1) 73 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) 74 75 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL) 76 77 #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \ 78 (c)->regs + S3C64XX_SPI_SLAVE_SEL) 79 80 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 81 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 82 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 83 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 84 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 85 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 86 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 87 88 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 89 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 90 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 91 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 92 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 93 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 94 95 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 96 97 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 98 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 99 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 100 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 101 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 102 103 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 104 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 105 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 106 #define S3C64XX_SPI_SWAP_RX_EN (1<<4) 107 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 108 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 109 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 110 #define S3C64XX_SPI_SWAP_TX_EN (1<<0) 111 112 #define S3C64XX_SPI_FBCLK_MSK (3<<0) 113 114 #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \ 115 (((i)->fifo_lvl_mask + 1))) \ 116 ? 1 : 0) 117 118 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0) 119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask) 120 #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask) 121 122 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 123 #define S3C64XX_SPI_TRAILCNT_OFF 19 124 125 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT 126 127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 128 129 #define SUSPND (1<<0) 130 #define SPIBUSY (1<<1) 131 #define RXBUSY (1<<2) 132 #define TXBUSY (1<<3) 133 134 /** 135 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 136 * @clk: Pointer to the spi clock. 137 * @src_clk: Pointer to the clock used to generate SPI signals. 138 * @master: Pointer to the SPI Protocol master. 139 * @workqueue: Work queue for the SPI xfer requests. 140 * @cntrlr_info: Platform specific data for the controller this driver manages. 141 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. 142 * @work: Work 143 * @queue: To log SPI xfer requests. 144 * @lock: Controller specific lock. 145 * @state: Set of FLAGS to indicate status. 146 * @rx_dmach: Controller's DMA channel for Rx. 147 * @tx_dmach: Controller's DMA channel for Tx. 148 * @sfr_start: BUS address of SPI controller regs. 149 * @regs: Pointer to ioremap'ed controller registers. 150 * @xfer_completion: To indicate completion of xfer task. 151 * @cur_mode: Stores the active configuration of the controller. 152 * @cur_bpw: Stores the active bits per word settings. 153 * @cur_speed: Stores the active xfer clock speed. 154 */ 155 struct s3c64xx_spi_driver_data { 156 void __iomem *regs; 157 struct clk *clk; 158 struct clk *src_clk; 159 struct platform_device *pdev; 160 struct spi_master *master; 161 struct workqueue_struct *workqueue; 162 struct s3c64xx_spi_info *cntrlr_info; 163 struct spi_device *tgl_spi; 164 struct work_struct work; 165 struct list_head queue; 166 spinlock_t lock; 167 enum dma_ch rx_dmach; 168 enum dma_ch tx_dmach; 169 unsigned long sfr_start; 170 struct completion xfer_completion; 171 unsigned state; 172 unsigned cur_mode, cur_bpw; 173 unsigned cur_speed; 174 }; 175 176 static struct s3c2410_dma_client s3c64xx_spi_dma_client = { 177 .name = "samsung-spi-dma", 178 }; 179 180 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) 181 { 182 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 183 void __iomem *regs = sdd->regs; 184 unsigned long loops; 185 u32 val; 186 187 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 188 189 val = readl(regs + S3C64XX_SPI_CH_CFG); 190 val |= S3C64XX_SPI_CH_SW_RST; 191 val &= ~S3C64XX_SPI_CH_HS_EN; 192 writel(val, regs + S3C64XX_SPI_CH_CFG); 193 194 /* Flush TxFIFO*/ 195 loops = msecs_to_loops(1); 196 do { 197 val = readl(regs + S3C64XX_SPI_STATUS); 198 } while (TX_FIFO_LVL(val, sci) && loops--); 199 200 if (loops == 0) 201 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 202 203 /* Flush RxFIFO*/ 204 loops = msecs_to_loops(1); 205 do { 206 val = readl(regs + S3C64XX_SPI_STATUS); 207 if (RX_FIFO_LVL(val, sci)) 208 readl(regs + S3C64XX_SPI_RX_DATA); 209 else 210 break; 211 } while (loops--); 212 213 if (loops == 0) 214 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 215 216 val = readl(regs + S3C64XX_SPI_CH_CFG); 217 val &= ~S3C64XX_SPI_CH_SW_RST; 218 writel(val, regs + S3C64XX_SPI_CH_CFG); 219 220 val = readl(regs + S3C64XX_SPI_MODE_CFG); 221 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 222 writel(val, regs + S3C64XX_SPI_MODE_CFG); 223 224 val = readl(regs + S3C64XX_SPI_CH_CFG); 225 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 226 writel(val, regs + S3C64XX_SPI_CH_CFG); 227 } 228 229 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, 230 struct spi_device *spi, 231 struct spi_transfer *xfer, int dma_mode) 232 { 233 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 234 void __iomem *regs = sdd->regs; 235 u32 modecfg, chcfg; 236 237 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 238 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 239 240 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 241 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 242 243 if (dma_mode) { 244 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 245 } else { 246 /* Always shift in data in FIFO, even if xfer is Tx only, 247 * this helps setting PCKT_CNT value for generating clocks 248 * as exactly needed. 249 */ 250 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 251 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 252 | S3C64XX_SPI_PACKET_CNT_EN, 253 regs + S3C64XX_SPI_PACKET_CNT); 254 } 255 256 if (xfer->tx_buf != NULL) { 257 sdd->state |= TXBUSY; 258 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 259 if (dma_mode) { 260 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 261 s3c2410_dma_config(sdd->tx_dmach, sdd->cur_bpw / 8); 262 s3c2410_dma_enqueue(sdd->tx_dmach, (void *)sdd, 263 xfer->tx_dma, xfer->len); 264 s3c2410_dma_ctrl(sdd->tx_dmach, S3C2410_DMAOP_START); 265 } else { 266 switch (sdd->cur_bpw) { 267 case 32: 268 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, 269 xfer->tx_buf, xfer->len / 4); 270 break; 271 case 16: 272 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, 273 xfer->tx_buf, xfer->len / 2); 274 break; 275 default: 276 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, 277 xfer->tx_buf, xfer->len); 278 break; 279 } 280 } 281 } 282 283 if (xfer->rx_buf != NULL) { 284 sdd->state |= RXBUSY; 285 286 if (sci->high_speed && sdd->cur_speed >= 30000000UL 287 && !(sdd->cur_mode & SPI_CPHA)) 288 chcfg |= S3C64XX_SPI_CH_HS_EN; 289 290 if (dma_mode) { 291 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 292 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 293 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 294 | S3C64XX_SPI_PACKET_CNT_EN, 295 regs + S3C64XX_SPI_PACKET_CNT); 296 s3c2410_dma_config(sdd->rx_dmach, sdd->cur_bpw / 8); 297 s3c2410_dma_enqueue(sdd->rx_dmach, (void *)sdd, 298 xfer->rx_dma, xfer->len); 299 s3c2410_dma_ctrl(sdd->rx_dmach, S3C2410_DMAOP_START); 300 } 301 } 302 303 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 304 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 305 } 306 307 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, 308 struct spi_device *spi) 309 { 310 struct s3c64xx_spi_csinfo *cs; 311 312 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */ 313 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ 314 /* Deselect the last toggled device */ 315 cs = sdd->tgl_spi->controller_data; 316 cs->set_level(cs->line, 317 spi->mode & SPI_CS_HIGH ? 0 : 1); 318 } 319 sdd->tgl_spi = NULL; 320 } 321 322 cs = spi->controller_data; 323 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); 324 } 325 326 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, 327 struct spi_transfer *xfer, int dma_mode) 328 { 329 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 330 void __iomem *regs = sdd->regs; 331 unsigned long val; 332 int ms; 333 334 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 335 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 336 ms += 10; /* some tolerance */ 337 338 if (dma_mode) { 339 val = msecs_to_jiffies(ms) + 10; 340 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 341 } else { 342 u32 status; 343 val = msecs_to_loops(ms); 344 do { 345 status = readl(regs + S3C64XX_SPI_STATUS); 346 } while (RX_FIFO_LVL(status, sci) < xfer->len && --val); 347 } 348 349 if (!val) 350 return -EIO; 351 352 if (dma_mode) { 353 u32 status; 354 355 /* 356 * DmaTx returns after simply writing data in the FIFO, 357 * w/o waiting for real transmission on the bus to finish. 358 * DmaRx returns only after Dma read data from FIFO which 359 * needs bus transmission to finish, so we don't worry if 360 * Xfer involved Rx(with or without Tx). 361 */ 362 if (xfer->rx_buf == NULL) { 363 val = msecs_to_loops(10); 364 status = readl(regs + S3C64XX_SPI_STATUS); 365 while ((TX_FIFO_LVL(status, sci) 366 || !S3C64XX_SPI_ST_TX_DONE(status, sci)) 367 && --val) { 368 cpu_relax(); 369 status = readl(regs + S3C64XX_SPI_STATUS); 370 } 371 372 if (!val) 373 return -EIO; 374 } 375 } else { 376 /* If it was only Tx */ 377 if (xfer->rx_buf == NULL) { 378 sdd->state &= ~TXBUSY; 379 return 0; 380 } 381 382 switch (sdd->cur_bpw) { 383 case 32: 384 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 385 xfer->rx_buf, xfer->len / 4); 386 break; 387 case 16: 388 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 389 xfer->rx_buf, xfer->len / 2); 390 break; 391 default: 392 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 393 xfer->rx_buf, xfer->len); 394 break; 395 } 396 sdd->state &= ~RXBUSY; 397 } 398 399 return 0; 400 } 401 402 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, 403 struct spi_device *spi) 404 { 405 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 406 407 if (sdd->tgl_spi == spi) 408 sdd->tgl_spi = NULL; 409 410 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); 411 } 412 413 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 414 { 415 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 416 void __iomem *regs = sdd->regs; 417 u32 val; 418 419 /* Disable Clock */ 420 if (sci->clk_from_cmu) { 421 clk_disable(sdd->src_clk); 422 } else { 423 val = readl(regs + S3C64XX_SPI_CLK_CFG); 424 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 425 writel(val, regs + S3C64XX_SPI_CLK_CFG); 426 } 427 428 /* Set Polarity and Phase */ 429 val = readl(regs + S3C64XX_SPI_CH_CFG); 430 val &= ~(S3C64XX_SPI_CH_SLAVE | 431 S3C64XX_SPI_CPOL_L | 432 S3C64XX_SPI_CPHA_B); 433 434 if (sdd->cur_mode & SPI_CPOL) 435 val |= S3C64XX_SPI_CPOL_L; 436 437 if (sdd->cur_mode & SPI_CPHA) 438 val |= S3C64XX_SPI_CPHA_B; 439 440 writel(val, regs + S3C64XX_SPI_CH_CFG); 441 442 /* Set Channel & DMA Mode */ 443 val = readl(regs + S3C64XX_SPI_MODE_CFG); 444 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 445 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 446 447 switch (sdd->cur_bpw) { 448 case 32: 449 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 450 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 451 break; 452 case 16: 453 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 454 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 455 break; 456 default: 457 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 458 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 459 break; 460 } 461 462 writel(val, regs + S3C64XX_SPI_MODE_CFG); 463 464 if (sci->clk_from_cmu) { 465 /* Configure Clock */ 466 /* There is half-multiplier before the SPI */ 467 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); 468 /* Enable Clock */ 469 clk_enable(sdd->src_clk); 470 } else { 471 /* Configure Clock */ 472 val = readl(regs + S3C64XX_SPI_CLK_CFG); 473 val &= ~S3C64XX_SPI_PSR_MASK; 474 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) 475 & S3C64XX_SPI_PSR_MASK); 476 writel(val, regs + S3C64XX_SPI_CLK_CFG); 477 478 /* Enable Clock */ 479 val = readl(regs + S3C64XX_SPI_CLK_CFG); 480 val |= S3C64XX_SPI_ENCLK_ENABLE; 481 writel(val, regs + S3C64XX_SPI_CLK_CFG); 482 } 483 } 484 485 static void s3c64xx_spi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id, 486 int size, enum s3c2410_dma_buffresult res) 487 { 488 struct s3c64xx_spi_driver_data *sdd = buf_id; 489 unsigned long flags; 490 491 spin_lock_irqsave(&sdd->lock, flags); 492 493 if (res == S3C2410_RES_OK) 494 sdd->state &= ~RXBUSY; 495 else 496 dev_err(&sdd->pdev->dev, "DmaAbrtRx-%d\n", size); 497 498 /* If the other done */ 499 if (!(sdd->state & TXBUSY)) 500 complete(&sdd->xfer_completion); 501 502 spin_unlock_irqrestore(&sdd->lock, flags); 503 } 504 505 static void s3c64xx_spi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id, 506 int size, enum s3c2410_dma_buffresult res) 507 { 508 struct s3c64xx_spi_driver_data *sdd = buf_id; 509 unsigned long flags; 510 511 spin_lock_irqsave(&sdd->lock, flags); 512 513 if (res == S3C2410_RES_OK) 514 sdd->state &= ~TXBUSY; 515 else 516 dev_err(&sdd->pdev->dev, "DmaAbrtTx-%d \n", size); 517 518 /* If the other done */ 519 if (!(sdd->state & RXBUSY)) 520 complete(&sdd->xfer_completion); 521 522 spin_unlock_irqrestore(&sdd->lock, flags); 523 } 524 525 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 526 527 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, 528 struct spi_message *msg) 529 { 530 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 531 struct device *dev = &sdd->pdev->dev; 532 struct spi_transfer *xfer; 533 534 if (msg->is_dma_mapped) 535 return 0; 536 537 /* First mark all xfer unmapped */ 538 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 539 xfer->rx_dma = XFER_DMAADDR_INVALID; 540 xfer->tx_dma = XFER_DMAADDR_INVALID; 541 } 542 543 /* Map until end or first fail */ 544 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 545 546 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) 547 continue; 548 549 if (xfer->tx_buf != NULL) { 550 xfer->tx_dma = dma_map_single(dev, 551 (void *)xfer->tx_buf, xfer->len, 552 DMA_TO_DEVICE); 553 if (dma_mapping_error(dev, xfer->tx_dma)) { 554 dev_err(dev, "dma_map_single Tx failed\n"); 555 xfer->tx_dma = XFER_DMAADDR_INVALID; 556 return -ENOMEM; 557 } 558 } 559 560 if (xfer->rx_buf != NULL) { 561 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf, 562 xfer->len, DMA_FROM_DEVICE); 563 if (dma_mapping_error(dev, xfer->rx_dma)) { 564 dev_err(dev, "dma_map_single Rx failed\n"); 565 dma_unmap_single(dev, xfer->tx_dma, 566 xfer->len, DMA_TO_DEVICE); 567 xfer->tx_dma = XFER_DMAADDR_INVALID; 568 xfer->rx_dma = XFER_DMAADDR_INVALID; 569 return -ENOMEM; 570 } 571 } 572 } 573 574 return 0; 575 } 576 577 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, 578 struct spi_message *msg) 579 { 580 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 581 struct device *dev = &sdd->pdev->dev; 582 struct spi_transfer *xfer; 583 584 if (msg->is_dma_mapped) 585 return; 586 587 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 588 589 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) 590 continue; 591 592 if (xfer->rx_buf != NULL 593 && xfer->rx_dma != XFER_DMAADDR_INVALID) 594 dma_unmap_single(dev, xfer->rx_dma, 595 xfer->len, DMA_FROM_DEVICE); 596 597 if (xfer->tx_buf != NULL 598 && xfer->tx_dma != XFER_DMAADDR_INVALID) 599 dma_unmap_single(dev, xfer->tx_dma, 600 xfer->len, DMA_TO_DEVICE); 601 } 602 } 603 604 static void handle_msg(struct s3c64xx_spi_driver_data *sdd, 605 struct spi_message *msg) 606 { 607 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 608 struct spi_device *spi = msg->spi; 609 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 610 struct spi_transfer *xfer; 611 int status = 0, cs_toggle = 0; 612 u32 speed; 613 u8 bpw; 614 615 /* If Master's(controller) state differs from that needed by Slave */ 616 if (sdd->cur_speed != spi->max_speed_hz 617 || sdd->cur_mode != spi->mode 618 || sdd->cur_bpw != spi->bits_per_word) { 619 sdd->cur_bpw = spi->bits_per_word; 620 sdd->cur_speed = spi->max_speed_hz; 621 sdd->cur_mode = spi->mode; 622 s3c64xx_spi_config(sdd); 623 } 624 625 /* Map all the transfers if needed */ 626 if (s3c64xx_spi_map_mssg(sdd, msg)) { 627 dev_err(&spi->dev, 628 "Xfer: Unable to map message buffers!\n"); 629 status = -ENOMEM; 630 goto out; 631 } 632 633 /* Configure feedback delay */ 634 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 635 636 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 637 638 unsigned long flags; 639 int use_dma; 640 641 INIT_COMPLETION(sdd->xfer_completion); 642 643 /* Only BPW and Speed may change across transfers */ 644 bpw = xfer->bits_per_word ? : spi->bits_per_word; 645 speed = xfer->speed_hz ? : spi->max_speed_hz; 646 647 if (xfer->len % (bpw / 8)) { 648 dev_err(&spi->dev, 649 "Xfer length(%u) not a multiple of word size(%u)\n", 650 xfer->len, bpw / 8); 651 status = -EIO; 652 goto out; 653 } 654 655 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 656 sdd->cur_bpw = bpw; 657 sdd->cur_speed = speed; 658 s3c64xx_spi_config(sdd); 659 } 660 661 /* Polling method for xfers not bigger than FIFO capacity */ 662 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) 663 use_dma = 0; 664 else 665 use_dma = 1; 666 667 spin_lock_irqsave(&sdd->lock, flags); 668 669 /* Pending only which is to be done */ 670 sdd->state &= ~RXBUSY; 671 sdd->state &= ~TXBUSY; 672 673 enable_datapath(sdd, spi, xfer, use_dma); 674 675 /* Slave Select */ 676 enable_cs(sdd, spi); 677 678 /* Start the signals */ 679 S3C64XX_SPI_ACT(sdd); 680 681 spin_unlock_irqrestore(&sdd->lock, flags); 682 683 status = wait_for_xfer(sdd, xfer, use_dma); 684 685 /* Quiese the signals */ 686 S3C64XX_SPI_DEACT(sdd); 687 688 if (status) { 689 dev_err(&spi->dev, "I/O Error: " 690 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n", 691 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 692 (sdd->state & RXBUSY) ? 'f' : 'p', 693 (sdd->state & TXBUSY) ? 'f' : 'p', 694 xfer->len); 695 696 if (use_dma) { 697 if (xfer->tx_buf != NULL 698 && (sdd->state & TXBUSY)) 699 s3c2410_dma_ctrl(sdd->tx_dmach, 700 S3C2410_DMAOP_FLUSH); 701 if (xfer->rx_buf != NULL 702 && (sdd->state & RXBUSY)) 703 s3c2410_dma_ctrl(sdd->rx_dmach, 704 S3C2410_DMAOP_FLUSH); 705 } 706 707 goto out; 708 } 709 710 if (xfer->delay_usecs) 711 udelay(xfer->delay_usecs); 712 713 if (xfer->cs_change) { 714 /* Hint that the next mssg is gonna be 715 for the same device */ 716 if (list_is_last(&xfer->transfer_list, 717 &msg->transfers)) 718 cs_toggle = 1; 719 else 720 disable_cs(sdd, spi); 721 } 722 723 msg->actual_length += xfer->len; 724 725 flush_fifo(sdd); 726 } 727 728 out: 729 if (!cs_toggle || status) 730 disable_cs(sdd, spi); 731 else 732 sdd->tgl_spi = spi; 733 734 s3c64xx_spi_unmap_mssg(sdd, msg); 735 736 msg->status = status; 737 738 if (msg->complete) 739 msg->complete(msg->context); 740 } 741 742 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) 743 { 744 if (s3c2410_dma_request(sdd->rx_dmach, 745 &s3c64xx_spi_dma_client, NULL) < 0) { 746 dev_err(&sdd->pdev->dev, "cannot get RxDMA\n"); 747 return 0; 748 } 749 s3c2410_dma_set_buffdone_fn(sdd->rx_dmach, s3c64xx_spi_dma_rxcb); 750 s3c2410_dma_devconfig(sdd->rx_dmach, S3C2410_DMASRC_HW, 751 sdd->sfr_start + S3C64XX_SPI_RX_DATA); 752 753 if (s3c2410_dma_request(sdd->tx_dmach, 754 &s3c64xx_spi_dma_client, NULL) < 0) { 755 dev_err(&sdd->pdev->dev, "cannot get TxDMA\n"); 756 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client); 757 return 0; 758 } 759 s3c2410_dma_set_buffdone_fn(sdd->tx_dmach, s3c64xx_spi_dma_txcb); 760 s3c2410_dma_devconfig(sdd->tx_dmach, S3C2410_DMASRC_MEM, 761 sdd->sfr_start + S3C64XX_SPI_TX_DATA); 762 763 return 1; 764 } 765 766 static void s3c64xx_spi_work(struct work_struct *work) 767 { 768 struct s3c64xx_spi_driver_data *sdd = container_of(work, 769 struct s3c64xx_spi_driver_data, work); 770 unsigned long flags; 771 772 /* Acquire DMA channels */ 773 while (!acquire_dma(sdd)) 774 msleep(10); 775 776 spin_lock_irqsave(&sdd->lock, flags); 777 778 while (!list_empty(&sdd->queue) 779 && !(sdd->state & SUSPND)) { 780 781 struct spi_message *msg; 782 783 msg = container_of(sdd->queue.next, struct spi_message, queue); 784 785 list_del_init(&msg->queue); 786 787 /* Set Xfer busy flag */ 788 sdd->state |= SPIBUSY; 789 790 spin_unlock_irqrestore(&sdd->lock, flags); 791 792 handle_msg(sdd, msg); 793 794 spin_lock_irqsave(&sdd->lock, flags); 795 796 sdd->state &= ~SPIBUSY; 797 } 798 799 spin_unlock_irqrestore(&sdd->lock, flags); 800 801 /* Free DMA channels */ 802 s3c2410_dma_free(sdd->tx_dmach, &s3c64xx_spi_dma_client); 803 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client); 804 } 805 806 static int s3c64xx_spi_transfer(struct spi_device *spi, 807 struct spi_message *msg) 808 { 809 struct s3c64xx_spi_driver_data *sdd; 810 unsigned long flags; 811 812 sdd = spi_master_get_devdata(spi->master); 813 814 spin_lock_irqsave(&sdd->lock, flags); 815 816 if (sdd->state & SUSPND) { 817 spin_unlock_irqrestore(&sdd->lock, flags); 818 return -ESHUTDOWN; 819 } 820 821 msg->status = -EINPROGRESS; 822 msg->actual_length = 0; 823 824 list_add_tail(&msg->queue, &sdd->queue); 825 826 queue_work(sdd->workqueue, &sdd->work); 827 828 spin_unlock_irqrestore(&sdd->lock, flags); 829 830 return 0; 831 } 832 833 /* 834 * Here we only check the validity of requested configuration 835 * and save the configuration in a local data-structure. 836 * The controller is actually configured only just before we 837 * get a message to transfer. 838 */ 839 static int s3c64xx_spi_setup(struct spi_device *spi) 840 { 841 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 842 struct s3c64xx_spi_driver_data *sdd; 843 struct s3c64xx_spi_info *sci; 844 struct spi_message *msg; 845 unsigned long flags; 846 int err = 0; 847 848 if (cs == NULL || cs->set_level == NULL) { 849 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); 850 return -ENODEV; 851 } 852 853 sdd = spi_master_get_devdata(spi->master); 854 sci = sdd->cntrlr_info; 855 856 spin_lock_irqsave(&sdd->lock, flags); 857 858 list_for_each_entry(msg, &sdd->queue, queue) { 859 /* Is some mssg is already queued for this device */ 860 if (msg->spi == spi) { 861 dev_err(&spi->dev, 862 "setup: attempt while mssg in queue!\n"); 863 spin_unlock_irqrestore(&sdd->lock, flags); 864 return -EBUSY; 865 } 866 } 867 868 if (sdd->state & SUSPND) { 869 spin_unlock_irqrestore(&sdd->lock, flags); 870 dev_err(&spi->dev, 871 "setup: SPI-%d not active!\n", spi->master->bus_num); 872 return -ESHUTDOWN; 873 } 874 875 spin_unlock_irqrestore(&sdd->lock, flags); 876 877 if (spi->bits_per_word != 8 878 && spi->bits_per_word != 16 879 && spi->bits_per_word != 32) { 880 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n", 881 spi->bits_per_word); 882 err = -EINVAL; 883 goto setup_exit; 884 } 885 886 /* Check if we can provide the requested rate */ 887 if (!sci->clk_from_cmu) { 888 u32 psr, speed; 889 890 /* Max possible */ 891 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); 892 893 if (spi->max_speed_hz > speed) 894 spi->max_speed_hz = speed; 895 896 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; 897 psr &= S3C64XX_SPI_PSR_MASK; 898 if (psr == S3C64XX_SPI_PSR_MASK) 899 psr--; 900 901 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 902 if (spi->max_speed_hz < speed) { 903 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 904 psr++; 905 } else { 906 err = -EINVAL; 907 goto setup_exit; 908 } 909 } 910 911 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 912 if (spi->max_speed_hz >= speed) 913 spi->max_speed_hz = speed; 914 else 915 err = -EINVAL; 916 } 917 918 setup_exit: 919 920 /* setup() returns with device de-selected */ 921 disable_cs(sdd, spi); 922 923 return err; 924 } 925 926 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) 927 { 928 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 929 void __iomem *regs = sdd->regs; 930 unsigned int val; 931 932 sdd->cur_speed = 0; 933 934 S3C64XX_SPI_DEACT(sdd); 935 936 /* Disable Interrupts - we use Polling if not DMA mode */ 937 writel(0, regs + S3C64XX_SPI_INT_EN); 938 939 if (!sci->clk_from_cmu) 940 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 941 regs + S3C64XX_SPI_CLK_CFG); 942 writel(0, regs + S3C64XX_SPI_MODE_CFG); 943 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 944 945 /* Clear any irq pending bits */ 946 writel(readl(regs + S3C64XX_SPI_PENDING_CLR), 947 regs + S3C64XX_SPI_PENDING_CLR); 948 949 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 950 951 val = readl(regs + S3C64XX_SPI_MODE_CFG); 952 val &= ~S3C64XX_SPI_MODE_4BURST; 953 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 954 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 955 writel(val, regs + S3C64XX_SPI_MODE_CFG); 956 957 flush_fifo(sdd); 958 } 959 960 static int __init s3c64xx_spi_probe(struct platform_device *pdev) 961 { 962 struct resource *mem_res, *dmatx_res, *dmarx_res; 963 struct s3c64xx_spi_driver_data *sdd; 964 struct s3c64xx_spi_info *sci; 965 struct spi_master *master; 966 int ret; 967 968 if (pdev->id < 0) { 969 dev_err(&pdev->dev, 970 "Invalid platform device id-%d\n", pdev->id); 971 return -ENODEV; 972 } 973 974 if (pdev->dev.platform_data == NULL) { 975 dev_err(&pdev->dev, "platform_data missing!\n"); 976 return -ENODEV; 977 } 978 979 sci = pdev->dev.platform_data; 980 if (!sci->src_clk_name) { 981 dev_err(&pdev->dev, 982 "Board init must call s3c64xx_spi_set_info()\n"); 983 return -EINVAL; 984 } 985 986 /* Check for availability of necessary resource */ 987 988 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 989 if (dmatx_res == NULL) { 990 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n"); 991 return -ENXIO; 992 } 993 994 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 995 if (dmarx_res == NULL) { 996 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n"); 997 return -ENXIO; 998 } 999 1000 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1001 if (mem_res == NULL) { 1002 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); 1003 return -ENXIO; 1004 } 1005 1006 master = spi_alloc_master(&pdev->dev, 1007 sizeof(struct s3c64xx_spi_driver_data)); 1008 if (master == NULL) { 1009 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 1010 return -ENOMEM; 1011 } 1012 1013 platform_set_drvdata(pdev, master); 1014 1015 sdd = spi_master_get_devdata(master); 1016 sdd->master = master; 1017 sdd->cntrlr_info = sci; 1018 sdd->pdev = pdev; 1019 sdd->sfr_start = mem_res->start; 1020 sdd->tx_dmach = dmatx_res->start; 1021 sdd->rx_dmach = dmarx_res->start; 1022 1023 sdd->cur_bpw = 8; 1024 1025 master->bus_num = pdev->id; 1026 master->setup = s3c64xx_spi_setup; 1027 master->transfer = s3c64xx_spi_transfer; 1028 master->num_chipselect = sci->num_cs; 1029 master->dma_alignment = 8; 1030 /* the spi->mode bits understood by this driver: */ 1031 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1032 1033 if (request_mem_region(mem_res->start, 1034 resource_size(mem_res), pdev->name) == NULL) { 1035 dev_err(&pdev->dev, "Req mem region failed\n"); 1036 ret = -ENXIO; 1037 goto err0; 1038 } 1039 1040 sdd->regs = ioremap(mem_res->start, resource_size(mem_res)); 1041 if (sdd->regs == NULL) { 1042 dev_err(&pdev->dev, "Unable to remap IO\n"); 1043 ret = -ENXIO; 1044 goto err1; 1045 } 1046 1047 if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) { 1048 dev_err(&pdev->dev, "Unable to config gpio\n"); 1049 ret = -EBUSY; 1050 goto err2; 1051 } 1052 1053 /* Setup clocks */ 1054 sdd->clk = clk_get(&pdev->dev, "spi"); 1055 if (IS_ERR(sdd->clk)) { 1056 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); 1057 ret = PTR_ERR(sdd->clk); 1058 goto err3; 1059 } 1060 1061 if (clk_enable(sdd->clk)) { 1062 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); 1063 ret = -EBUSY; 1064 goto err4; 1065 } 1066 1067 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name); 1068 if (IS_ERR(sdd->src_clk)) { 1069 dev_err(&pdev->dev, 1070 "Unable to acquire clock '%s'\n", sci->src_clk_name); 1071 ret = PTR_ERR(sdd->src_clk); 1072 goto err5; 1073 } 1074 1075 if (clk_enable(sdd->src_clk)) { 1076 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", 1077 sci->src_clk_name); 1078 ret = -EBUSY; 1079 goto err6; 1080 } 1081 1082 sdd->workqueue = create_singlethread_workqueue( 1083 dev_name(master->dev.parent)); 1084 if (sdd->workqueue == NULL) { 1085 dev_err(&pdev->dev, "Unable to create workqueue\n"); 1086 ret = -ENOMEM; 1087 goto err7; 1088 } 1089 1090 /* Setup Deufult Mode */ 1091 s3c64xx_spi_hwinit(sdd, pdev->id); 1092 1093 spin_lock_init(&sdd->lock); 1094 init_completion(&sdd->xfer_completion); 1095 INIT_WORK(&sdd->work, s3c64xx_spi_work); 1096 INIT_LIST_HEAD(&sdd->queue); 1097 1098 if (spi_register_master(master)) { 1099 dev_err(&pdev->dev, "cannot register SPI master\n"); 1100 ret = -EBUSY; 1101 goto err8; 1102 } 1103 1104 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " 1105 "with %d Slaves attached\n", 1106 pdev->id, master->num_chipselect); 1107 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", 1108 mem_res->end, mem_res->start, 1109 sdd->rx_dmach, sdd->tx_dmach); 1110 1111 return 0; 1112 1113 err8: 1114 destroy_workqueue(sdd->workqueue); 1115 err7: 1116 clk_disable(sdd->src_clk); 1117 err6: 1118 clk_put(sdd->src_clk); 1119 err5: 1120 clk_disable(sdd->clk); 1121 err4: 1122 clk_put(sdd->clk); 1123 err3: 1124 err2: 1125 iounmap((void *) sdd->regs); 1126 err1: 1127 release_mem_region(mem_res->start, resource_size(mem_res)); 1128 err0: 1129 platform_set_drvdata(pdev, NULL); 1130 spi_master_put(master); 1131 1132 return ret; 1133 } 1134 1135 static int s3c64xx_spi_remove(struct platform_device *pdev) 1136 { 1137 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 1138 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1139 struct resource *mem_res; 1140 unsigned long flags; 1141 1142 spin_lock_irqsave(&sdd->lock, flags); 1143 sdd->state |= SUSPND; 1144 spin_unlock_irqrestore(&sdd->lock, flags); 1145 1146 while (sdd->state & SPIBUSY) 1147 msleep(10); 1148 1149 spi_unregister_master(master); 1150 1151 destroy_workqueue(sdd->workqueue); 1152 1153 clk_disable(sdd->src_clk); 1154 clk_put(sdd->src_clk); 1155 1156 clk_disable(sdd->clk); 1157 clk_put(sdd->clk); 1158 1159 iounmap((void *) sdd->regs); 1160 1161 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1162 if (mem_res != NULL) 1163 release_mem_region(mem_res->start, resource_size(mem_res)); 1164 1165 platform_set_drvdata(pdev, NULL); 1166 spi_master_put(master); 1167 1168 return 0; 1169 } 1170 1171 #ifdef CONFIG_PM 1172 static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state) 1173 { 1174 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 1175 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1176 unsigned long flags; 1177 1178 spin_lock_irqsave(&sdd->lock, flags); 1179 sdd->state |= SUSPND; 1180 spin_unlock_irqrestore(&sdd->lock, flags); 1181 1182 while (sdd->state & SPIBUSY) 1183 msleep(10); 1184 1185 /* Disable the clock */ 1186 clk_disable(sdd->src_clk); 1187 clk_disable(sdd->clk); 1188 1189 sdd->cur_speed = 0; /* Output Clock is stopped */ 1190 1191 return 0; 1192 } 1193 1194 static int s3c64xx_spi_resume(struct platform_device *pdev) 1195 { 1196 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 1197 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1198 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1199 unsigned long flags; 1200 1201 sci->cfg_gpio(pdev); 1202 1203 /* Enable the clock */ 1204 clk_enable(sdd->src_clk); 1205 clk_enable(sdd->clk); 1206 1207 s3c64xx_spi_hwinit(sdd, pdev->id); 1208 1209 spin_lock_irqsave(&sdd->lock, flags); 1210 sdd->state &= ~SUSPND; 1211 spin_unlock_irqrestore(&sdd->lock, flags); 1212 1213 return 0; 1214 } 1215 #else 1216 #define s3c64xx_spi_suspend NULL 1217 #define s3c64xx_spi_resume NULL 1218 #endif /* CONFIG_PM */ 1219 1220 static struct platform_driver s3c64xx_spi_driver = { 1221 .driver = { 1222 .name = "s3c64xx-spi", 1223 .owner = THIS_MODULE, 1224 }, 1225 .remove = s3c64xx_spi_remove, 1226 .suspend = s3c64xx_spi_suspend, 1227 .resume = s3c64xx_spi_resume, 1228 }; 1229 MODULE_ALIAS("platform:s3c64xx-spi"); 1230 1231 static int __init s3c64xx_spi_init(void) 1232 { 1233 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe); 1234 } 1235 subsys_initcall(s3c64xx_spi_init); 1236 1237 static void __exit s3c64xx_spi_exit(void) 1238 { 1239 platform_driver_unregister(&s3c64xx_spi_driver); 1240 } 1241 module_exit(s3c64xx_spi_exit); 1242 1243 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1244 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1245 MODULE_LICENSE("GPL"); 1246