1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2009 Samsung Electronics Co., Ltd. 4 // Jaswinder Singh <jassi.brar@samsung.com> 5 6 #include <linux/init.h> 7 #include <linux/module.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/spi/spi.h> 16 #include <linux/gpio.h> 17 #include <linux/of.h> 18 #include <linux/of_gpio.h> 19 20 #include <linux/platform_data/spi-s3c64xx.h> 21 22 #define MAX_SPI_PORTS 6 23 #define S3C64XX_SPI_QUIRK_POLL (1 << 0) 24 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) 25 #define AUTOSUSPEND_TIMEOUT 2000 26 27 /* Registers and bit-fields */ 28 29 #define S3C64XX_SPI_CH_CFG 0x00 30 #define S3C64XX_SPI_CLK_CFG 0x04 31 #define S3C64XX_SPI_MODE_CFG 0x08 32 #define S3C64XX_SPI_SLAVE_SEL 0x0C 33 #define S3C64XX_SPI_INT_EN 0x10 34 #define S3C64XX_SPI_STATUS 0x14 35 #define S3C64XX_SPI_TX_DATA 0x18 36 #define S3C64XX_SPI_RX_DATA 0x1C 37 #define S3C64XX_SPI_PACKET_CNT 0x20 38 #define S3C64XX_SPI_PENDING_CLR 0x24 39 #define S3C64XX_SPI_SWAP_CFG 0x28 40 #define S3C64XX_SPI_FB_CLK 0x2C 41 42 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 43 #define S3C64XX_SPI_CH_SW_RST (1<<5) 44 #define S3C64XX_SPI_CH_SLAVE (1<<4) 45 #define S3C64XX_SPI_CPOL_L (1<<3) 46 #define S3C64XX_SPI_CPHA_B (1<<2) 47 #define S3C64XX_SPI_CH_RXCH_ON (1<<1) 48 #define S3C64XX_SPI_CH_TXCH_ON (1<<0) 49 50 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 51 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 52 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 53 #define S3C64XX_SPI_PSR_MASK 0xff 54 55 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 56 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 57 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 58 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 59 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 60 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 61 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 62 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 63 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 64 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 65 #define S3C64XX_SPI_MODE_4BURST (1<<0) 66 67 #define S3C64XX_SPI_SLAVE_AUTO (1<<1) 68 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) 69 #define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4) 70 71 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 72 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 73 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 74 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 75 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 76 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 77 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 78 79 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 80 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 81 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 82 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 83 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 84 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 85 86 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 87 88 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 89 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 90 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 91 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 92 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 93 94 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 95 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 96 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 97 #define S3C64XX_SPI_SWAP_RX_EN (1<<4) 98 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 99 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 100 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 101 #define S3C64XX_SPI_SWAP_TX_EN (1<<0) 102 103 #define S3C64XX_SPI_FBCLK_MSK (3<<0) 104 105 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) 106 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ 107 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) 108 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) 109 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ 110 FIFO_LVL_MASK(i)) 111 112 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 113 #define S3C64XX_SPI_TRAILCNT_OFF 19 114 115 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT 116 117 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 118 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) 119 120 #define RXBUSY (1<<2) 121 #define TXBUSY (1<<3) 122 123 struct s3c64xx_spi_dma_data { 124 struct dma_chan *ch; 125 enum dma_transfer_direction direction; 126 }; 127 128 /** 129 * struct s3c64xx_spi_info - SPI Controller hardware info 130 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. 131 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. 132 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. 133 * @quirks: Bitmask of known quirks 134 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. 135 * @clk_from_cmu: True, if the controller does not include a clock mux and 136 * prescaler unit. 137 * @clk_ioclk: True if clock is present on this device 138 * 139 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but 140 * differ in some aspects such as the size of the fifo and spi bus clock 141 * setup. Such differences are specified to the driver using this structure 142 * which is provided as driver data to the driver. 143 */ 144 struct s3c64xx_spi_port_config { 145 int fifo_lvl_mask[MAX_SPI_PORTS]; 146 int rx_lvl_offset; 147 int tx_st_done; 148 int quirks; 149 bool high_speed; 150 bool clk_from_cmu; 151 bool clk_ioclk; 152 }; 153 154 /** 155 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 156 * @clk: Pointer to the spi clock. 157 * @src_clk: Pointer to the clock used to generate SPI signals. 158 * @ioclk: Pointer to the i/o clock between master and slave 159 * @pdev: Pointer to device's platform device data 160 * @master: Pointer to the SPI Protocol master. 161 * @cntrlr_info: Platform specific data for the controller this driver manages. 162 * @lock: Controller specific lock. 163 * @state: Set of FLAGS to indicate status. 164 * @rx_dmach: Controller's DMA channel for Rx. 165 * @tx_dmach: Controller's DMA channel for Tx. 166 * @sfr_start: BUS address of SPI controller regs. 167 * @regs: Pointer to ioremap'ed controller registers. 168 * @irq: interrupt 169 * @xfer_completion: To indicate completion of xfer task. 170 * @cur_mode: Stores the active configuration of the controller. 171 * @cur_bpw: Stores the active bits per word settings. 172 * @cur_speed: Current clock speed 173 * @rx_dma: Local receive DMA data (e.g. chan and direction) 174 * @tx_dma: Local transmit DMA data (e.g. chan and direction) 175 * @port_conf: Local SPI port configuartion data 176 * @port_id: Port identification number 177 */ 178 struct s3c64xx_spi_driver_data { 179 void __iomem *regs; 180 struct clk *clk; 181 struct clk *src_clk; 182 struct clk *ioclk; 183 struct platform_device *pdev; 184 struct spi_master *master; 185 struct s3c64xx_spi_info *cntrlr_info; 186 spinlock_t lock; 187 unsigned long sfr_start; 188 struct completion xfer_completion; 189 unsigned state; 190 unsigned cur_mode, cur_bpw; 191 unsigned cur_speed; 192 struct s3c64xx_spi_dma_data rx_dma; 193 struct s3c64xx_spi_dma_data tx_dma; 194 struct s3c64xx_spi_port_config *port_conf; 195 unsigned int port_id; 196 }; 197 198 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) 199 { 200 void __iomem *regs = sdd->regs; 201 unsigned long loops; 202 u32 val; 203 204 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 205 206 val = readl(regs + S3C64XX_SPI_CH_CFG); 207 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 208 writel(val, regs + S3C64XX_SPI_CH_CFG); 209 210 val = readl(regs + S3C64XX_SPI_CH_CFG); 211 val |= S3C64XX_SPI_CH_SW_RST; 212 val &= ~S3C64XX_SPI_CH_HS_EN; 213 writel(val, regs + S3C64XX_SPI_CH_CFG); 214 215 /* Flush TxFIFO*/ 216 loops = msecs_to_loops(1); 217 do { 218 val = readl(regs + S3C64XX_SPI_STATUS); 219 } while (TX_FIFO_LVL(val, sdd) && loops--); 220 221 if (loops == 0) 222 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 223 224 /* Flush RxFIFO*/ 225 loops = msecs_to_loops(1); 226 do { 227 val = readl(regs + S3C64XX_SPI_STATUS); 228 if (RX_FIFO_LVL(val, sdd)) 229 readl(regs + S3C64XX_SPI_RX_DATA); 230 else 231 break; 232 } while (loops--); 233 234 if (loops == 0) 235 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 236 237 val = readl(regs + S3C64XX_SPI_CH_CFG); 238 val &= ~S3C64XX_SPI_CH_SW_RST; 239 writel(val, regs + S3C64XX_SPI_CH_CFG); 240 241 val = readl(regs + S3C64XX_SPI_MODE_CFG); 242 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 243 writel(val, regs + S3C64XX_SPI_MODE_CFG); 244 } 245 246 static void s3c64xx_spi_dmacb(void *data) 247 { 248 struct s3c64xx_spi_driver_data *sdd; 249 struct s3c64xx_spi_dma_data *dma = data; 250 unsigned long flags; 251 252 if (dma->direction == DMA_DEV_TO_MEM) 253 sdd = container_of(data, 254 struct s3c64xx_spi_driver_data, rx_dma); 255 else 256 sdd = container_of(data, 257 struct s3c64xx_spi_driver_data, tx_dma); 258 259 spin_lock_irqsave(&sdd->lock, flags); 260 261 if (dma->direction == DMA_DEV_TO_MEM) { 262 sdd->state &= ~RXBUSY; 263 if (!(sdd->state & TXBUSY)) 264 complete(&sdd->xfer_completion); 265 } else { 266 sdd->state &= ~TXBUSY; 267 if (!(sdd->state & RXBUSY)) 268 complete(&sdd->xfer_completion); 269 } 270 271 spin_unlock_irqrestore(&sdd->lock, flags); 272 } 273 274 static void prepare_dma(struct s3c64xx_spi_dma_data *dma, 275 struct sg_table *sgt) 276 { 277 struct s3c64xx_spi_driver_data *sdd; 278 struct dma_slave_config config; 279 struct dma_async_tx_descriptor *desc; 280 281 memset(&config, 0, sizeof(config)); 282 283 if (dma->direction == DMA_DEV_TO_MEM) { 284 sdd = container_of((void *)dma, 285 struct s3c64xx_spi_driver_data, rx_dma); 286 config.direction = dma->direction; 287 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 288 config.src_addr_width = sdd->cur_bpw / 8; 289 config.src_maxburst = 1; 290 dmaengine_slave_config(dma->ch, &config); 291 } else { 292 sdd = container_of((void *)dma, 293 struct s3c64xx_spi_driver_data, tx_dma); 294 config.direction = dma->direction; 295 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 296 config.dst_addr_width = sdd->cur_bpw / 8; 297 config.dst_maxburst = 1; 298 dmaengine_slave_config(dma->ch, &config); 299 } 300 301 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, 302 dma->direction, DMA_PREP_INTERRUPT); 303 304 desc->callback = s3c64xx_spi_dmacb; 305 desc->callback_param = dma; 306 307 dmaengine_submit(desc); 308 dma_async_issue_pending(dma->ch); 309 } 310 311 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) 312 { 313 struct s3c64xx_spi_driver_data *sdd = 314 spi_master_get_devdata(spi->master); 315 316 if (sdd->cntrlr_info->no_cs) 317 return; 318 319 if (enable) { 320 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { 321 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 322 } else { 323 u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL); 324 325 ssel |= (S3C64XX_SPI_SLAVE_AUTO | 326 S3C64XX_SPI_SLAVE_NSC_CNT_2); 327 writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 328 } 329 } else { 330 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 331 writel(S3C64XX_SPI_SLAVE_SIG_INACT, 332 sdd->regs + S3C64XX_SPI_SLAVE_SEL); 333 } 334 } 335 336 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) 337 { 338 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 339 340 if (is_polling(sdd)) 341 return 0; 342 343 spi->dma_rx = sdd->rx_dma.ch; 344 spi->dma_tx = sdd->tx_dma.ch; 345 346 return 0; 347 } 348 349 static bool s3c64xx_spi_can_dma(struct spi_master *master, 350 struct spi_device *spi, 351 struct spi_transfer *xfer) 352 { 353 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 354 355 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; 356 } 357 358 static void s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, 359 struct spi_transfer *xfer, int dma_mode) 360 { 361 void __iomem *regs = sdd->regs; 362 u32 modecfg, chcfg; 363 364 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 365 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 366 367 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 368 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 369 370 if (dma_mode) { 371 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 372 } else { 373 /* Always shift in data in FIFO, even if xfer is Tx only, 374 * this helps setting PCKT_CNT value for generating clocks 375 * as exactly needed. 376 */ 377 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 378 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 379 | S3C64XX_SPI_PACKET_CNT_EN, 380 regs + S3C64XX_SPI_PACKET_CNT); 381 } 382 383 if (xfer->tx_buf != NULL) { 384 sdd->state |= TXBUSY; 385 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 386 if (dma_mode) { 387 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 388 prepare_dma(&sdd->tx_dma, &xfer->tx_sg); 389 } else { 390 switch (sdd->cur_bpw) { 391 case 32: 392 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, 393 xfer->tx_buf, xfer->len / 4); 394 break; 395 case 16: 396 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, 397 xfer->tx_buf, xfer->len / 2); 398 break; 399 default: 400 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, 401 xfer->tx_buf, xfer->len); 402 break; 403 } 404 } 405 } 406 407 if (xfer->rx_buf != NULL) { 408 sdd->state |= RXBUSY; 409 410 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL 411 && !(sdd->cur_mode & SPI_CPHA)) 412 chcfg |= S3C64XX_SPI_CH_HS_EN; 413 414 if (dma_mode) { 415 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 416 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 417 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 418 | S3C64XX_SPI_PACKET_CNT_EN, 419 regs + S3C64XX_SPI_PACKET_CNT); 420 prepare_dma(&sdd->rx_dma, &xfer->rx_sg); 421 } 422 } 423 424 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 425 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 426 } 427 428 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 429 int timeout_ms) 430 { 431 void __iomem *regs = sdd->regs; 432 unsigned long val = 1; 433 u32 status; 434 435 /* max fifo depth available */ 436 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; 437 438 if (timeout_ms) 439 val = msecs_to_loops(timeout_ms); 440 441 do { 442 status = readl(regs + S3C64XX_SPI_STATUS); 443 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); 444 445 /* return the actual received data length */ 446 return RX_FIFO_LVL(status, sdd); 447 } 448 449 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, 450 struct spi_transfer *xfer) 451 { 452 void __iomem *regs = sdd->regs; 453 unsigned long val; 454 u32 status; 455 int ms; 456 457 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 458 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 459 ms += 10; /* some tolerance */ 460 461 val = msecs_to_jiffies(ms) + 10; 462 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 463 464 /* 465 * If the previous xfer was completed within timeout, then 466 * proceed further else return -EIO. 467 * DmaTx returns after simply writing data in the FIFO, 468 * w/o waiting for real transmission on the bus to finish. 469 * DmaRx returns only after Dma read data from FIFO which 470 * needs bus transmission to finish, so we don't worry if 471 * Xfer involved Rx(with or without Tx). 472 */ 473 if (val && !xfer->rx_buf) { 474 val = msecs_to_loops(10); 475 status = readl(regs + S3C64XX_SPI_STATUS); 476 while ((TX_FIFO_LVL(status, sdd) 477 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) 478 && --val) { 479 cpu_relax(); 480 status = readl(regs + S3C64XX_SPI_STATUS); 481 } 482 483 } 484 485 /* If timed out while checking rx/tx status return error */ 486 if (!val) 487 return -EIO; 488 489 return 0; 490 } 491 492 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, 493 struct spi_transfer *xfer) 494 { 495 void __iomem *regs = sdd->regs; 496 unsigned long val; 497 u32 status; 498 int loops; 499 u32 cpy_len; 500 u8 *buf; 501 int ms; 502 503 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 504 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 505 ms += 10; /* some tolerance */ 506 507 val = msecs_to_loops(ms); 508 do { 509 status = readl(regs + S3C64XX_SPI_STATUS); 510 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 511 512 if (!val) 513 return -EIO; 514 515 /* If it was only Tx */ 516 if (!xfer->rx_buf) { 517 sdd->state &= ~TXBUSY; 518 return 0; 519 } 520 521 /* 522 * If the receive length is bigger than the controller fifo 523 * size, calculate the loops and read the fifo as many times. 524 * loops = length / max fifo size (calculated by using the 525 * fifo mask). 526 * For any size less than the fifo size the below code is 527 * executed atleast once. 528 */ 529 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); 530 buf = xfer->rx_buf; 531 do { 532 /* wait for data to be received in the fifo */ 533 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, 534 (loops ? ms : 0)); 535 536 switch (sdd->cur_bpw) { 537 case 32: 538 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 539 buf, cpy_len / 4); 540 break; 541 case 16: 542 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 543 buf, cpy_len / 2); 544 break; 545 default: 546 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 547 buf, cpy_len); 548 break; 549 } 550 551 buf = buf + cpy_len; 552 } while (loops--); 553 sdd->state &= ~RXBUSY; 554 555 return 0; 556 } 557 558 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 559 { 560 void __iomem *regs = sdd->regs; 561 u32 val; 562 563 /* Disable Clock */ 564 if (!sdd->port_conf->clk_from_cmu) { 565 val = readl(regs + S3C64XX_SPI_CLK_CFG); 566 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 567 writel(val, regs + S3C64XX_SPI_CLK_CFG); 568 } 569 570 /* Set Polarity and Phase */ 571 val = readl(regs + S3C64XX_SPI_CH_CFG); 572 val &= ~(S3C64XX_SPI_CH_SLAVE | 573 S3C64XX_SPI_CPOL_L | 574 S3C64XX_SPI_CPHA_B); 575 576 if (sdd->cur_mode & SPI_CPOL) 577 val |= S3C64XX_SPI_CPOL_L; 578 579 if (sdd->cur_mode & SPI_CPHA) 580 val |= S3C64XX_SPI_CPHA_B; 581 582 writel(val, regs + S3C64XX_SPI_CH_CFG); 583 584 /* Set Channel & DMA Mode */ 585 val = readl(regs + S3C64XX_SPI_MODE_CFG); 586 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 587 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 588 589 switch (sdd->cur_bpw) { 590 case 32: 591 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 592 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 593 break; 594 case 16: 595 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 596 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 597 break; 598 default: 599 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 600 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 601 break; 602 } 603 604 writel(val, regs + S3C64XX_SPI_MODE_CFG); 605 606 if (sdd->port_conf->clk_from_cmu) { 607 /* The src_clk clock is divided internally by 2 */ 608 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); 609 } else { 610 /* Configure Clock */ 611 val = readl(regs + S3C64XX_SPI_CLK_CFG); 612 val &= ~S3C64XX_SPI_PSR_MASK; 613 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) 614 & S3C64XX_SPI_PSR_MASK); 615 writel(val, regs + S3C64XX_SPI_CLK_CFG); 616 617 /* Enable Clock */ 618 val = readl(regs + S3C64XX_SPI_CLK_CFG); 619 val |= S3C64XX_SPI_ENCLK_ENABLE; 620 writel(val, regs + S3C64XX_SPI_CLK_CFG); 621 } 622 } 623 624 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 625 626 static int s3c64xx_spi_prepare_message(struct spi_master *master, 627 struct spi_message *msg) 628 { 629 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 630 struct spi_device *spi = msg->spi; 631 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 632 633 /* Configure feedback delay */ 634 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 635 636 return 0; 637 } 638 639 static int s3c64xx_spi_transfer_one(struct spi_master *master, 640 struct spi_device *spi, 641 struct spi_transfer *xfer) 642 { 643 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 644 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1; 645 const void *tx_buf = NULL; 646 void *rx_buf = NULL; 647 int target_len = 0, origin_len = 0; 648 int use_dma = 0; 649 int status; 650 u32 speed; 651 u8 bpw; 652 unsigned long flags; 653 654 reinit_completion(&sdd->xfer_completion); 655 656 /* Only BPW and Speed may change across transfers */ 657 bpw = xfer->bits_per_word; 658 speed = xfer->speed_hz; 659 660 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 661 sdd->cur_bpw = bpw; 662 sdd->cur_speed = speed; 663 sdd->cur_mode = spi->mode; 664 s3c64xx_spi_config(sdd); 665 } 666 667 if (!is_polling(sdd) && (xfer->len > fifo_len) && 668 sdd->rx_dma.ch && sdd->tx_dma.ch) { 669 use_dma = 1; 670 671 } else if (is_polling(sdd) && xfer->len > fifo_len) { 672 tx_buf = xfer->tx_buf; 673 rx_buf = xfer->rx_buf; 674 origin_len = xfer->len; 675 676 target_len = xfer->len; 677 if (xfer->len > fifo_len) 678 xfer->len = fifo_len; 679 } 680 681 do { 682 spin_lock_irqsave(&sdd->lock, flags); 683 684 /* Pending only which is to be done */ 685 sdd->state &= ~RXBUSY; 686 sdd->state &= ~TXBUSY; 687 688 s3c64xx_enable_datapath(sdd, xfer, use_dma); 689 690 /* Start the signals */ 691 s3c64xx_spi_set_cs(spi, true); 692 693 spin_unlock_irqrestore(&sdd->lock, flags); 694 695 if (use_dma) 696 status = s3c64xx_wait_for_dma(sdd, xfer); 697 else 698 status = s3c64xx_wait_for_pio(sdd, xfer); 699 700 if (status) { 701 dev_err(&spi->dev, 702 "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", 703 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 704 (sdd->state & RXBUSY) ? 'f' : 'p', 705 (sdd->state & TXBUSY) ? 'f' : 'p', 706 xfer->len); 707 708 if (use_dma) { 709 if (xfer->tx_buf && (sdd->state & TXBUSY)) 710 dmaengine_terminate_all(sdd->tx_dma.ch); 711 if (xfer->rx_buf && (sdd->state & RXBUSY)) 712 dmaengine_terminate_all(sdd->rx_dma.ch); 713 } 714 } else { 715 s3c64xx_flush_fifo(sdd); 716 } 717 if (target_len > 0) { 718 target_len -= xfer->len; 719 720 if (xfer->tx_buf) 721 xfer->tx_buf += xfer->len; 722 723 if (xfer->rx_buf) 724 xfer->rx_buf += xfer->len; 725 726 if (target_len > fifo_len) 727 xfer->len = fifo_len; 728 else 729 xfer->len = target_len; 730 } 731 } while (target_len > 0); 732 733 if (origin_len) { 734 /* Restore original xfer buffers and length */ 735 xfer->tx_buf = tx_buf; 736 xfer->rx_buf = rx_buf; 737 xfer->len = origin_len; 738 } 739 740 return status; 741 } 742 743 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( 744 struct spi_device *spi) 745 { 746 struct s3c64xx_spi_csinfo *cs; 747 struct device_node *slave_np, *data_np = NULL; 748 u32 fb_delay = 0; 749 750 slave_np = spi->dev.of_node; 751 if (!slave_np) { 752 dev_err(&spi->dev, "device node not found\n"); 753 return ERR_PTR(-EINVAL); 754 } 755 756 data_np = of_get_child_by_name(slave_np, "controller-data"); 757 if (!data_np) { 758 dev_err(&spi->dev, "child node 'controller-data' not found\n"); 759 return ERR_PTR(-EINVAL); 760 } 761 762 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 763 if (!cs) { 764 of_node_put(data_np); 765 return ERR_PTR(-ENOMEM); 766 } 767 768 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 769 cs->fb_delay = fb_delay; 770 of_node_put(data_np); 771 return cs; 772 } 773 774 /* 775 * Here we only check the validity of requested configuration 776 * and save the configuration in a local data-structure. 777 * The controller is actually configured only just before we 778 * get a message to transfer. 779 */ 780 static int s3c64xx_spi_setup(struct spi_device *spi) 781 { 782 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 783 struct s3c64xx_spi_driver_data *sdd; 784 int err; 785 786 sdd = spi_master_get_devdata(spi->master); 787 if (spi->dev.of_node) { 788 cs = s3c64xx_get_slave_ctrldata(spi); 789 spi->controller_data = cs; 790 } else if (cs) { 791 /* On non-DT platforms the SPI core will set spi->cs_gpio 792 * to -ENOENT. The GPIO pin used to drive the chip select 793 * is defined by using platform data so spi->cs_gpio value 794 * has to be override to have the proper GPIO pin number. 795 */ 796 spi->cs_gpio = cs->line; 797 } 798 799 if (IS_ERR_OR_NULL(cs)) { 800 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); 801 return -ENODEV; 802 } 803 804 if (!spi_get_ctldata(spi)) { 805 if (gpio_is_valid(spi->cs_gpio)) { 806 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, 807 dev_name(&spi->dev)); 808 if (err) { 809 dev_err(&spi->dev, 810 "Failed to get /CS gpio [%d]: %d\n", 811 spi->cs_gpio, err); 812 goto err_gpio_req; 813 } 814 } 815 816 spi_set_ctldata(spi, cs); 817 } 818 819 pm_runtime_get_sync(&sdd->pdev->dev); 820 821 /* Check if we can provide the requested rate */ 822 if (!sdd->port_conf->clk_from_cmu) { 823 u32 psr, speed; 824 825 /* Max possible */ 826 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); 827 828 if (spi->max_speed_hz > speed) 829 spi->max_speed_hz = speed; 830 831 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; 832 psr &= S3C64XX_SPI_PSR_MASK; 833 if (psr == S3C64XX_SPI_PSR_MASK) 834 psr--; 835 836 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 837 if (spi->max_speed_hz < speed) { 838 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 839 psr++; 840 } else { 841 err = -EINVAL; 842 goto setup_exit; 843 } 844 } 845 846 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 847 if (spi->max_speed_hz >= speed) { 848 spi->max_speed_hz = speed; 849 } else { 850 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", 851 spi->max_speed_hz); 852 err = -EINVAL; 853 goto setup_exit; 854 } 855 } 856 857 pm_runtime_mark_last_busy(&sdd->pdev->dev); 858 pm_runtime_put_autosuspend(&sdd->pdev->dev); 859 s3c64xx_spi_set_cs(spi, false); 860 861 return 0; 862 863 setup_exit: 864 pm_runtime_mark_last_busy(&sdd->pdev->dev); 865 pm_runtime_put_autosuspend(&sdd->pdev->dev); 866 /* setup() returns with device de-selected */ 867 s3c64xx_spi_set_cs(spi, false); 868 869 if (gpio_is_valid(spi->cs_gpio)) 870 gpio_free(spi->cs_gpio); 871 spi_set_ctldata(spi, NULL); 872 873 err_gpio_req: 874 if (spi->dev.of_node) 875 kfree(cs); 876 877 return err; 878 } 879 880 static void s3c64xx_spi_cleanup(struct spi_device *spi) 881 { 882 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 883 884 if (gpio_is_valid(spi->cs_gpio)) { 885 gpio_free(spi->cs_gpio); 886 if (spi->dev.of_node) 887 kfree(cs); 888 else { 889 /* On non-DT platforms, the SPI core sets 890 * spi->cs_gpio to -ENOENT and .setup() 891 * overrides it with the GPIO pin value 892 * passed using platform data. 893 */ 894 spi->cs_gpio = -ENOENT; 895 } 896 } 897 898 spi_set_ctldata(spi, NULL); 899 } 900 901 static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 902 { 903 struct s3c64xx_spi_driver_data *sdd = data; 904 struct spi_master *spi = sdd->master; 905 unsigned int val, clr = 0; 906 907 val = readl(sdd->regs + S3C64XX_SPI_STATUS); 908 909 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { 910 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; 911 dev_err(&spi->dev, "RX overrun\n"); 912 } 913 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { 914 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; 915 dev_err(&spi->dev, "RX underrun\n"); 916 } 917 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { 918 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; 919 dev_err(&spi->dev, "TX overrun\n"); 920 } 921 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { 922 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 923 dev_err(&spi->dev, "TX underrun\n"); 924 } 925 926 /* Clear the pending irq by setting and then clearing it */ 927 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); 928 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); 929 930 return IRQ_HANDLED; 931 } 932 933 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) 934 { 935 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 936 void __iomem *regs = sdd->regs; 937 unsigned int val; 938 939 sdd->cur_speed = 0; 940 941 if (sci->no_cs) 942 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 943 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 944 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 945 946 /* Disable Interrupts - we use Polling if not DMA mode */ 947 writel(0, regs + S3C64XX_SPI_INT_EN); 948 949 if (!sdd->port_conf->clk_from_cmu) 950 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 951 regs + S3C64XX_SPI_CLK_CFG); 952 writel(0, regs + S3C64XX_SPI_MODE_CFG); 953 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 954 955 /* Clear any irq pending bits, should set and clear the bits */ 956 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | 957 S3C64XX_SPI_PND_RX_UNDERRUN_CLR | 958 S3C64XX_SPI_PND_TX_OVERRUN_CLR | 959 S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 960 writel(val, regs + S3C64XX_SPI_PENDING_CLR); 961 writel(0, regs + S3C64XX_SPI_PENDING_CLR); 962 963 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 964 965 val = readl(regs + S3C64XX_SPI_MODE_CFG); 966 val &= ~S3C64XX_SPI_MODE_4BURST; 967 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 968 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 969 writel(val, regs + S3C64XX_SPI_MODE_CFG); 970 971 s3c64xx_flush_fifo(sdd); 972 } 973 974 #ifdef CONFIG_OF 975 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 976 { 977 struct s3c64xx_spi_info *sci; 978 u32 temp; 979 980 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); 981 if (!sci) 982 return ERR_PTR(-ENOMEM); 983 984 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { 985 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); 986 sci->src_clk_nr = 0; 987 } else { 988 sci->src_clk_nr = temp; 989 } 990 991 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { 992 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); 993 sci->num_cs = 1; 994 } else { 995 sci->num_cs = temp; 996 } 997 998 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); 999 1000 return sci; 1001 } 1002 #else 1003 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1004 { 1005 return dev_get_platdata(dev); 1006 } 1007 #endif 1008 1009 static const struct of_device_id s3c64xx_spi_dt_match[]; 1010 1011 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( 1012 struct platform_device *pdev) 1013 { 1014 #ifdef CONFIG_OF 1015 if (pdev->dev.of_node) { 1016 const struct of_device_id *match; 1017 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); 1018 return (struct s3c64xx_spi_port_config *)match->data; 1019 } 1020 #endif 1021 return (struct s3c64xx_spi_port_config *) 1022 platform_get_device_id(pdev)->driver_data; 1023 } 1024 1025 static int s3c64xx_spi_probe(struct platform_device *pdev) 1026 { 1027 struct resource *mem_res; 1028 struct s3c64xx_spi_driver_data *sdd; 1029 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); 1030 struct spi_master *master; 1031 int ret, irq; 1032 char clk_name[16]; 1033 1034 if (!sci && pdev->dev.of_node) { 1035 sci = s3c64xx_spi_parse_dt(&pdev->dev); 1036 if (IS_ERR(sci)) 1037 return PTR_ERR(sci); 1038 } 1039 1040 if (!sci) { 1041 dev_err(&pdev->dev, "platform_data missing!\n"); 1042 return -ENODEV; 1043 } 1044 1045 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1046 if (mem_res == NULL) { 1047 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); 1048 return -ENXIO; 1049 } 1050 1051 irq = platform_get_irq(pdev, 0); 1052 if (irq < 0) { 1053 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); 1054 return irq; 1055 } 1056 1057 master = spi_alloc_master(&pdev->dev, 1058 sizeof(struct s3c64xx_spi_driver_data)); 1059 if (master == NULL) { 1060 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 1061 return -ENOMEM; 1062 } 1063 1064 platform_set_drvdata(pdev, master); 1065 1066 sdd = spi_master_get_devdata(master); 1067 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); 1068 sdd->master = master; 1069 sdd->cntrlr_info = sci; 1070 sdd->pdev = pdev; 1071 sdd->sfr_start = mem_res->start; 1072 if (pdev->dev.of_node) { 1073 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1074 if (ret < 0) { 1075 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 1076 ret); 1077 goto err_deref_master; 1078 } 1079 sdd->port_id = ret; 1080 } else { 1081 sdd->port_id = pdev->id; 1082 } 1083 1084 sdd->cur_bpw = 8; 1085 1086 sdd->tx_dma.direction = DMA_MEM_TO_DEV; 1087 sdd->rx_dma.direction = DMA_DEV_TO_MEM; 1088 1089 master->dev.of_node = pdev->dev.of_node; 1090 master->bus_num = sdd->port_id; 1091 master->setup = s3c64xx_spi_setup; 1092 master->cleanup = s3c64xx_spi_cleanup; 1093 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1094 master->prepare_message = s3c64xx_spi_prepare_message; 1095 master->transfer_one = s3c64xx_spi_transfer_one; 1096 master->num_chipselect = sci->num_cs; 1097 master->dma_alignment = 8; 1098 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1099 SPI_BPW_MASK(8); 1100 /* the spi->mode bits understood by this driver: */ 1101 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1102 master->auto_runtime_pm = true; 1103 if (!is_polling(sdd)) 1104 master->can_dma = s3c64xx_spi_can_dma; 1105 1106 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); 1107 if (IS_ERR(sdd->regs)) { 1108 ret = PTR_ERR(sdd->regs); 1109 goto err_deref_master; 1110 } 1111 1112 if (sci->cfg_gpio && sci->cfg_gpio()) { 1113 dev_err(&pdev->dev, "Unable to config gpio\n"); 1114 ret = -EBUSY; 1115 goto err_deref_master; 1116 } 1117 1118 /* Setup clocks */ 1119 sdd->clk = devm_clk_get(&pdev->dev, "spi"); 1120 if (IS_ERR(sdd->clk)) { 1121 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); 1122 ret = PTR_ERR(sdd->clk); 1123 goto err_deref_master; 1124 } 1125 1126 ret = clk_prepare_enable(sdd->clk); 1127 if (ret) { 1128 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); 1129 goto err_deref_master; 1130 } 1131 1132 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1133 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); 1134 if (IS_ERR(sdd->src_clk)) { 1135 dev_err(&pdev->dev, 1136 "Unable to acquire clock '%s'\n", clk_name); 1137 ret = PTR_ERR(sdd->src_clk); 1138 goto err_disable_clk; 1139 } 1140 1141 ret = clk_prepare_enable(sdd->src_clk); 1142 if (ret) { 1143 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); 1144 goto err_disable_clk; 1145 } 1146 1147 if (sdd->port_conf->clk_ioclk) { 1148 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk"); 1149 if (IS_ERR(sdd->ioclk)) { 1150 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n"); 1151 ret = PTR_ERR(sdd->ioclk); 1152 goto err_disable_src_clk; 1153 } 1154 1155 ret = clk_prepare_enable(sdd->ioclk); 1156 if (ret) { 1157 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n"); 1158 goto err_disable_src_clk; 1159 } 1160 } 1161 1162 if (!is_polling(sdd)) { 1163 /* Acquire DMA channels */ 1164 sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx"); 1165 if (IS_ERR(sdd->rx_dma.ch)) { 1166 dev_err(&pdev->dev, "Failed to get RX DMA channel\n"); 1167 ret = PTR_ERR(sdd->rx_dma.ch); 1168 goto err_disable_io_clk; 1169 } 1170 sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx"); 1171 if (IS_ERR(sdd->tx_dma.ch)) { 1172 dev_err(&pdev->dev, "Failed to get TX DMA channel\n"); 1173 ret = PTR_ERR(sdd->tx_dma.ch); 1174 goto err_release_rx_dma; 1175 } 1176 } 1177 1178 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1179 pm_runtime_use_autosuspend(&pdev->dev); 1180 pm_runtime_set_active(&pdev->dev); 1181 pm_runtime_enable(&pdev->dev); 1182 pm_runtime_get_sync(&pdev->dev); 1183 1184 /* Setup Deufult Mode */ 1185 s3c64xx_spi_hwinit(sdd); 1186 1187 spin_lock_init(&sdd->lock); 1188 init_completion(&sdd->xfer_completion); 1189 1190 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, 1191 "spi-s3c64xx", sdd); 1192 if (ret != 0) { 1193 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", 1194 irq, ret); 1195 goto err_pm_put; 1196 } 1197 1198 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1199 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1200 sdd->regs + S3C64XX_SPI_INT_EN); 1201 1202 ret = devm_spi_register_master(&pdev->dev, master); 1203 if (ret != 0) { 1204 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); 1205 goto err_pm_put; 1206 } 1207 1208 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", 1209 sdd->port_id, master->num_chipselect); 1210 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", 1211 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1); 1212 1213 pm_runtime_mark_last_busy(&pdev->dev); 1214 pm_runtime_put_autosuspend(&pdev->dev); 1215 1216 return 0; 1217 1218 err_pm_put: 1219 pm_runtime_put_noidle(&pdev->dev); 1220 pm_runtime_disable(&pdev->dev); 1221 pm_runtime_set_suspended(&pdev->dev); 1222 1223 if (!is_polling(sdd)) 1224 dma_release_channel(sdd->tx_dma.ch); 1225 err_release_rx_dma: 1226 if (!is_polling(sdd)) 1227 dma_release_channel(sdd->rx_dma.ch); 1228 err_disable_io_clk: 1229 clk_disable_unprepare(sdd->ioclk); 1230 err_disable_src_clk: 1231 clk_disable_unprepare(sdd->src_clk); 1232 err_disable_clk: 1233 clk_disable_unprepare(sdd->clk); 1234 err_deref_master: 1235 spi_master_put(master); 1236 1237 return ret; 1238 } 1239 1240 static int s3c64xx_spi_remove(struct platform_device *pdev) 1241 { 1242 struct spi_master *master = platform_get_drvdata(pdev); 1243 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1244 1245 pm_runtime_get_sync(&pdev->dev); 1246 1247 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1248 1249 if (!is_polling(sdd)) { 1250 dma_release_channel(sdd->rx_dma.ch); 1251 dma_release_channel(sdd->tx_dma.ch); 1252 } 1253 1254 clk_disable_unprepare(sdd->ioclk); 1255 1256 clk_disable_unprepare(sdd->src_clk); 1257 1258 clk_disable_unprepare(sdd->clk); 1259 1260 pm_runtime_put_noidle(&pdev->dev); 1261 pm_runtime_disable(&pdev->dev); 1262 pm_runtime_set_suspended(&pdev->dev); 1263 1264 return 0; 1265 } 1266 1267 #ifdef CONFIG_PM_SLEEP 1268 static int s3c64xx_spi_suspend(struct device *dev) 1269 { 1270 struct spi_master *master = dev_get_drvdata(dev); 1271 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1272 1273 int ret = spi_master_suspend(master); 1274 if (ret) 1275 return ret; 1276 1277 ret = pm_runtime_force_suspend(dev); 1278 if (ret < 0) 1279 return ret; 1280 1281 sdd->cur_speed = 0; /* Output Clock is stopped */ 1282 1283 return 0; 1284 } 1285 1286 static int s3c64xx_spi_resume(struct device *dev) 1287 { 1288 struct spi_master *master = dev_get_drvdata(dev); 1289 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1290 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1291 int ret; 1292 1293 if (sci->cfg_gpio) 1294 sci->cfg_gpio(); 1295 1296 ret = pm_runtime_force_resume(dev); 1297 if (ret < 0) 1298 return ret; 1299 1300 return spi_master_resume(master); 1301 } 1302 #endif /* CONFIG_PM_SLEEP */ 1303 1304 #ifdef CONFIG_PM 1305 static int s3c64xx_spi_runtime_suspend(struct device *dev) 1306 { 1307 struct spi_master *master = dev_get_drvdata(dev); 1308 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1309 1310 clk_disable_unprepare(sdd->clk); 1311 clk_disable_unprepare(sdd->src_clk); 1312 clk_disable_unprepare(sdd->ioclk); 1313 1314 return 0; 1315 } 1316 1317 static int s3c64xx_spi_runtime_resume(struct device *dev) 1318 { 1319 struct spi_master *master = dev_get_drvdata(dev); 1320 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1321 int ret; 1322 1323 if (sdd->port_conf->clk_ioclk) { 1324 ret = clk_prepare_enable(sdd->ioclk); 1325 if (ret != 0) 1326 return ret; 1327 } 1328 1329 ret = clk_prepare_enable(sdd->src_clk); 1330 if (ret != 0) 1331 goto err_disable_ioclk; 1332 1333 ret = clk_prepare_enable(sdd->clk); 1334 if (ret != 0) 1335 goto err_disable_src_clk; 1336 1337 s3c64xx_spi_hwinit(sdd); 1338 1339 return 0; 1340 1341 err_disable_src_clk: 1342 clk_disable_unprepare(sdd->src_clk); 1343 err_disable_ioclk: 1344 clk_disable_unprepare(sdd->ioclk); 1345 1346 return ret; 1347 } 1348 #endif /* CONFIG_PM */ 1349 1350 static const struct dev_pm_ops s3c64xx_spi_pm = { 1351 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) 1352 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, 1353 s3c64xx_spi_runtime_resume, NULL) 1354 }; 1355 1356 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1357 .fifo_lvl_mask = { 0x7f }, 1358 .rx_lvl_offset = 13, 1359 .tx_st_done = 21, 1360 .high_speed = true, 1361 }; 1362 1363 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1364 .fifo_lvl_mask = { 0x7f, 0x7F }, 1365 .rx_lvl_offset = 13, 1366 .tx_st_done = 21, 1367 }; 1368 1369 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1370 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1371 .rx_lvl_offset = 15, 1372 .tx_st_done = 25, 1373 .high_speed = true, 1374 }; 1375 1376 static struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1377 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1378 .rx_lvl_offset = 15, 1379 .tx_st_done = 25, 1380 .high_speed = true, 1381 .clk_from_cmu = true, 1382 }; 1383 1384 static struct s3c64xx_spi_port_config exynos7_spi_port_config = { 1385 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, 1386 .rx_lvl_offset = 15, 1387 .tx_st_done = 25, 1388 .high_speed = true, 1389 .clk_from_cmu = true, 1390 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1391 }; 1392 1393 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = { 1394 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, 1395 .rx_lvl_offset = 15, 1396 .tx_st_done = 25, 1397 .high_speed = true, 1398 .clk_from_cmu = true, 1399 .clk_ioclk = true, 1400 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1401 }; 1402 1403 static const struct platform_device_id s3c64xx_spi_driver_ids[] = { 1404 { 1405 .name = "s3c2443-spi", 1406 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, 1407 }, { 1408 .name = "s3c6410-spi", 1409 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1410 }, 1411 { }, 1412 }; 1413 1414 static const struct of_device_id s3c64xx_spi_dt_match[] = { 1415 { .compatible = "samsung,s3c2443-spi", 1416 .data = (void *)&s3c2443_spi_port_config, 1417 }, 1418 { .compatible = "samsung,s3c6410-spi", 1419 .data = (void *)&s3c6410_spi_port_config, 1420 }, 1421 { .compatible = "samsung,s5pv210-spi", 1422 .data = (void *)&s5pv210_spi_port_config, 1423 }, 1424 { .compatible = "samsung,exynos4210-spi", 1425 .data = (void *)&exynos4_spi_port_config, 1426 }, 1427 { .compatible = "samsung,exynos7-spi", 1428 .data = (void *)&exynos7_spi_port_config, 1429 }, 1430 { .compatible = "samsung,exynos5433-spi", 1431 .data = (void *)&exynos5433_spi_port_config, 1432 }, 1433 { }, 1434 }; 1435 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1436 1437 static struct platform_driver s3c64xx_spi_driver = { 1438 .driver = { 1439 .name = "s3c64xx-spi", 1440 .pm = &s3c64xx_spi_pm, 1441 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), 1442 }, 1443 .probe = s3c64xx_spi_probe, 1444 .remove = s3c64xx_spi_remove, 1445 .id_table = s3c64xx_spi_driver_ids, 1446 }; 1447 MODULE_ALIAS("platform:s3c64xx-spi"); 1448 1449 module_platform_driver(s3c64xx_spi_driver); 1450 1451 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1452 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1453 MODULE_LICENSE("GPL"); 1454