1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2009 Samsung Electronics Co., Ltd. 4 // Jaswinder Singh <jassi.brar@samsung.com> 5 6 #include <linux/init.h> 7 #include <linux/module.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/spi/spi.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 19 #include <linux/platform_data/spi-s3c64xx.h> 20 21 #define MAX_SPI_PORTS 12 22 #define S3C64XX_SPI_QUIRK_POLL (1 << 0) 23 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) 24 #define AUTOSUSPEND_TIMEOUT 2000 25 26 /* Registers and bit-fields */ 27 28 #define S3C64XX_SPI_CH_CFG 0x00 29 #define S3C64XX_SPI_CLK_CFG 0x04 30 #define S3C64XX_SPI_MODE_CFG 0x08 31 #define S3C64XX_SPI_CS_REG 0x0C 32 #define S3C64XX_SPI_INT_EN 0x10 33 #define S3C64XX_SPI_STATUS 0x14 34 #define S3C64XX_SPI_TX_DATA 0x18 35 #define S3C64XX_SPI_RX_DATA 0x1C 36 #define S3C64XX_SPI_PACKET_CNT 0x20 37 #define S3C64XX_SPI_PENDING_CLR 0x24 38 #define S3C64XX_SPI_SWAP_CFG 0x28 39 #define S3C64XX_SPI_FB_CLK 0x2C 40 41 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 42 #define S3C64XX_SPI_CH_SW_RST (1<<5) 43 #define S3C64XX_SPI_CH_SLAVE (1<<4) 44 #define S3C64XX_SPI_CPOL_L (1<<3) 45 #define S3C64XX_SPI_CPHA_B (1<<2) 46 #define S3C64XX_SPI_CH_RXCH_ON (1<<1) 47 #define S3C64XX_SPI_CH_TXCH_ON (1<<0) 48 49 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 50 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 51 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 52 #define S3C64XX_SPI_PSR_MASK 0xff 53 54 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 55 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 56 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 57 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 58 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 59 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 60 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 61 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 62 #define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) 63 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 64 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 65 #define S3C64XX_SPI_MODE_4BURST (1<<0) 66 67 #define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) 68 #define S3C64XX_SPI_CS_AUTO (1<<1) 69 #define S3C64XX_SPI_CS_SIG_INACT (1<<0) 70 71 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 72 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 73 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 74 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 75 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 76 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 77 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 78 79 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 80 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 81 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 82 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 83 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 84 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 85 86 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 87 #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) 88 89 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 90 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 91 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 92 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 93 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 94 95 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 96 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 97 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 98 #define S3C64XX_SPI_SWAP_RX_EN (1<<4) 99 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 100 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 101 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 102 #define S3C64XX_SPI_SWAP_TX_EN (1<<0) 103 104 #define S3C64XX_SPI_FBCLK_MSK (3<<0) 105 106 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) 107 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ 108 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) 109 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) 110 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ 111 FIFO_LVL_MASK(i)) 112 113 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 114 #define S3C64XX_SPI_TRAILCNT_OFF 19 115 116 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT 117 118 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 119 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) 120 121 #define RXBUSY (1<<2) 122 #define TXBUSY (1<<3) 123 124 struct s3c64xx_spi_dma_data { 125 struct dma_chan *ch; 126 dma_cookie_t cookie; 127 enum dma_transfer_direction direction; 128 }; 129 130 /** 131 * struct s3c64xx_spi_port_config - SPI Controller hardware info 132 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. 133 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. 134 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. 135 * @clk_div: Internal clock divider 136 * @quirks: Bitmask of known quirks 137 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. 138 * @clk_from_cmu: True, if the controller does not include a clock mux and 139 * prescaler unit. 140 * @clk_ioclk: True if clock is present on this device 141 * @has_loopback: True if loopback mode can be supported 142 * 143 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but 144 * differ in some aspects such as the size of the fifo and spi bus clock 145 * setup. Such differences are specified to the driver using this structure 146 * which is provided as driver data to the driver. 147 */ 148 struct s3c64xx_spi_port_config { 149 int fifo_lvl_mask[MAX_SPI_PORTS]; 150 int rx_lvl_offset; 151 int tx_st_done; 152 int quirks; 153 int clk_div; 154 bool high_speed; 155 bool clk_from_cmu; 156 bool clk_ioclk; 157 bool has_loopback; 158 }; 159 160 /** 161 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 162 * @clk: Pointer to the spi clock. 163 * @src_clk: Pointer to the clock used to generate SPI signals. 164 * @ioclk: Pointer to the i/o clock between master and slave 165 * @pdev: Pointer to device's platform device data 166 * @master: Pointer to the SPI Protocol master. 167 * @cntrlr_info: Platform specific data for the controller this driver manages. 168 * @lock: Controller specific lock. 169 * @state: Set of FLAGS to indicate status. 170 * @sfr_start: BUS address of SPI controller regs. 171 * @regs: Pointer to ioremap'ed controller registers. 172 * @xfer_completion: To indicate completion of xfer task. 173 * @cur_mode: Stores the active configuration of the controller. 174 * @cur_bpw: Stores the active bits per word settings. 175 * @cur_speed: Current clock speed 176 * @rx_dma: Local receive DMA data (e.g. chan and direction) 177 * @tx_dma: Local transmit DMA data (e.g. chan and direction) 178 * @port_conf: Local SPI port configuartion data 179 * @port_id: Port identification number 180 */ 181 struct s3c64xx_spi_driver_data { 182 void __iomem *regs; 183 struct clk *clk; 184 struct clk *src_clk; 185 struct clk *ioclk; 186 struct platform_device *pdev; 187 struct spi_master *master; 188 struct s3c64xx_spi_info *cntrlr_info; 189 spinlock_t lock; 190 unsigned long sfr_start; 191 struct completion xfer_completion; 192 unsigned state; 193 unsigned cur_mode, cur_bpw; 194 unsigned cur_speed; 195 struct s3c64xx_spi_dma_data rx_dma; 196 struct s3c64xx_spi_dma_data tx_dma; 197 const struct s3c64xx_spi_port_config *port_conf; 198 unsigned int port_id; 199 }; 200 201 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) 202 { 203 void __iomem *regs = sdd->regs; 204 unsigned long loops; 205 u32 val; 206 207 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 208 209 val = readl(regs + S3C64XX_SPI_CH_CFG); 210 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 211 writel(val, regs + S3C64XX_SPI_CH_CFG); 212 213 val = readl(regs + S3C64XX_SPI_CH_CFG); 214 val |= S3C64XX_SPI_CH_SW_RST; 215 val &= ~S3C64XX_SPI_CH_HS_EN; 216 writel(val, regs + S3C64XX_SPI_CH_CFG); 217 218 /* Flush TxFIFO*/ 219 loops = msecs_to_loops(1); 220 do { 221 val = readl(regs + S3C64XX_SPI_STATUS); 222 } while (TX_FIFO_LVL(val, sdd) && loops--); 223 224 if (loops == 0) 225 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 226 227 /* Flush RxFIFO*/ 228 loops = msecs_to_loops(1); 229 do { 230 val = readl(regs + S3C64XX_SPI_STATUS); 231 if (RX_FIFO_LVL(val, sdd)) 232 readl(regs + S3C64XX_SPI_RX_DATA); 233 else 234 break; 235 } while (loops--); 236 237 if (loops == 0) 238 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 239 240 val = readl(regs + S3C64XX_SPI_CH_CFG); 241 val &= ~S3C64XX_SPI_CH_SW_RST; 242 writel(val, regs + S3C64XX_SPI_CH_CFG); 243 244 val = readl(regs + S3C64XX_SPI_MODE_CFG); 245 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 246 writel(val, regs + S3C64XX_SPI_MODE_CFG); 247 } 248 249 static void s3c64xx_spi_dmacb(void *data) 250 { 251 struct s3c64xx_spi_driver_data *sdd; 252 struct s3c64xx_spi_dma_data *dma = data; 253 unsigned long flags; 254 255 if (dma->direction == DMA_DEV_TO_MEM) 256 sdd = container_of(data, 257 struct s3c64xx_spi_driver_data, rx_dma); 258 else 259 sdd = container_of(data, 260 struct s3c64xx_spi_driver_data, tx_dma); 261 262 spin_lock_irqsave(&sdd->lock, flags); 263 264 if (dma->direction == DMA_DEV_TO_MEM) { 265 sdd->state &= ~RXBUSY; 266 if (!(sdd->state & TXBUSY)) 267 complete(&sdd->xfer_completion); 268 } else { 269 sdd->state &= ~TXBUSY; 270 if (!(sdd->state & RXBUSY)) 271 complete(&sdd->xfer_completion); 272 } 273 274 spin_unlock_irqrestore(&sdd->lock, flags); 275 } 276 277 static int prepare_dma(struct s3c64xx_spi_dma_data *dma, 278 struct sg_table *sgt) 279 { 280 struct s3c64xx_spi_driver_data *sdd; 281 struct dma_slave_config config; 282 struct dma_async_tx_descriptor *desc; 283 int ret; 284 285 memset(&config, 0, sizeof(config)); 286 287 if (dma->direction == DMA_DEV_TO_MEM) { 288 sdd = container_of((void *)dma, 289 struct s3c64xx_spi_driver_data, rx_dma); 290 config.direction = dma->direction; 291 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 292 config.src_addr_width = sdd->cur_bpw / 8; 293 config.src_maxburst = 1; 294 dmaengine_slave_config(dma->ch, &config); 295 } else { 296 sdd = container_of((void *)dma, 297 struct s3c64xx_spi_driver_data, tx_dma); 298 config.direction = dma->direction; 299 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 300 config.dst_addr_width = sdd->cur_bpw / 8; 301 config.dst_maxburst = 1; 302 dmaengine_slave_config(dma->ch, &config); 303 } 304 305 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, 306 dma->direction, DMA_PREP_INTERRUPT); 307 if (!desc) { 308 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", 309 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx"); 310 return -ENOMEM; 311 } 312 313 desc->callback = s3c64xx_spi_dmacb; 314 desc->callback_param = dma; 315 316 dma->cookie = dmaengine_submit(desc); 317 ret = dma_submit_error(dma->cookie); 318 if (ret) { 319 dev_err(&sdd->pdev->dev, "DMA submission failed"); 320 return -EIO; 321 } 322 323 dma_async_issue_pending(dma->ch); 324 return 0; 325 } 326 327 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) 328 { 329 struct s3c64xx_spi_driver_data *sdd = 330 spi_master_get_devdata(spi->master); 331 332 if (sdd->cntrlr_info->no_cs) 333 return; 334 335 if (enable) { 336 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { 337 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 338 } else { 339 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); 340 341 ssel |= (S3C64XX_SPI_CS_AUTO | 342 S3C64XX_SPI_CS_NSC_CNT_2); 343 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); 344 } 345 } else { 346 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 347 writel(S3C64XX_SPI_CS_SIG_INACT, 348 sdd->regs + S3C64XX_SPI_CS_REG); 349 } 350 } 351 352 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) 353 { 354 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 355 356 if (is_polling(sdd)) 357 return 0; 358 359 /* Requests DMA channels */ 360 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx"); 361 if (IS_ERR(sdd->rx_dma.ch)) { 362 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n"); 363 sdd->rx_dma.ch = NULL; 364 return 0; 365 } 366 367 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx"); 368 if (IS_ERR(sdd->tx_dma.ch)) { 369 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n"); 370 dma_release_channel(sdd->rx_dma.ch); 371 sdd->tx_dma.ch = NULL; 372 sdd->rx_dma.ch = NULL; 373 return 0; 374 } 375 376 spi->dma_rx = sdd->rx_dma.ch; 377 spi->dma_tx = sdd->tx_dma.ch; 378 379 return 0; 380 } 381 382 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) 383 { 384 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 385 386 if (is_polling(sdd)) 387 return 0; 388 389 /* Releases DMA channels if they are allocated */ 390 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { 391 dma_release_channel(sdd->rx_dma.ch); 392 dma_release_channel(sdd->tx_dma.ch); 393 sdd->rx_dma.ch = NULL; 394 sdd->tx_dma.ch = NULL; 395 } 396 397 return 0; 398 } 399 400 static bool s3c64xx_spi_can_dma(struct spi_master *master, 401 struct spi_device *spi, 402 struct spi_transfer *xfer) 403 { 404 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 405 406 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { 407 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; 408 } else { 409 return false; 410 } 411 412 } 413 414 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, 415 struct spi_transfer *xfer, int dma_mode) 416 { 417 void __iomem *regs = sdd->regs; 418 u32 modecfg, chcfg; 419 int ret = 0; 420 421 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 422 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 423 424 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 425 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 426 427 if (dma_mode) { 428 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 429 } else { 430 /* Always shift in data in FIFO, even if xfer is Tx only, 431 * this helps setting PCKT_CNT value for generating clocks 432 * as exactly needed. 433 */ 434 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 435 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 436 | S3C64XX_SPI_PACKET_CNT_EN, 437 regs + S3C64XX_SPI_PACKET_CNT); 438 } 439 440 if (xfer->tx_buf != NULL) { 441 sdd->state |= TXBUSY; 442 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 443 if (dma_mode) { 444 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 445 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); 446 } else { 447 switch (sdd->cur_bpw) { 448 case 32: 449 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, 450 xfer->tx_buf, xfer->len / 4); 451 break; 452 case 16: 453 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, 454 xfer->tx_buf, xfer->len / 2); 455 break; 456 default: 457 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, 458 xfer->tx_buf, xfer->len); 459 break; 460 } 461 } 462 } 463 464 if (xfer->rx_buf != NULL) { 465 sdd->state |= RXBUSY; 466 467 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL 468 && !(sdd->cur_mode & SPI_CPHA)) 469 chcfg |= S3C64XX_SPI_CH_HS_EN; 470 471 if (dma_mode) { 472 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 473 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 474 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 475 | S3C64XX_SPI_PACKET_CNT_EN, 476 regs + S3C64XX_SPI_PACKET_CNT); 477 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg); 478 } 479 } 480 481 if (ret) 482 return ret; 483 484 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 485 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 486 487 return 0; 488 } 489 490 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 491 int timeout_ms) 492 { 493 void __iomem *regs = sdd->regs; 494 unsigned long val = 1; 495 u32 status; 496 497 /* max fifo depth available */ 498 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; 499 500 if (timeout_ms) 501 val = msecs_to_loops(timeout_ms); 502 503 do { 504 status = readl(regs + S3C64XX_SPI_STATUS); 505 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); 506 507 /* return the actual received data length */ 508 return RX_FIFO_LVL(status, sdd); 509 } 510 511 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, 512 struct spi_transfer *xfer) 513 { 514 void __iomem *regs = sdd->regs; 515 unsigned long val; 516 u32 status; 517 int ms; 518 519 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 520 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 521 ms += 30; /* some tolerance */ 522 ms = max(ms, 100); /* minimum timeout */ 523 524 val = msecs_to_jiffies(ms) + 10; 525 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 526 527 /* 528 * If the previous xfer was completed within timeout, then 529 * proceed further else return -EIO. 530 * DmaTx returns after simply writing data in the FIFO, 531 * w/o waiting for real transmission on the bus to finish. 532 * DmaRx returns only after Dma read data from FIFO which 533 * needs bus transmission to finish, so we don't worry if 534 * Xfer involved Rx(with or without Tx). 535 */ 536 if (val && !xfer->rx_buf) { 537 val = msecs_to_loops(10); 538 status = readl(regs + S3C64XX_SPI_STATUS); 539 while ((TX_FIFO_LVL(status, sdd) 540 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) 541 && --val) { 542 cpu_relax(); 543 status = readl(regs + S3C64XX_SPI_STATUS); 544 } 545 546 } 547 548 /* If timed out while checking rx/tx status return error */ 549 if (!val) 550 return -EIO; 551 552 return 0; 553 } 554 555 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, 556 struct spi_transfer *xfer) 557 { 558 void __iomem *regs = sdd->regs; 559 unsigned long val; 560 u32 status; 561 int loops; 562 u32 cpy_len; 563 u8 *buf; 564 int ms; 565 566 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 567 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 568 ms += 10; /* some tolerance */ 569 570 val = msecs_to_loops(ms); 571 do { 572 status = readl(regs + S3C64XX_SPI_STATUS); 573 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 574 575 if (!val) 576 return -EIO; 577 578 /* If it was only Tx */ 579 if (!xfer->rx_buf) { 580 sdd->state &= ~TXBUSY; 581 return 0; 582 } 583 584 /* 585 * If the receive length is bigger than the controller fifo 586 * size, calculate the loops and read the fifo as many times. 587 * loops = length / max fifo size (calculated by using the 588 * fifo mask). 589 * For any size less than the fifo size the below code is 590 * executed atleast once. 591 */ 592 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); 593 buf = xfer->rx_buf; 594 do { 595 /* wait for data to be received in the fifo */ 596 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, 597 (loops ? ms : 0)); 598 599 switch (sdd->cur_bpw) { 600 case 32: 601 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 602 buf, cpy_len / 4); 603 break; 604 case 16: 605 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 606 buf, cpy_len / 2); 607 break; 608 default: 609 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 610 buf, cpy_len); 611 break; 612 } 613 614 buf = buf + cpy_len; 615 } while (loops--); 616 sdd->state &= ~RXBUSY; 617 618 return 0; 619 } 620 621 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 622 { 623 void __iomem *regs = sdd->regs; 624 int ret; 625 u32 val; 626 int div = sdd->port_conf->clk_div; 627 628 /* Disable Clock */ 629 if (!sdd->port_conf->clk_from_cmu) { 630 val = readl(regs + S3C64XX_SPI_CLK_CFG); 631 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 632 writel(val, regs + S3C64XX_SPI_CLK_CFG); 633 } 634 635 /* Set Polarity and Phase */ 636 val = readl(regs + S3C64XX_SPI_CH_CFG); 637 val &= ~(S3C64XX_SPI_CH_SLAVE | 638 S3C64XX_SPI_CPOL_L | 639 S3C64XX_SPI_CPHA_B); 640 641 if (sdd->cur_mode & SPI_CPOL) 642 val |= S3C64XX_SPI_CPOL_L; 643 644 if (sdd->cur_mode & SPI_CPHA) 645 val |= S3C64XX_SPI_CPHA_B; 646 647 writel(val, regs + S3C64XX_SPI_CH_CFG); 648 649 /* Set Channel & DMA Mode */ 650 val = readl(regs + S3C64XX_SPI_MODE_CFG); 651 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 652 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 653 654 switch (sdd->cur_bpw) { 655 case 32: 656 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 657 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 658 break; 659 case 16: 660 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 661 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 662 break; 663 default: 664 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 665 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 666 break; 667 } 668 669 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) 670 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK; 671 672 writel(val, regs + S3C64XX_SPI_MODE_CFG); 673 674 if (sdd->port_conf->clk_from_cmu) { 675 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); 676 if (ret) 677 return ret; 678 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; 679 } else { 680 /* Configure Clock */ 681 val = readl(regs + S3C64XX_SPI_CLK_CFG); 682 val &= ~S3C64XX_SPI_PSR_MASK; 683 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) 684 & S3C64XX_SPI_PSR_MASK); 685 writel(val, regs + S3C64XX_SPI_CLK_CFG); 686 687 /* Enable Clock */ 688 val = readl(regs + S3C64XX_SPI_CLK_CFG); 689 val |= S3C64XX_SPI_ENCLK_ENABLE; 690 writel(val, regs + S3C64XX_SPI_CLK_CFG); 691 } 692 693 return 0; 694 } 695 696 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 697 698 static int s3c64xx_spi_prepare_message(struct spi_master *master, 699 struct spi_message *msg) 700 { 701 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 702 struct spi_device *spi = msg->spi; 703 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 704 705 /* Configure feedback delay */ 706 if (!cs) 707 /* No delay if not defined */ 708 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK); 709 else 710 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 711 712 return 0; 713 } 714 715 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi) 716 { 717 struct spi_controller *ctlr = spi->controller; 718 719 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX; 720 } 721 722 static int s3c64xx_spi_transfer_one(struct spi_master *master, 723 struct spi_device *spi, 724 struct spi_transfer *xfer) 725 { 726 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 727 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1; 728 const void *tx_buf = NULL; 729 void *rx_buf = NULL; 730 int target_len = 0, origin_len = 0; 731 int use_dma = 0; 732 int status; 733 u32 speed; 734 u8 bpw; 735 unsigned long flags; 736 737 reinit_completion(&sdd->xfer_completion); 738 739 /* Only BPW and Speed may change across transfers */ 740 bpw = xfer->bits_per_word; 741 speed = xfer->speed_hz; 742 743 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 744 sdd->cur_bpw = bpw; 745 sdd->cur_speed = speed; 746 sdd->cur_mode = spi->mode; 747 status = s3c64xx_spi_config(sdd); 748 if (status) 749 return status; 750 } 751 752 if (!is_polling(sdd) && (xfer->len > fifo_len) && 753 sdd->rx_dma.ch && sdd->tx_dma.ch) { 754 use_dma = 1; 755 756 } else if (xfer->len > fifo_len) { 757 tx_buf = xfer->tx_buf; 758 rx_buf = xfer->rx_buf; 759 origin_len = xfer->len; 760 761 target_len = xfer->len; 762 if (xfer->len > fifo_len) 763 xfer->len = fifo_len; 764 } 765 766 do { 767 spin_lock_irqsave(&sdd->lock, flags); 768 769 /* Pending only which is to be done */ 770 sdd->state &= ~RXBUSY; 771 sdd->state &= ~TXBUSY; 772 773 /* Start the signals */ 774 s3c64xx_spi_set_cs(spi, true); 775 776 status = s3c64xx_enable_datapath(sdd, xfer, use_dma); 777 778 spin_unlock_irqrestore(&sdd->lock, flags); 779 780 if (status) { 781 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status); 782 break; 783 } 784 785 if (use_dma) 786 status = s3c64xx_wait_for_dma(sdd, xfer); 787 else 788 status = s3c64xx_wait_for_pio(sdd, xfer); 789 790 if (status) { 791 dev_err(&spi->dev, 792 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n", 793 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 794 (sdd->state & RXBUSY) ? 'f' : 'p', 795 (sdd->state & TXBUSY) ? 'f' : 'p', 796 xfer->len, use_dma ? 1 : 0, status); 797 798 if (use_dma) { 799 struct dma_tx_state s; 800 801 if (xfer->tx_buf && (sdd->state & TXBUSY)) { 802 dmaengine_pause(sdd->tx_dma.ch); 803 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); 804 dmaengine_terminate_all(sdd->tx_dma.ch); 805 dev_err(&spi->dev, "TX residue: %d\n", s.residue); 806 807 } 808 if (xfer->rx_buf && (sdd->state & RXBUSY)) { 809 dmaengine_pause(sdd->rx_dma.ch); 810 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); 811 dmaengine_terminate_all(sdd->rx_dma.ch); 812 dev_err(&spi->dev, "RX residue: %d\n", s.residue); 813 } 814 } 815 } else { 816 s3c64xx_flush_fifo(sdd); 817 } 818 if (target_len > 0) { 819 target_len -= xfer->len; 820 821 if (xfer->tx_buf) 822 xfer->tx_buf += xfer->len; 823 824 if (xfer->rx_buf) 825 xfer->rx_buf += xfer->len; 826 827 if (target_len > fifo_len) 828 xfer->len = fifo_len; 829 else 830 xfer->len = target_len; 831 } 832 } while (target_len > 0); 833 834 if (origin_len) { 835 /* Restore original xfer buffers and length */ 836 xfer->tx_buf = tx_buf; 837 xfer->rx_buf = rx_buf; 838 xfer->len = origin_len; 839 } 840 841 return status; 842 } 843 844 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( 845 struct spi_device *spi) 846 { 847 struct s3c64xx_spi_csinfo *cs; 848 struct device_node *slave_np, *data_np = NULL; 849 u32 fb_delay = 0; 850 851 slave_np = spi->dev.of_node; 852 if (!slave_np) { 853 dev_err(&spi->dev, "device node not found\n"); 854 return ERR_PTR(-EINVAL); 855 } 856 857 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 858 if (!cs) 859 return ERR_PTR(-ENOMEM); 860 861 data_np = of_get_child_by_name(slave_np, "controller-data"); 862 if (!data_np) { 863 dev_info(&spi->dev, "feedback delay set to default (0)\n"); 864 return cs; 865 } 866 867 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 868 cs->fb_delay = fb_delay; 869 of_node_put(data_np); 870 return cs; 871 } 872 873 /* 874 * Here we only check the validity of requested configuration 875 * and save the configuration in a local data-structure. 876 * The controller is actually configured only just before we 877 * get a message to transfer. 878 */ 879 static int s3c64xx_spi_setup(struct spi_device *spi) 880 { 881 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 882 struct s3c64xx_spi_driver_data *sdd; 883 int err; 884 int div; 885 886 sdd = spi_master_get_devdata(spi->master); 887 if (spi->dev.of_node) { 888 cs = s3c64xx_get_slave_ctrldata(spi); 889 spi->controller_data = cs; 890 } 891 892 /* NULL is fine, we just avoid using the FB delay (=0) */ 893 if (IS_ERR(cs)) { 894 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0)); 895 return -ENODEV; 896 } 897 898 if (!spi_get_ctldata(spi)) 899 spi_set_ctldata(spi, cs); 900 901 pm_runtime_get_sync(&sdd->pdev->dev); 902 903 div = sdd->port_conf->clk_div; 904 905 /* Check if we can provide the requested rate */ 906 if (!sdd->port_conf->clk_from_cmu) { 907 u32 psr, speed; 908 909 /* Max possible */ 910 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); 911 912 if (spi->max_speed_hz > speed) 913 spi->max_speed_hz = speed; 914 915 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; 916 psr &= S3C64XX_SPI_PSR_MASK; 917 if (psr == S3C64XX_SPI_PSR_MASK) 918 psr--; 919 920 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 921 if (spi->max_speed_hz < speed) { 922 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 923 psr++; 924 } else { 925 err = -EINVAL; 926 goto setup_exit; 927 } 928 } 929 930 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 931 if (spi->max_speed_hz >= speed) { 932 spi->max_speed_hz = speed; 933 } else { 934 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", 935 spi->max_speed_hz); 936 err = -EINVAL; 937 goto setup_exit; 938 } 939 } 940 941 pm_runtime_mark_last_busy(&sdd->pdev->dev); 942 pm_runtime_put_autosuspend(&sdd->pdev->dev); 943 s3c64xx_spi_set_cs(spi, false); 944 945 return 0; 946 947 setup_exit: 948 pm_runtime_mark_last_busy(&sdd->pdev->dev); 949 pm_runtime_put_autosuspend(&sdd->pdev->dev); 950 /* setup() returns with device de-selected */ 951 s3c64xx_spi_set_cs(spi, false); 952 953 spi_set_ctldata(spi, NULL); 954 955 /* This was dynamically allocated on the DT path */ 956 if (spi->dev.of_node) 957 kfree(cs); 958 959 return err; 960 } 961 962 static void s3c64xx_spi_cleanup(struct spi_device *spi) 963 { 964 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 965 966 /* This was dynamically allocated on the DT path */ 967 if (spi->dev.of_node) 968 kfree(cs); 969 970 spi_set_ctldata(spi, NULL); 971 } 972 973 static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 974 { 975 struct s3c64xx_spi_driver_data *sdd = data; 976 struct spi_master *spi = sdd->master; 977 unsigned int val, clr = 0; 978 979 val = readl(sdd->regs + S3C64XX_SPI_STATUS); 980 981 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { 982 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; 983 dev_err(&spi->dev, "RX overrun\n"); 984 } 985 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { 986 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; 987 dev_err(&spi->dev, "RX underrun\n"); 988 } 989 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { 990 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; 991 dev_err(&spi->dev, "TX overrun\n"); 992 } 993 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { 994 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 995 dev_err(&spi->dev, "TX underrun\n"); 996 } 997 998 /* Clear the pending irq by setting and then clearing it */ 999 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); 1000 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); 1001 1002 return IRQ_HANDLED; 1003 } 1004 1005 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) 1006 { 1007 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1008 void __iomem *regs = sdd->regs; 1009 unsigned int val; 1010 1011 sdd->cur_speed = 0; 1012 1013 if (sci->no_cs) 1014 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 1015 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 1016 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); 1017 1018 /* Disable Interrupts - we use Polling if not DMA mode */ 1019 writel(0, regs + S3C64XX_SPI_INT_EN); 1020 1021 if (!sdd->port_conf->clk_from_cmu) 1022 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 1023 regs + S3C64XX_SPI_CLK_CFG); 1024 writel(0, regs + S3C64XX_SPI_MODE_CFG); 1025 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 1026 1027 /* Clear any irq pending bits, should set and clear the bits */ 1028 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | 1029 S3C64XX_SPI_PND_RX_UNDERRUN_CLR | 1030 S3C64XX_SPI_PND_TX_OVERRUN_CLR | 1031 S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 1032 writel(val, regs + S3C64XX_SPI_PENDING_CLR); 1033 writel(0, regs + S3C64XX_SPI_PENDING_CLR); 1034 1035 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 1036 1037 val = readl(regs + S3C64XX_SPI_MODE_CFG); 1038 val &= ~S3C64XX_SPI_MODE_4BURST; 1039 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1040 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1041 writel(val, regs + S3C64XX_SPI_MODE_CFG); 1042 1043 s3c64xx_flush_fifo(sdd); 1044 } 1045 1046 #ifdef CONFIG_OF 1047 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1048 { 1049 struct s3c64xx_spi_info *sci; 1050 u32 temp; 1051 1052 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); 1053 if (!sci) 1054 return ERR_PTR(-ENOMEM); 1055 1056 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { 1057 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); 1058 sci->src_clk_nr = 0; 1059 } else { 1060 sci->src_clk_nr = temp; 1061 } 1062 1063 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { 1064 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); 1065 sci->num_cs = 1; 1066 } else { 1067 sci->num_cs = temp; 1068 } 1069 1070 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); 1071 1072 return sci; 1073 } 1074 #else 1075 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1076 { 1077 return dev_get_platdata(dev); 1078 } 1079 #endif 1080 1081 static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( 1082 struct platform_device *pdev) 1083 { 1084 #ifdef CONFIG_OF 1085 if (pdev->dev.of_node) 1086 return of_device_get_match_data(&pdev->dev); 1087 #endif 1088 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; 1089 } 1090 1091 static int s3c64xx_spi_probe(struct platform_device *pdev) 1092 { 1093 struct resource *mem_res; 1094 struct s3c64xx_spi_driver_data *sdd; 1095 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); 1096 struct spi_master *master; 1097 int ret, irq; 1098 char clk_name[16]; 1099 1100 if (!sci && pdev->dev.of_node) { 1101 sci = s3c64xx_spi_parse_dt(&pdev->dev); 1102 if (IS_ERR(sci)) 1103 return PTR_ERR(sci); 1104 } 1105 1106 if (!sci) { 1107 dev_err(&pdev->dev, "platform_data missing!\n"); 1108 return -ENODEV; 1109 } 1110 1111 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1112 if (mem_res == NULL) { 1113 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); 1114 return -ENXIO; 1115 } 1116 1117 irq = platform_get_irq(pdev, 0); 1118 if (irq < 0) { 1119 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); 1120 return irq; 1121 } 1122 1123 master = spi_alloc_master(&pdev->dev, 1124 sizeof(struct s3c64xx_spi_driver_data)); 1125 if (master == NULL) { 1126 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 1127 return -ENOMEM; 1128 } 1129 1130 platform_set_drvdata(pdev, master); 1131 1132 sdd = spi_master_get_devdata(master); 1133 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); 1134 sdd->master = master; 1135 sdd->cntrlr_info = sci; 1136 sdd->pdev = pdev; 1137 sdd->sfr_start = mem_res->start; 1138 if (pdev->dev.of_node) { 1139 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1140 if (ret < 0) { 1141 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 1142 ret); 1143 goto err_deref_master; 1144 } 1145 sdd->port_id = ret; 1146 } else { 1147 sdd->port_id = pdev->id; 1148 } 1149 1150 sdd->cur_bpw = 8; 1151 1152 sdd->tx_dma.direction = DMA_MEM_TO_DEV; 1153 sdd->rx_dma.direction = DMA_DEV_TO_MEM; 1154 1155 master->dev.of_node = pdev->dev.of_node; 1156 master->bus_num = sdd->port_id; 1157 master->setup = s3c64xx_spi_setup; 1158 master->cleanup = s3c64xx_spi_cleanup; 1159 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1160 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; 1161 master->prepare_message = s3c64xx_spi_prepare_message; 1162 master->transfer_one = s3c64xx_spi_transfer_one; 1163 master->max_transfer_size = s3c64xx_spi_max_transfer_size; 1164 master->num_chipselect = sci->num_cs; 1165 master->use_gpio_descriptors = true; 1166 master->dma_alignment = 8; 1167 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1168 SPI_BPW_MASK(8); 1169 /* the spi->mode bits understood by this driver: */ 1170 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1171 if (sdd->port_conf->has_loopback) 1172 master->mode_bits |= SPI_LOOP; 1173 master->auto_runtime_pm = true; 1174 if (!is_polling(sdd)) 1175 master->can_dma = s3c64xx_spi_can_dma; 1176 1177 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); 1178 if (IS_ERR(sdd->regs)) { 1179 ret = PTR_ERR(sdd->regs); 1180 goto err_deref_master; 1181 } 1182 1183 if (sci->cfg_gpio && sci->cfg_gpio()) { 1184 dev_err(&pdev->dev, "Unable to config gpio\n"); 1185 ret = -EBUSY; 1186 goto err_deref_master; 1187 } 1188 1189 /* Setup clocks */ 1190 sdd->clk = devm_clk_get(&pdev->dev, "spi"); 1191 if (IS_ERR(sdd->clk)) { 1192 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); 1193 ret = PTR_ERR(sdd->clk); 1194 goto err_deref_master; 1195 } 1196 1197 ret = clk_prepare_enable(sdd->clk); 1198 if (ret) { 1199 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); 1200 goto err_deref_master; 1201 } 1202 1203 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1204 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); 1205 if (IS_ERR(sdd->src_clk)) { 1206 dev_err(&pdev->dev, 1207 "Unable to acquire clock '%s'\n", clk_name); 1208 ret = PTR_ERR(sdd->src_clk); 1209 goto err_disable_clk; 1210 } 1211 1212 ret = clk_prepare_enable(sdd->src_clk); 1213 if (ret) { 1214 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); 1215 goto err_disable_clk; 1216 } 1217 1218 if (sdd->port_conf->clk_ioclk) { 1219 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk"); 1220 if (IS_ERR(sdd->ioclk)) { 1221 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n"); 1222 ret = PTR_ERR(sdd->ioclk); 1223 goto err_disable_src_clk; 1224 } 1225 1226 ret = clk_prepare_enable(sdd->ioclk); 1227 if (ret) { 1228 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n"); 1229 goto err_disable_src_clk; 1230 } 1231 } 1232 1233 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1234 pm_runtime_use_autosuspend(&pdev->dev); 1235 pm_runtime_set_active(&pdev->dev); 1236 pm_runtime_enable(&pdev->dev); 1237 pm_runtime_get_sync(&pdev->dev); 1238 1239 /* Setup Deufult Mode */ 1240 s3c64xx_spi_hwinit(sdd); 1241 1242 spin_lock_init(&sdd->lock); 1243 init_completion(&sdd->xfer_completion); 1244 1245 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, 1246 "spi-s3c64xx", sdd); 1247 if (ret != 0) { 1248 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", 1249 irq, ret); 1250 goto err_pm_put; 1251 } 1252 1253 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1254 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1255 sdd->regs + S3C64XX_SPI_INT_EN); 1256 1257 ret = devm_spi_register_master(&pdev->dev, master); 1258 if (ret != 0) { 1259 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); 1260 goto err_pm_put; 1261 } 1262 1263 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", 1264 sdd->port_id, master->num_chipselect); 1265 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", 1266 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1); 1267 1268 pm_runtime_mark_last_busy(&pdev->dev); 1269 pm_runtime_put_autosuspend(&pdev->dev); 1270 1271 return 0; 1272 1273 err_pm_put: 1274 pm_runtime_put_noidle(&pdev->dev); 1275 pm_runtime_disable(&pdev->dev); 1276 pm_runtime_set_suspended(&pdev->dev); 1277 1278 clk_disable_unprepare(sdd->ioclk); 1279 err_disable_src_clk: 1280 clk_disable_unprepare(sdd->src_clk); 1281 err_disable_clk: 1282 clk_disable_unprepare(sdd->clk); 1283 err_deref_master: 1284 spi_master_put(master); 1285 1286 return ret; 1287 } 1288 1289 static void s3c64xx_spi_remove(struct platform_device *pdev) 1290 { 1291 struct spi_master *master = platform_get_drvdata(pdev); 1292 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1293 1294 pm_runtime_get_sync(&pdev->dev); 1295 1296 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1297 1298 if (!is_polling(sdd)) { 1299 dma_release_channel(sdd->rx_dma.ch); 1300 dma_release_channel(sdd->tx_dma.ch); 1301 } 1302 1303 clk_disable_unprepare(sdd->ioclk); 1304 1305 clk_disable_unprepare(sdd->src_clk); 1306 1307 clk_disable_unprepare(sdd->clk); 1308 1309 pm_runtime_put_noidle(&pdev->dev); 1310 pm_runtime_disable(&pdev->dev); 1311 pm_runtime_set_suspended(&pdev->dev); 1312 } 1313 1314 #ifdef CONFIG_PM_SLEEP 1315 static int s3c64xx_spi_suspend(struct device *dev) 1316 { 1317 struct spi_master *master = dev_get_drvdata(dev); 1318 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1319 1320 int ret = spi_master_suspend(master); 1321 if (ret) 1322 return ret; 1323 1324 ret = pm_runtime_force_suspend(dev); 1325 if (ret < 0) 1326 return ret; 1327 1328 sdd->cur_speed = 0; /* Output Clock is stopped */ 1329 1330 return 0; 1331 } 1332 1333 static int s3c64xx_spi_resume(struct device *dev) 1334 { 1335 struct spi_master *master = dev_get_drvdata(dev); 1336 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1337 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1338 int ret; 1339 1340 if (sci->cfg_gpio) 1341 sci->cfg_gpio(); 1342 1343 ret = pm_runtime_force_resume(dev); 1344 if (ret < 0) 1345 return ret; 1346 1347 return spi_master_resume(master); 1348 } 1349 #endif /* CONFIG_PM_SLEEP */ 1350 1351 #ifdef CONFIG_PM 1352 static int s3c64xx_spi_runtime_suspend(struct device *dev) 1353 { 1354 struct spi_master *master = dev_get_drvdata(dev); 1355 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1356 1357 clk_disable_unprepare(sdd->clk); 1358 clk_disable_unprepare(sdd->src_clk); 1359 clk_disable_unprepare(sdd->ioclk); 1360 1361 return 0; 1362 } 1363 1364 static int s3c64xx_spi_runtime_resume(struct device *dev) 1365 { 1366 struct spi_master *master = dev_get_drvdata(dev); 1367 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1368 int ret; 1369 1370 if (sdd->port_conf->clk_ioclk) { 1371 ret = clk_prepare_enable(sdd->ioclk); 1372 if (ret != 0) 1373 return ret; 1374 } 1375 1376 ret = clk_prepare_enable(sdd->src_clk); 1377 if (ret != 0) 1378 goto err_disable_ioclk; 1379 1380 ret = clk_prepare_enable(sdd->clk); 1381 if (ret != 0) 1382 goto err_disable_src_clk; 1383 1384 s3c64xx_spi_hwinit(sdd); 1385 1386 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1387 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1388 sdd->regs + S3C64XX_SPI_INT_EN); 1389 1390 return 0; 1391 1392 err_disable_src_clk: 1393 clk_disable_unprepare(sdd->src_clk); 1394 err_disable_ioclk: 1395 clk_disable_unprepare(sdd->ioclk); 1396 1397 return ret; 1398 } 1399 #endif /* CONFIG_PM */ 1400 1401 static const struct dev_pm_ops s3c64xx_spi_pm = { 1402 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) 1403 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, 1404 s3c64xx_spi_runtime_resume, NULL) 1405 }; 1406 1407 static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1408 .fifo_lvl_mask = { 0x7f }, 1409 .rx_lvl_offset = 13, 1410 .tx_st_done = 21, 1411 .clk_div = 2, 1412 .high_speed = true, 1413 }; 1414 1415 static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1416 .fifo_lvl_mask = { 0x7f, 0x7F }, 1417 .rx_lvl_offset = 13, 1418 .tx_st_done = 21, 1419 .clk_div = 2, 1420 }; 1421 1422 static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1423 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1424 .rx_lvl_offset = 15, 1425 .tx_st_done = 25, 1426 .clk_div = 2, 1427 .high_speed = true, 1428 }; 1429 1430 static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1431 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1432 .rx_lvl_offset = 15, 1433 .tx_st_done = 25, 1434 .clk_div = 2, 1435 .high_speed = true, 1436 .clk_from_cmu = true, 1437 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1438 }; 1439 1440 static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { 1441 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, 1442 .rx_lvl_offset = 15, 1443 .tx_st_done = 25, 1444 .clk_div = 2, 1445 .high_speed = true, 1446 .clk_from_cmu = true, 1447 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1448 }; 1449 1450 static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { 1451 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, 1452 .rx_lvl_offset = 15, 1453 .tx_st_done = 25, 1454 .clk_div = 2, 1455 .high_speed = true, 1456 .clk_from_cmu = true, 1457 .clk_ioclk = true, 1458 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1459 }; 1460 1461 static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { 1462 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 1463 0x7f, 0x7f, 0x7f, 0x7f}, 1464 .rx_lvl_offset = 15, 1465 .tx_st_done = 25, 1466 .clk_div = 4, 1467 .high_speed = true, 1468 .clk_from_cmu = true, 1469 .clk_ioclk = true, 1470 .has_loopback = true, 1471 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1472 }; 1473 1474 static const struct s3c64xx_spi_port_config fsd_spi_port_config = { 1475 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, 1476 .rx_lvl_offset = 15, 1477 .tx_st_done = 25, 1478 .clk_div = 2, 1479 .high_speed = true, 1480 .clk_from_cmu = true, 1481 .clk_ioclk = false, 1482 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1483 }; 1484 1485 static const struct platform_device_id s3c64xx_spi_driver_ids[] = { 1486 { 1487 .name = "s3c2443-spi", 1488 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, 1489 }, { 1490 .name = "s3c6410-spi", 1491 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1492 }, 1493 { }, 1494 }; 1495 1496 static const struct of_device_id s3c64xx_spi_dt_match[] = { 1497 { .compatible = "samsung,s3c2443-spi", 1498 .data = (void *)&s3c2443_spi_port_config, 1499 }, 1500 { .compatible = "samsung,s3c6410-spi", 1501 .data = (void *)&s3c6410_spi_port_config, 1502 }, 1503 { .compatible = "samsung,s5pv210-spi", 1504 .data = (void *)&s5pv210_spi_port_config, 1505 }, 1506 { .compatible = "samsung,exynos4210-spi", 1507 .data = (void *)&exynos4_spi_port_config, 1508 }, 1509 { .compatible = "samsung,exynos7-spi", 1510 .data = (void *)&exynos7_spi_port_config, 1511 }, 1512 { .compatible = "samsung,exynos5433-spi", 1513 .data = (void *)&exynos5433_spi_port_config, 1514 }, 1515 { .compatible = "samsung,exynosautov9-spi", 1516 .data = (void *)&exynosautov9_spi_port_config, 1517 }, 1518 { .compatible = "tesla,fsd-spi", 1519 .data = (void *)&fsd_spi_port_config, 1520 }, 1521 { }, 1522 }; 1523 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1524 1525 static struct platform_driver s3c64xx_spi_driver = { 1526 .driver = { 1527 .name = "s3c64xx-spi", 1528 .pm = &s3c64xx_spi_pm, 1529 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), 1530 }, 1531 .probe = s3c64xx_spi_probe, 1532 .remove_new = s3c64xx_spi_remove, 1533 .id_table = s3c64xx_spi_driver_ids, 1534 }; 1535 MODULE_ALIAS("platform:s3c64xx-spi"); 1536 1537 module_platform_driver(s3c64xx_spi_driver); 1538 1539 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1540 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1541 MODULE_LICENSE("GPL"); 1542