183c624d8SFabrizio Castro // SPDX-License-Identifier: GPL-2.0-or-later 283c624d8SFabrizio Castro /* 383c624d8SFabrizio Castro * Renesas RZ/V2M Clocked Serial Interface (CSI) driver 483c624d8SFabrizio Castro * 583c624d8SFabrizio Castro * Copyright (C) 2023 Renesas Electronics Corporation 683c624d8SFabrizio Castro */ 783c624d8SFabrizio Castro 8*f572ba79SFabrizio Castro #include <linux/bits.h> 983c624d8SFabrizio Castro #include <linux/clk.h> 1083c624d8SFabrizio Castro #include <linux/count_zeros.h> 1183c624d8SFabrizio Castro #include <linux/interrupt.h> 1283c624d8SFabrizio Castro #include <linux/iopoll.h> 1383c624d8SFabrizio Castro #include <linux/platform_device.h> 1483c624d8SFabrizio Castro #include <linux/reset.h> 1583c624d8SFabrizio Castro #include <linux/spi/spi.h> 1683c624d8SFabrizio Castro 1783c624d8SFabrizio Castro /* Registers */ 1883c624d8SFabrizio Castro #define CSI_MODE 0x00 /* CSI mode control */ 1983c624d8SFabrizio Castro #define CSI_CLKSEL 0x04 /* CSI clock select */ 2083c624d8SFabrizio Castro #define CSI_CNT 0x08 /* CSI control */ 2183c624d8SFabrizio Castro #define CSI_INT 0x0C /* CSI interrupt status */ 2283c624d8SFabrizio Castro #define CSI_IFIFOL 0x10 /* CSI receive FIFO level display */ 2383c624d8SFabrizio Castro #define CSI_OFIFOL 0x14 /* CSI transmit FIFO level display */ 2483c624d8SFabrizio Castro #define CSI_IFIFO 0x18 /* CSI receive window */ 2583c624d8SFabrizio Castro #define CSI_OFIFO 0x1C /* CSI transmit window */ 2683c624d8SFabrizio Castro #define CSI_FIFOTRG 0x20 /* CSI FIFO trigger level */ 2783c624d8SFabrizio Castro 2883c624d8SFabrizio Castro /* CSI_MODE */ 2983c624d8SFabrizio Castro #define CSI_MODE_CSIE BIT(7) 3083c624d8SFabrizio Castro #define CSI_MODE_TRMD BIT(6) 3183c624d8SFabrizio Castro #define CSI_MODE_CCL BIT(5) 3283c624d8SFabrizio Castro #define CSI_MODE_DIR BIT(4) 3383c624d8SFabrizio Castro #define CSI_MODE_CSOT BIT(0) 3483c624d8SFabrizio Castro 3583c624d8SFabrizio Castro #define CSI_MODE_SETUP 0x00000040 3683c624d8SFabrizio Castro 3783c624d8SFabrizio Castro /* CSI_CLKSEL */ 3883c624d8SFabrizio Castro #define CSI_CLKSEL_CKP BIT(17) 3983c624d8SFabrizio Castro #define CSI_CLKSEL_DAP BIT(16) 4083c624d8SFabrizio Castro #define CSI_CLKSEL_SLAVE BIT(15) 4183c624d8SFabrizio Castro #define CSI_CLKSEL_CKS GENMASK(14, 1) 4283c624d8SFabrizio Castro 4383c624d8SFabrizio Castro /* CSI_CNT */ 4483c624d8SFabrizio Castro #define CSI_CNT_CSIRST BIT(28) 4583c624d8SFabrizio Castro #define CSI_CNT_R_TRGEN BIT(19) 4683c624d8SFabrizio Castro #define CSI_CNT_UNDER_E BIT(13) 4783c624d8SFabrizio Castro #define CSI_CNT_OVERF_E BIT(12) 4883c624d8SFabrizio Castro #define CSI_CNT_TREND_E BIT(9) 4983c624d8SFabrizio Castro #define CSI_CNT_CSIEND_E BIT(8) 5083c624d8SFabrizio Castro #define CSI_CNT_T_TRGR_E BIT(4) 5183c624d8SFabrizio Castro #define CSI_CNT_R_TRGR_E BIT(0) 5283c624d8SFabrizio Castro 5383c624d8SFabrizio Castro /* CSI_INT */ 5483c624d8SFabrizio Castro #define CSI_INT_UNDER BIT(13) 5583c624d8SFabrizio Castro #define CSI_INT_OVERF BIT(12) 5683c624d8SFabrizio Castro #define CSI_INT_TREND BIT(9) 5783c624d8SFabrizio Castro #define CSI_INT_CSIEND BIT(8) 5883c624d8SFabrizio Castro #define CSI_INT_T_TRGR BIT(4) 5983c624d8SFabrizio Castro #define CSI_INT_R_TRGR BIT(0) 6083c624d8SFabrizio Castro 6183c624d8SFabrizio Castro /* CSI_FIFOTRG */ 6283c624d8SFabrizio Castro #define CSI_FIFOTRG_R_TRG GENMASK(2, 0) 6383c624d8SFabrizio Castro 6483c624d8SFabrizio Castro #define CSI_FIFO_SIZE_BYTES 32 6583c624d8SFabrizio Castro #define CSI_FIFO_HALF_SIZE 16 6683c624d8SFabrizio Castro #define CSI_EN_DIS_TIMEOUT_US 100 6783c624d8SFabrizio Castro #define CSI_CKS_MAX 0x3FFF 6883c624d8SFabrizio Castro 6983c624d8SFabrizio Castro #define UNDERRUN_ERROR BIT(0) 7083c624d8SFabrizio Castro #define OVERFLOW_ERROR BIT(1) 7183c624d8SFabrizio Castro #define TX_TIMEOUT_ERROR BIT(2) 7283c624d8SFabrizio Castro #define RX_TIMEOUT_ERROR BIT(3) 7383c624d8SFabrizio Castro 7483c624d8SFabrizio Castro #define CSI_MAX_SPI_SCKO 8000000 7583c624d8SFabrizio Castro 7683c624d8SFabrizio Castro struct rzv2m_csi_priv { 7783c624d8SFabrizio Castro void __iomem *base; 7883c624d8SFabrizio Castro struct clk *csiclk; 7983c624d8SFabrizio Castro struct clk *pclk; 8083c624d8SFabrizio Castro struct device *dev; 8183c624d8SFabrizio Castro struct spi_controller *controller; 8283c624d8SFabrizio Castro const u8 *txbuf; 8383c624d8SFabrizio Castro u8 *rxbuf; 8483c624d8SFabrizio Castro int buffer_len; 8583c624d8SFabrizio Castro int bytes_sent; 8683c624d8SFabrizio Castro int bytes_received; 8783c624d8SFabrizio Castro int bytes_to_transfer; 8883c624d8SFabrizio Castro int words_to_transfer; 8983c624d8SFabrizio Castro unsigned char bytes_per_word; 9083c624d8SFabrizio Castro wait_queue_head_t wait; 9183c624d8SFabrizio Castro u8 errors; 9283c624d8SFabrizio Castro u32 status; 9383c624d8SFabrizio Castro }; 9483c624d8SFabrizio Castro 9583c624d8SFabrizio Castro static const unsigned char x_trg[] = { 9683c624d8SFabrizio Castro 0, 1, 1, 2, 2, 2, 2, 3, 9783c624d8SFabrizio Castro 3, 3, 3, 3, 3, 3, 3, 4, 9883c624d8SFabrizio Castro 4, 4, 4, 4, 4, 4, 4, 4, 9983c624d8SFabrizio Castro 4, 4, 4, 4, 4, 4, 4, 5 10083c624d8SFabrizio Castro }; 10183c624d8SFabrizio Castro 10283c624d8SFabrizio Castro static const unsigned char x_trg_words[] = { 10383c624d8SFabrizio Castro 1, 2, 2, 4, 4, 4, 4, 8, 10483c624d8SFabrizio Castro 8, 8, 8, 8, 8, 8, 8, 16, 10583c624d8SFabrizio Castro 16, 16, 16, 16, 16, 16, 16, 16, 10683c624d8SFabrizio Castro 16, 16, 16, 16, 16, 16, 16, 32 10783c624d8SFabrizio Castro }; 10883c624d8SFabrizio Castro 10983c624d8SFabrizio Castro static void rzv2m_csi_reg_write_bit(const struct rzv2m_csi_priv *csi, 11083c624d8SFabrizio Castro int reg_offs, int bit_mask, u32 value) 11183c624d8SFabrizio Castro { 11283c624d8SFabrizio Castro int nr_zeros; 11383c624d8SFabrizio Castro u32 tmp; 11483c624d8SFabrizio Castro 11583c624d8SFabrizio Castro nr_zeros = count_trailing_zeros(bit_mask); 11683c624d8SFabrizio Castro value <<= nr_zeros; 11783c624d8SFabrizio Castro 11883c624d8SFabrizio Castro tmp = (readl(csi->base + reg_offs) & ~bit_mask) | value; 11983c624d8SFabrizio Castro writel(tmp, csi->base + reg_offs); 12083c624d8SFabrizio Castro } 12183c624d8SFabrizio Castro 12283c624d8SFabrizio Castro static int rzv2m_csi_sw_reset(struct rzv2m_csi_priv *csi, int assert) 12383c624d8SFabrizio Castro { 12483c624d8SFabrizio Castro u32 reg; 12583c624d8SFabrizio Castro 12683c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_CSIRST, assert); 12783c624d8SFabrizio Castro 12883c624d8SFabrizio Castro if (assert) { 12983c624d8SFabrizio Castro return readl_poll_timeout(csi->base + CSI_MODE, reg, 13083c624d8SFabrizio Castro !(reg & CSI_MODE_CSOT), 0, 13183c624d8SFabrizio Castro CSI_EN_DIS_TIMEOUT_US); 13283c624d8SFabrizio Castro } 13383c624d8SFabrizio Castro 13483c624d8SFabrizio Castro return 0; 13583c624d8SFabrizio Castro } 13683c624d8SFabrizio Castro 13783c624d8SFabrizio Castro static int rzv2m_csi_start_stop_operation(const struct rzv2m_csi_priv *csi, 13883c624d8SFabrizio Castro int enable, bool wait) 13983c624d8SFabrizio Castro { 14083c624d8SFabrizio Castro u32 reg; 14183c624d8SFabrizio Castro 14283c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CSIE, enable); 14383c624d8SFabrizio Castro 14483c624d8SFabrizio Castro if (!enable && wait) 14583c624d8SFabrizio Castro return readl_poll_timeout(csi->base + CSI_MODE, reg, 14683c624d8SFabrizio Castro !(reg & CSI_MODE_CSOT), 0, 14783c624d8SFabrizio Castro CSI_EN_DIS_TIMEOUT_US); 14883c624d8SFabrizio Castro 14983c624d8SFabrizio Castro return 0; 15083c624d8SFabrizio Castro } 15183c624d8SFabrizio Castro 15283c624d8SFabrizio Castro static int rzv2m_csi_fill_txfifo(struct rzv2m_csi_priv *csi) 15383c624d8SFabrizio Castro { 15483c624d8SFabrizio Castro int i; 15583c624d8SFabrizio Castro 15683c624d8SFabrizio Castro if (readl(csi->base + CSI_OFIFOL)) 15783c624d8SFabrizio Castro return -EIO; 15883c624d8SFabrizio Castro 15983c624d8SFabrizio Castro if (csi->bytes_per_word == 2) { 16083c624d8SFabrizio Castro u16 *buf = (u16 *)csi->txbuf; 16183c624d8SFabrizio Castro 16283c624d8SFabrizio Castro for (i = 0; i < csi->words_to_transfer; i++) 16383c624d8SFabrizio Castro writel(buf[i], csi->base + CSI_OFIFO); 16483c624d8SFabrizio Castro } else { 16583c624d8SFabrizio Castro u8 *buf = (u8 *)csi->txbuf; 16683c624d8SFabrizio Castro 16783c624d8SFabrizio Castro for (i = 0; i < csi->words_to_transfer; i++) 16883c624d8SFabrizio Castro writel(buf[i], csi->base + CSI_OFIFO); 16983c624d8SFabrizio Castro } 17083c624d8SFabrizio Castro 17183c624d8SFabrizio Castro csi->txbuf += csi->bytes_to_transfer; 17283c624d8SFabrizio Castro csi->bytes_sent += csi->bytes_to_transfer; 17383c624d8SFabrizio Castro 17483c624d8SFabrizio Castro return 0; 17583c624d8SFabrizio Castro } 17683c624d8SFabrizio Castro 17783c624d8SFabrizio Castro static int rzv2m_csi_read_rxfifo(struct rzv2m_csi_priv *csi) 17883c624d8SFabrizio Castro { 17983c624d8SFabrizio Castro int i; 18083c624d8SFabrizio Castro 18183c624d8SFabrizio Castro if (readl(csi->base + CSI_IFIFOL) != csi->bytes_to_transfer) 18283c624d8SFabrizio Castro return -EIO; 18383c624d8SFabrizio Castro 18483c624d8SFabrizio Castro if (csi->bytes_per_word == 2) { 18583c624d8SFabrizio Castro u16 *buf = (u16 *)csi->rxbuf; 18683c624d8SFabrizio Castro 18783c624d8SFabrizio Castro for (i = 0; i < csi->words_to_transfer; i++) 18883c624d8SFabrizio Castro buf[i] = (u16)readl(csi->base + CSI_IFIFO); 18983c624d8SFabrizio Castro } else { 19083c624d8SFabrizio Castro u8 *buf = (u8 *)csi->rxbuf; 19183c624d8SFabrizio Castro 19283c624d8SFabrizio Castro for (i = 0; i < csi->words_to_transfer; i++) 19383c624d8SFabrizio Castro buf[i] = (u8)readl(csi->base + CSI_IFIFO); 19483c624d8SFabrizio Castro } 19583c624d8SFabrizio Castro 19683c624d8SFabrizio Castro csi->rxbuf += csi->bytes_to_transfer; 19783c624d8SFabrizio Castro csi->bytes_received += csi->bytes_to_transfer; 19883c624d8SFabrizio Castro 19983c624d8SFabrizio Castro return 0; 20083c624d8SFabrizio Castro } 20183c624d8SFabrizio Castro 20283c624d8SFabrizio Castro static inline void rzv2m_csi_calc_current_transfer(struct rzv2m_csi_priv *csi) 20383c624d8SFabrizio Castro { 20483c624d8SFabrizio Castro int bytes_transferred = max_t(int, csi->bytes_received, csi->bytes_sent); 20583c624d8SFabrizio Castro int bytes_remaining = csi->buffer_len - bytes_transferred; 20683c624d8SFabrizio Castro int to_transfer; 20783c624d8SFabrizio Castro 20883c624d8SFabrizio Castro if (csi->txbuf) 20983c624d8SFabrizio Castro /* 21083c624d8SFabrizio Castro * Leaving a little bit of headroom in the FIFOs makes it very 21183c624d8SFabrizio Castro * hard to raise an overflow error (which is only possible 21283c624d8SFabrizio Castro * when IP transmits and receives at the same time). 21383c624d8SFabrizio Castro */ 21483c624d8SFabrizio Castro to_transfer = min_t(int, CSI_FIFO_HALF_SIZE, bytes_remaining); 21583c624d8SFabrizio Castro else 21683c624d8SFabrizio Castro to_transfer = min_t(int, CSI_FIFO_SIZE_BYTES, bytes_remaining); 21783c624d8SFabrizio Castro 21883c624d8SFabrizio Castro if (csi->bytes_per_word == 2) 21983c624d8SFabrizio Castro to_transfer >>= 1; 22083c624d8SFabrizio Castro 22183c624d8SFabrizio Castro /* 22283c624d8SFabrizio Castro * We can only choose a trigger level from a predefined set of values. 22383c624d8SFabrizio Castro * This will pick a value that is the greatest possible integer that's 22483c624d8SFabrizio Castro * less than or equal to the number of bytes we need to transfer. 22583c624d8SFabrizio Castro * This may result in multiple smaller transfers. 22683c624d8SFabrizio Castro */ 22783c624d8SFabrizio Castro csi->words_to_transfer = x_trg_words[to_transfer - 1]; 22883c624d8SFabrizio Castro 22983c624d8SFabrizio Castro if (csi->bytes_per_word == 2) 23083c624d8SFabrizio Castro csi->bytes_to_transfer = csi->words_to_transfer << 1; 23183c624d8SFabrizio Castro else 23283c624d8SFabrizio Castro csi->bytes_to_transfer = csi->words_to_transfer; 23383c624d8SFabrizio Castro } 23483c624d8SFabrizio Castro 23583c624d8SFabrizio Castro static inline void rzv2m_csi_set_rx_fifo_trigger_level(struct rzv2m_csi_priv *csi) 23683c624d8SFabrizio Castro { 23783c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_FIFOTRG, CSI_FIFOTRG_R_TRG, 23883c624d8SFabrizio Castro x_trg[csi->words_to_transfer - 1]); 23983c624d8SFabrizio Castro } 24083c624d8SFabrizio Castro 24183c624d8SFabrizio Castro static inline void rzv2m_csi_enable_rx_trigger(struct rzv2m_csi_priv *csi, 24283c624d8SFabrizio Castro bool enable) 24383c624d8SFabrizio Castro { 24483c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_R_TRGEN, enable); 24583c624d8SFabrizio Castro } 24683c624d8SFabrizio Castro 24783c624d8SFabrizio Castro static void rzv2m_csi_disable_irqs(const struct rzv2m_csi_priv *csi, 24883c624d8SFabrizio Castro u32 enable_bits) 24983c624d8SFabrizio Castro { 25083c624d8SFabrizio Castro u32 cnt = readl(csi->base + CSI_CNT); 25183c624d8SFabrizio Castro 25283c624d8SFabrizio Castro writel(cnt & ~enable_bits, csi->base + CSI_CNT); 25383c624d8SFabrizio Castro } 25483c624d8SFabrizio Castro 25583c624d8SFabrizio Castro static void rzv2m_csi_disable_all_irqs(struct rzv2m_csi_priv *csi) 25683c624d8SFabrizio Castro { 25783c624d8SFabrizio Castro rzv2m_csi_disable_irqs(csi, CSI_CNT_R_TRGR_E | CSI_CNT_T_TRGR_E | 25883c624d8SFabrizio Castro CSI_CNT_CSIEND_E | CSI_CNT_TREND_E | 25983c624d8SFabrizio Castro CSI_CNT_OVERF_E | CSI_CNT_UNDER_E); 26083c624d8SFabrizio Castro } 26183c624d8SFabrizio Castro 26283c624d8SFabrizio Castro static inline void rzv2m_csi_clear_irqs(struct rzv2m_csi_priv *csi, u32 irqs) 26383c624d8SFabrizio Castro { 26483c624d8SFabrizio Castro writel(irqs, csi->base + CSI_INT); 26583c624d8SFabrizio Castro } 26683c624d8SFabrizio Castro 26783c624d8SFabrizio Castro static void rzv2m_csi_clear_all_irqs(struct rzv2m_csi_priv *csi) 26883c624d8SFabrizio Castro { 26983c624d8SFabrizio Castro rzv2m_csi_clear_irqs(csi, CSI_INT_UNDER | CSI_INT_OVERF | 27083c624d8SFabrizio Castro CSI_INT_TREND | CSI_INT_CSIEND | CSI_INT_T_TRGR | 27183c624d8SFabrizio Castro CSI_INT_R_TRGR); 27283c624d8SFabrizio Castro } 27383c624d8SFabrizio Castro 27483c624d8SFabrizio Castro static void rzv2m_csi_enable_irqs(struct rzv2m_csi_priv *csi, u32 enable_bits) 27583c624d8SFabrizio Castro { 27683c624d8SFabrizio Castro u32 cnt = readl(csi->base + CSI_CNT); 27783c624d8SFabrizio Castro 27883c624d8SFabrizio Castro writel(cnt | enable_bits, csi->base + CSI_CNT); 27983c624d8SFabrizio Castro } 28083c624d8SFabrizio Castro 28183c624d8SFabrizio Castro static int rzv2m_csi_wait_for_interrupt(struct rzv2m_csi_priv *csi, 28283c624d8SFabrizio Castro u32 wait_mask, u32 enable_bits) 28383c624d8SFabrizio Castro { 28483c624d8SFabrizio Castro int ret; 28583c624d8SFabrizio Castro 28683c624d8SFabrizio Castro rzv2m_csi_enable_irqs(csi, enable_bits); 28783c624d8SFabrizio Castro 28883c624d8SFabrizio Castro ret = wait_event_timeout(csi->wait, 28983c624d8SFabrizio Castro ((csi->status & wait_mask) == wait_mask) || 29083c624d8SFabrizio Castro csi->errors, HZ); 29183c624d8SFabrizio Castro 29283c624d8SFabrizio Castro rzv2m_csi_disable_irqs(csi, enable_bits); 29383c624d8SFabrizio Castro 29483c624d8SFabrizio Castro if (csi->errors) 29583c624d8SFabrizio Castro return -EIO; 29683c624d8SFabrizio Castro 29783c624d8SFabrizio Castro if (!ret) 29883c624d8SFabrizio Castro return -ETIMEDOUT; 29983c624d8SFabrizio Castro 30083c624d8SFabrizio Castro return 0; 30183c624d8SFabrizio Castro } 30283c624d8SFabrizio Castro 30383c624d8SFabrizio Castro static int rzv2m_csi_wait_for_tx_empty(struct rzv2m_csi_priv *csi) 30483c624d8SFabrizio Castro { 30583c624d8SFabrizio Castro int ret; 30683c624d8SFabrizio Castro 30783c624d8SFabrizio Castro if (readl(csi->base + CSI_OFIFOL) == 0) 30883c624d8SFabrizio Castro return 0; 30983c624d8SFabrizio Castro 31083c624d8SFabrizio Castro ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_TREND, CSI_CNT_TREND_E); 31183c624d8SFabrizio Castro 31283c624d8SFabrizio Castro if (ret == -ETIMEDOUT) 31383c624d8SFabrizio Castro csi->errors |= TX_TIMEOUT_ERROR; 31483c624d8SFabrizio Castro 31583c624d8SFabrizio Castro return ret; 31683c624d8SFabrizio Castro } 31783c624d8SFabrizio Castro 31883c624d8SFabrizio Castro static inline int rzv2m_csi_wait_for_rx_ready(struct rzv2m_csi_priv *csi) 31983c624d8SFabrizio Castro { 32083c624d8SFabrizio Castro int ret; 32183c624d8SFabrizio Castro 32283c624d8SFabrizio Castro if (readl(csi->base + CSI_IFIFOL) == csi->bytes_to_transfer) 32383c624d8SFabrizio Castro return 0; 32483c624d8SFabrizio Castro 32583c624d8SFabrizio Castro ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_R_TRGR, 32683c624d8SFabrizio Castro CSI_CNT_R_TRGR_E); 32783c624d8SFabrizio Castro 32883c624d8SFabrizio Castro if (ret == -ETIMEDOUT) 32983c624d8SFabrizio Castro csi->errors |= RX_TIMEOUT_ERROR; 33083c624d8SFabrizio Castro 33183c624d8SFabrizio Castro return ret; 33283c624d8SFabrizio Castro } 33383c624d8SFabrizio Castro 33483c624d8SFabrizio Castro static irqreturn_t rzv2m_csi_irq_handler(int irq, void *data) 33583c624d8SFabrizio Castro { 33683c624d8SFabrizio Castro struct rzv2m_csi_priv *csi = (struct rzv2m_csi_priv *)data; 33783c624d8SFabrizio Castro 33883c624d8SFabrizio Castro csi->status = readl(csi->base + CSI_INT); 33983c624d8SFabrizio Castro rzv2m_csi_disable_irqs(csi, csi->status); 34083c624d8SFabrizio Castro 34183c624d8SFabrizio Castro if (csi->status & CSI_INT_OVERF) 34283c624d8SFabrizio Castro csi->errors |= OVERFLOW_ERROR; 34383c624d8SFabrizio Castro if (csi->status & CSI_INT_UNDER) 34483c624d8SFabrizio Castro csi->errors |= UNDERRUN_ERROR; 34583c624d8SFabrizio Castro 34683c624d8SFabrizio Castro wake_up(&csi->wait); 34783c624d8SFabrizio Castro 34883c624d8SFabrizio Castro return IRQ_HANDLED; 34983c624d8SFabrizio Castro } 35083c624d8SFabrizio Castro 35183c624d8SFabrizio Castro static void rzv2m_csi_setup_clock(struct rzv2m_csi_priv *csi, u32 spi_hz) 35283c624d8SFabrizio Castro { 35383c624d8SFabrizio Castro unsigned long csiclk_rate = clk_get_rate(csi->csiclk); 35483c624d8SFabrizio Castro unsigned long pclk_rate = clk_get_rate(csi->pclk); 35583c624d8SFabrizio Castro unsigned long csiclk_rate_limit = pclk_rate >> 1; 35683c624d8SFabrizio Castro u32 cks; 35783c624d8SFabrizio Castro 35883c624d8SFabrizio Castro /* 35983c624d8SFabrizio Castro * There is a restriction on the frequency of CSICLK, it has to be <= 36083c624d8SFabrizio Castro * PCLK / 2. 36183c624d8SFabrizio Castro */ 36283c624d8SFabrizio Castro if (csiclk_rate > csiclk_rate_limit) { 36383c624d8SFabrizio Castro clk_set_rate(csi->csiclk, csiclk_rate >> 1); 36483c624d8SFabrizio Castro csiclk_rate = clk_get_rate(csi->csiclk); 36583c624d8SFabrizio Castro } else if ((csiclk_rate << 1) <= csiclk_rate_limit) { 36683c624d8SFabrizio Castro clk_set_rate(csi->csiclk, csiclk_rate << 1); 36783c624d8SFabrizio Castro csiclk_rate = clk_get_rate(csi->csiclk); 36883c624d8SFabrizio Castro } 36983c624d8SFabrizio Castro 37083c624d8SFabrizio Castro spi_hz = spi_hz > CSI_MAX_SPI_SCKO ? CSI_MAX_SPI_SCKO : spi_hz; 37183c624d8SFabrizio Castro 37283c624d8SFabrizio Castro cks = DIV_ROUND_UP(csiclk_rate, spi_hz << 1); 37383c624d8SFabrizio Castro if (cks > CSI_CKS_MAX) 37483c624d8SFabrizio Castro cks = CSI_CKS_MAX; 37583c624d8SFabrizio Castro 37683c624d8SFabrizio Castro dev_dbg(csi->dev, "SPI clk rate is %ldHz\n", csiclk_rate / (cks << 1)); 37783c624d8SFabrizio Castro 37883c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_CKS, cks); 37983c624d8SFabrizio Castro } 38083c624d8SFabrizio Castro 38183c624d8SFabrizio Castro static void rzv2m_csi_setup_operating_mode(struct rzv2m_csi_priv *csi, 38283c624d8SFabrizio Castro struct spi_transfer *t) 38383c624d8SFabrizio Castro { 38483c624d8SFabrizio Castro if (t->rx_buf && !t->tx_buf) 38583c624d8SFabrizio Castro /* Reception-only mode */ 38683c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 0); 38783c624d8SFabrizio Castro else 38883c624d8SFabrizio Castro /* Send and receive mode */ 38983c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 1); 39083c624d8SFabrizio Castro 39183c624d8SFabrizio Castro csi->bytes_per_word = t->bits_per_word / 8; 39283c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CCL, 39383c624d8SFabrizio Castro csi->bytes_per_word == 2); 39483c624d8SFabrizio Castro } 39583c624d8SFabrizio Castro 39683c624d8SFabrizio Castro static int rzv2m_csi_setup(struct spi_device *spi) 39783c624d8SFabrizio Castro { 39883c624d8SFabrizio Castro struct rzv2m_csi_priv *csi = spi_controller_get_devdata(spi->controller); 39983c624d8SFabrizio Castro int ret; 40083c624d8SFabrizio Castro 40183c624d8SFabrizio Castro rzv2m_csi_sw_reset(csi, 0); 40283c624d8SFabrizio Castro 40383c624d8SFabrizio Castro writel(CSI_MODE_SETUP, csi->base + CSI_MODE); 40483c624d8SFabrizio Castro 40583c624d8SFabrizio Castro /* Setup clock polarity and phase timing */ 40683c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_CKP, 40783c624d8SFabrizio Castro !(spi->mode & SPI_CPOL)); 40883c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_DAP, 40983c624d8SFabrizio Castro !(spi->mode & SPI_CPHA)); 41083c624d8SFabrizio Castro 41183c624d8SFabrizio Castro /* Setup serial data order */ 41283c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_DIR, 41383c624d8SFabrizio Castro !!(spi->mode & SPI_LSB_FIRST)); 41483c624d8SFabrizio Castro 41583c624d8SFabrizio Castro /* Set the operation mode as master */ 41683c624d8SFabrizio Castro rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE, 0); 41783c624d8SFabrizio Castro 41883c624d8SFabrizio Castro /* Give the IP a SW reset */ 41983c624d8SFabrizio Castro ret = rzv2m_csi_sw_reset(csi, 1); 42083c624d8SFabrizio Castro if (ret) 42183c624d8SFabrizio Castro return ret; 42283c624d8SFabrizio Castro rzv2m_csi_sw_reset(csi, 0); 42383c624d8SFabrizio Castro 42483c624d8SFabrizio Castro /* 42583c624d8SFabrizio Castro * We need to enable the communication so that the clock will settle 42683c624d8SFabrizio Castro * for the right polarity before enabling the CS. 42783c624d8SFabrizio Castro */ 42883c624d8SFabrizio Castro rzv2m_csi_start_stop_operation(csi, 1, false); 42983c624d8SFabrizio Castro udelay(10); 43083c624d8SFabrizio Castro rzv2m_csi_start_stop_operation(csi, 0, false); 43183c624d8SFabrizio Castro 43283c624d8SFabrizio Castro return 0; 43383c624d8SFabrizio Castro } 43483c624d8SFabrizio Castro 43583c624d8SFabrizio Castro static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi) 43683c624d8SFabrizio Castro { 43783c624d8SFabrizio Castro bool tx_completed = csi->txbuf ? false : true; 43883c624d8SFabrizio Castro bool rx_completed = csi->rxbuf ? false : true; 43983c624d8SFabrizio Castro int ret = 0; 44083c624d8SFabrizio Castro 44183c624d8SFabrizio Castro /* Make sure the TX FIFO is empty */ 44283c624d8SFabrizio Castro writel(0, csi->base + CSI_OFIFOL); 44383c624d8SFabrizio Castro 44483c624d8SFabrizio Castro csi->bytes_sent = 0; 44583c624d8SFabrizio Castro csi->bytes_received = 0; 44683c624d8SFabrizio Castro csi->errors = 0; 44783c624d8SFabrizio Castro 44883c624d8SFabrizio Castro rzv2m_csi_disable_all_irqs(csi); 44983c624d8SFabrizio Castro rzv2m_csi_clear_all_irqs(csi); 45083c624d8SFabrizio Castro rzv2m_csi_enable_rx_trigger(csi, true); 45183c624d8SFabrizio Castro 45283c624d8SFabrizio Castro while (!tx_completed || !rx_completed) { 45383c624d8SFabrizio Castro /* 45483c624d8SFabrizio Castro * Decide how many words we are going to transfer during 45583c624d8SFabrizio Castro * this cycle (for both TX and RX), then set the RX FIFO trigger 45683c624d8SFabrizio Castro * level accordingly. No need to set a trigger level for the 45783c624d8SFabrizio Castro * TX FIFO, as this IP comes with an interrupt that fires when 45883c624d8SFabrizio Castro * the TX FIFO is empty. 45983c624d8SFabrizio Castro */ 46083c624d8SFabrizio Castro rzv2m_csi_calc_current_transfer(csi); 46183c624d8SFabrizio Castro rzv2m_csi_set_rx_fifo_trigger_level(csi); 46283c624d8SFabrizio Castro 46383c624d8SFabrizio Castro rzv2m_csi_enable_irqs(csi, CSI_INT_OVERF | CSI_INT_UNDER); 46483c624d8SFabrizio Castro 46583c624d8SFabrizio Castro /* Make sure the RX FIFO is empty */ 46683c624d8SFabrizio Castro writel(0, csi->base + CSI_IFIFOL); 46783c624d8SFabrizio Castro 46883c624d8SFabrizio Castro writel(readl(csi->base + CSI_INT), csi->base + CSI_INT); 46983c624d8SFabrizio Castro csi->status = 0; 47083c624d8SFabrizio Castro 47183c624d8SFabrizio Castro rzv2m_csi_start_stop_operation(csi, 1, false); 47283c624d8SFabrizio Castro 47383c624d8SFabrizio Castro /* TX */ 47483c624d8SFabrizio Castro if (csi->txbuf) { 47583c624d8SFabrizio Castro ret = rzv2m_csi_fill_txfifo(csi); 47683c624d8SFabrizio Castro if (ret) 47783c624d8SFabrizio Castro break; 47883c624d8SFabrizio Castro 47983c624d8SFabrizio Castro ret = rzv2m_csi_wait_for_tx_empty(csi); 48083c624d8SFabrizio Castro if (ret) 48183c624d8SFabrizio Castro break; 48283c624d8SFabrizio Castro 48383c624d8SFabrizio Castro if (csi->bytes_sent == csi->buffer_len) 48483c624d8SFabrizio Castro tx_completed = true; 48583c624d8SFabrizio Castro } 48683c624d8SFabrizio Castro 48783c624d8SFabrizio Castro /* 48883c624d8SFabrizio Castro * Make sure the RX FIFO contains the desired number of words. 48983c624d8SFabrizio Castro * We then either flush its content, or we copy it onto 49083c624d8SFabrizio Castro * csi->rxbuf. 49183c624d8SFabrizio Castro */ 49283c624d8SFabrizio Castro ret = rzv2m_csi_wait_for_rx_ready(csi); 49383c624d8SFabrizio Castro if (ret) 49483c624d8SFabrizio Castro break; 49583c624d8SFabrizio Castro 49683c624d8SFabrizio Castro /* RX */ 49783c624d8SFabrizio Castro if (csi->rxbuf) { 49883c624d8SFabrizio Castro rzv2m_csi_start_stop_operation(csi, 0, false); 49983c624d8SFabrizio Castro 50083c624d8SFabrizio Castro ret = rzv2m_csi_read_rxfifo(csi); 50183c624d8SFabrizio Castro if (ret) 50283c624d8SFabrizio Castro break; 50383c624d8SFabrizio Castro 50483c624d8SFabrizio Castro if (csi->bytes_received == csi->buffer_len) 50583c624d8SFabrizio Castro rx_completed = true; 50683c624d8SFabrizio Castro } 50783c624d8SFabrizio Castro 50883c624d8SFabrizio Castro ret = rzv2m_csi_start_stop_operation(csi, 0, true); 50983c624d8SFabrizio Castro if (ret) 51083c624d8SFabrizio Castro goto pio_quit; 51183c624d8SFabrizio Castro 51283c624d8SFabrizio Castro if (csi->errors) { 51383c624d8SFabrizio Castro ret = -EIO; 51483c624d8SFabrizio Castro goto pio_quit; 51583c624d8SFabrizio Castro } 51683c624d8SFabrizio Castro } 51783c624d8SFabrizio Castro 51883c624d8SFabrizio Castro rzv2m_csi_start_stop_operation(csi, 0, true); 51983c624d8SFabrizio Castro 52083c624d8SFabrizio Castro pio_quit: 52183c624d8SFabrizio Castro rzv2m_csi_disable_all_irqs(csi); 52283c624d8SFabrizio Castro rzv2m_csi_enable_rx_trigger(csi, false); 52383c624d8SFabrizio Castro rzv2m_csi_clear_all_irqs(csi); 52483c624d8SFabrizio Castro 52583c624d8SFabrizio Castro return ret; 52683c624d8SFabrizio Castro } 52783c624d8SFabrizio Castro 52883c624d8SFabrizio Castro static int rzv2m_csi_transfer_one(struct spi_controller *controller, 52983c624d8SFabrizio Castro struct spi_device *spi, 53083c624d8SFabrizio Castro struct spi_transfer *transfer) 53183c624d8SFabrizio Castro { 53283c624d8SFabrizio Castro struct rzv2m_csi_priv *csi = spi_controller_get_devdata(controller); 53383c624d8SFabrizio Castro struct device *dev = csi->dev; 53483c624d8SFabrizio Castro int ret; 53583c624d8SFabrizio Castro 53683c624d8SFabrizio Castro csi->txbuf = transfer->tx_buf; 53783c624d8SFabrizio Castro csi->rxbuf = transfer->rx_buf; 53883c624d8SFabrizio Castro csi->buffer_len = transfer->len; 53983c624d8SFabrizio Castro 54083c624d8SFabrizio Castro rzv2m_csi_setup_operating_mode(csi, transfer); 54183c624d8SFabrizio Castro 54283c624d8SFabrizio Castro rzv2m_csi_setup_clock(csi, transfer->speed_hz); 54383c624d8SFabrizio Castro 54483c624d8SFabrizio Castro ret = rzv2m_csi_pio_transfer(csi); 54583c624d8SFabrizio Castro if (ret) { 54683c624d8SFabrizio Castro if (csi->errors & UNDERRUN_ERROR) 54783c624d8SFabrizio Castro dev_err(dev, "Underrun error\n"); 54883c624d8SFabrizio Castro if (csi->errors & OVERFLOW_ERROR) 54983c624d8SFabrizio Castro dev_err(dev, "Overflow error\n"); 55083c624d8SFabrizio Castro if (csi->errors & TX_TIMEOUT_ERROR) 55183c624d8SFabrizio Castro dev_err(dev, "TX timeout error\n"); 55283c624d8SFabrizio Castro if (csi->errors & RX_TIMEOUT_ERROR) 55383c624d8SFabrizio Castro dev_err(dev, "RX timeout error\n"); 55483c624d8SFabrizio Castro } 55583c624d8SFabrizio Castro 55683c624d8SFabrizio Castro return ret; 55783c624d8SFabrizio Castro } 55883c624d8SFabrizio Castro 55983c624d8SFabrizio Castro static int rzv2m_csi_probe(struct platform_device *pdev) 56083c624d8SFabrizio Castro { 56183c624d8SFabrizio Castro struct spi_controller *controller; 56283c624d8SFabrizio Castro struct device *dev = &pdev->dev; 56383c624d8SFabrizio Castro struct rzv2m_csi_priv *csi; 56483c624d8SFabrizio Castro struct reset_control *rstc; 56583c624d8SFabrizio Castro int irq; 56683c624d8SFabrizio Castro int ret; 56783c624d8SFabrizio Castro 56883c624d8SFabrizio Castro controller = devm_spi_alloc_master(dev, sizeof(*csi)); 56983c624d8SFabrizio Castro if (!controller) 57083c624d8SFabrizio Castro return -ENOMEM; 57183c624d8SFabrizio Castro 57283c624d8SFabrizio Castro csi = spi_controller_get_devdata(controller); 57383c624d8SFabrizio Castro platform_set_drvdata(pdev, csi); 57483c624d8SFabrizio Castro 57583c624d8SFabrizio Castro csi->dev = dev; 57683c624d8SFabrizio Castro csi->controller = controller; 57783c624d8SFabrizio Castro 57883c624d8SFabrizio Castro csi->base = devm_platform_ioremap_resource(pdev, 0); 57983c624d8SFabrizio Castro if (IS_ERR(csi->base)) 58083c624d8SFabrizio Castro return PTR_ERR(csi->base); 58183c624d8SFabrizio Castro 58283c624d8SFabrizio Castro irq = platform_get_irq(pdev, 0); 58383c624d8SFabrizio Castro if (irq < 0) 58483c624d8SFabrizio Castro return irq; 58583c624d8SFabrizio Castro 58683c624d8SFabrizio Castro csi->csiclk = devm_clk_get(dev, "csiclk"); 58783c624d8SFabrizio Castro if (IS_ERR(csi->csiclk)) 58883c624d8SFabrizio Castro return dev_err_probe(dev, PTR_ERR(csi->csiclk), 58983c624d8SFabrizio Castro "could not get csiclk\n"); 59083c624d8SFabrizio Castro 59183c624d8SFabrizio Castro csi->pclk = devm_clk_get(dev, "pclk"); 59283c624d8SFabrizio Castro if (IS_ERR(csi->pclk)) 59383c624d8SFabrizio Castro return dev_err_probe(dev, PTR_ERR(csi->pclk), 59483c624d8SFabrizio Castro "could not get pclk\n"); 59583c624d8SFabrizio Castro 59683c624d8SFabrizio Castro rstc = devm_reset_control_get_shared(dev, NULL); 59783c624d8SFabrizio Castro if (IS_ERR(rstc)) 59883c624d8SFabrizio Castro return dev_err_probe(dev, PTR_ERR(rstc), "Missing reset ctrl\n"); 59983c624d8SFabrizio Castro 60083c624d8SFabrizio Castro init_waitqueue_head(&csi->wait); 60183c624d8SFabrizio Castro 60283c624d8SFabrizio Castro controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 60383c624d8SFabrizio Castro controller->dev.of_node = pdev->dev.of_node; 60483c624d8SFabrizio Castro controller->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); 60583c624d8SFabrizio Castro controller->setup = rzv2m_csi_setup; 60683c624d8SFabrizio Castro controller->transfer_one = rzv2m_csi_transfer_one; 60783c624d8SFabrizio Castro controller->use_gpio_descriptors = true; 60883c624d8SFabrizio Castro 60983c624d8SFabrizio Castro ret = devm_request_irq(dev, irq, rzv2m_csi_irq_handler, 0, 61083c624d8SFabrizio Castro dev_name(dev), csi); 61183c624d8SFabrizio Castro if (ret) 61283c624d8SFabrizio Castro return dev_err_probe(dev, ret, "cannot request IRQ\n"); 61383c624d8SFabrizio Castro 61483c624d8SFabrizio Castro /* 61583c624d8SFabrizio Castro * The reset also affects other HW that is not under the control 61683c624d8SFabrizio Castro * of Linux. Therefore, all we can do is make sure the reset is 61783c624d8SFabrizio Castro * deasserted. 61883c624d8SFabrizio Castro */ 61983c624d8SFabrizio Castro reset_control_deassert(rstc); 62083c624d8SFabrizio Castro 62183c624d8SFabrizio Castro /* Make sure the IP is in SW reset state */ 62283c624d8SFabrizio Castro ret = rzv2m_csi_sw_reset(csi, 1); 62383c624d8SFabrizio Castro if (ret) 62483c624d8SFabrizio Castro return ret; 62583c624d8SFabrizio Castro 62683c624d8SFabrizio Castro ret = clk_prepare_enable(csi->csiclk); 62783c624d8SFabrizio Castro if (ret) 62883c624d8SFabrizio Castro return dev_err_probe(dev, ret, "could not enable csiclk\n"); 62983c624d8SFabrizio Castro 63083c624d8SFabrizio Castro ret = spi_register_controller(controller); 63183c624d8SFabrizio Castro if (ret) { 63283c624d8SFabrizio Castro clk_disable_unprepare(csi->csiclk); 63383c624d8SFabrizio Castro return dev_err_probe(dev, ret, "register controller failed\n"); 63483c624d8SFabrizio Castro } 63583c624d8SFabrizio Castro 63683c624d8SFabrizio Castro return 0; 63783c624d8SFabrizio Castro } 63883c624d8SFabrizio Castro 63993033314SUwe Kleine-König static void rzv2m_csi_remove(struct platform_device *pdev) 64083c624d8SFabrizio Castro { 64183c624d8SFabrizio Castro struct rzv2m_csi_priv *csi = platform_get_drvdata(pdev); 64283c624d8SFabrizio Castro 64383c624d8SFabrizio Castro spi_unregister_controller(csi->controller); 64483c624d8SFabrizio Castro rzv2m_csi_sw_reset(csi, 1); 64583c624d8SFabrizio Castro clk_disable_unprepare(csi->csiclk); 64683c624d8SFabrizio Castro } 64783c624d8SFabrizio Castro 64883c624d8SFabrizio Castro static const struct of_device_id rzv2m_csi_match[] = { 64983c624d8SFabrizio Castro { .compatible = "renesas,rzv2m-csi" }, 65083c624d8SFabrizio Castro { /* sentinel */ } 65183c624d8SFabrizio Castro }; 65283c624d8SFabrizio Castro MODULE_DEVICE_TABLE(of, rzv2m_csi_match); 65383c624d8SFabrizio Castro 65483c624d8SFabrizio Castro static struct platform_driver rzv2m_csi_drv = { 65583c624d8SFabrizio Castro .probe = rzv2m_csi_probe, 65693033314SUwe Kleine-König .remove_new = rzv2m_csi_remove, 65783c624d8SFabrizio Castro .driver = { 65883c624d8SFabrizio Castro .name = "rzv2m_csi", 65983c624d8SFabrizio Castro .of_match_table = rzv2m_csi_match, 66083c624d8SFabrizio Castro }, 66183c624d8SFabrizio Castro }; 66283c624d8SFabrizio Castro module_platform_driver(rzv2m_csi_drv); 66383c624d8SFabrizio Castro 66483c624d8SFabrizio Castro MODULE_LICENSE("GPL"); 66583c624d8SFabrizio Castro MODULE_AUTHOR("Fabrizio Castro <castro.fabrizio.jz@renesas.com>"); 66683c624d8SFabrizio Castro MODULE_DESCRIPTION("Clocked Serial Interface Driver"); 667