1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH RSPI driver 4 * 5 * Copyright (C) 2012, 2013 Renesas Solutions Corp. 6 * Copyright (C) 2014 Glider bvba 7 * 8 * Based on spi-sh.c: 9 * Copyright (C) 2011 Renesas Solutions Corp. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/sched.h> 15 #include <linux/errno.h> 16 #include <linux/interrupt.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/clk.h> 20 #include <linux/dmaengine.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/of_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/sh_dma.h> 25 #include <linux/spi/spi.h> 26 #include <linux/spi/rspi.h> 27 28 #define RSPI_SPCR 0x00 /* Control Register */ 29 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ 30 #define RSPI_SPPCR 0x02 /* Pin Control Register */ 31 #define RSPI_SPSR 0x03 /* Status Register */ 32 #define RSPI_SPDR 0x04 /* Data Register */ 33 #define RSPI_SPSCR 0x08 /* Sequence Control Register */ 34 #define RSPI_SPSSR 0x09 /* Sequence Status Register */ 35 #define RSPI_SPBR 0x0a /* Bit Rate Register */ 36 #define RSPI_SPDCR 0x0b /* Data Control Register */ 37 #define RSPI_SPCKD 0x0c /* Clock Delay Register */ 38 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ 39 #define RSPI_SPND 0x0e /* Next-Access Delay Register */ 40 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ 41 #define RSPI_SPCMD0 0x10 /* Command Register 0 */ 42 #define RSPI_SPCMD1 0x12 /* Command Register 1 */ 43 #define RSPI_SPCMD2 0x14 /* Command Register 2 */ 44 #define RSPI_SPCMD3 0x16 /* Command Register 3 */ 45 #define RSPI_SPCMD4 0x18 /* Command Register 4 */ 46 #define RSPI_SPCMD5 0x1a /* Command Register 5 */ 47 #define RSPI_SPCMD6 0x1c /* Command Register 6 */ 48 #define RSPI_SPCMD7 0x1e /* Command Register 7 */ 49 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) 50 #define RSPI_NUM_SPCMD 8 51 #define RSPI_RZ_NUM_SPCMD 4 52 #define QSPI_NUM_SPCMD 4 53 54 /* RSPI on RZ only */ 55 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ 56 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ 57 58 /* QSPI only */ 59 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ 60 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ 61 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ 62 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ 63 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ 64 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ 65 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) 66 67 /* SPCR - Control Register */ 68 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ 69 #define SPCR_SPE 0x40 /* Function Enable */ 70 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ 71 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ 72 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ 73 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ 74 /* RSPI on SH only */ 75 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ 76 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ 77 /* QSPI on R-Car Gen2 only */ 78 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ 79 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ 80 81 /* SSLP - Slave Select Polarity Register */ 82 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ 83 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ 84 85 /* SPPCR - Pin Control Register */ 86 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ 87 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ 88 #define SPPCR_SPOM 0x04 89 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ 90 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ 91 92 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ 93 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ 94 95 /* SPSR - Status Register */ 96 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ 97 #define SPSR_TEND 0x40 /* Transmit End */ 98 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ 99 #define SPSR_PERF 0x08 /* Parity Error Flag */ 100 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ 101 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ 102 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ 103 104 /* SPSCR - Sequence Control Register */ 105 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ 106 107 /* SPSSR - Sequence Status Register */ 108 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ 109 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ 110 111 /* SPDCR - Data Control Register */ 112 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ 113 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ 114 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ 115 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) 116 #define SPDCR_SPLWORD SPDCR_SPLW1 117 #define SPDCR_SPLBYTE SPDCR_SPLW0 118 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ 119 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ 120 #define SPDCR_SLSEL1 0x08 121 #define SPDCR_SLSEL0 0x04 122 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ 123 #define SPDCR_SPFC1 0x02 124 #define SPDCR_SPFC0 0x01 125 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ 126 127 /* SPCKD - Clock Delay Register */ 128 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ 129 130 /* SSLND - Slave Select Negation Delay Register */ 131 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ 132 133 /* SPND - Next-Access Delay Register */ 134 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ 135 136 /* SPCR2 - Control Register 2 */ 137 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ 138 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ 139 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ 140 #define SPCR2_SPPE 0x01 /* Parity Enable */ 141 142 /* SPCMDn - Command Registers */ 143 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ 144 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ 145 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ 146 #define SPCMD_LSBF 0x1000 /* LSB First */ 147 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ 148 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 149 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ 150 #define SPCMD_SPB_16BIT 0x0100 151 #define SPCMD_SPB_20BIT 0x0000 152 #define SPCMD_SPB_24BIT 0x0100 153 #define SPCMD_SPB_32BIT 0x0200 154 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ 155 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ 156 #define SPCMD_SPIMOD1 0x0040 157 #define SPCMD_SPIMOD0 0x0020 158 #define SPCMD_SPIMOD_SINGLE 0 159 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 160 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 161 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ 162 #define SPCMD_SSLA(i) ((i) << 4) /* SSL Assert Signal Setting */ 163 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ 164 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ 165 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ 166 167 /* SPBFCR - Buffer Control Register */ 168 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ 169 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ 170 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 171 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 172 /* QSPI on R-Car Gen2 */ 173 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */ 174 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */ 175 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */ 176 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */ 177 178 #define QSPI_BUFFER_SIZE 32u 179 180 struct rspi_data { 181 void __iomem *addr; 182 u32 max_speed_hz; 183 struct spi_controller *ctlr; 184 wait_queue_head_t wait; 185 struct clk *clk; 186 u16 spcmd; 187 u8 spsr; 188 u8 sppcr; 189 int rx_irq, tx_irq; 190 const struct spi_ops *ops; 191 192 unsigned dma_callbacked:1; 193 unsigned byte_access:1; 194 }; 195 196 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) 197 { 198 iowrite8(data, rspi->addr + offset); 199 } 200 201 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) 202 { 203 iowrite16(data, rspi->addr + offset); 204 } 205 206 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) 207 { 208 iowrite32(data, rspi->addr + offset); 209 } 210 211 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) 212 { 213 return ioread8(rspi->addr + offset); 214 } 215 216 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) 217 { 218 return ioread16(rspi->addr + offset); 219 } 220 221 static void rspi_write_data(const struct rspi_data *rspi, u16 data) 222 { 223 if (rspi->byte_access) 224 rspi_write8(rspi, data, RSPI_SPDR); 225 else /* 16 bit */ 226 rspi_write16(rspi, data, RSPI_SPDR); 227 } 228 229 static u16 rspi_read_data(const struct rspi_data *rspi) 230 { 231 if (rspi->byte_access) 232 return rspi_read8(rspi, RSPI_SPDR); 233 else /* 16 bit */ 234 return rspi_read16(rspi, RSPI_SPDR); 235 } 236 237 /* optional functions */ 238 struct spi_ops { 239 int (*set_config_register)(struct rspi_data *rspi, int access_size); 240 int (*transfer_one)(struct spi_controller *ctlr, 241 struct spi_device *spi, struct spi_transfer *xfer); 242 u16 mode_bits; 243 u16 flags; 244 u16 fifo_size; 245 u8 num_hw_ss; 246 }; 247 248 /* 249 * functions for RSPI on legacy SH 250 */ 251 static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 252 { 253 int spbr; 254 255 /* Sets output mode, MOSI signal, and (optionally) loopback */ 256 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 257 258 /* Sets transfer bit rate */ 259 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 260 2 * rspi->max_speed_hz) - 1; 261 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 262 263 /* Disable dummy transmission, set 16-bit word access, 1 frame */ 264 rspi_write8(rspi, 0, RSPI_SPDCR); 265 rspi->byte_access = 0; 266 267 /* Sets RSPCK, SSL, next-access delay value */ 268 rspi_write8(rspi, 0x00, RSPI_SPCKD); 269 rspi_write8(rspi, 0x00, RSPI_SSLND); 270 rspi_write8(rspi, 0x00, RSPI_SPND); 271 272 /* Sets parity, interrupt mask */ 273 rspi_write8(rspi, 0x00, RSPI_SPCR2); 274 275 /* Resets sequencer */ 276 rspi_write8(rspi, 0, RSPI_SPSCR); 277 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 278 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 279 280 /* Sets RSPI mode */ 281 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 282 283 return 0; 284 } 285 286 /* 287 * functions for RSPI on RZ 288 */ 289 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) 290 { 291 int spbr; 292 int div = 0; 293 unsigned long clksrc; 294 295 /* Sets output mode, MOSI signal, and (optionally) loopback */ 296 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 297 298 clksrc = clk_get_rate(rspi->clk); 299 while (div < 3) { 300 if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */ 301 break; 302 div++; 303 clksrc /= 2; 304 } 305 306 /* Sets transfer bit rate */ 307 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1; 308 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 309 rspi->spcmd |= div << 2; 310 311 /* Disable dummy transmission, set byte access */ 312 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); 313 rspi->byte_access = 1; 314 315 /* Sets RSPCK, SSL, next-access delay value */ 316 rspi_write8(rspi, 0x00, RSPI_SPCKD); 317 rspi_write8(rspi, 0x00, RSPI_SSLND); 318 rspi_write8(rspi, 0x00, RSPI_SPND); 319 320 /* Resets sequencer */ 321 rspi_write8(rspi, 0, RSPI_SPSCR); 322 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 323 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 324 325 /* Sets RSPI mode */ 326 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 327 328 return 0; 329 } 330 331 /* 332 * functions for QSPI 333 */ 334 static int qspi_set_config_register(struct rspi_data *rspi, int access_size) 335 { 336 int spbr; 337 338 /* Sets output mode, MOSI signal, and (optionally) loopback */ 339 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 340 341 /* Sets transfer bit rate */ 342 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz); 343 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 344 345 /* Disable dummy transmission, set byte access */ 346 rspi_write8(rspi, 0, RSPI_SPDCR); 347 rspi->byte_access = 1; 348 349 /* Sets RSPCK, SSL, next-access delay value */ 350 rspi_write8(rspi, 0x00, RSPI_SPCKD); 351 rspi_write8(rspi, 0x00, RSPI_SSLND); 352 rspi_write8(rspi, 0x00, RSPI_SPND); 353 354 /* Data Length Setting */ 355 if (access_size == 8) 356 rspi->spcmd |= SPCMD_SPB_8BIT; 357 else if (access_size == 16) 358 rspi->spcmd |= SPCMD_SPB_16BIT; 359 else 360 rspi->spcmd |= SPCMD_SPB_32BIT; 361 362 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; 363 364 /* Resets transfer data length */ 365 rspi_write32(rspi, 0, QSPI_SPBMUL0); 366 367 /* Resets transmit and receive buffer */ 368 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 369 /* Sets buffer to allow normal operation */ 370 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 371 372 /* Resets sequencer */ 373 rspi_write8(rspi, 0, RSPI_SPSCR); 374 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 375 376 /* Sets RSPI mode */ 377 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 378 379 return 0; 380 } 381 382 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg) 383 { 384 u8 data; 385 386 data = rspi_read8(rspi, reg); 387 data &= ~mask; 388 data |= (val & mask); 389 rspi_write8(rspi, data, reg); 390 } 391 392 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi, 393 unsigned int len) 394 { 395 unsigned int n; 396 397 n = min(len, QSPI_BUFFER_SIZE); 398 399 if (len >= QSPI_BUFFER_SIZE) { 400 /* sets triggering number to 32 bytes */ 401 qspi_update(rspi, SPBFCR_TXTRG_MASK, 402 SPBFCR_TXTRG_32B, QSPI_SPBFCR); 403 } else { 404 /* sets triggering number to 1 byte */ 405 qspi_update(rspi, SPBFCR_TXTRG_MASK, 406 SPBFCR_TXTRG_1B, QSPI_SPBFCR); 407 } 408 409 return n; 410 } 411 412 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len) 413 { 414 unsigned int n; 415 416 n = min(len, QSPI_BUFFER_SIZE); 417 418 if (len >= QSPI_BUFFER_SIZE) { 419 /* sets triggering number to 32 bytes */ 420 qspi_update(rspi, SPBFCR_RXTRG_MASK, 421 SPBFCR_RXTRG_32B, QSPI_SPBFCR); 422 } else { 423 /* sets triggering number to 1 byte */ 424 qspi_update(rspi, SPBFCR_RXTRG_MASK, 425 SPBFCR_RXTRG_1B, QSPI_SPBFCR); 426 } 427 return n; 428 } 429 430 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) 431 { 432 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); 433 } 434 435 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) 436 { 437 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); 438 } 439 440 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, 441 u8 enable_bit) 442 { 443 int ret; 444 445 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 446 if (rspi->spsr & wait_mask) 447 return 0; 448 449 rspi_enable_irq(rspi, enable_bit); 450 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 451 if (ret == 0 && !(rspi->spsr & wait_mask)) 452 return -ETIMEDOUT; 453 454 return 0; 455 } 456 457 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi) 458 { 459 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 460 } 461 462 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi) 463 { 464 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE); 465 } 466 467 static int rspi_data_out(struct rspi_data *rspi, u8 data) 468 { 469 int error = rspi_wait_for_tx_empty(rspi); 470 if (error < 0) { 471 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); 472 return error; 473 } 474 rspi_write_data(rspi, data); 475 return 0; 476 } 477 478 static int rspi_data_in(struct rspi_data *rspi) 479 { 480 int error; 481 u8 data; 482 483 error = rspi_wait_for_rx_full(rspi); 484 if (error < 0) { 485 dev_err(&rspi->ctlr->dev, "receive timeout\n"); 486 return error; 487 } 488 data = rspi_read_data(rspi); 489 return data; 490 } 491 492 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx, 493 unsigned int n) 494 { 495 while (n-- > 0) { 496 if (tx) { 497 int ret = rspi_data_out(rspi, *tx++); 498 if (ret < 0) 499 return ret; 500 } 501 if (rx) { 502 int ret = rspi_data_in(rspi); 503 if (ret < 0) 504 return ret; 505 *rx++ = ret; 506 } 507 } 508 509 return 0; 510 } 511 512 static void rspi_dma_complete(void *arg) 513 { 514 struct rspi_data *rspi = arg; 515 516 rspi->dma_callbacked = 1; 517 wake_up_interruptible(&rspi->wait); 518 } 519 520 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, 521 struct sg_table *rx) 522 { 523 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 524 u8 irq_mask = 0; 525 unsigned int other_irq = 0; 526 dma_cookie_t cookie; 527 int ret; 528 529 /* First prepare and submit the DMA request(s), as this may fail */ 530 if (rx) { 531 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl, 532 rx->nents, DMA_DEV_TO_MEM, 533 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 534 if (!desc_rx) { 535 ret = -EAGAIN; 536 goto no_dma_rx; 537 } 538 539 desc_rx->callback = rspi_dma_complete; 540 desc_rx->callback_param = rspi; 541 cookie = dmaengine_submit(desc_rx); 542 if (dma_submit_error(cookie)) { 543 ret = cookie; 544 goto no_dma_rx; 545 } 546 547 irq_mask |= SPCR_SPRIE; 548 } 549 550 if (tx) { 551 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl, 552 tx->nents, DMA_MEM_TO_DEV, 553 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 554 if (!desc_tx) { 555 ret = -EAGAIN; 556 goto no_dma_tx; 557 } 558 559 if (rx) { 560 /* No callback */ 561 desc_tx->callback = NULL; 562 } else { 563 desc_tx->callback = rspi_dma_complete; 564 desc_tx->callback_param = rspi; 565 } 566 cookie = dmaengine_submit(desc_tx); 567 if (dma_submit_error(cookie)) { 568 ret = cookie; 569 goto no_dma_tx; 570 } 571 572 irq_mask |= SPCR_SPTIE; 573 } 574 575 /* 576 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be 577 * called. So, this driver disables the IRQ while DMA transfer. 578 */ 579 if (tx) 580 disable_irq(other_irq = rspi->tx_irq); 581 if (rx && rspi->rx_irq != other_irq) 582 disable_irq(rspi->rx_irq); 583 584 rspi_enable_irq(rspi, irq_mask); 585 rspi->dma_callbacked = 0; 586 587 /* Now start DMA */ 588 if (rx) 589 dma_async_issue_pending(rspi->ctlr->dma_rx); 590 if (tx) 591 dma_async_issue_pending(rspi->ctlr->dma_tx); 592 593 ret = wait_event_interruptible_timeout(rspi->wait, 594 rspi->dma_callbacked, HZ); 595 if (ret > 0 && rspi->dma_callbacked) { 596 ret = 0; 597 } else { 598 if (!ret) { 599 dev_err(&rspi->ctlr->dev, "DMA timeout\n"); 600 ret = -ETIMEDOUT; 601 } 602 if (tx) 603 dmaengine_terminate_all(rspi->ctlr->dma_tx); 604 if (rx) 605 dmaengine_terminate_all(rspi->ctlr->dma_rx); 606 } 607 608 rspi_disable_irq(rspi, irq_mask); 609 610 if (tx) 611 enable_irq(rspi->tx_irq); 612 if (rx && rspi->rx_irq != other_irq) 613 enable_irq(rspi->rx_irq); 614 615 return ret; 616 617 no_dma_tx: 618 if (rx) 619 dmaengine_terminate_all(rspi->ctlr->dma_rx); 620 no_dma_rx: 621 if (ret == -EAGAIN) { 622 dev_warn_once(&rspi->ctlr->dev, 623 "DMA not available, falling back to PIO\n"); 624 } 625 return ret; 626 } 627 628 static void rspi_receive_init(const struct rspi_data *rspi) 629 { 630 u8 spsr; 631 632 spsr = rspi_read8(rspi, RSPI_SPSR); 633 if (spsr & SPSR_SPRF) 634 rspi_read_data(rspi); /* dummy read */ 635 if (spsr & SPSR_OVRF) 636 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 637 RSPI_SPSR); 638 } 639 640 static void rspi_rz_receive_init(const struct rspi_data *rspi) 641 { 642 rspi_receive_init(rspi); 643 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); 644 rspi_write8(rspi, 0, RSPI_SPBFCR); 645 } 646 647 static void qspi_receive_init(const struct rspi_data *rspi) 648 { 649 u8 spsr; 650 651 spsr = rspi_read8(rspi, RSPI_SPSR); 652 if (spsr & SPSR_SPRF) 653 rspi_read_data(rspi); /* dummy read */ 654 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 655 rspi_write8(rspi, 0, QSPI_SPBFCR); 656 } 657 658 static bool __rspi_can_dma(const struct rspi_data *rspi, 659 const struct spi_transfer *xfer) 660 { 661 return xfer->len > rspi->ops->fifo_size; 662 } 663 664 static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi, 665 struct spi_transfer *xfer) 666 { 667 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 668 669 return __rspi_can_dma(rspi, xfer); 670 } 671 672 static int rspi_dma_check_then_transfer(struct rspi_data *rspi, 673 struct spi_transfer *xfer) 674 { 675 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer)) 676 return -EAGAIN; 677 678 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ 679 return rspi_dma_transfer(rspi, &xfer->tx_sg, 680 xfer->rx_buf ? &xfer->rx_sg : NULL); 681 } 682 683 static int rspi_common_transfer(struct rspi_data *rspi, 684 struct spi_transfer *xfer) 685 { 686 int ret; 687 688 ret = rspi_dma_check_then_transfer(rspi, xfer); 689 if (ret != -EAGAIN) 690 return ret; 691 692 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); 693 if (ret < 0) 694 return ret; 695 696 /* Wait for the last transmission */ 697 rspi_wait_for_tx_empty(rspi); 698 699 return 0; 700 } 701 702 static int rspi_transfer_one(struct spi_controller *ctlr, 703 struct spi_device *spi, struct spi_transfer *xfer) 704 { 705 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 706 u8 spcr; 707 708 spcr = rspi_read8(rspi, RSPI_SPCR); 709 if (xfer->rx_buf) { 710 rspi_receive_init(rspi); 711 spcr &= ~SPCR_TXMD; 712 } else { 713 spcr |= SPCR_TXMD; 714 } 715 rspi_write8(rspi, spcr, RSPI_SPCR); 716 717 return rspi_common_transfer(rspi, xfer); 718 } 719 720 static int rspi_rz_transfer_one(struct spi_controller *ctlr, 721 struct spi_device *spi, 722 struct spi_transfer *xfer) 723 { 724 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 725 726 rspi_rz_receive_init(rspi); 727 728 return rspi_common_transfer(rspi, xfer); 729 } 730 731 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx, 732 u8 *rx, unsigned int len) 733 { 734 unsigned int i, n; 735 int ret; 736 737 while (len > 0) { 738 n = qspi_set_send_trigger(rspi, len); 739 qspi_set_receive_trigger(rspi, len); 740 ret = rspi_wait_for_tx_empty(rspi); 741 if (ret < 0) { 742 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); 743 return ret; 744 } 745 for (i = 0; i < n; i++) 746 rspi_write_data(rspi, *tx++); 747 748 ret = rspi_wait_for_rx_full(rspi); 749 if (ret < 0) { 750 dev_err(&rspi->ctlr->dev, "receive timeout\n"); 751 return ret; 752 } 753 for (i = 0; i < n; i++) 754 *rx++ = rspi_read_data(rspi); 755 756 len -= n; 757 } 758 759 return 0; 760 } 761 762 static int qspi_transfer_out_in(struct rspi_data *rspi, 763 struct spi_transfer *xfer) 764 { 765 int ret; 766 767 qspi_receive_init(rspi); 768 769 ret = rspi_dma_check_then_transfer(rspi, xfer); 770 if (ret != -EAGAIN) 771 return ret; 772 773 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf, 774 xfer->rx_buf, xfer->len); 775 } 776 777 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) 778 { 779 const u8 *tx = xfer->tx_buf; 780 unsigned int n = xfer->len; 781 unsigned int i, len; 782 int ret; 783 784 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { 785 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); 786 if (ret != -EAGAIN) 787 return ret; 788 } 789 790 while (n > 0) { 791 len = qspi_set_send_trigger(rspi, n); 792 ret = rspi_wait_for_tx_empty(rspi); 793 if (ret < 0) { 794 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); 795 return ret; 796 } 797 for (i = 0; i < len; i++) 798 rspi_write_data(rspi, *tx++); 799 800 n -= len; 801 } 802 803 /* Wait for the last transmission */ 804 rspi_wait_for_tx_empty(rspi); 805 806 return 0; 807 } 808 809 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) 810 { 811 u8 *rx = xfer->rx_buf; 812 unsigned int n = xfer->len; 813 unsigned int i, len; 814 int ret; 815 816 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { 817 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); 818 if (ret != -EAGAIN) 819 return ret; 820 } 821 822 while (n > 0) { 823 len = qspi_set_receive_trigger(rspi, n); 824 ret = rspi_wait_for_rx_full(rspi); 825 if (ret < 0) { 826 dev_err(&rspi->ctlr->dev, "receive timeout\n"); 827 return ret; 828 } 829 for (i = 0; i < len; i++) 830 *rx++ = rspi_read_data(rspi); 831 832 n -= len; 833 } 834 835 return 0; 836 } 837 838 static int qspi_transfer_one(struct spi_controller *ctlr, 839 struct spi_device *spi, struct spi_transfer *xfer) 840 { 841 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 842 843 if (spi->mode & SPI_LOOP) { 844 return qspi_transfer_out_in(rspi, xfer); 845 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { 846 /* Quad or Dual SPI Write */ 847 return qspi_transfer_out(rspi, xfer); 848 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) { 849 /* Quad or Dual SPI Read */ 850 return qspi_transfer_in(rspi, xfer); 851 } else { 852 /* Single SPI Transfer */ 853 return qspi_transfer_out_in(rspi, xfer); 854 } 855 } 856 857 static u16 qspi_transfer_mode(const struct spi_transfer *xfer) 858 { 859 if (xfer->tx_buf) 860 switch (xfer->tx_nbits) { 861 case SPI_NBITS_QUAD: 862 return SPCMD_SPIMOD_QUAD; 863 case SPI_NBITS_DUAL: 864 return SPCMD_SPIMOD_DUAL; 865 default: 866 return 0; 867 } 868 if (xfer->rx_buf) 869 switch (xfer->rx_nbits) { 870 case SPI_NBITS_QUAD: 871 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; 872 case SPI_NBITS_DUAL: 873 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; 874 default: 875 return 0; 876 } 877 878 return 0; 879 } 880 881 static int qspi_setup_sequencer(struct rspi_data *rspi, 882 const struct spi_message *msg) 883 { 884 const struct spi_transfer *xfer; 885 unsigned int i = 0, len = 0; 886 u16 current_mode = 0xffff, mode; 887 888 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 889 mode = qspi_transfer_mode(xfer); 890 if (mode == current_mode) { 891 len += xfer->len; 892 continue; 893 } 894 895 /* Transfer mode change */ 896 if (i) { 897 /* Set transfer data length of previous transfer */ 898 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 899 } 900 901 if (i >= QSPI_NUM_SPCMD) { 902 dev_err(&msg->spi->dev, 903 "Too many different transfer modes"); 904 return -EINVAL; 905 } 906 907 /* Program transfer mode for this transfer */ 908 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); 909 current_mode = mode; 910 len = xfer->len; 911 i++; 912 } 913 if (i) { 914 /* Set final transfer data length and sequence length */ 915 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 916 rspi_write8(rspi, i - 1, RSPI_SPSCR); 917 } 918 919 return 0; 920 } 921 922 static int rspi_prepare_message(struct spi_controller *ctlr, 923 struct spi_message *msg) 924 { 925 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 926 struct spi_device *spi = msg->spi; 927 int ret; 928 929 rspi->max_speed_hz = spi->max_speed_hz; 930 931 rspi->spcmd = SPCMD_SSLKP; 932 if (spi->mode & SPI_CPOL) 933 rspi->spcmd |= SPCMD_CPOL; 934 if (spi->mode & SPI_CPHA) 935 rspi->spcmd |= SPCMD_CPHA; 936 937 /* Configure slave signal to assert */ 938 rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs 939 : spi->chip_select); 940 941 /* CMOS output mode and MOSI signal from previous transfer */ 942 rspi->sppcr = 0; 943 if (spi->mode & SPI_LOOP) 944 rspi->sppcr |= SPPCR_SPLP; 945 946 rspi->ops->set_config_register(rspi, 8); 947 948 if (msg->spi->mode & 949 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { 950 /* Setup sequencer for messages with multiple transfer modes */ 951 ret = qspi_setup_sequencer(rspi, msg); 952 if (ret < 0) 953 return ret; 954 } 955 956 /* Enable SPI function in master mode */ 957 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); 958 return 0; 959 } 960 961 static int rspi_unprepare_message(struct spi_controller *ctlr, 962 struct spi_message *msg) 963 { 964 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 965 966 /* Disable SPI function */ 967 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 968 969 /* Reset sequencer for Single SPI Transfers */ 970 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 971 rspi_write8(rspi, 0, RSPI_SPSCR); 972 return 0; 973 } 974 975 static irqreturn_t rspi_irq_mux(int irq, void *_sr) 976 { 977 struct rspi_data *rspi = _sr; 978 u8 spsr; 979 irqreturn_t ret = IRQ_NONE; 980 u8 disable_irq = 0; 981 982 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 983 if (spsr & SPSR_SPRF) 984 disable_irq |= SPCR_SPRIE; 985 if (spsr & SPSR_SPTEF) 986 disable_irq |= SPCR_SPTIE; 987 988 if (disable_irq) { 989 ret = IRQ_HANDLED; 990 rspi_disable_irq(rspi, disable_irq); 991 wake_up(&rspi->wait); 992 } 993 994 return ret; 995 } 996 997 static irqreturn_t rspi_irq_rx(int irq, void *_sr) 998 { 999 struct rspi_data *rspi = _sr; 1000 u8 spsr; 1001 1002 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 1003 if (spsr & SPSR_SPRF) { 1004 rspi_disable_irq(rspi, SPCR_SPRIE); 1005 wake_up(&rspi->wait); 1006 return IRQ_HANDLED; 1007 } 1008 1009 return 0; 1010 } 1011 1012 static irqreturn_t rspi_irq_tx(int irq, void *_sr) 1013 { 1014 struct rspi_data *rspi = _sr; 1015 u8 spsr; 1016 1017 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 1018 if (spsr & SPSR_SPTEF) { 1019 rspi_disable_irq(rspi, SPCR_SPTIE); 1020 wake_up(&rspi->wait); 1021 return IRQ_HANDLED; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static struct dma_chan *rspi_request_dma_chan(struct device *dev, 1028 enum dma_transfer_direction dir, 1029 unsigned int id, 1030 dma_addr_t port_addr) 1031 { 1032 dma_cap_mask_t mask; 1033 struct dma_chan *chan; 1034 struct dma_slave_config cfg; 1035 int ret; 1036 1037 dma_cap_zero(mask); 1038 dma_cap_set(DMA_SLAVE, mask); 1039 1040 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 1041 (void *)(unsigned long)id, dev, 1042 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1043 if (!chan) { 1044 dev_warn(dev, "dma_request_slave_channel_compat failed\n"); 1045 return NULL; 1046 } 1047 1048 memset(&cfg, 0, sizeof(cfg)); 1049 cfg.direction = dir; 1050 if (dir == DMA_MEM_TO_DEV) { 1051 cfg.dst_addr = port_addr; 1052 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1053 } else { 1054 cfg.src_addr = port_addr; 1055 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1056 } 1057 1058 ret = dmaengine_slave_config(chan, &cfg); 1059 if (ret) { 1060 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 1061 dma_release_channel(chan); 1062 return NULL; 1063 } 1064 1065 return chan; 1066 } 1067 1068 static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr, 1069 const struct resource *res) 1070 { 1071 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev); 1072 unsigned int dma_tx_id, dma_rx_id; 1073 1074 if (dev->of_node) { 1075 /* In the OF case we will get the slave IDs from the DT */ 1076 dma_tx_id = 0; 1077 dma_rx_id = 0; 1078 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) { 1079 dma_tx_id = rspi_pd->dma_tx_id; 1080 dma_rx_id = rspi_pd->dma_rx_id; 1081 } else { 1082 /* The driver assumes no error. */ 1083 return 0; 1084 } 1085 1086 ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id, 1087 res->start + RSPI_SPDR); 1088 if (!ctlr->dma_tx) 1089 return -ENODEV; 1090 1091 ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id, 1092 res->start + RSPI_SPDR); 1093 if (!ctlr->dma_rx) { 1094 dma_release_channel(ctlr->dma_tx); 1095 ctlr->dma_tx = NULL; 1096 return -ENODEV; 1097 } 1098 1099 ctlr->can_dma = rspi_can_dma; 1100 dev_info(dev, "DMA available"); 1101 return 0; 1102 } 1103 1104 static void rspi_release_dma(struct spi_controller *ctlr) 1105 { 1106 if (ctlr->dma_tx) 1107 dma_release_channel(ctlr->dma_tx); 1108 if (ctlr->dma_rx) 1109 dma_release_channel(ctlr->dma_rx); 1110 } 1111 1112 static int rspi_remove(struct platform_device *pdev) 1113 { 1114 struct rspi_data *rspi = platform_get_drvdata(pdev); 1115 1116 rspi_release_dma(rspi->ctlr); 1117 pm_runtime_disable(&pdev->dev); 1118 1119 return 0; 1120 } 1121 1122 static const struct spi_ops rspi_ops = { 1123 .set_config_register = rspi_set_config_register, 1124 .transfer_one = rspi_transfer_one, 1125 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 1126 .flags = SPI_CONTROLLER_MUST_TX, 1127 .fifo_size = 8, 1128 .num_hw_ss = 2, 1129 }; 1130 1131 static const struct spi_ops rspi_rz_ops = { 1132 .set_config_register = rspi_rz_set_config_register, 1133 .transfer_one = rspi_rz_transfer_one, 1134 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 1135 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, 1136 .fifo_size = 8, /* 8 for TX, 32 for RX */ 1137 .num_hw_ss = 1, 1138 }; 1139 1140 static const struct spi_ops qspi_ops = { 1141 .set_config_register = qspi_set_config_register, 1142 .transfer_one = qspi_transfer_one, 1143 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | 1144 SPI_TX_DUAL | SPI_TX_QUAD | 1145 SPI_RX_DUAL | SPI_RX_QUAD, 1146 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, 1147 .fifo_size = 32, 1148 .num_hw_ss = 1, 1149 }; 1150 1151 #ifdef CONFIG_OF 1152 static const struct of_device_id rspi_of_match[] = { 1153 /* RSPI on legacy SH */ 1154 { .compatible = "renesas,rspi", .data = &rspi_ops }, 1155 /* RSPI on RZ/A1H */ 1156 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, 1157 /* QSPI on R-Car Gen2 */ 1158 { .compatible = "renesas,qspi", .data = &qspi_ops }, 1159 { /* sentinel */ } 1160 }; 1161 1162 MODULE_DEVICE_TABLE(of, rspi_of_match); 1163 1164 static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr) 1165 { 1166 u32 num_cs; 1167 int error; 1168 1169 /* Parse DT properties */ 1170 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); 1171 if (error) { 1172 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); 1173 return error; 1174 } 1175 1176 ctlr->num_chipselect = num_cs; 1177 return 0; 1178 } 1179 #else 1180 #define rspi_of_match NULL 1181 static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr) 1182 { 1183 return -EINVAL; 1184 } 1185 #endif /* CONFIG_OF */ 1186 1187 static int rspi_request_irq(struct device *dev, unsigned int irq, 1188 irq_handler_t handler, const char *suffix, 1189 void *dev_id) 1190 { 1191 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", 1192 dev_name(dev), suffix); 1193 if (!name) 1194 return -ENOMEM; 1195 1196 return devm_request_irq(dev, irq, handler, 0, name, dev_id); 1197 } 1198 1199 static int rspi_probe(struct platform_device *pdev) 1200 { 1201 struct resource *res; 1202 struct spi_controller *ctlr; 1203 struct rspi_data *rspi; 1204 int ret; 1205 const struct rspi_plat_data *rspi_pd; 1206 const struct spi_ops *ops; 1207 1208 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 1209 if (ctlr == NULL) 1210 return -ENOMEM; 1211 1212 ops = of_device_get_match_data(&pdev->dev); 1213 if (ops) { 1214 ret = rspi_parse_dt(&pdev->dev, ctlr); 1215 if (ret) 1216 goto error1; 1217 } else { 1218 ops = (struct spi_ops *)pdev->id_entry->driver_data; 1219 rspi_pd = dev_get_platdata(&pdev->dev); 1220 if (rspi_pd && rspi_pd->num_chipselect) 1221 ctlr->num_chipselect = rspi_pd->num_chipselect; 1222 else 1223 ctlr->num_chipselect = 2; /* default */ 1224 } 1225 1226 /* ops parameter check */ 1227 if (!ops->set_config_register) { 1228 dev_err(&pdev->dev, "there is no set_config_register\n"); 1229 ret = -ENODEV; 1230 goto error1; 1231 } 1232 1233 rspi = spi_controller_get_devdata(ctlr); 1234 platform_set_drvdata(pdev, rspi); 1235 rspi->ops = ops; 1236 rspi->ctlr = ctlr; 1237 1238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1239 rspi->addr = devm_ioremap_resource(&pdev->dev, res); 1240 if (IS_ERR(rspi->addr)) { 1241 ret = PTR_ERR(rspi->addr); 1242 goto error1; 1243 } 1244 1245 rspi->clk = devm_clk_get(&pdev->dev, NULL); 1246 if (IS_ERR(rspi->clk)) { 1247 dev_err(&pdev->dev, "cannot get clock\n"); 1248 ret = PTR_ERR(rspi->clk); 1249 goto error1; 1250 } 1251 1252 pm_runtime_enable(&pdev->dev); 1253 1254 init_waitqueue_head(&rspi->wait); 1255 1256 ctlr->bus_num = pdev->id; 1257 ctlr->auto_runtime_pm = true; 1258 ctlr->transfer_one = ops->transfer_one; 1259 ctlr->prepare_message = rspi_prepare_message; 1260 ctlr->unprepare_message = rspi_unprepare_message; 1261 ctlr->mode_bits = ops->mode_bits; 1262 ctlr->flags = ops->flags; 1263 ctlr->dev.of_node = pdev->dev.of_node; 1264 ctlr->use_gpio_descriptors = true; 1265 ctlr->max_native_cs = rspi->ops->num_hw_ss; 1266 1267 ret = platform_get_irq_byname_optional(pdev, "rx"); 1268 if (ret < 0) { 1269 ret = platform_get_irq_byname_optional(pdev, "mux"); 1270 if (ret < 0) 1271 ret = platform_get_irq(pdev, 0); 1272 if (ret >= 0) 1273 rspi->rx_irq = rspi->tx_irq = ret; 1274 } else { 1275 rspi->rx_irq = ret; 1276 ret = platform_get_irq_byname(pdev, "tx"); 1277 if (ret >= 0) 1278 rspi->tx_irq = ret; 1279 } 1280 1281 if (rspi->rx_irq == rspi->tx_irq) { 1282 /* Single multiplexed interrupt */ 1283 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, 1284 "mux", rspi); 1285 } else { 1286 /* Multi-interrupt mode, only SPRI and SPTI are used */ 1287 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, 1288 "rx", rspi); 1289 if (!ret) 1290 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, 1291 rspi_irq_tx, "tx", rspi); 1292 } 1293 if (ret < 0) { 1294 dev_err(&pdev->dev, "request_irq error\n"); 1295 goto error2; 1296 } 1297 1298 ret = rspi_request_dma(&pdev->dev, ctlr, res); 1299 if (ret < 0) 1300 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1301 1302 ret = devm_spi_register_controller(&pdev->dev, ctlr); 1303 if (ret < 0) { 1304 dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); 1305 goto error3; 1306 } 1307 1308 dev_info(&pdev->dev, "probed\n"); 1309 1310 return 0; 1311 1312 error3: 1313 rspi_release_dma(ctlr); 1314 error2: 1315 pm_runtime_disable(&pdev->dev); 1316 error1: 1317 spi_controller_put(ctlr); 1318 1319 return ret; 1320 } 1321 1322 static const struct platform_device_id spi_driver_ids[] = { 1323 { "rspi", (kernel_ulong_t)&rspi_ops }, 1324 {}, 1325 }; 1326 1327 MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1328 1329 #ifdef CONFIG_PM_SLEEP 1330 static int rspi_suspend(struct device *dev) 1331 { 1332 struct rspi_data *rspi = dev_get_drvdata(dev); 1333 1334 return spi_controller_suspend(rspi->ctlr); 1335 } 1336 1337 static int rspi_resume(struct device *dev) 1338 { 1339 struct rspi_data *rspi = dev_get_drvdata(dev); 1340 1341 return spi_controller_resume(rspi->ctlr); 1342 } 1343 1344 static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume); 1345 #define DEV_PM_OPS &rspi_pm_ops 1346 #else 1347 #define DEV_PM_OPS NULL 1348 #endif /* CONFIG_PM_SLEEP */ 1349 1350 static struct platform_driver rspi_driver = { 1351 .probe = rspi_probe, 1352 .remove = rspi_remove, 1353 .id_table = spi_driver_ids, 1354 .driver = { 1355 .name = "renesas_spi", 1356 .pm = DEV_PM_OPS, 1357 .of_match_table = of_match_ptr(rspi_of_match), 1358 }, 1359 }; 1360 module_platform_driver(rspi_driver); 1361 1362 MODULE_DESCRIPTION("Renesas RSPI bus driver"); 1363 MODULE_LICENSE("GPL v2"); 1364 MODULE_AUTHOR("Yoshihiro Shimoda"); 1365 MODULE_ALIAS("platform:rspi"); 1366