1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH RSPI driver 4 * 5 * Copyright (C) 2012, 2013 Renesas Solutions Corp. 6 * Copyright (C) 2014 Glider bvba 7 * 8 * Based on spi-sh.c: 9 * Copyright (C) 2011 Renesas Solutions Corp. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/sched.h> 15 #include <linux/errno.h> 16 #include <linux/interrupt.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/clk.h> 20 #include <linux/dmaengine.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/of_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/sh_dma.h> 25 #include <linux/spi/spi.h> 26 #include <linux/spi/rspi.h> 27 28 #define RSPI_SPCR 0x00 /* Control Register */ 29 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ 30 #define RSPI_SPPCR 0x02 /* Pin Control Register */ 31 #define RSPI_SPSR 0x03 /* Status Register */ 32 #define RSPI_SPDR 0x04 /* Data Register */ 33 #define RSPI_SPSCR 0x08 /* Sequence Control Register */ 34 #define RSPI_SPSSR 0x09 /* Sequence Status Register */ 35 #define RSPI_SPBR 0x0a /* Bit Rate Register */ 36 #define RSPI_SPDCR 0x0b /* Data Control Register */ 37 #define RSPI_SPCKD 0x0c /* Clock Delay Register */ 38 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ 39 #define RSPI_SPND 0x0e /* Next-Access Delay Register */ 40 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ 41 #define RSPI_SPCMD0 0x10 /* Command Register 0 */ 42 #define RSPI_SPCMD1 0x12 /* Command Register 1 */ 43 #define RSPI_SPCMD2 0x14 /* Command Register 2 */ 44 #define RSPI_SPCMD3 0x16 /* Command Register 3 */ 45 #define RSPI_SPCMD4 0x18 /* Command Register 4 */ 46 #define RSPI_SPCMD5 0x1a /* Command Register 5 */ 47 #define RSPI_SPCMD6 0x1c /* Command Register 6 */ 48 #define RSPI_SPCMD7 0x1e /* Command Register 7 */ 49 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) 50 #define RSPI_NUM_SPCMD 8 51 #define RSPI_RZ_NUM_SPCMD 4 52 #define QSPI_NUM_SPCMD 4 53 54 /* RSPI on RZ only */ 55 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ 56 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ 57 58 /* QSPI only */ 59 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ 60 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ 61 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ 62 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ 63 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ 64 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ 65 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) 66 67 /* SPCR - Control Register */ 68 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ 69 #define SPCR_SPE 0x40 /* Function Enable */ 70 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ 71 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ 72 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ 73 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ 74 /* RSPI on SH only */ 75 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ 76 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ 77 /* QSPI on R-Car Gen2 only */ 78 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ 79 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ 80 81 /* SSLP - Slave Select Polarity Register */ 82 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ 83 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ 84 85 /* SPPCR - Pin Control Register */ 86 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ 87 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ 88 #define SPPCR_SPOM 0x04 89 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ 90 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ 91 92 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ 93 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ 94 95 /* SPSR - Status Register */ 96 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ 97 #define SPSR_TEND 0x40 /* Transmit End */ 98 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ 99 #define SPSR_PERF 0x08 /* Parity Error Flag */ 100 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ 101 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ 102 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ 103 104 /* SPSCR - Sequence Control Register */ 105 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ 106 107 /* SPSSR - Sequence Status Register */ 108 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ 109 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ 110 111 /* SPDCR - Data Control Register */ 112 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ 113 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ 114 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ 115 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) 116 #define SPDCR_SPLWORD SPDCR_SPLW1 117 #define SPDCR_SPLBYTE SPDCR_SPLW0 118 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ 119 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ 120 #define SPDCR_SLSEL1 0x08 121 #define SPDCR_SLSEL0 0x04 122 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ 123 #define SPDCR_SPFC1 0x02 124 #define SPDCR_SPFC0 0x01 125 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ 126 127 /* SPCKD - Clock Delay Register */ 128 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ 129 130 /* SSLND - Slave Select Negation Delay Register */ 131 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ 132 133 /* SPND - Next-Access Delay Register */ 134 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ 135 136 /* SPCR2 - Control Register 2 */ 137 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ 138 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ 139 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ 140 #define SPCR2_SPPE 0x01 /* Parity Enable */ 141 142 /* SPCMDn - Command Registers */ 143 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ 144 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ 145 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ 146 #define SPCMD_LSBF 0x1000 /* LSB First */ 147 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ 148 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 149 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ 150 #define SPCMD_SPB_16BIT 0x0100 151 #define SPCMD_SPB_20BIT 0x0000 152 #define SPCMD_SPB_24BIT 0x0100 153 #define SPCMD_SPB_32BIT 0x0200 154 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ 155 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ 156 #define SPCMD_SPIMOD1 0x0040 157 #define SPCMD_SPIMOD0 0x0020 158 #define SPCMD_SPIMOD_SINGLE 0 159 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 160 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 161 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ 162 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ 163 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ 164 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ 165 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ 166 167 /* SPBFCR - Buffer Control Register */ 168 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ 169 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ 170 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 171 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 172 /* QSPI on R-Car Gen2 */ 173 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */ 174 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */ 175 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */ 176 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */ 177 178 #define QSPI_BUFFER_SIZE 32u 179 180 struct rspi_data { 181 void __iomem *addr; 182 u32 max_speed_hz; 183 struct spi_controller *ctlr; 184 wait_queue_head_t wait; 185 struct clk *clk; 186 u16 spcmd; 187 u8 spsr; 188 u8 sppcr; 189 int rx_irq, tx_irq; 190 const struct spi_ops *ops; 191 192 unsigned dma_callbacked:1; 193 unsigned byte_access:1; 194 }; 195 196 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) 197 { 198 iowrite8(data, rspi->addr + offset); 199 } 200 201 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) 202 { 203 iowrite16(data, rspi->addr + offset); 204 } 205 206 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) 207 { 208 iowrite32(data, rspi->addr + offset); 209 } 210 211 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) 212 { 213 return ioread8(rspi->addr + offset); 214 } 215 216 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) 217 { 218 return ioread16(rspi->addr + offset); 219 } 220 221 static void rspi_write_data(const struct rspi_data *rspi, u16 data) 222 { 223 if (rspi->byte_access) 224 rspi_write8(rspi, data, RSPI_SPDR); 225 else /* 16 bit */ 226 rspi_write16(rspi, data, RSPI_SPDR); 227 } 228 229 static u16 rspi_read_data(const struct rspi_data *rspi) 230 { 231 if (rspi->byte_access) 232 return rspi_read8(rspi, RSPI_SPDR); 233 else /* 16 bit */ 234 return rspi_read16(rspi, RSPI_SPDR); 235 } 236 237 /* optional functions */ 238 struct spi_ops { 239 int (*set_config_register)(struct rspi_data *rspi, int access_size); 240 int (*transfer_one)(struct spi_controller *ctlr, 241 struct spi_device *spi, struct spi_transfer *xfer); 242 u16 mode_bits; 243 u16 flags; 244 u16 fifo_size; 245 }; 246 247 /* 248 * functions for RSPI on legacy SH 249 */ 250 static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 251 { 252 int spbr; 253 254 /* Sets output mode, MOSI signal, and (optionally) loopback */ 255 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 256 257 /* Sets transfer bit rate */ 258 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 259 2 * rspi->max_speed_hz) - 1; 260 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 261 262 /* Disable dummy transmission, set 16-bit word access, 1 frame */ 263 rspi_write8(rspi, 0, RSPI_SPDCR); 264 rspi->byte_access = 0; 265 266 /* Sets RSPCK, SSL, next-access delay value */ 267 rspi_write8(rspi, 0x00, RSPI_SPCKD); 268 rspi_write8(rspi, 0x00, RSPI_SSLND); 269 rspi_write8(rspi, 0x00, RSPI_SPND); 270 271 /* Sets parity, interrupt mask */ 272 rspi_write8(rspi, 0x00, RSPI_SPCR2); 273 274 /* Resets sequencer */ 275 rspi_write8(rspi, 0, RSPI_SPSCR); 276 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 277 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 278 279 /* Sets RSPI mode */ 280 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 281 282 return 0; 283 } 284 285 /* 286 * functions for RSPI on RZ 287 */ 288 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) 289 { 290 int spbr; 291 int div = 0; 292 unsigned long clksrc; 293 294 /* Sets output mode, MOSI signal, and (optionally) loopback */ 295 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 296 297 clksrc = clk_get_rate(rspi->clk); 298 while (div < 3) { 299 if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */ 300 break; 301 div++; 302 clksrc /= 2; 303 } 304 305 /* Sets transfer bit rate */ 306 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1; 307 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 308 rspi->spcmd |= div << 2; 309 310 /* Disable dummy transmission, set byte access */ 311 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); 312 rspi->byte_access = 1; 313 314 /* Sets RSPCK, SSL, next-access delay value */ 315 rspi_write8(rspi, 0x00, RSPI_SPCKD); 316 rspi_write8(rspi, 0x00, RSPI_SSLND); 317 rspi_write8(rspi, 0x00, RSPI_SPND); 318 319 /* Resets sequencer */ 320 rspi_write8(rspi, 0, RSPI_SPSCR); 321 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 322 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 323 324 /* Sets RSPI mode */ 325 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 326 327 return 0; 328 } 329 330 /* 331 * functions for QSPI 332 */ 333 static int qspi_set_config_register(struct rspi_data *rspi, int access_size) 334 { 335 int spbr; 336 337 /* Sets output mode, MOSI signal, and (optionally) loopback */ 338 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 339 340 /* Sets transfer bit rate */ 341 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz); 342 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 343 344 /* Disable dummy transmission, set byte access */ 345 rspi_write8(rspi, 0, RSPI_SPDCR); 346 rspi->byte_access = 1; 347 348 /* Sets RSPCK, SSL, next-access delay value */ 349 rspi_write8(rspi, 0x00, RSPI_SPCKD); 350 rspi_write8(rspi, 0x00, RSPI_SSLND); 351 rspi_write8(rspi, 0x00, RSPI_SPND); 352 353 /* Data Length Setting */ 354 if (access_size == 8) 355 rspi->spcmd |= SPCMD_SPB_8BIT; 356 else if (access_size == 16) 357 rspi->spcmd |= SPCMD_SPB_16BIT; 358 else 359 rspi->spcmd |= SPCMD_SPB_32BIT; 360 361 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; 362 363 /* Resets transfer data length */ 364 rspi_write32(rspi, 0, QSPI_SPBMUL0); 365 366 /* Resets transmit and receive buffer */ 367 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 368 /* Sets buffer to allow normal operation */ 369 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 370 371 /* Resets sequencer */ 372 rspi_write8(rspi, 0, RSPI_SPSCR); 373 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 374 375 /* Sets RSPI mode */ 376 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 377 378 return 0; 379 } 380 381 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg) 382 { 383 u8 data; 384 385 data = rspi_read8(rspi, reg); 386 data &= ~mask; 387 data |= (val & mask); 388 rspi_write8(rspi, data, reg); 389 } 390 391 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi, 392 unsigned int len) 393 { 394 unsigned int n; 395 396 n = min(len, QSPI_BUFFER_SIZE); 397 398 if (len >= QSPI_BUFFER_SIZE) { 399 /* sets triggering number to 32 bytes */ 400 qspi_update(rspi, SPBFCR_TXTRG_MASK, 401 SPBFCR_TXTRG_32B, QSPI_SPBFCR); 402 } else { 403 /* sets triggering number to 1 byte */ 404 qspi_update(rspi, SPBFCR_TXTRG_MASK, 405 SPBFCR_TXTRG_1B, QSPI_SPBFCR); 406 } 407 408 return n; 409 } 410 411 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len) 412 { 413 unsigned int n; 414 415 n = min(len, QSPI_BUFFER_SIZE); 416 417 if (len >= QSPI_BUFFER_SIZE) { 418 /* sets triggering number to 32 bytes */ 419 qspi_update(rspi, SPBFCR_RXTRG_MASK, 420 SPBFCR_RXTRG_32B, QSPI_SPBFCR); 421 } else { 422 /* sets triggering number to 1 byte */ 423 qspi_update(rspi, SPBFCR_RXTRG_MASK, 424 SPBFCR_RXTRG_1B, QSPI_SPBFCR); 425 } 426 return n; 427 } 428 429 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) 430 431 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) 432 { 433 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); 434 } 435 436 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) 437 { 438 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); 439 } 440 441 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, 442 u8 enable_bit) 443 { 444 int ret; 445 446 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 447 if (rspi->spsr & wait_mask) 448 return 0; 449 450 rspi_enable_irq(rspi, enable_bit); 451 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 452 if (ret == 0 && !(rspi->spsr & wait_mask)) 453 return -ETIMEDOUT; 454 455 return 0; 456 } 457 458 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi) 459 { 460 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 461 } 462 463 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi) 464 { 465 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE); 466 } 467 468 static int rspi_data_out(struct rspi_data *rspi, u8 data) 469 { 470 int error = rspi_wait_for_tx_empty(rspi); 471 if (error < 0) { 472 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); 473 return error; 474 } 475 rspi_write_data(rspi, data); 476 return 0; 477 } 478 479 static int rspi_data_in(struct rspi_data *rspi) 480 { 481 int error; 482 u8 data; 483 484 error = rspi_wait_for_rx_full(rspi); 485 if (error < 0) { 486 dev_err(&rspi->ctlr->dev, "receive timeout\n"); 487 return error; 488 } 489 data = rspi_read_data(rspi); 490 return data; 491 } 492 493 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx, 494 unsigned int n) 495 { 496 while (n-- > 0) { 497 if (tx) { 498 int ret = rspi_data_out(rspi, *tx++); 499 if (ret < 0) 500 return ret; 501 } 502 if (rx) { 503 int ret = rspi_data_in(rspi); 504 if (ret < 0) 505 return ret; 506 *rx++ = ret; 507 } 508 } 509 510 return 0; 511 } 512 513 static void rspi_dma_complete(void *arg) 514 { 515 struct rspi_data *rspi = arg; 516 517 rspi->dma_callbacked = 1; 518 wake_up_interruptible(&rspi->wait); 519 } 520 521 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, 522 struct sg_table *rx) 523 { 524 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 525 u8 irq_mask = 0; 526 unsigned int other_irq = 0; 527 dma_cookie_t cookie; 528 int ret; 529 530 /* First prepare and submit the DMA request(s), as this may fail */ 531 if (rx) { 532 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl, 533 rx->nents, DMA_DEV_TO_MEM, 534 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 535 if (!desc_rx) { 536 ret = -EAGAIN; 537 goto no_dma_rx; 538 } 539 540 desc_rx->callback = rspi_dma_complete; 541 desc_rx->callback_param = rspi; 542 cookie = dmaengine_submit(desc_rx); 543 if (dma_submit_error(cookie)) { 544 ret = cookie; 545 goto no_dma_rx; 546 } 547 548 irq_mask |= SPCR_SPRIE; 549 } 550 551 if (tx) { 552 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl, 553 tx->nents, DMA_MEM_TO_DEV, 554 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 555 if (!desc_tx) { 556 ret = -EAGAIN; 557 goto no_dma_tx; 558 } 559 560 if (rx) { 561 /* No callback */ 562 desc_tx->callback = NULL; 563 } else { 564 desc_tx->callback = rspi_dma_complete; 565 desc_tx->callback_param = rspi; 566 } 567 cookie = dmaengine_submit(desc_tx); 568 if (dma_submit_error(cookie)) { 569 ret = cookie; 570 goto no_dma_tx; 571 } 572 573 irq_mask |= SPCR_SPTIE; 574 } 575 576 /* 577 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be 578 * called. So, this driver disables the IRQ while DMA transfer. 579 */ 580 if (tx) 581 disable_irq(other_irq = rspi->tx_irq); 582 if (rx && rspi->rx_irq != other_irq) 583 disable_irq(rspi->rx_irq); 584 585 rspi_enable_irq(rspi, irq_mask); 586 rspi->dma_callbacked = 0; 587 588 /* Now start DMA */ 589 if (rx) 590 dma_async_issue_pending(rspi->ctlr->dma_rx); 591 if (tx) 592 dma_async_issue_pending(rspi->ctlr->dma_tx); 593 594 ret = wait_event_interruptible_timeout(rspi->wait, 595 rspi->dma_callbacked, HZ); 596 if (ret > 0 && rspi->dma_callbacked) { 597 ret = 0; 598 } else { 599 if (!ret) { 600 dev_err(&rspi->ctlr->dev, "DMA timeout\n"); 601 ret = -ETIMEDOUT; 602 } 603 if (tx) 604 dmaengine_terminate_all(rspi->ctlr->dma_tx); 605 if (rx) 606 dmaengine_terminate_all(rspi->ctlr->dma_rx); 607 } 608 609 rspi_disable_irq(rspi, irq_mask); 610 611 if (tx) 612 enable_irq(rspi->tx_irq); 613 if (rx && rspi->rx_irq != other_irq) 614 enable_irq(rspi->rx_irq); 615 616 return ret; 617 618 no_dma_tx: 619 if (rx) 620 dmaengine_terminate_all(rspi->ctlr->dma_rx); 621 no_dma_rx: 622 if (ret == -EAGAIN) { 623 pr_warn_once("%s %s: DMA not available, falling back to PIO\n", 624 dev_driver_string(&rspi->ctlr->dev), 625 dev_name(&rspi->ctlr->dev)); 626 } 627 return ret; 628 } 629 630 static void rspi_receive_init(const struct rspi_data *rspi) 631 { 632 u8 spsr; 633 634 spsr = rspi_read8(rspi, RSPI_SPSR); 635 if (spsr & SPSR_SPRF) 636 rspi_read_data(rspi); /* dummy read */ 637 if (spsr & SPSR_OVRF) 638 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 639 RSPI_SPSR); 640 } 641 642 static void rspi_rz_receive_init(const struct rspi_data *rspi) 643 { 644 rspi_receive_init(rspi); 645 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); 646 rspi_write8(rspi, 0, RSPI_SPBFCR); 647 } 648 649 static void qspi_receive_init(const struct rspi_data *rspi) 650 { 651 u8 spsr; 652 653 spsr = rspi_read8(rspi, RSPI_SPSR); 654 if (spsr & SPSR_SPRF) 655 rspi_read_data(rspi); /* dummy read */ 656 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 657 rspi_write8(rspi, 0, QSPI_SPBFCR); 658 } 659 660 static bool __rspi_can_dma(const struct rspi_data *rspi, 661 const struct spi_transfer *xfer) 662 { 663 return xfer->len > rspi->ops->fifo_size; 664 } 665 666 static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi, 667 struct spi_transfer *xfer) 668 { 669 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 670 671 return __rspi_can_dma(rspi, xfer); 672 } 673 674 static int rspi_dma_check_then_transfer(struct rspi_data *rspi, 675 struct spi_transfer *xfer) 676 { 677 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer)) 678 return -EAGAIN; 679 680 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ 681 return rspi_dma_transfer(rspi, &xfer->tx_sg, 682 xfer->rx_buf ? &xfer->rx_sg : NULL); 683 } 684 685 static int rspi_common_transfer(struct rspi_data *rspi, 686 struct spi_transfer *xfer) 687 { 688 int ret; 689 690 ret = rspi_dma_check_then_transfer(rspi, xfer); 691 if (ret != -EAGAIN) 692 return ret; 693 694 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); 695 if (ret < 0) 696 return ret; 697 698 /* Wait for the last transmission */ 699 rspi_wait_for_tx_empty(rspi); 700 701 return 0; 702 } 703 704 static int rspi_transfer_one(struct spi_controller *ctlr, 705 struct spi_device *spi, struct spi_transfer *xfer) 706 { 707 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 708 u8 spcr; 709 710 spcr = rspi_read8(rspi, RSPI_SPCR); 711 if (xfer->rx_buf) { 712 rspi_receive_init(rspi); 713 spcr &= ~SPCR_TXMD; 714 } else { 715 spcr |= SPCR_TXMD; 716 } 717 rspi_write8(rspi, spcr, RSPI_SPCR); 718 719 return rspi_common_transfer(rspi, xfer); 720 } 721 722 static int rspi_rz_transfer_one(struct spi_controller *ctlr, 723 struct spi_device *spi, 724 struct spi_transfer *xfer) 725 { 726 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 727 728 rspi_rz_receive_init(rspi); 729 730 return rspi_common_transfer(rspi, xfer); 731 } 732 733 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx, 734 u8 *rx, unsigned int len) 735 { 736 unsigned int i, n; 737 int ret; 738 739 while (len > 0) { 740 n = qspi_set_send_trigger(rspi, len); 741 qspi_set_receive_trigger(rspi, len); 742 ret = rspi_wait_for_tx_empty(rspi); 743 if (ret < 0) { 744 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); 745 return ret; 746 } 747 for (i = 0; i < n; i++) 748 rspi_write_data(rspi, *tx++); 749 750 ret = rspi_wait_for_rx_full(rspi); 751 if (ret < 0) { 752 dev_err(&rspi->ctlr->dev, "receive timeout\n"); 753 return ret; 754 } 755 for (i = 0; i < n; i++) 756 *rx++ = rspi_read_data(rspi); 757 758 len -= n; 759 } 760 761 return 0; 762 } 763 764 static int qspi_transfer_out_in(struct rspi_data *rspi, 765 struct spi_transfer *xfer) 766 { 767 int ret; 768 769 qspi_receive_init(rspi); 770 771 ret = rspi_dma_check_then_transfer(rspi, xfer); 772 if (ret != -EAGAIN) 773 return ret; 774 775 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf, 776 xfer->rx_buf, xfer->len); 777 } 778 779 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) 780 { 781 const u8 *tx = xfer->tx_buf; 782 unsigned int n = xfer->len; 783 unsigned int i, len; 784 int ret; 785 786 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { 787 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); 788 if (ret != -EAGAIN) 789 return ret; 790 } 791 792 while (n > 0) { 793 len = qspi_set_send_trigger(rspi, n); 794 ret = rspi_wait_for_tx_empty(rspi); 795 if (ret < 0) { 796 dev_err(&rspi->ctlr->dev, "transmit timeout\n"); 797 return ret; 798 } 799 for (i = 0; i < len; i++) 800 rspi_write_data(rspi, *tx++); 801 802 n -= len; 803 } 804 805 /* Wait for the last transmission */ 806 rspi_wait_for_tx_empty(rspi); 807 808 return 0; 809 } 810 811 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) 812 { 813 u8 *rx = xfer->rx_buf; 814 unsigned int n = xfer->len; 815 unsigned int i, len; 816 int ret; 817 818 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) { 819 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); 820 if (ret != -EAGAIN) 821 return ret; 822 } 823 824 while (n > 0) { 825 len = qspi_set_receive_trigger(rspi, n); 826 ret = rspi_wait_for_rx_full(rspi); 827 if (ret < 0) { 828 dev_err(&rspi->ctlr->dev, "receive timeout\n"); 829 return ret; 830 } 831 for (i = 0; i < len; i++) 832 *rx++ = rspi_read_data(rspi); 833 834 n -= len; 835 } 836 837 return 0; 838 } 839 840 static int qspi_transfer_one(struct spi_controller *ctlr, 841 struct spi_device *spi, struct spi_transfer *xfer) 842 { 843 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 844 845 if (spi->mode & SPI_LOOP) { 846 return qspi_transfer_out_in(rspi, xfer); 847 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { 848 /* Quad or Dual SPI Write */ 849 return qspi_transfer_out(rspi, xfer); 850 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) { 851 /* Quad or Dual SPI Read */ 852 return qspi_transfer_in(rspi, xfer); 853 } else { 854 /* Single SPI Transfer */ 855 return qspi_transfer_out_in(rspi, xfer); 856 } 857 } 858 859 static u16 qspi_transfer_mode(const struct spi_transfer *xfer) 860 { 861 if (xfer->tx_buf) 862 switch (xfer->tx_nbits) { 863 case SPI_NBITS_QUAD: 864 return SPCMD_SPIMOD_QUAD; 865 case SPI_NBITS_DUAL: 866 return SPCMD_SPIMOD_DUAL; 867 default: 868 return 0; 869 } 870 if (xfer->rx_buf) 871 switch (xfer->rx_nbits) { 872 case SPI_NBITS_QUAD: 873 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; 874 case SPI_NBITS_DUAL: 875 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; 876 default: 877 return 0; 878 } 879 880 return 0; 881 } 882 883 static int qspi_setup_sequencer(struct rspi_data *rspi, 884 const struct spi_message *msg) 885 { 886 const struct spi_transfer *xfer; 887 unsigned int i = 0, len = 0; 888 u16 current_mode = 0xffff, mode; 889 890 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 891 mode = qspi_transfer_mode(xfer); 892 if (mode == current_mode) { 893 len += xfer->len; 894 continue; 895 } 896 897 /* Transfer mode change */ 898 if (i) { 899 /* Set transfer data length of previous transfer */ 900 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 901 } 902 903 if (i >= QSPI_NUM_SPCMD) { 904 dev_err(&msg->spi->dev, 905 "Too many different transfer modes"); 906 return -EINVAL; 907 } 908 909 /* Program transfer mode for this transfer */ 910 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); 911 current_mode = mode; 912 len = xfer->len; 913 i++; 914 } 915 if (i) { 916 /* Set final transfer data length and sequence length */ 917 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 918 rspi_write8(rspi, i - 1, RSPI_SPSCR); 919 } 920 921 return 0; 922 } 923 924 static int rspi_prepare_message(struct spi_controller *ctlr, 925 struct spi_message *msg) 926 { 927 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 928 struct spi_device *spi = msg->spi; 929 int ret; 930 931 rspi->max_speed_hz = spi->max_speed_hz; 932 933 rspi->spcmd = SPCMD_SSLKP; 934 if (spi->mode & SPI_CPOL) 935 rspi->spcmd |= SPCMD_CPOL; 936 if (spi->mode & SPI_CPHA) 937 rspi->spcmd |= SPCMD_CPHA; 938 939 /* CMOS output mode and MOSI signal from previous transfer */ 940 rspi->sppcr = 0; 941 if (spi->mode & SPI_LOOP) 942 rspi->sppcr |= SPPCR_SPLP; 943 944 set_config_register(rspi, 8); 945 946 if (msg->spi->mode & 947 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { 948 /* Setup sequencer for messages with multiple transfer modes */ 949 ret = qspi_setup_sequencer(rspi, msg); 950 if (ret < 0) 951 return ret; 952 } 953 954 /* Enable SPI function in master mode */ 955 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); 956 return 0; 957 } 958 959 static int rspi_unprepare_message(struct spi_controller *ctlr, 960 struct spi_message *msg) 961 { 962 struct rspi_data *rspi = spi_controller_get_devdata(ctlr); 963 964 /* Disable SPI function */ 965 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 966 967 /* Reset sequencer for Single SPI Transfers */ 968 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 969 rspi_write8(rspi, 0, RSPI_SPSCR); 970 return 0; 971 } 972 973 static irqreturn_t rspi_irq_mux(int irq, void *_sr) 974 { 975 struct rspi_data *rspi = _sr; 976 u8 spsr; 977 irqreturn_t ret = IRQ_NONE; 978 u8 disable_irq = 0; 979 980 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 981 if (spsr & SPSR_SPRF) 982 disable_irq |= SPCR_SPRIE; 983 if (spsr & SPSR_SPTEF) 984 disable_irq |= SPCR_SPTIE; 985 986 if (disable_irq) { 987 ret = IRQ_HANDLED; 988 rspi_disable_irq(rspi, disable_irq); 989 wake_up(&rspi->wait); 990 } 991 992 return ret; 993 } 994 995 static irqreturn_t rspi_irq_rx(int irq, void *_sr) 996 { 997 struct rspi_data *rspi = _sr; 998 u8 spsr; 999 1000 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 1001 if (spsr & SPSR_SPRF) { 1002 rspi_disable_irq(rspi, SPCR_SPRIE); 1003 wake_up(&rspi->wait); 1004 return IRQ_HANDLED; 1005 } 1006 1007 return 0; 1008 } 1009 1010 static irqreturn_t rspi_irq_tx(int irq, void *_sr) 1011 { 1012 struct rspi_data *rspi = _sr; 1013 u8 spsr; 1014 1015 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 1016 if (spsr & SPSR_SPTEF) { 1017 rspi_disable_irq(rspi, SPCR_SPTIE); 1018 wake_up(&rspi->wait); 1019 return IRQ_HANDLED; 1020 } 1021 1022 return 0; 1023 } 1024 1025 static struct dma_chan *rspi_request_dma_chan(struct device *dev, 1026 enum dma_transfer_direction dir, 1027 unsigned int id, 1028 dma_addr_t port_addr) 1029 { 1030 dma_cap_mask_t mask; 1031 struct dma_chan *chan; 1032 struct dma_slave_config cfg; 1033 int ret; 1034 1035 dma_cap_zero(mask); 1036 dma_cap_set(DMA_SLAVE, mask); 1037 1038 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 1039 (void *)(unsigned long)id, dev, 1040 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1041 if (!chan) { 1042 dev_warn(dev, "dma_request_slave_channel_compat failed\n"); 1043 return NULL; 1044 } 1045 1046 memset(&cfg, 0, sizeof(cfg)); 1047 cfg.direction = dir; 1048 if (dir == DMA_MEM_TO_DEV) { 1049 cfg.dst_addr = port_addr; 1050 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1051 } else { 1052 cfg.src_addr = port_addr; 1053 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1054 } 1055 1056 ret = dmaengine_slave_config(chan, &cfg); 1057 if (ret) { 1058 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 1059 dma_release_channel(chan); 1060 return NULL; 1061 } 1062 1063 return chan; 1064 } 1065 1066 static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr, 1067 const struct resource *res) 1068 { 1069 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev); 1070 unsigned int dma_tx_id, dma_rx_id; 1071 1072 if (dev->of_node) { 1073 /* In the OF case we will get the slave IDs from the DT */ 1074 dma_tx_id = 0; 1075 dma_rx_id = 0; 1076 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) { 1077 dma_tx_id = rspi_pd->dma_tx_id; 1078 dma_rx_id = rspi_pd->dma_rx_id; 1079 } else { 1080 /* The driver assumes no error. */ 1081 return 0; 1082 } 1083 1084 ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id, 1085 res->start + RSPI_SPDR); 1086 if (!ctlr->dma_tx) 1087 return -ENODEV; 1088 1089 ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id, 1090 res->start + RSPI_SPDR); 1091 if (!ctlr->dma_rx) { 1092 dma_release_channel(ctlr->dma_tx); 1093 ctlr->dma_tx = NULL; 1094 return -ENODEV; 1095 } 1096 1097 ctlr->can_dma = rspi_can_dma; 1098 dev_info(dev, "DMA available"); 1099 return 0; 1100 } 1101 1102 static void rspi_release_dma(struct spi_controller *ctlr) 1103 { 1104 if (ctlr->dma_tx) 1105 dma_release_channel(ctlr->dma_tx); 1106 if (ctlr->dma_rx) 1107 dma_release_channel(ctlr->dma_rx); 1108 } 1109 1110 static int rspi_remove(struct platform_device *pdev) 1111 { 1112 struct rspi_data *rspi = platform_get_drvdata(pdev); 1113 1114 rspi_release_dma(rspi->ctlr); 1115 pm_runtime_disable(&pdev->dev); 1116 1117 return 0; 1118 } 1119 1120 static const struct spi_ops rspi_ops = { 1121 .set_config_register = rspi_set_config_register, 1122 .transfer_one = rspi_transfer_one, 1123 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 1124 .flags = SPI_CONTROLLER_MUST_TX, 1125 .fifo_size = 8, 1126 }; 1127 1128 static const struct spi_ops rspi_rz_ops = { 1129 .set_config_register = rspi_rz_set_config_register, 1130 .transfer_one = rspi_rz_transfer_one, 1131 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 1132 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, 1133 .fifo_size = 8, /* 8 for TX, 32 for RX */ 1134 }; 1135 1136 static const struct spi_ops qspi_ops = { 1137 .set_config_register = qspi_set_config_register, 1138 .transfer_one = qspi_transfer_one, 1139 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | 1140 SPI_TX_DUAL | SPI_TX_QUAD | 1141 SPI_RX_DUAL | SPI_RX_QUAD, 1142 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, 1143 .fifo_size = 32, 1144 }; 1145 1146 #ifdef CONFIG_OF 1147 static const struct of_device_id rspi_of_match[] = { 1148 /* RSPI on legacy SH */ 1149 { .compatible = "renesas,rspi", .data = &rspi_ops }, 1150 /* RSPI on RZ/A1H */ 1151 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, 1152 /* QSPI on R-Car Gen2 */ 1153 { .compatible = "renesas,qspi", .data = &qspi_ops }, 1154 { /* sentinel */ } 1155 }; 1156 1157 MODULE_DEVICE_TABLE(of, rspi_of_match); 1158 1159 static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr) 1160 { 1161 u32 num_cs; 1162 int error; 1163 1164 /* Parse DT properties */ 1165 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); 1166 if (error) { 1167 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); 1168 return error; 1169 } 1170 1171 ctlr->num_chipselect = num_cs; 1172 return 0; 1173 } 1174 #else 1175 #define rspi_of_match NULL 1176 static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr) 1177 { 1178 return -EINVAL; 1179 } 1180 #endif /* CONFIG_OF */ 1181 1182 static int rspi_request_irq(struct device *dev, unsigned int irq, 1183 irq_handler_t handler, const char *suffix, 1184 void *dev_id) 1185 { 1186 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", 1187 dev_name(dev), suffix); 1188 if (!name) 1189 return -ENOMEM; 1190 1191 return devm_request_irq(dev, irq, handler, 0, name, dev_id); 1192 } 1193 1194 static int rspi_probe(struct platform_device *pdev) 1195 { 1196 struct resource *res; 1197 struct spi_controller *ctlr; 1198 struct rspi_data *rspi; 1199 int ret; 1200 const struct rspi_plat_data *rspi_pd; 1201 const struct spi_ops *ops; 1202 1203 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 1204 if (ctlr == NULL) 1205 return -ENOMEM; 1206 1207 ops = of_device_get_match_data(&pdev->dev); 1208 if (ops) { 1209 ret = rspi_parse_dt(&pdev->dev, ctlr); 1210 if (ret) 1211 goto error1; 1212 } else { 1213 ops = (struct spi_ops *)pdev->id_entry->driver_data; 1214 rspi_pd = dev_get_platdata(&pdev->dev); 1215 if (rspi_pd && rspi_pd->num_chipselect) 1216 ctlr->num_chipselect = rspi_pd->num_chipselect; 1217 else 1218 ctlr->num_chipselect = 2; /* default */ 1219 } 1220 1221 /* ops parameter check */ 1222 if (!ops->set_config_register) { 1223 dev_err(&pdev->dev, "there is no set_config_register\n"); 1224 ret = -ENODEV; 1225 goto error1; 1226 } 1227 1228 rspi = spi_controller_get_devdata(ctlr); 1229 platform_set_drvdata(pdev, rspi); 1230 rspi->ops = ops; 1231 rspi->ctlr = ctlr; 1232 1233 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1234 rspi->addr = devm_ioremap_resource(&pdev->dev, res); 1235 if (IS_ERR(rspi->addr)) { 1236 ret = PTR_ERR(rspi->addr); 1237 goto error1; 1238 } 1239 1240 rspi->clk = devm_clk_get(&pdev->dev, NULL); 1241 if (IS_ERR(rspi->clk)) { 1242 dev_err(&pdev->dev, "cannot get clock\n"); 1243 ret = PTR_ERR(rspi->clk); 1244 goto error1; 1245 } 1246 1247 pm_runtime_enable(&pdev->dev); 1248 1249 init_waitqueue_head(&rspi->wait); 1250 1251 ctlr->bus_num = pdev->id; 1252 ctlr->auto_runtime_pm = true; 1253 ctlr->transfer_one = ops->transfer_one; 1254 ctlr->prepare_message = rspi_prepare_message; 1255 ctlr->unprepare_message = rspi_unprepare_message; 1256 ctlr->mode_bits = ops->mode_bits; 1257 ctlr->flags = ops->flags; 1258 ctlr->dev.of_node = pdev->dev.of_node; 1259 1260 ret = platform_get_irq_byname(pdev, "rx"); 1261 if (ret < 0) { 1262 ret = platform_get_irq_byname(pdev, "mux"); 1263 if (ret < 0) 1264 ret = platform_get_irq(pdev, 0); 1265 if (ret >= 0) 1266 rspi->rx_irq = rspi->tx_irq = ret; 1267 } else { 1268 rspi->rx_irq = ret; 1269 ret = platform_get_irq_byname(pdev, "tx"); 1270 if (ret >= 0) 1271 rspi->tx_irq = ret; 1272 } 1273 if (ret < 0) { 1274 dev_err(&pdev->dev, "platform_get_irq error\n"); 1275 goto error2; 1276 } 1277 1278 if (rspi->rx_irq == rspi->tx_irq) { 1279 /* Single multiplexed interrupt */ 1280 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, 1281 "mux", rspi); 1282 } else { 1283 /* Multi-interrupt mode, only SPRI and SPTI are used */ 1284 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, 1285 "rx", rspi); 1286 if (!ret) 1287 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, 1288 rspi_irq_tx, "tx", rspi); 1289 } 1290 if (ret < 0) { 1291 dev_err(&pdev->dev, "request_irq error\n"); 1292 goto error2; 1293 } 1294 1295 ret = rspi_request_dma(&pdev->dev, ctlr, res); 1296 if (ret < 0) 1297 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1298 1299 ret = devm_spi_register_controller(&pdev->dev, ctlr); 1300 if (ret < 0) { 1301 dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); 1302 goto error3; 1303 } 1304 1305 dev_info(&pdev->dev, "probed\n"); 1306 1307 return 0; 1308 1309 error3: 1310 rspi_release_dma(ctlr); 1311 error2: 1312 pm_runtime_disable(&pdev->dev); 1313 error1: 1314 spi_controller_put(ctlr); 1315 1316 return ret; 1317 } 1318 1319 static const struct platform_device_id spi_driver_ids[] = { 1320 { "rspi", (kernel_ulong_t)&rspi_ops }, 1321 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, 1322 { "qspi", (kernel_ulong_t)&qspi_ops }, 1323 {}, 1324 }; 1325 1326 MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1327 1328 #ifdef CONFIG_PM_SLEEP 1329 static int rspi_suspend(struct device *dev) 1330 { 1331 struct rspi_data *rspi = dev_get_drvdata(dev); 1332 1333 return spi_controller_suspend(rspi->ctlr); 1334 } 1335 1336 static int rspi_resume(struct device *dev) 1337 { 1338 struct rspi_data *rspi = dev_get_drvdata(dev); 1339 1340 return spi_controller_resume(rspi->ctlr); 1341 } 1342 1343 static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume); 1344 #define DEV_PM_OPS &rspi_pm_ops 1345 #else 1346 #define DEV_PM_OPS NULL 1347 #endif /* CONFIG_PM_SLEEP */ 1348 1349 static struct platform_driver rspi_driver = { 1350 .probe = rspi_probe, 1351 .remove = rspi_remove, 1352 .id_table = spi_driver_ids, 1353 .driver = { 1354 .name = "renesas_spi", 1355 .pm = DEV_PM_OPS, 1356 .of_match_table = of_match_ptr(rspi_of_match), 1357 }, 1358 }; 1359 module_platform_driver(rspi_driver); 1360 1361 MODULE_DESCRIPTION("Renesas RSPI bus driver"); 1362 MODULE_LICENSE("GPL v2"); 1363 MODULE_AUTHOR("Yoshihiro Shimoda"); 1364 MODULE_ALIAS("platform:rspi"); 1365