1 /* 2 * SH RSPI driver 3 * 4 * Copyright (C) 2012, 2013 Renesas Solutions Corp. 5 * Copyright (C) 2014 Glider bvba 6 * 7 * Based on spi-sh.c: 8 * Copyright (C) 2011 Renesas Solutions Corp. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; version 2 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * 23 */ 24 25 #include <linux/module.h> 26 #include <linux/kernel.h> 27 #include <linux/sched.h> 28 #include <linux/errno.h> 29 #include <linux/interrupt.h> 30 #include <linux/platform_device.h> 31 #include <linux/io.h> 32 #include <linux/clk.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/of_device.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/sh_dma.h> 38 #include <linux/spi/spi.h> 39 #include <linux/spi/rspi.h> 40 41 #define RSPI_SPCR 0x00 /* Control Register */ 42 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ 43 #define RSPI_SPPCR 0x02 /* Pin Control Register */ 44 #define RSPI_SPSR 0x03 /* Status Register */ 45 #define RSPI_SPDR 0x04 /* Data Register */ 46 #define RSPI_SPSCR 0x08 /* Sequence Control Register */ 47 #define RSPI_SPSSR 0x09 /* Sequence Status Register */ 48 #define RSPI_SPBR 0x0a /* Bit Rate Register */ 49 #define RSPI_SPDCR 0x0b /* Data Control Register */ 50 #define RSPI_SPCKD 0x0c /* Clock Delay Register */ 51 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ 52 #define RSPI_SPND 0x0e /* Next-Access Delay Register */ 53 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ 54 #define RSPI_SPCMD0 0x10 /* Command Register 0 */ 55 #define RSPI_SPCMD1 0x12 /* Command Register 1 */ 56 #define RSPI_SPCMD2 0x14 /* Command Register 2 */ 57 #define RSPI_SPCMD3 0x16 /* Command Register 3 */ 58 #define RSPI_SPCMD4 0x18 /* Command Register 4 */ 59 #define RSPI_SPCMD5 0x1a /* Command Register 5 */ 60 #define RSPI_SPCMD6 0x1c /* Command Register 6 */ 61 #define RSPI_SPCMD7 0x1e /* Command Register 7 */ 62 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) 63 #define RSPI_NUM_SPCMD 8 64 #define RSPI_RZ_NUM_SPCMD 4 65 #define QSPI_NUM_SPCMD 4 66 67 /* RSPI on RZ only */ 68 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ 69 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ 70 71 /* QSPI only */ 72 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ 73 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ 74 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ 75 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ 76 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ 77 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ 78 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) 79 80 /* SPCR - Control Register */ 81 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ 82 #define SPCR_SPE 0x40 /* Function Enable */ 83 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ 84 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ 85 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ 86 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ 87 /* RSPI on SH only */ 88 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ 89 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ 90 /* QSPI on R-Car M2 only */ 91 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ 92 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ 93 94 /* SSLP - Slave Select Polarity Register */ 95 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ 96 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ 97 98 /* SPPCR - Pin Control Register */ 99 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ 100 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ 101 #define SPPCR_SPOM 0x04 102 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ 103 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ 104 105 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ 106 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ 107 108 /* SPSR - Status Register */ 109 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ 110 #define SPSR_TEND 0x40 /* Transmit End */ 111 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ 112 #define SPSR_PERF 0x08 /* Parity Error Flag */ 113 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ 114 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ 115 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ 116 117 /* SPSCR - Sequence Control Register */ 118 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ 119 120 /* SPSSR - Sequence Status Register */ 121 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ 122 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ 123 124 /* SPDCR - Data Control Register */ 125 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ 126 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ 127 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ 128 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) 129 #define SPDCR_SPLWORD SPDCR_SPLW1 130 #define SPDCR_SPLBYTE SPDCR_SPLW0 131 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ 132 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ 133 #define SPDCR_SLSEL1 0x08 134 #define SPDCR_SLSEL0 0x04 135 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ 136 #define SPDCR_SPFC1 0x02 137 #define SPDCR_SPFC0 0x01 138 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ 139 140 /* SPCKD - Clock Delay Register */ 141 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ 142 143 /* SSLND - Slave Select Negation Delay Register */ 144 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ 145 146 /* SPND - Next-Access Delay Register */ 147 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ 148 149 /* SPCR2 - Control Register 2 */ 150 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ 151 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ 152 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ 153 #define SPCR2_SPPE 0x01 /* Parity Enable */ 154 155 /* SPCMDn - Command Registers */ 156 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ 157 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ 158 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ 159 #define SPCMD_LSBF 0x1000 /* LSB First */ 160 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ 161 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 162 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ 163 #define SPCMD_SPB_16BIT 0x0100 164 #define SPCMD_SPB_20BIT 0x0000 165 #define SPCMD_SPB_24BIT 0x0100 166 #define SPCMD_SPB_32BIT 0x0200 167 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ 168 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ 169 #define SPCMD_SPIMOD1 0x0040 170 #define SPCMD_SPIMOD0 0x0020 171 #define SPCMD_SPIMOD_SINGLE 0 172 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 173 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 174 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ 175 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ 176 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ 177 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ 178 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ 179 180 /* SPBFCR - Buffer Control Register */ 181 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ 182 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ 183 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 184 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 185 186 struct rspi_data { 187 void __iomem *addr; 188 u32 max_speed_hz; 189 struct spi_master *master; 190 wait_queue_head_t wait; 191 struct clk *clk; 192 u16 spcmd; 193 u8 spsr; 194 u8 sppcr; 195 int rx_irq, tx_irq; 196 const struct spi_ops *ops; 197 198 unsigned dma_callbacked:1; 199 unsigned byte_access:1; 200 }; 201 202 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) 203 { 204 iowrite8(data, rspi->addr + offset); 205 } 206 207 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) 208 { 209 iowrite16(data, rspi->addr + offset); 210 } 211 212 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) 213 { 214 iowrite32(data, rspi->addr + offset); 215 } 216 217 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) 218 { 219 return ioread8(rspi->addr + offset); 220 } 221 222 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) 223 { 224 return ioread16(rspi->addr + offset); 225 } 226 227 static void rspi_write_data(const struct rspi_data *rspi, u16 data) 228 { 229 if (rspi->byte_access) 230 rspi_write8(rspi, data, RSPI_SPDR); 231 else /* 16 bit */ 232 rspi_write16(rspi, data, RSPI_SPDR); 233 } 234 235 static u16 rspi_read_data(const struct rspi_data *rspi) 236 { 237 if (rspi->byte_access) 238 return rspi_read8(rspi, RSPI_SPDR); 239 else /* 16 bit */ 240 return rspi_read16(rspi, RSPI_SPDR); 241 } 242 243 /* optional functions */ 244 struct spi_ops { 245 int (*set_config_register)(struct rspi_data *rspi, int access_size); 246 int (*transfer_one)(struct spi_master *master, struct spi_device *spi, 247 struct spi_transfer *xfer); 248 u16 mode_bits; 249 u16 flags; 250 u16 fifo_size; 251 }; 252 253 /* 254 * functions for RSPI on legacy SH 255 */ 256 static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 257 { 258 int spbr; 259 260 /* Sets output mode, MOSI signal, and (optionally) loopback */ 261 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 262 263 /* Sets transfer bit rate */ 264 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 265 2 * rspi->max_speed_hz) - 1; 266 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 267 268 /* Disable dummy transmission, set 16-bit word access, 1 frame */ 269 rspi_write8(rspi, 0, RSPI_SPDCR); 270 rspi->byte_access = 0; 271 272 /* Sets RSPCK, SSL, next-access delay value */ 273 rspi_write8(rspi, 0x00, RSPI_SPCKD); 274 rspi_write8(rspi, 0x00, RSPI_SSLND); 275 rspi_write8(rspi, 0x00, RSPI_SPND); 276 277 /* Sets parity, interrupt mask */ 278 rspi_write8(rspi, 0x00, RSPI_SPCR2); 279 280 /* Sets SPCMD */ 281 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 282 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 283 284 /* Sets RSPI mode */ 285 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 286 287 return 0; 288 } 289 290 /* 291 * functions for RSPI on RZ 292 */ 293 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) 294 { 295 int spbr; 296 297 /* Sets output mode, MOSI signal, and (optionally) loopback */ 298 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 299 300 /* Sets transfer bit rate */ 301 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 302 2 * rspi->max_speed_hz) - 1; 303 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 304 305 /* Disable dummy transmission, set byte access */ 306 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); 307 rspi->byte_access = 1; 308 309 /* Sets RSPCK, SSL, next-access delay value */ 310 rspi_write8(rspi, 0x00, RSPI_SPCKD); 311 rspi_write8(rspi, 0x00, RSPI_SSLND); 312 rspi_write8(rspi, 0x00, RSPI_SPND); 313 314 /* Sets SPCMD */ 315 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 316 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 317 318 /* Sets RSPI mode */ 319 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 320 321 return 0; 322 } 323 324 /* 325 * functions for QSPI 326 */ 327 static int qspi_set_config_register(struct rspi_data *rspi, int access_size) 328 { 329 int spbr; 330 331 /* Sets output mode, MOSI signal, and (optionally) loopback */ 332 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 333 334 /* Sets transfer bit rate */ 335 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz); 336 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 337 338 /* Disable dummy transmission, set byte access */ 339 rspi_write8(rspi, 0, RSPI_SPDCR); 340 rspi->byte_access = 1; 341 342 /* Sets RSPCK, SSL, next-access delay value */ 343 rspi_write8(rspi, 0x00, RSPI_SPCKD); 344 rspi_write8(rspi, 0x00, RSPI_SSLND); 345 rspi_write8(rspi, 0x00, RSPI_SPND); 346 347 /* Data Length Setting */ 348 if (access_size == 8) 349 rspi->spcmd |= SPCMD_SPB_8BIT; 350 else if (access_size == 16) 351 rspi->spcmd |= SPCMD_SPB_16BIT; 352 else 353 rspi->spcmd |= SPCMD_SPB_32BIT; 354 355 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; 356 357 /* Resets transfer data length */ 358 rspi_write32(rspi, 0, QSPI_SPBMUL0); 359 360 /* Resets transmit and receive buffer */ 361 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 362 /* Sets buffer to allow normal operation */ 363 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 364 365 /* Sets SPCMD */ 366 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 367 368 /* Enables SPI function in master mode */ 369 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); 370 371 return 0; 372 } 373 374 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) 375 376 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) 377 { 378 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); 379 } 380 381 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) 382 { 383 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); 384 } 385 386 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, 387 u8 enable_bit) 388 { 389 int ret; 390 391 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 392 if (rspi->spsr & wait_mask) 393 return 0; 394 395 rspi_enable_irq(rspi, enable_bit); 396 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 397 if (ret == 0 && !(rspi->spsr & wait_mask)) 398 return -ETIMEDOUT; 399 400 return 0; 401 } 402 403 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi) 404 { 405 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 406 } 407 408 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi) 409 { 410 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE); 411 } 412 413 static int rspi_data_out(struct rspi_data *rspi, u8 data) 414 { 415 int error = rspi_wait_for_tx_empty(rspi); 416 if (error < 0) { 417 dev_err(&rspi->master->dev, "transmit timeout\n"); 418 return error; 419 } 420 rspi_write_data(rspi, data); 421 return 0; 422 } 423 424 static int rspi_data_in(struct rspi_data *rspi) 425 { 426 int error; 427 u8 data; 428 429 error = rspi_wait_for_rx_full(rspi); 430 if (error < 0) { 431 dev_err(&rspi->master->dev, "receive timeout\n"); 432 return error; 433 } 434 data = rspi_read_data(rspi); 435 return data; 436 } 437 438 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx, 439 unsigned int n) 440 { 441 while (n-- > 0) { 442 if (tx) { 443 int ret = rspi_data_out(rspi, *tx++); 444 if (ret < 0) 445 return ret; 446 } 447 if (rx) { 448 int ret = rspi_data_in(rspi); 449 if (ret < 0) 450 return ret; 451 *rx++ = ret; 452 } 453 } 454 455 return 0; 456 } 457 458 static void rspi_dma_complete(void *arg) 459 { 460 struct rspi_data *rspi = arg; 461 462 rspi->dma_callbacked = 1; 463 wake_up_interruptible(&rspi->wait); 464 } 465 466 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, 467 struct sg_table *rx) 468 { 469 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 470 u8 irq_mask = 0; 471 unsigned int other_irq = 0; 472 dma_cookie_t cookie; 473 int ret; 474 475 if (tx) { 476 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx, 477 tx->sgl, tx->nents, DMA_TO_DEVICE, 478 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 479 if (!desc_tx) 480 goto no_dma; 481 482 irq_mask |= SPCR_SPTIE; 483 } 484 if (rx) { 485 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx, 486 rx->sgl, rx->nents, DMA_FROM_DEVICE, 487 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 488 if (!desc_rx) 489 goto no_dma; 490 491 irq_mask |= SPCR_SPRIE; 492 } 493 494 /* 495 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be 496 * called. So, this driver disables the IRQ while DMA transfer. 497 */ 498 if (tx) 499 disable_irq(other_irq = rspi->tx_irq); 500 if (rx && rspi->rx_irq != other_irq) 501 disable_irq(rspi->rx_irq); 502 503 rspi_enable_irq(rspi, irq_mask); 504 rspi->dma_callbacked = 0; 505 506 if (rx) { 507 desc_rx->callback = rspi_dma_complete; 508 desc_rx->callback_param = rspi; 509 cookie = dmaengine_submit(desc_rx); 510 if (dma_submit_error(cookie)) 511 return cookie; 512 dma_async_issue_pending(rspi->master->dma_rx); 513 } 514 if (tx) { 515 if (rx) { 516 /* No callback */ 517 desc_tx->callback = NULL; 518 } else { 519 desc_tx->callback = rspi_dma_complete; 520 desc_tx->callback_param = rspi; 521 } 522 cookie = dmaengine_submit(desc_tx); 523 if (dma_submit_error(cookie)) 524 return cookie; 525 dma_async_issue_pending(rspi->master->dma_tx); 526 } 527 528 ret = wait_event_interruptible_timeout(rspi->wait, 529 rspi->dma_callbacked, HZ); 530 if (ret > 0 && rspi->dma_callbacked) 531 ret = 0; 532 else if (!ret) 533 ret = -ETIMEDOUT; 534 535 rspi_disable_irq(rspi, irq_mask); 536 537 if (tx) 538 enable_irq(rspi->tx_irq); 539 if (rx && rspi->rx_irq != other_irq) 540 enable_irq(rspi->rx_irq); 541 542 return ret; 543 544 no_dma: 545 pr_warn_once("%s %s: DMA not available, falling back to PIO\n", 546 dev_driver_string(&rspi->master->dev), 547 dev_name(&rspi->master->dev)); 548 return -EAGAIN; 549 } 550 551 static void rspi_receive_init(const struct rspi_data *rspi) 552 { 553 u8 spsr; 554 555 spsr = rspi_read8(rspi, RSPI_SPSR); 556 if (spsr & SPSR_SPRF) 557 rspi_read_data(rspi); /* dummy read */ 558 if (spsr & SPSR_OVRF) 559 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 560 RSPI_SPSR); 561 } 562 563 static void rspi_rz_receive_init(const struct rspi_data *rspi) 564 { 565 rspi_receive_init(rspi); 566 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); 567 rspi_write8(rspi, 0, RSPI_SPBFCR); 568 } 569 570 static void qspi_receive_init(const struct rspi_data *rspi) 571 { 572 u8 spsr; 573 574 spsr = rspi_read8(rspi, RSPI_SPSR); 575 if (spsr & SPSR_SPRF) 576 rspi_read_data(rspi); /* dummy read */ 577 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 578 rspi_write8(rspi, 0, QSPI_SPBFCR); 579 } 580 581 static bool __rspi_can_dma(const struct rspi_data *rspi, 582 const struct spi_transfer *xfer) 583 { 584 return xfer->len > rspi->ops->fifo_size; 585 } 586 587 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi, 588 struct spi_transfer *xfer) 589 { 590 struct rspi_data *rspi = spi_master_get_devdata(master); 591 592 return __rspi_can_dma(rspi, xfer); 593 } 594 595 static int rspi_common_transfer(struct rspi_data *rspi, 596 struct spi_transfer *xfer) 597 { 598 int ret; 599 600 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) { 601 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ 602 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, 603 xfer->rx_buf ? &xfer->rx_sg : NULL); 604 if (ret != -EAGAIN) 605 return ret; 606 } 607 608 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); 609 if (ret < 0) 610 return ret; 611 612 /* Wait for the last transmission */ 613 rspi_wait_for_tx_empty(rspi); 614 615 return 0; 616 } 617 618 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, 619 struct spi_transfer *xfer) 620 { 621 struct rspi_data *rspi = spi_master_get_devdata(master); 622 u8 spcr; 623 624 spcr = rspi_read8(rspi, RSPI_SPCR); 625 if (xfer->rx_buf) { 626 rspi_receive_init(rspi); 627 spcr &= ~SPCR_TXMD; 628 } else { 629 spcr |= SPCR_TXMD; 630 } 631 rspi_write8(rspi, spcr, RSPI_SPCR); 632 633 return rspi_common_transfer(rspi, xfer); 634 } 635 636 static int rspi_rz_transfer_one(struct spi_master *master, 637 struct spi_device *spi, 638 struct spi_transfer *xfer) 639 { 640 struct rspi_data *rspi = spi_master_get_devdata(master); 641 642 rspi_rz_receive_init(rspi); 643 644 return rspi_common_transfer(rspi, xfer); 645 } 646 647 static int qspi_transfer_out_in(struct rspi_data *rspi, 648 struct spi_transfer *xfer) 649 { 650 qspi_receive_init(rspi); 651 652 return rspi_common_transfer(rspi, xfer); 653 } 654 655 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) 656 { 657 int ret; 658 659 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) { 660 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); 661 if (ret != -EAGAIN) 662 return ret; 663 } 664 665 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len); 666 if (ret < 0) 667 return ret; 668 669 /* Wait for the last transmission */ 670 rspi_wait_for_tx_empty(rspi); 671 672 return 0; 673 } 674 675 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) 676 { 677 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) { 678 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); 679 if (ret != -EAGAIN) 680 return ret; 681 } 682 683 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len); 684 } 685 686 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, 687 struct spi_transfer *xfer) 688 { 689 struct rspi_data *rspi = spi_master_get_devdata(master); 690 691 if (spi->mode & SPI_LOOP) { 692 return qspi_transfer_out_in(rspi, xfer); 693 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { 694 /* Quad or Dual SPI Write */ 695 return qspi_transfer_out(rspi, xfer); 696 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) { 697 /* Quad or Dual SPI Read */ 698 return qspi_transfer_in(rspi, xfer); 699 } else { 700 /* Single SPI Transfer */ 701 return qspi_transfer_out_in(rspi, xfer); 702 } 703 } 704 705 static int rspi_setup(struct spi_device *spi) 706 { 707 struct rspi_data *rspi = spi_master_get_devdata(spi->master); 708 709 rspi->max_speed_hz = spi->max_speed_hz; 710 711 rspi->spcmd = SPCMD_SSLKP; 712 if (spi->mode & SPI_CPOL) 713 rspi->spcmd |= SPCMD_CPOL; 714 if (spi->mode & SPI_CPHA) 715 rspi->spcmd |= SPCMD_CPHA; 716 717 /* CMOS output mode and MOSI signal from previous transfer */ 718 rspi->sppcr = 0; 719 if (spi->mode & SPI_LOOP) 720 rspi->sppcr |= SPPCR_SPLP; 721 722 set_config_register(rspi, 8); 723 724 return 0; 725 } 726 727 static u16 qspi_transfer_mode(const struct spi_transfer *xfer) 728 { 729 if (xfer->tx_buf) 730 switch (xfer->tx_nbits) { 731 case SPI_NBITS_QUAD: 732 return SPCMD_SPIMOD_QUAD; 733 case SPI_NBITS_DUAL: 734 return SPCMD_SPIMOD_DUAL; 735 default: 736 return 0; 737 } 738 if (xfer->rx_buf) 739 switch (xfer->rx_nbits) { 740 case SPI_NBITS_QUAD: 741 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; 742 case SPI_NBITS_DUAL: 743 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; 744 default: 745 return 0; 746 } 747 748 return 0; 749 } 750 751 static int qspi_setup_sequencer(struct rspi_data *rspi, 752 const struct spi_message *msg) 753 { 754 const struct spi_transfer *xfer; 755 unsigned int i = 0, len = 0; 756 u16 current_mode = 0xffff, mode; 757 758 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 759 mode = qspi_transfer_mode(xfer); 760 if (mode == current_mode) { 761 len += xfer->len; 762 continue; 763 } 764 765 /* Transfer mode change */ 766 if (i) { 767 /* Set transfer data length of previous transfer */ 768 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 769 } 770 771 if (i >= QSPI_NUM_SPCMD) { 772 dev_err(&msg->spi->dev, 773 "Too many different transfer modes"); 774 return -EINVAL; 775 } 776 777 /* Program transfer mode for this transfer */ 778 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); 779 current_mode = mode; 780 len = xfer->len; 781 i++; 782 } 783 if (i) { 784 /* Set final transfer data length and sequence length */ 785 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 786 rspi_write8(rspi, i - 1, RSPI_SPSCR); 787 } 788 789 return 0; 790 } 791 792 static int rspi_prepare_message(struct spi_master *master, 793 struct spi_message *msg) 794 { 795 struct rspi_data *rspi = spi_master_get_devdata(master); 796 int ret; 797 798 if (msg->spi->mode & 799 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { 800 /* Setup sequencer for messages with multiple transfer modes */ 801 ret = qspi_setup_sequencer(rspi, msg); 802 if (ret < 0) 803 return ret; 804 } 805 806 /* Enable SPI function in master mode */ 807 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); 808 return 0; 809 } 810 811 static int rspi_unprepare_message(struct spi_master *master, 812 struct spi_message *msg) 813 { 814 struct rspi_data *rspi = spi_master_get_devdata(master); 815 816 /* Disable SPI function */ 817 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 818 819 /* Reset sequencer for Single SPI Transfers */ 820 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 821 rspi_write8(rspi, 0, RSPI_SPSCR); 822 return 0; 823 } 824 825 static irqreturn_t rspi_irq_mux(int irq, void *_sr) 826 { 827 struct rspi_data *rspi = _sr; 828 u8 spsr; 829 irqreturn_t ret = IRQ_NONE; 830 u8 disable_irq = 0; 831 832 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 833 if (spsr & SPSR_SPRF) 834 disable_irq |= SPCR_SPRIE; 835 if (spsr & SPSR_SPTEF) 836 disable_irq |= SPCR_SPTIE; 837 838 if (disable_irq) { 839 ret = IRQ_HANDLED; 840 rspi_disable_irq(rspi, disable_irq); 841 wake_up(&rspi->wait); 842 } 843 844 return ret; 845 } 846 847 static irqreturn_t rspi_irq_rx(int irq, void *_sr) 848 { 849 struct rspi_data *rspi = _sr; 850 u8 spsr; 851 852 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 853 if (spsr & SPSR_SPRF) { 854 rspi_disable_irq(rspi, SPCR_SPRIE); 855 wake_up(&rspi->wait); 856 return IRQ_HANDLED; 857 } 858 859 return 0; 860 } 861 862 static irqreturn_t rspi_irq_tx(int irq, void *_sr) 863 { 864 struct rspi_data *rspi = _sr; 865 u8 spsr; 866 867 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 868 if (spsr & SPSR_SPTEF) { 869 rspi_disable_irq(rspi, SPCR_SPTIE); 870 wake_up(&rspi->wait); 871 return IRQ_HANDLED; 872 } 873 874 return 0; 875 } 876 877 static struct dma_chan *rspi_request_dma_chan(struct device *dev, 878 enum dma_transfer_direction dir, 879 unsigned int id, 880 dma_addr_t port_addr) 881 { 882 dma_cap_mask_t mask; 883 struct dma_chan *chan; 884 struct dma_slave_config cfg; 885 int ret; 886 887 dma_cap_zero(mask); 888 dma_cap_set(DMA_SLAVE, mask); 889 890 chan = dma_request_channel(mask, shdma_chan_filter, 891 (void *)(unsigned long)id); 892 if (!chan) { 893 dev_warn(dev, "dma_request_channel failed\n"); 894 return NULL; 895 } 896 897 memset(&cfg, 0, sizeof(cfg)); 898 cfg.slave_id = id; 899 cfg.direction = dir; 900 if (dir == DMA_MEM_TO_DEV) 901 cfg.dst_addr = port_addr; 902 else 903 cfg.src_addr = port_addr; 904 905 ret = dmaengine_slave_config(chan, &cfg); 906 if (ret) { 907 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 908 dma_release_channel(chan); 909 return NULL; 910 } 911 912 return chan; 913 } 914 915 static int rspi_request_dma(struct device *dev, struct spi_master *master, 916 const struct resource *res) 917 { 918 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev); 919 920 if (!rspi_pd || !rspi_pd->dma_rx_id || !rspi_pd->dma_tx_id) 921 return 0; /* The driver assumes no error. */ 922 923 master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, 924 rspi_pd->dma_rx_id, 925 res->start + RSPI_SPDR); 926 if (!master->dma_rx) 927 return -ENODEV; 928 929 master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, 930 rspi_pd->dma_tx_id, 931 res->start + RSPI_SPDR); 932 if (!master->dma_tx) { 933 dma_release_channel(master->dma_rx); 934 master->dma_rx = NULL; 935 return -ENODEV; 936 } 937 938 master->can_dma = rspi_can_dma; 939 dev_info(dev, "DMA available"); 940 return 0; 941 } 942 943 static void rspi_release_dma(struct spi_master *master) 944 { 945 if (master->dma_tx) 946 dma_release_channel(master->dma_tx); 947 if (master->dma_rx) 948 dma_release_channel(master->dma_rx); 949 } 950 951 static int rspi_remove(struct platform_device *pdev) 952 { 953 struct rspi_data *rspi = platform_get_drvdata(pdev); 954 955 rspi_release_dma(rspi->master); 956 pm_runtime_disable(&pdev->dev); 957 958 return 0; 959 } 960 961 static const struct spi_ops rspi_ops = { 962 .set_config_register = rspi_set_config_register, 963 .transfer_one = rspi_transfer_one, 964 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 965 .flags = SPI_MASTER_MUST_TX, 966 .fifo_size = 8, 967 }; 968 969 static const struct spi_ops rspi_rz_ops = { 970 .set_config_register = rspi_rz_set_config_register, 971 .transfer_one = rspi_rz_transfer_one, 972 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 973 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX, 974 .fifo_size = 8, /* 8 for TX, 32 for RX */ 975 }; 976 977 static const struct spi_ops qspi_ops = { 978 .set_config_register = qspi_set_config_register, 979 .transfer_one = qspi_transfer_one, 980 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | 981 SPI_TX_DUAL | SPI_TX_QUAD | 982 SPI_RX_DUAL | SPI_RX_QUAD, 983 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX, 984 .fifo_size = 32, 985 }; 986 987 #ifdef CONFIG_OF 988 static const struct of_device_id rspi_of_match[] = { 989 /* RSPI on legacy SH */ 990 { .compatible = "renesas,rspi", .data = &rspi_ops }, 991 /* RSPI on RZ/A1H */ 992 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, 993 /* QSPI on R-Car Gen2 */ 994 { .compatible = "renesas,qspi", .data = &qspi_ops }, 995 { /* sentinel */ } 996 }; 997 998 MODULE_DEVICE_TABLE(of, rspi_of_match); 999 1000 static int rspi_parse_dt(struct device *dev, struct spi_master *master) 1001 { 1002 u32 num_cs; 1003 int error; 1004 1005 /* Parse DT properties */ 1006 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); 1007 if (error) { 1008 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); 1009 return error; 1010 } 1011 1012 master->num_chipselect = num_cs; 1013 return 0; 1014 } 1015 #else 1016 #define rspi_of_match NULL 1017 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master) 1018 { 1019 return -EINVAL; 1020 } 1021 #endif /* CONFIG_OF */ 1022 1023 static int rspi_request_irq(struct device *dev, unsigned int irq, 1024 irq_handler_t handler, const char *suffix, 1025 void *dev_id) 1026 { 1027 const char *base = dev_name(dev); 1028 size_t len = strlen(base) + strlen(suffix) + 2; 1029 char *name = devm_kzalloc(dev, len, GFP_KERNEL); 1030 if (!name) 1031 return -ENOMEM; 1032 snprintf(name, len, "%s:%s", base, suffix); 1033 return devm_request_irq(dev, irq, handler, 0, name, dev_id); 1034 } 1035 1036 static int rspi_probe(struct platform_device *pdev) 1037 { 1038 struct resource *res; 1039 struct spi_master *master; 1040 struct rspi_data *rspi; 1041 int ret; 1042 const struct of_device_id *of_id; 1043 const struct rspi_plat_data *rspi_pd; 1044 const struct spi_ops *ops; 1045 1046 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 1047 if (master == NULL) { 1048 dev_err(&pdev->dev, "spi_alloc_master error.\n"); 1049 return -ENOMEM; 1050 } 1051 1052 of_id = of_match_device(rspi_of_match, &pdev->dev); 1053 if (of_id) { 1054 ops = of_id->data; 1055 ret = rspi_parse_dt(&pdev->dev, master); 1056 if (ret) 1057 goto error1; 1058 } else { 1059 ops = (struct spi_ops *)pdev->id_entry->driver_data; 1060 rspi_pd = dev_get_platdata(&pdev->dev); 1061 if (rspi_pd && rspi_pd->num_chipselect) 1062 master->num_chipselect = rspi_pd->num_chipselect; 1063 else 1064 master->num_chipselect = 2; /* default */ 1065 }; 1066 1067 /* ops parameter check */ 1068 if (!ops->set_config_register) { 1069 dev_err(&pdev->dev, "there is no set_config_register\n"); 1070 ret = -ENODEV; 1071 goto error1; 1072 } 1073 1074 rspi = spi_master_get_devdata(master); 1075 platform_set_drvdata(pdev, rspi); 1076 rspi->ops = ops; 1077 rspi->master = master; 1078 1079 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1080 rspi->addr = devm_ioremap_resource(&pdev->dev, res); 1081 if (IS_ERR(rspi->addr)) { 1082 ret = PTR_ERR(rspi->addr); 1083 goto error1; 1084 } 1085 1086 rspi->clk = devm_clk_get(&pdev->dev, NULL); 1087 if (IS_ERR(rspi->clk)) { 1088 dev_err(&pdev->dev, "cannot get clock\n"); 1089 ret = PTR_ERR(rspi->clk); 1090 goto error1; 1091 } 1092 1093 pm_runtime_enable(&pdev->dev); 1094 1095 init_waitqueue_head(&rspi->wait); 1096 1097 master->bus_num = pdev->id; 1098 master->setup = rspi_setup; 1099 master->auto_runtime_pm = true; 1100 master->transfer_one = ops->transfer_one; 1101 master->prepare_message = rspi_prepare_message; 1102 master->unprepare_message = rspi_unprepare_message; 1103 master->mode_bits = ops->mode_bits; 1104 master->flags = ops->flags; 1105 master->dev.of_node = pdev->dev.of_node; 1106 1107 ret = platform_get_irq_byname(pdev, "rx"); 1108 if (ret < 0) { 1109 ret = platform_get_irq_byname(pdev, "mux"); 1110 if (ret < 0) 1111 ret = platform_get_irq(pdev, 0); 1112 if (ret >= 0) 1113 rspi->rx_irq = rspi->tx_irq = ret; 1114 } else { 1115 rspi->rx_irq = ret; 1116 ret = platform_get_irq_byname(pdev, "tx"); 1117 if (ret >= 0) 1118 rspi->tx_irq = ret; 1119 } 1120 if (ret < 0) { 1121 dev_err(&pdev->dev, "platform_get_irq error\n"); 1122 goto error2; 1123 } 1124 1125 if (rspi->rx_irq == rspi->tx_irq) { 1126 /* Single multiplexed interrupt */ 1127 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, 1128 "mux", rspi); 1129 } else { 1130 /* Multi-interrupt mode, only SPRI and SPTI are used */ 1131 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, 1132 "rx", rspi); 1133 if (!ret) 1134 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, 1135 rspi_irq_tx, "tx", rspi); 1136 } 1137 if (ret < 0) { 1138 dev_err(&pdev->dev, "request_irq error\n"); 1139 goto error2; 1140 } 1141 1142 ret = rspi_request_dma(&pdev->dev, master, res); 1143 if (ret < 0) 1144 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1145 1146 ret = devm_spi_register_master(&pdev->dev, master); 1147 if (ret < 0) { 1148 dev_err(&pdev->dev, "spi_register_master error.\n"); 1149 goto error3; 1150 } 1151 1152 dev_info(&pdev->dev, "probed\n"); 1153 1154 return 0; 1155 1156 error3: 1157 rspi_release_dma(master); 1158 error2: 1159 pm_runtime_disable(&pdev->dev); 1160 error1: 1161 spi_master_put(master); 1162 1163 return ret; 1164 } 1165 1166 static struct platform_device_id spi_driver_ids[] = { 1167 { "rspi", (kernel_ulong_t)&rspi_ops }, 1168 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, 1169 { "qspi", (kernel_ulong_t)&qspi_ops }, 1170 {}, 1171 }; 1172 1173 MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1174 1175 static struct platform_driver rspi_driver = { 1176 .probe = rspi_probe, 1177 .remove = rspi_remove, 1178 .id_table = spi_driver_ids, 1179 .driver = { 1180 .name = "renesas_spi", 1181 .owner = THIS_MODULE, 1182 .of_match_table = of_match_ptr(rspi_of_match), 1183 }, 1184 }; 1185 module_platform_driver(rspi_driver); 1186 1187 MODULE_DESCRIPTION("Renesas RSPI bus driver"); 1188 MODULE_LICENSE("GPL v2"); 1189 MODULE_AUTHOR("Yoshihiro Shimoda"); 1190 MODULE_ALIAS("platform:rspi"); 1191