10b2182ddSShimoda, Yoshihiro /* 20b2182ddSShimoda, Yoshihiro * SH RSPI driver 30b2182ddSShimoda, Yoshihiro * 40b2182ddSShimoda, Yoshihiro * Copyright (C) 2012 Renesas Solutions Corp. 50b2182ddSShimoda, Yoshihiro * 60b2182ddSShimoda, Yoshihiro * Based on spi-sh.c: 70b2182ddSShimoda, Yoshihiro * Copyright (C) 2011 Renesas Solutions Corp. 80b2182ddSShimoda, Yoshihiro * 90b2182ddSShimoda, Yoshihiro * This program is free software; you can redistribute it and/or modify 100b2182ddSShimoda, Yoshihiro * it under the terms of the GNU General Public License as published by 110b2182ddSShimoda, Yoshihiro * the Free Software Foundation; version 2 of the License. 120b2182ddSShimoda, Yoshihiro * 130b2182ddSShimoda, Yoshihiro * This program is distributed in the hope that it will be useful, 140b2182ddSShimoda, Yoshihiro * but WITHOUT ANY WARRANTY; without even the implied warranty of 150b2182ddSShimoda, Yoshihiro * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 160b2182ddSShimoda, Yoshihiro * GNU General Public License for more details. 170b2182ddSShimoda, Yoshihiro * 180b2182ddSShimoda, Yoshihiro * You should have received a copy of the GNU General Public License 190b2182ddSShimoda, Yoshihiro * along with this program; if not, write to the Free Software 200b2182ddSShimoda, Yoshihiro * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 210b2182ddSShimoda, Yoshihiro * 220b2182ddSShimoda, Yoshihiro */ 230b2182ddSShimoda, Yoshihiro 240b2182ddSShimoda, Yoshihiro #include <linux/module.h> 250b2182ddSShimoda, Yoshihiro #include <linux/kernel.h> 260b2182ddSShimoda, Yoshihiro #include <linux/sched.h> 270b2182ddSShimoda, Yoshihiro #include <linux/errno.h> 280b2182ddSShimoda, Yoshihiro #include <linux/list.h> 290b2182ddSShimoda, Yoshihiro #include <linux/workqueue.h> 300b2182ddSShimoda, Yoshihiro #include <linux/interrupt.h> 310b2182ddSShimoda, Yoshihiro #include <linux/platform_device.h> 320b2182ddSShimoda, Yoshihiro #include <linux/io.h> 330b2182ddSShimoda, Yoshihiro #include <linux/clk.h> 34a3633fe7SShimoda, Yoshihiro #include <linux/dmaengine.h> 35a3633fe7SShimoda, Yoshihiro #include <linux/dma-mapping.h> 36a3633fe7SShimoda, Yoshihiro #include <linux/sh_dma.h> 370b2182ddSShimoda, Yoshihiro #include <linux/spi/spi.h> 38a3633fe7SShimoda, Yoshihiro #include <linux/spi/rspi.h> 390b2182ddSShimoda, Yoshihiro 400b2182ddSShimoda, Yoshihiro #define RSPI_SPCR 0x00 410b2182ddSShimoda, Yoshihiro #define RSPI_SSLP 0x01 420b2182ddSShimoda, Yoshihiro #define RSPI_SPPCR 0x02 430b2182ddSShimoda, Yoshihiro #define RSPI_SPSR 0x03 440b2182ddSShimoda, Yoshihiro #define RSPI_SPDR 0x04 450b2182ddSShimoda, Yoshihiro #define RSPI_SPSCR 0x08 460b2182ddSShimoda, Yoshihiro #define RSPI_SPSSR 0x09 470b2182ddSShimoda, Yoshihiro #define RSPI_SPBR 0x0a 480b2182ddSShimoda, Yoshihiro #define RSPI_SPDCR 0x0b 490b2182ddSShimoda, Yoshihiro #define RSPI_SPCKD 0x0c 500b2182ddSShimoda, Yoshihiro #define RSPI_SSLND 0x0d 510b2182ddSShimoda, Yoshihiro #define RSPI_SPND 0x0e 520b2182ddSShimoda, Yoshihiro #define RSPI_SPCR2 0x0f 530b2182ddSShimoda, Yoshihiro #define RSPI_SPCMD0 0x10 540b2182ddSShimoda, Yoshihiro #define RSPI_SPCMD1 0x12 550b2182ddSShimoda, Yoshihiro #define RSPI_SPCMD2 0x14 560b2182ddSShimoda, Yoshihiro #define RSPI_SPCMD3 0x16 570b2182ddSShimoda, Yoshihiro #define RSPI_SPCMD4 0x18 580b2182ddSShimoda, Yoshihiro #define RSPI_SPCMD5 0x1a 590b2182ddSShimoda, Yoshihiro #define RSPI_SPCMD6 0x1c 600b2182ddSShimoda, Yoshihiro #define RSPI_SPCMD7 0x1e 610b2182ddSShimoda, Yoshihiro 620b2182ddSShimoda, Yoshihiro /* SPCR */ 630b2182ddSShimoda, Yoshihiro #define SPCR_SPRIE 0x80 640b2182ddSShimoda, Yoshihiro #define SPCR_SPE 0x40 650b2182ddSShimoda, Yoshihiro #define SPCR_SPTIE 0x20 660b2182ddSShimoda, Yoshihiro #define SPCR_SPEIE 0x10 670b2182ddSShimoda, Yoshihiro #define SPCR_MSTR 0x08 680b2182ddSShimoda, Yoshihiro #define SPCR_MODFEN 0x04 690b2182ddSShimoda, Yoshihiro #define SPCR_TXMD 0x02 700b2182ddSShimoda, Yoshihiro #define SPCR_SPMS 0x01 710b2182ddSShimoda, Yoshihiro 720b2182ddSShimoda, Yoshihiro /* SSLP */ 730b2182ddSShimoda, Yoshihiro #define SSLP_SSL1P 0x02 740b2182ddSShimoda, Yoshihiro #define SSLP_SSL0P 0x01 750b2182ddSShimoda, Yoshihiro 760b2182ddSShimoda, Yoshihiro /* SPPCR */ 770b2182ddSShimoda, Yoshihiro #define SPPCR_MOIFE 0x20 780b2182ddSShimoda, Yoshihiro #define SPPCR_MOIFV 0x10 790b2182ddSShimoda, Yoshihiro #define SPPCR_SPOM 0x04 800b2182ddSShimoda, Yoshihiro #define SPPCR_SPLP2 0x02 810b2182ddSShimoda, Yoshihiro #define SPPCR_SPLP 0x01 820b2182ddSShimoda, Yoshihiro 830b2182ddSShimoda, Yoshihiro /* SPSR */ 840b2182ddSShimoda, Yoshihiro #define SPSR_SPRF 0x80 850b2182ddSShimoda, Yoshihiro #define SPSR_SPTEF 0x20 860b2182ddSShimoda, Yoshihiro #define SPSR_PERF 0x08 870b2182ddSShimoda, Yoshihiro #define SPSR_MODF 0x04 880b2182ddSShimoda, Yoshihiro #define SPSR_IDLNF 0x02 890b2182ddSShimoda, Yoshihiro #define SPSR_OVRF 0x01 900b2182ddSShimoda, Yoshihiro 910b2182ddSShimoda, Yoshihiro /* SPSCR */ 920b2182ddSShimoda, Yoshihiro #define SPSCR_SPSLN_MASK 0x07 930b2182ddSShimoda, Yoshihiro 940b2182ddSShimoda, Yoshihiro /* SPSSR */ 950b2182ddSShimoda, Yoshihiro #define SPSSR_SPECM_MASK 0x70 960b2182ddSShimoda, Yoshihiro #define SPSSR_SPCP_MASK 0x07 970b2182ddSShimoda, Yoshihiro 980b2182ddSShimoda, Yoshihiro /* SPDCR */ 990b2182ddSShimoda, Yoshihiro #define SPDCR_SPLW 0x20 1000b2182ddSShimoda, Yoshihiro #define SPDCR_SPRDTD 0x10 1010b2182ddSShimoda, Yoshihiro #define SPDCR_SLSEL1 0x08 1020b2182ddSShimoda, Yoshihiro #define SPDCR_SLSEL0 0x04 1030b2182ddSShimoda, Yoshihiro #define SPDCR_SLSEL_MASK 0x0c 1040b2182ddSShimoda, Yoshihiro #define SPDCR_SPFC1 0x02 1050b2182ddSShimoda, Yoshihiro #define SPDCR_SPFC0 0x01 1060b2182ddSShimoda, Yoshihiro 1070b2182ddSShimoda, Yoshihiro /* SPCKD */ 1080b2182ddSShimoda, Yoshihiro #define SPCKD_SCKDL_MASK 0x07 1090b2182ddSShimoda, Yoshihiro 1100b2182ddSShimoda, Yoshihiro /* SSLND */ 1110b2182ddSShimoda, Yoshihiro #define SSLND_SLNDL_MASK 0x07 1120b2182ddSShimoda, Yoshihiro 1130b2182ddSShimoda, Yoshihiro /* SPND */ 1140b2182ddSShimoda, Yoshihiro #define SPND_SPNDL_MASK 0x07 1150b2182ddSShimoda, Yoshihiro 1160b2182ddSShimoda, Yoshihiro /* SPCR2 */ 1170b2182ddSShimoda, Yoshihiro #define SPCR2_PTE 0x08 1180b2182ddSShimoda, Yoshihiro #define SPCR2_SPIE 0x04 1190b2182ddSShimoda, Yoshihiro #define SPCR2_SPOE 0x02 1200b2182ddSShimoda, Yoshihiro #define SPCR2_SPPE 0x01 1210b2182ddSShimoda, Yoshihiro 1220b2182ddSShimoda, Yoshihiro /* SPCMDn */ 1230b2182ddSShimoda, Yoshihiro #define SPCMD_SCKDEN 0x8000 1240b2182ddSShimoda, Yoshihiro #define SPCMD_SLNDEN 0x4000 1250b2182ddSShimoda, Yoshihiro #define SPCMD_SPNDEN 0x2000 1260b2182ddSShimoda, Yoshihiro #define SPCMD_LSBF 0x1000 1270b2182ddSShimoda, Yoshihiro #define SPCMD_SPB_MASK 0x0f00 1280b2182ddSShimoda, Yoshihiro #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 1290b2182ddSShimoda, Yoshihiro #define SPCMD_SPB_20BIT 0x0000 1300b2182ddSShimoda, Yoshihiro #define SPCMD_SPB_24BIT 0x0100 1310b2182ddSShimoda, Yoshihiro #define SPCMD_SPB_32BIT 0x0200 1320b2182ddSShimoda, Yoshihiro #define SPCMD_SSLKP 0x0080 1330b2182ddSShimoda, Yoshihiro #define SPCMD_SSLA_MASK 0x0030 1340b2182ddSShimoda, Yoshihiro #define SPCMD_BRDV_MASK 0x000c 1350b2182ddSShimoda, Yoshihiro #define SPCMD_CPOL 0x0002 1360b2182ddSShimoda, Yoshihiro #define SPCMD_CPHA 0x0001 1370b2182ddSShimoda, Yoshihiro 1380b2182ddSShimoda, Yoshihiro struct rspi_data { 1390b2182ddSShimoda, Yoshihiro void __iomem *addr; 1400b2182ddSShimoda, Yoshihiro u32 max_speed_hz; 1410b2182ddSShimoda, Yoshihiro struct spi_master *master; 1420b2182ddSShimoda, Yoshihiro struct list_head queue; 1430b2182ddSShimoda, Yoshihiro struct work_struct ws; 1440b2182ddSShimoda, Yoshihiro wait_queue_head_t wait; 1450b2182ddSShimoda, Yoshihiro spinlock_t lock; 1460b2182ddSShimoda, Yoshihiro struct clk *clk; 1470b2182ddSShimoda, Yoshihiro unsigned char spsr; 148a3633fe7SShimoda, Yoshihiro 149a3633fe7SShimoda, Yoshihiro /* for dmaengine */ 150a3633fe7SShimoda, Yoshihiro struct dma_chan *chan_tx; 151a3633fe7SShimoda, Yoshihiro struct dma_chan *chan_rx; 152a3633fe7SShimoda, Yoshihiro int irq; 153a3633fe7SShimoda, Yoshihiro 154a3633fe7SShimoda, Yoshihiro unsigned dma_width_16bit:1; 155a3633fe7SShimoda, Yoshihiro unsigned dma_callbacked:1; 1560b2182ddSShimoda, Yoshihiro }; 1570b2182ddSShimoda, Yoshihiro 1580b2182ddSShimoda, Yoshihiro static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset) 1590b2182ddSShimoda, Yoshihiro { 1600b2182ddSShimoda, Yoshihiro iowrite8(data, rspi->addr + offset); 1610b2182ddSShimoda, Yoshihiro } 1620b2182ddSShimoda, Yoshihiro 1630b2182ddSShimoda, Yoshihiro static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset) 1640b2182ddSShimoda, Yoshihiro { 1650b2182ddSShimoda, Yoshihiro iowrite16(data, rspi->addr + offset); 1660b2182ddSShimoda, Yoshihiro } 1670b2182ddSShimoda, Yoshihiro 1680b2182ddSShimoda, Yoshihiro static u8 rspi_read8(struct rspi_data *rspi, u16 offset) 1690b2182ddSShimoda, Yoshihiro { 1700b2182ddSShimoda, Yoshihiro return ioread8(rspi->addr + offset); 1710b2182ddSShimoda, Yoshihiro } 1720b2182ddSShimoda, Yoshihiro 1730b2182ddSShimoda, Yoshihiro static u16 rspi_read16(struct rspi_data *rspi, u16 offset) 1740b2182ddSShimoda, Yoshihiro { 1750b2182ddSShimoda, Yoshihiro return ioread16(rspi->addr + offset); 1760b2182ddSShimoda, Yoshihiro } 1770b2182ddSShimoda, Yoshihiro 1780b2182ddSShimoda, Yoshihiro static unsigned char rspi_calc_spbr(struct rspi_data *rspi) 1790b2182ddSShimoda, Yoshihiro { 1800b2182ddSShimoda, Yoshihiro int tmp; 1810b2182ddSShimoda, Yoshihiro unsigned char spbr; 1820b2182ddSShimoda, Yoshihiro 1830b2182ddSShimoda, Yoshihiro tmp = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; 1840b2182ddSShimoda, Yoshihiro spbr = clamp(tmp, 0, 255); 1850b2182ddSShimoda, Yoshihiro 1860b2182ddSShimoda, Yoshihiro return spbr; 1870b2182ddSShimoda, Yoshihiro } 1880b2182ddSShimoda, Yoshihiro 1890b2182ddSShimoda, Yoshihiro static void rspi_enable_irq(struct rspi_data *rspi, u8 enable) 1900b2182ddSShimoda, Yoshihiro { 1910b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); 1920b2182ddSShimoda, Yoshihiro } 1930b2182ddSShimoda, Yoshihiro 1940b2182ddSShimoda, Yoshihiro static void rspi_disable_irq(struct rspi_data *rspi, u8 disable) 1950b2182ddSShimoda, Yoshihiro { 1960b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); 1970b2182ddSShimoda, Yoshihiro } 1980b2182ddSShimoda, Yoshihiro 1990b2182ddSShimoda, Yoshihiro static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, 2000b2182ddSShimoda, Yoshihiro u8 enable_bit) 2010b2182ddSShimoda, Yoshihiro { 2020b2182ddSShimoda, Yoshihiro int ret; 2030b2182ddSShimoda, Yoshihiro 2040b2182ddSShimoda, Yoshihiro rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 2050b2182ddSShimoda, Yoshihiro rspi_enable_irq(rspi, enable_bit); 2060b2182ddSShimoda, Yoshihiro ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 2070b2182ddSShimoda, Yoshihiro if (ret == 0 && !(rspi->spsr & wait_mask)) 2080b2182ddSShimoda, Yoshihiro return -ETIMEDOUT; 2090b2182ddSShimoda, Yoshihiro 2100b2182ddSShimoda, Yoshihiro return 0; 2110b2182ddSShimoda, Yoshihiro } 2120b2182ddSShimoda, Yoshihiro 2130b2182ddSShimoda, Yoshihiro static void rspi_assert_ssl(struct rspi_data *rspi) 2140b2182ddSShimoda, Yoshihiro { 2150b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); 2160b2182ddSShimoda, Yoshihiro } 2170b2182ddSShimoda, Yoshihiro 2180b2182ddSShimoda, Yoshihiro static void rspi_negate_ssl(struct rspi_data *rspi) 2190b2182ddSShimoda, Yoshihiro { 2200b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 2210b2182ddSShimoda, Yoshihiro } 2220b2182ddSShimoda, Yoshihiro 2230b2182ddSShimoda, Yoshihiro static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 2240b2182ddSShimoda, Yoshihiro { 2250b2182ddSShimoda, Yoshihiro /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ 2260b2182ddSShimoda, Yoshihiro rspi_write8(rspi, 0x00, RSPI_SPPCR); 2270b2182ddSShimoda, Yoshihiro 2280b2182ddSShimoda, Yoshihiro /* Sets transfer bit rate */ 2290b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_calc_spbr(rspi), RSPI_SPBR); 2300b2182ddSShimoda, Yoshihiro 2310b2182ddSShimoda, Yoshihiro /* Sets number of frames to be used: 1 frame */ 2320b2182ddSShimoda, Yoshihiro rspi_write8(rspi, 0x00, RSPI_SPDCR); 2330b2182ddSShimoda, Yoshihiro 2340b2182ddSShimoda, Yoshihiro /* Sets RSPCK, SSL, next-access delay value */ 2350b2182ddSShimoda, Yoshihiro rspi_write8(rspi, 0x00, RSPI_SPCKD); 2360b2182ddSShimoda, Yoshihiro rspi_write8(rspi, 0x00, RSPI_SSLND); 2370b2182ddSShimoda, Yoshihiro rspi_write8(rspi, 0x00, RSPI_SPND); 2380b2182ddSShimoda, Yoshihiro 2390b2182ddSShimoda, Yoshihiro /* Sets parity, interrupt mask */ 2400b2182ddSShimoda, Yoshihiro rspi_write8(rspi, 0x00, RSPI_SPCR2); 2410b2182ddSShimoda, Yoshihiro 2420b2182ddSShimoda, Yoshihiro /* Sets SPCMD */ 2430b2182ddSShimoda, Yoshihiro rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP, 2440b2182ddSShimoda, Yoshihiro RSPI_SPCMD0); 2450b2182ddSShimoda, Yoshihiro 2460b2182ddSShimoda, Yoshihiro /* Sets RSPI mode */ 2470b2182ddSShimoda, Yoshihiro rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 2480b2182ddSShimoda, Yoshihiro 2490b2182ddSShimoda, Yoshihiro return 0; 2500b2182ddSShimoda, Yoshihiro } 2510b2182ddSShimoda, Yoshihiro 2520b2182ddSShimoda, Yoshihiro static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg, 2530b2182ddSShimoda, Yoshihiro struct spi_transfer *t) 2540b2182ddSShimoda, Yoshihiro { 2550b2182ddSShimoda, Yoshihiro int remain = t->len; 2560b2182ddSShimoda, Yoshihiro u8 *data; 2570b2182ddSShimoda, Yoshihiro 2580b2182ddSShimoda, Yoshihiro data = (u8 *)t->tx_buf; 2590b2182ddSShimoda, Yoshihiro while (remain > 0) { 2600b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, 2610b2182ddSShimoda, Yoshihiro RSPI_SPCR); 2620b2182ddSShimoda, Yoshihiro 2630b2182ddSShimoda, Yoshihiro if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { 2640b2182ddSShimoda, Yoshihiro dev_err(&rspi->master->dev, 2650b2182ddSShimoda, Yoshihiro "%s: tx empty timeout\n", __func__); 2660b2182ddSShimoda, Yoshihiro return -ETIMEDOUT; 2670b2182ddSShimoda, Yoshihiro } 2680b2182ddSShimoda, Yoshihiro 2690b2182ddSShimoda, Yoshihiro rspi_write16(rspi, *data, RSPI_SPDR); 2700b2182ddSShimoda, Yoshihiro data++; 2710b2182ddSShimoda, Yoshihiro remain--; 2720b2182ddSShimoda, Yoshihiro } 2730b2182ddSShimoda, Yoshihiro 2740b2182ddSShimoda, Yoshihiro /* Waiting for the last transmition */ 2750b2182ddSShimoda, Yoshihiro rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 2760b2182ddSShimoda, Yoshihiro 2770b2182ddSShimoda, Yoshihiro return 0; 2780b2182ddSShimoda, Yoshihiro } 2790b2182ddSShimoda, Yoshihiro 280a3633fe7SShimoda, Yoshihiro static void rspi_dma_complete(void *arg) 2810b2182ddSShimoda, Yoshihiro { 282a3633fe7SShimoda, Yoshihiro struct rspi_data *rspi = arg; 283a3633fe7SShimoda, Yoshihiro 284a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked = 1; 285a3633fe7SShimoda, Yoshihiro wake_up_interruptible(&rspi->wait); 286a3633fe7SShimoda, Yoshihiro } 287a3633fe7SShimoda, Yoshihiro 288a3633fe7SShimoda, Yoshihiro static int rspi_dma_map_sg(struct scatterlist *sg, void *buf, unsigned len, 289a3633fe7SShimoda, Yoshihiro struct dma_chan *chan, 290a3633fe7SShimoda, Yoshihiro enum dma_transfer_direction dir) 291a3633fe7SShimoda, Yoshihiro { 292a3633fe7SShimoda, Yoshihiro sg_init_table(sg, 1); 293a3633fe7SShimoda, Yoshihiro sg_set_buf(sg, buf, len); 294a3633fe7SShimoda, Yoshihiro sg_dma_len(sg) = len; 295a3633fe7SShimoda, Yoshihiro return dma_map_sg(chan->device->dev, sg, 1, dir); 296a3633fe7SShimoda, Yoshihiro } 297a3633fe7SShimoda, Yoshihiro 298a3633fe7SShimoda, Yoshihiro static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, 299a3633fe7SShimoda, Yoshihiro enum dma_transfer_direction dir) 300a3633fe7SShimoda, Yoshihiro { 301a3633fe7SShimoda, Yoshihiro dma_unmap_sg(chan->device->dev, sg, 1, dir); 302a3633fe7SShimoda, Yoshihiro } 303a3633fe7SShimoda, Yoshihiro 304a3633fe7SShimoda, Yoshihiro static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) 305a3633fe7SShimoda, Yoshihiro { 306a3633fe7SShimoda, Yoshihiro u16 *dst = buf; 307a3633fe7SShimoda, Yoshihiro const u8 *src = data; 308a3633fe7SShimoda, Yoshihiro 309a3633fe7SShimoda, Yoshihiro while (len) { 310a3633fe7SShimoda, Yoshihiro *dst++ = (u16)(*src++); 311a3633fe7SShimoda, Yoshihiro len--; 312a3633fe7SShimoda, Yoshihiro } 313a3633fe7SShimoda, Yoshihiro } 314a3633fe7SShimoda, Yoshihiro 315a3633fe7SShimoda, Yoshihiro static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) 316a3633fe7SShimoda, Yoshihiro { 317a3633fe7SShimoda, Yoshihiro u8 *dst = buf; 318a3633fe7SShimoda, Yoshihiro const u16 *src = data; 319a3633fe7SShimoda, Yoshihiro 320a3633fe7SShimoda, Yoshihiro while (len) { 321a3633fe7SShimoda, Yoshihiro *dst++ = (u8)*src++; 322a3633fe7SShimoda, Yoshihiro len--; 323a3633fe7SShimoda, Yoshihiro } 324a3633fe7SShimoda, Yoshihiro } 325a3633fe7SShimoda, Yoshihiro 326a3633fe7SShimoda, Yoshihiro static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) 327a3633fe7SShimoda, Yoshihiro { 328a3633fe7SShimoda, Yoshihiro struct scatterlist sg; 329a3633fe7SShimoda, Yoshihiro void *buf = NULL; 330a3633fe7SShimoda, Yoshihiro struct dma_async_tx_descriptor *desc; 331a3633fe7SShimoda, Yoshihiro unsigned len; 332a3633fe7SShimoda, Yoshihiro int ret = 0; 333a3633fe7SShimoda, Yoshihiro 334a3633fe7SShimoda, Yoshihiro if (rspi->dma_width_16bit) { 335a3633fe7SShimoda, Yoshihiro /* 336a3633fe7SShimoda, Yoshihiro * If DMAC bus width is 16-bit, the driver allocates a dummy 337a3633fe7SShimoda, Yoshihiro * buffer. And, the driver converts original data into the 338a3633fe7SShimoda, Yoshihiro * DMAC data as the following format: 339a3633fe7SShimoda, Yoshihiro * original data: 1st byte, 2nd byte ... 340a3633fe7SShimoda, Yoshihiro * DMAC data: 1st byte, dummy, 2nd byte, dummy ... 341a3633fe7SShimoda, Yoshihiro */ 342a3633fe7SShimoda, Yoshihiro len = t->len * 2; 343a3633fe7SShimoda, Yoshihiro buf = kmalloc(len, GFP_KERNEL); 344a3633fe7SShimoda, Yoshihiro if (!buf) 345a3633fe7SShimoda, Yoshihiro return -ENOMEM; 346a3633fe7SShimoda, Yoshihiro rspi_memory_to_8bit(buf, t->tx_buf, t->len); 347a3633fe7SShimoda, Yoshihiro } else { 348a3633fe7SShimoda, Yoshihiro len = t->len; 349a3633fe7SShimoda, Yoshihiro buf = (void *)t->tx_buf; 350a3633fe7SShimoda, Yoshihiro } 351a3633fe7SShimoda, Yoshihiro 352a3633fe7SShimoda, Yoshihiro if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { 353a3633fe7SShimoda, Yoshihiro ret = -EFAULT; 354a3633fe7SShimoda, Yoshihiro goto end_nomap; 355a3633fe7SShimoda, Yoshihiro } 356a3633fe7SShimoda, Yoshihiro desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, 357a3633fe7SShimoda, Yoshihiro DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 358a3633fe7SShimoda, Yoshihiro if (!desc) { 359a3633fe7SShimoda, Yoshihiro ret = -EIO; 360a3633fe7SShimoda, Yoshihiro goto end; 361a3633fe7SShimoda, Yoshihiro } 362a3633fe7SShimoda, Yoshihiro 363a3633fe7SShimoda, Yoshihiro /* 364a3633fe7SShimoda, Yoshihiro * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 365a3633fe7SShimoda, Yoshihiro * called. So, this driver disables the IRQ while DMA transfer. 366a3633fe7SShimoda, Yoshihiro */ 367a3633fe7SShimoda, Yoshihiro disable_irq(rspi->irq); 368a3633fe7SShimoda, Yoshihiro 369a3633fe7SShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); 370a3633fe7SShimoda, Yoshihiro rspi_enable_irq(rspi, SPCR_SPTIE); 371a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked = 0; 372a3633fe7SShimoda, Yoshihiro 373a3633fe7SShimoda, Yoshihiro desc->callback = rspi_dma_complete; 374a3633fe7SShimoda, Yoshihiro desc->callback_param = rspi; 375a3633fe7SShimoda, Yoshihiro dmaengine_submit(desc); 376a3633fe7SShimoda, Yoshihiro dma_async_issue_pending(rspi->chan_tx); 377a3633fe7SShimoda, Yoshihiro 378a3633fe7SShimoda, Yoshihiro ret = wait_event_interruptible_timeout(rspi->wait, 379a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked, HZ); 380a3633fe7SShimoda, Yoshihiro if (ret > 0 && rspi->dma_callbacked) 381a3633fe7SShimoda, Yoshihiro ret = 0; 382a3633fe7SShimoda, Yoshihiro else if (!ret) 383a3633fe7SShimoda, Yoshihiro ret = -ETIMEDOUT; 384a3633fe7SShimoda, Yoshihiro rspi_disable_irq(rspi, SPCR_SPTIE); 385a3633fe7SShimoda, Yoshihiro 386a3633fe7SShimoda, Yoshihiro enable_irq(rspi->irq); 387a3633fe7SShimoda, Yoshihiro 388a3633fe7SShimoda, Yoshihiro end: 389a3633fe7SShimoda, Yoshihiro rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); 390a3633fe7SShimoda, Yoshihiro end_nomap: 391a3633fe7SShimoda, Yoshihiro if (rspi->dma_width_16bit) 392a3633fe7SShimoda, Yoshihiro kfree(buf); 393a3633fe7SShimoda, Yoshihiro 394a3633fe7SShimoda, Yoshihiro return ret; 395a3633fe7SShimoda, Yoshihiro } 396a3633fe7SShimoda, Yoshihiro 397a3633fe7SShimoda, Yoshihiro static void rspi_receive_init(struct rspi_data *rspi) 398a3633fe7SShimoda, Yoshihiro { 3990b2182ddSShimoda, Yoshihiro unsigned char spsr; 4000b2182ddSShimoda, Yoshihiro 4010b2182ddSShimoda, Yoshihiro spsr = rspi_read8(rspi, RSPI_SPSR); 4020b2182ddSShimoda, Yoshihiro if (spsr & SPSR_SPRF) 4030b2182ddSShimoda, Yoshihiro rspi_read16(rspi, RSPI_SPDR); /* dummy read */ 4040b2182ddSShimoda, Yoshihiro if (spsr & SPSR_OVRF) 4050b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 4060b2182ddSShimoda, Yoshihiro RSPI_SPCR); 407a3633fe7SShimoda, Yoshihiro } 408a3633fe7SShimoda, Yoshihiro 409a3633fe7SShimoda, Yoshihiro static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg, 410a3633fe7SShimoda, Yoshihiro struct spi_transfer *t) 411a3633fe7SShimoda, Yoshihiro { 412a3633fe7SShimoda, Yoshihiro int remain = t->len; 413a3633fe7SShimoda, Yoshihiro u8 *data; 414a3633fe7SShimoda, Yoshihiro 415a3633fe7SShimoda, Yoshihiro rspi_receive_init(rspi); 4160b2182ddSShimoda, Yoshihiro 4170b2182ddSShimoda, Yoshihiro data = (u8 *)t->rx_buf; 4180b2182ddSShimoda, Yoshihiro while (remain > 0) { 4190b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, 4200b2182ddSShimoda, Yoshihiro RSPI_SPCR); 4210b2182ddSShimoda, Yoshihiro 4220b2182ddSShimoda, Yoshihiro if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { 4230b2182ddSShimoda, Yoshihiro dev_err(&rspi->master->dev, 4240b2182ddSShimoda, Yoshihiro "%s: tx empty timeout\n", __func__); 4250b2182ddSShimoda, Yoshihiro return -ETIMEDOUT; 4260b2182ddSShimoda, Yoshihiro } 4270b2182ddSShimoda, Yoshihiro /* dummy write for generate clock */ 4280b2182ddSShimoda, Yoshihiro rspi_write16(rspi, 0x00, RSPI_SPDR); 4290b2182ddSShimoda, Yoshihiro 4300b2182ddSShimoda, Yoshihiro if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { 4310b2182ddSShimoda, Yoshihiro dev_err(&rspi->master->dev, 4320b2182ddSShimoda, Yoshihiro "%s: receive timeout\n", __func__); 4330b2182ddSShimoda, Yoshihiro return -ETIMEDOUT; 4340b2182ddSShimoda, Yoshihiro } 4350b2182ddSShimoda, Yoshihiro /* SPDR allows 16 or 32-bit access only */ 4360b2182ddSShimoda, Yoshihiro *data = (u8)rspi_read16(rspi, RSPI_SPDR); 4370b2182ddSShimoda, Yoshihiro 4380b2182ddSShimoda, Yoshihiro data++; 4390b2182ddSShimoda, Yoshihiro remain--; 4400b2182ddSShimoda, Yoshihiro } 4410b2182ddSShimoda, Yoshihiro 4420b2182ddSShimoda, Yoshihiro return 0; 4430b2182ddSShimoda, Yoshihiro } 4440b2182ddSShimoda, Yoshihiro 445a3633fe7SShimoda, Yoshihiro static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) 446a3633fe7SShimoda, Yoshihiro { 447a3633fe7SShimoda, Yoshihiro struct scatterlist sg, sg_dummy; 448a3633fe7SShimoda, Yoshihiro void *dummy = NULL, *rx_buf = NULL; 449a3633fe7SShimoda, Yoshihiro struct dma_async_tx_descriptor *desc, *desc_dummy; 450a3633fe7SShimoda, Yoshihiro unsigned len; 451a3633fe7SShimoda, Yoshihiro int ret = 0; 452a3633fe7SShimoda, Yoshihiro 453a3633fe7SShimoda, Yoshihiro if (rspi->dma_width_16bit) { 454a3633fe7SShimoda, Yoshihiro /* 455a3633fe7SShimoda, Yoshihiro * If DMAC bus width is 16-bit, the driver allocates a dummy 456a3633fe7SShimoda, Yoshihiro * buffer. And, finally the driver converts the DMAC data into 457a3633fe7SShimoda, Yoshihiro * actual data as the following format: 458a3633fe7SShimoda, Yoshihiro * DMAC data: 1st byte, dummy, 2nd byte, dummy ... 459a3633fe7SShimoda, Yoshihiro * actual data: 1st byte, 2nd byte ... 460a3633fe7SShimoda, Yoshihiro */ 461a3633fe7SShimoda, Yoshihiro len = t->len * 2; 462a3633fe7SShimoda, Yoshihiro rx_buf = kmalloc(len, GFP_KERNEL); 463a3633fe7SShimoda, Yoshihiro if (!rx_buf) 464a3633fe7SShimoda, Yoshihiro return -ENOMEM; 465a3633fe7SShimoda, Yoshihiro } else { 466a3633fe7SShimoda, Yoshihiro len = t->len; 467a3633fe7SShimoda, Yoshihiro rx_buf = t->rx_buf; 468a3633fe7SShimoda, Yoshihiro } 469a3633fe7SShimoda, Yoshihiro 470a3633fe7SShimoda, Yoshihiro /* prepare dummy transfer to generate SPI clocks */ 471a3633fe7SShimoda, Yoshihiro dummy = kzalloc(len, GFP_KERNEL); 472a3633fe7SShimoda, Yoshihiro if (!dummy) { 473a3633fe7SShimoda, Yoshihiro ret = -ENOMEM; 474a3633fe7SShimoda, Yoshihiro goto end_nomap; 475a3633fe7SShimoda, Yoshihiro } 476a3633fe7SShimoda, Yoshihiro if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, 477a3633fe7SShimoda, Yoshihiro DMA_TO_DEVICE)) { 478a3633fe7SShimoda, Yoshihiro ret = -EFAULT; 479a3633fe7SShimoda, Yoshihiro goto end_nomap; 480a3633fe7SShimoda, Yoshihiro } 481a3633fe7SShimoda, Yoshihiro desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, 482a3633fe7SShimoda, Yoshihiro DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 483a3633fe7SShimoda, Yoshihiro if (!desc_dummy) { 484a3633fe7SShimoda, Yoshihiro ret = -EIO; 485a3633fe7SShimoda, Yoshihiro goto end_dummy_mapped; 486a3633fe7SShimoda, Yoshihiro } 487a3633fe7SShimoda, Yoshihiro 488a3633fe7SShimoda, Yoshihiro /* prepare receive transfer */ 489a3633fe7SShimoda, Yoshihiro if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, 490a3633fe7SShimoda, Yoshihiro DMA_FROM_DEVICE)) { 491a3633fe7SShimoda, Yoshihiro ret = -EFAULT; 492a3633fe7SShimoda, Yoshihiro goto end_dummy_mapped; 493a3633fe7SShimoda, Yoshihiro 494a3633fe7SShimoda, Yoshihiro } 495a3633fe7SShimoda, Yoshihiro desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, 496a3633fe7SShimoda, Yoshihiro DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 497a3633fe7SShimoda, Yoshihiro if (!desc) { 498a3633fe7SShimoda, Yoshihiro ret = -EIO; 499a3633fe7SShimoda, Yoshihiro goto end; 500a3633fe7SShimoda, Yoshihiro } 501a3633fe7SShimoda, Yoshihiro 502a3633fe7SShimoda, Yoshihiro rspi_receive_init(rspi); 503a3633fe7SShimoda, Yoshihiro 504a3633fe7SShimoda, Yoshihiro /* 505a3633fe7SShimoda, Yoshihiro * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 506a3633fe7SShimoda, Yoshihiro * called. So, this driver disables the IRQ while DMA transfer. 507a3633fe7SShimoda, Yoshihiro */ 508a3633fe7SShimoda, Yoshihiro disable_irq(rspi->irq); 509a3633fe7SShimoda, Yoshihiro 510a3633fe7SShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); 511a3633fe7SShimoda, Yoshihiro rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 512a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked = 0; 513a3633fe7SShimoda, Yoshihiro 514a3633fe7SShimoda, Yoshihiro desc->callback = rspi_dma_complete; 515a3633fe7SShimoda, Yoshihiro desc->callback_param = rspi; 516a3633fe7SShimoda, Yoshihiro dmaengine_submit(desc); 517a3633fe7SShimoda, Yoshihiro dma_async_issue_pending(rspi->chan_rx); 518a3633fe7SShimoda, Yoshihiro 519a3633fe7SShimoda, Yoshihiro desc_dummy->callback = NULL; /* No callback */ 520a3633fe7SShimoda, Yoshihiro dmaengine_submit(desc_dummy); 521a3633fe7SShimoda, Yoshihiro dma_async_issue_pending(rspi->chan_tx); 522a3633fe7SShimoda, Yoshihiro 523a3633fe7SShimoda, Yoshihiro ret = wait_event_interruptible_timeout(rspi->wait, 524a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked, HZ); 525a3633fe7SShimoda, Yoshihiro if (ret > 0 && rspi->dma_callbacked) 526a3633fe7SShimoda, Yoshihiro ret = 0; 527a3633fe7SShimoda, Yoshihiro else if (!ret) 528a3633fe7SShimoda, Yoshihiro ret = -ETIMEDOUT; 529a3633fe7SShimoda, Yoshihiro rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 530a3633fe7SShimoda, Yoshihiro 531a3633fe7SShimoda, Yoshihiro enable_irq(rspi->irq); 532a3633fe7SShimoda, Yoshihiro 533a3633fe7SShimoda, Yoshihiro end: 534a3633fe7SShimoda, Yoshihiro rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); 535a3633fe7SShimoda, Yoshihiro end_dummy_mapped: 536a3633fe7SShimoda, Yoshihiro rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); 537a3633fe7SShimoda, Yoshihiro end_nomap: 538a3633fe7SShimoda, Yoshihiro if (rspi->dma_width_16bit) { 539a3633fe7SShimoda, Yoshihiro if (!ret) 540a3633fe7SShimoda, Yoshihiro rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); 541a3633fe7SShimoda, Yoshihiro kfree(rx_buf); 542a3633fe7SShimoda, Yoshihiro } 543a3633fe7SShimoda, Yoshihiro kfree(dummy); 544a3633fe7SShimoda, Yoshihiro 545a3633fe7SShimoda, Yoshihiro return ret; 546a3633fe7SShimoda, Yoshihiro } 547a3633fe7SShimoda, Yoshihiro 548a3633fe7SShimoda, Yoshihiro static int rspi_is_dma(struct rspi_data *rspi, struct spi_transfer *t) 549a3633fe7SShimoda, Yoshihiro { 550a3633fe7SShimoda, Yoshihiro if (t->tx_buf && rspi->chan_tx) 551a3633fe7SShimoda, Yoshihiro return 1; 552a3633fe7SShimoda, Yoshihiro /* If the module receives data by DMAC, it also needs TX DMAC */ 553a3633fe7SShimoda, Yoshihiro if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) 554a3633fe7SShimoda, Yoshihiro return 1; 555a3633fe7SShimoda, Yoshihiro 556a3633fe7SShimoda, Yoshihiro return 0; 557a3633fe7SShimoda, Yoshihiro } 558a3633fe7SShimoda, Yoshihiro 5590b2182ddSShimoda, Yoshihiro static void rspi_work(struct work_struct *work) 5600b2182ddSShimoda, Yoshihiro { 5610b2182ddSShimoda, Yoshihiro struct rspi_data *rspi = container_of(work, struct rspi_data, ws); 5620b2182ddSShimoda, Yoshihiro struct spi_message *mesg; 5630b2182ddSShimoda, Yoshihiro struct spi_transfer *t; 5640b2182ddSShimoda, Yoshihiro unsigned long flags; 5650b2182ddSShimoda, Yoshihiro int ret; 5660b2182ddSShimoda, Yoshihiro 5678d4d08ceSShimoda, Yoshihiro while (1) { 5680b2182ddSShimoda, Yoshihiro spin_lock_irqsave(&rspi->lock, flags); 5698d4d08ceSShimoda, Yoshihiro if (list_empty(&rspi->queue)) { 5708d4d08ceSShimoda, Yoshihiro spin_unlock_irqrestore(&rspi->lock, flags); 5718d4d08ceSShimoda, Yoshihiro break; 5728d4d08ceSShimoda, Yoshihiro } 5730b2182ddSShimoda, Yoshihiro mesg = list_entry(rspi->queue.next, struct spi_message, queue); 5740b2182ddSShimoda, Yoshihiro list_del_init(&mesg->queue); 5750b2182ddSShimoda, Yoshihiro spin_unlock_irqrestore(&rspi->lock, flags); 5760b2182ddSShimoda, Yoshihiro 5770b2182ddSShimoda, Yoshihiro rspi_assert_ssl(rspi); 5780b2182ddSShimoda, Yoshihiro 5790b2182ddSShimoda, Yoshihiro list_for_each_entry(t, &mesg->transfers, transfer_list) { 5800b2182ddSShimoda, Yoshihiro if (t->tx_buf) { 581a3633fe7SShimoda, Yoshihiro if (rspi_is_dma(rspi, t)) 582a3633fe7SShimoda, Yoshihiro ret = rspi_send_dma(rspi, t); 583a3633fe7SShimoda, Yoshihiro else 5840b2182ddSShimoda, Yoshihiro ret = rspi_send_pio(rspi, mesg, t); 5850b2182ddSShimoda, Yoshihiro if (ret < 0) 5860b2182ddSShimoda, Yoshihiro goto error; 5870b2182ddSShimoda, Yoshihiro } 5880b2182ddSShimoda, Yoshihiro if (t->rx_buf) { 589a3633fe7SShimoda, Yoshihiro if (rspi_is_dma(rspi, t)) 590a3633fe7SShimoda, Yoshihiro ret = rspi_receive_dma(rspi, t); 591a3633fe7SShimoda, Yoshihiro else 5920b2182ddSShimoda, Yoshihiro ret = rspi_receive_pio(rspi, mesg, t); 5930b2182ddSShimoda, Yoshihiro if (ret < 0) 5940b2182ddSShimoda, Yoshihiro goto error; 5950b2182ddSShimoda, Yoshihiro } 5960b2182ddSShimoda, Yoshihiro mesg->actual_length += t->len; 5970b2182ddSShimoda, Yoshihiro } 5980b2182ddSShimoda, Yoshihiro rspi_negate_ssl(rspi); 5990b2182ddSShimoda, Yoshihiro 6000b2182ddSShimoda, Yoshihiro mesg->status = 0; 6010b2182ddSShimoda, Yoshihiro mesg->complete(mesg->context); 6020b2182ddSShimoda, Yoshihiro } 6030b2182ddSShimoda, Yoshihiro 6040b2182ddSShimoda, Yoshihiro return; 6050b2182ddSShimoda, Yoshihiro 6060b2182ddSShimoda, Yoshihiro error: 6070b2182ddSShimoda, Yoshihiro mesg->status = ret; 6080b2182ddSShimoda, Yoshihiro mesg->complete(mesg->context); 6090b2182ddSShimoda, Yoshihiro } 6100b2182ddSShimoda, Yoshihiro 6110b2182ddSShimoda, Yoshihiro static int rspi_setup(struct spi_device *spi) 6120b2182ddSShimoda, Yoshihiro { 6130b2182ddSShimoda, Yoshihiro struct rspi_data *rspi = spi_master_get_devdata(spi->master); 6140b2182ddSShimoda, Yoshihiro 6150b2182ddSShimoda, Yoshihiro if (!spi->bits_per_word) 6160b2182ddSShimoda, Yoshihiro spi->bits_per_word = 8; 6170b2182ddSShimoda, Yoshihiro rspi->max_speed_hz = spi->max_speed_hz; 6180b2182ddSShimoda, Yoshihiro 6190b2182ddSShimoda, Yoshihiro rspi_set_config_register(rspi, 8); 6200b2182ddSShimoda, Yoshihiro 6210b2182ddSShimoda, Yoshihiro return 0; 6220b2182ddSShimoda, Yoshihiro } 6230b2182ddSShimoda, Yoshihiro 6240b2182ddSShimoda, Yoshihiro static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg) 6250b2182ddSShimoda, Yoshihiro { 6260b2182ddSShimoda, Yoshihiro struct rspi_data *rspi = spi_master_get_devdata(spi->master); 6270b2182ddSShimoda, Yoshihiro unsigned long flags; 6280b2182ddSShimoda, Yoshihiro 6290b2182ddSShimoda, Yoshihiro mesg->actual_length = 0; 6300b2182ddSShimoda, Yoshihiro mesg->status = -EINPROGRESS; 6310b2182ddSShimoda, Yoshihiro 6320b2182ddSShimoda, Yoshihiro spin_lock_irqsave(&rspi->lock, flags); 6330b2182ddSShimoda, Yoshihiro list_add_tail(&mesg->queue, &rspi->queue); 6340b2182ddSShimoda, Yoshihiro schedule_work(&rspi->ws); 6350b2182ddSShimoda, Yoshihiro spin_unlock_irqrestore(&rspi->lock, flags); 6360b2182ddSShimoda, Yoshihiro 6370b2182ddSShimoda, Yoshihiro return 0; 6380b2182ddSShimoda, Yoshihiro } 6390b2182ddSShimoda, Yoshihiro 6400b2182ddSShimoda, Yoshihiro static void rspi_cleanup(struct spi_device *spi) 6410b2182ddSShimoda, Yoshihiro { 6420b2182ddSShimoda, Yoshihiro } 6430b2182ddSShimoda, Yoshihiro 6440b2182ddSShimoda, Yoshihiro static irqreturn_t rspi_irq(int irq, void *_sr) 6450b2182ddSShimoda, Yoshihiro { 6460b2182ddSShimoda, Yoshihiro struct rspi_data *rspi = (struct rspi_data *)_sr; 6470b2182ddSShimoda, Yoshihiro unsigned long spsr; 6480b2182ddSShimoda, Yoshihiro irqreturn_t ret = IRQ_NONE; 6490b2182ddSShimoda, Yoshihiro unsigned char disable_irq = 0; 6500b2182ddSShimoda, Yoshihiro 6510b2182ddSShimoda, Yoshihiro rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 6520b2182ddSShimoda, Yoshihiro if (spsr & SPSR_SPRF) 6530b2182ddSShimoda, Yoshihiro disable_irq |= SPCR_SPRIE; 6540b2182ddSShimoda, Yoshihiro if (spsr & SPSR_SPTEF) 6550b2182ddSShimoda, Yoshihiro disable_irq |= SPCR_SPTIE; 6560b2182ddSShimoda, Yoshihiro 6570b2182ddSShimoda, Yoshihiro if (disable_irq) { 6580b2182ddSShimoda, Yoshihiro ret = IRQ_HANDLED; 6590b2182ddSShimoda, Yoshihiro rspi_disable_irq(rspi, disable_irq); 6600b2182ddSShimoda, Yoshihiro wake_up(&rspi->wait); 6610b2182ddSShimoda, Yoshihiro } 6620b2182ddSShimoda, Yoshihiro 6630b2182ddSShimoda, Yoshihiro return ret; 6640b2182ddSShimoda, Yoshihiro } 6650b2182ddSShimoda, Yoshihiro 666fd4a319bSGrant Likely static int rspi_request_dma(struct rspi_data *rspi, 667a3633fe7SShimoda, Yoshihiro struct platform_device *pdev) 668a3633fe7SShimoda, Yoshihiro { 669e2b05099SGuennadi Liakhovetski struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 670a3633fe7SShimoda, Yoshihiro struct rspi_plat_data *rspi_pd = pdev->dev.platform_data; 671a3633fe7SShimoda, Yoshihiro dma_cap_mask_t mask; 6720243c536SShimoda, Yoshihiro struct dma_slave_config cfg; 6730243c536SShimoda, Yoshihiro int ret; 674a3633fe7SShimoda, Yoshihiro 675e2b05099SGuennadi Liakhovetski if (!res || !rspi_pd) 6760243c536SShimoda, Yoshihiro return 0; /* The driver assumes no error. */ 677a3633fe7SShimoda, Yoshihiro 678a3633fe7SShimoda, Yoshihiro rspi->dma_width_16bit = rspi_pd->dma_width_16bit; 679a3633fe7SShimoda, Yoshihiro 680a3633fe7SShimoda, Yoshihiro /* If the module receives data by DMAC, it also needs TX DMAC */ 681a3633fe7SShimoda, Yoshihiro if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { 682a3633fe7SShimoda, Yoshihiro dma_cap_zero(mask); 683a3633fe7SShimoda, Yoshihiro dma_cap_set(DMA_SLAVE, mask); 6840243c536SShimoda, Yoshihiro rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, 6850243c536SShimoda, Yoshihiro (void *)rspi_pd->dma_rx_id); 6860243c536SShimoda, Yoshihiro if (rspi->chan_rx) { 6870243c536SShimoda, Yoshihiro cfg.slave_id = rspi_pd->dma_rx_id; 6880243c536SShimoda, Yoshihiro cfg.direction = DMA_DEV_TO_MEM; 689e2b05099SGuennadi Liakhovetski cfg.dst_addr = 0; 690e2b05099SGuennadi Liakhovetski cfg.src_addr = res->start + RSPI_SPDR; 6910243c536SShimoda, Yoshihiro ret = dmaengine_slave_config(rspi->chan_rx, &cfg); 6920243c536SShimoda, Yoshihiro if (!ret) 693a3633fe7SShimoda, Yoshihiro dev_info(&pdev->dev, "Use DMA when rx.\n"); 6940243c536SShimoda, Yoshihiro else 6950243c536SShimoda, Yoshihiro return ret; 6960243c536SShimoda, Yoshihiro } 697a3633fe7SShimoda, Yoshihiro } 698a3633fe7SShimoda, Yoshihiro if (rspi_pd->dma_tx_id) { 699a3633fe7SShimoda, Yoshihiro dma_cap_zero(mask); 700a3633fe7SShimoda, Yoshihiro dma_cap_set(DMA_SLAVE, mask); 7010243c536SShimoda, Yoshihiro rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, 7020243c536SShimoda, Yoshihiro (void *)rspi_pd->dma_tx_id); 7030243c536SShimoda, Yoshihiro if (rspi->chan_tx) { 7040243c536SShimoda, Yoshihiro cfg.slave_id = rspi_pd->dma_tx_id; 7050243c536SShimoda, Yoshihiro cfg.direction = DMA_MEM_TO_DEV; 706e2b05099SGuennadi Liakhovetski cfg.dst_addr = res->start + RSPI_SPDR; 707e2b05099SGuennadi Liakhovetski cfg.src_addr = 0; 7080243c536SShimoda, Yoshihiro ret = dmaengine_slave_config(rspi->chan_tx, &cfg); 7090243c536SShimoda, Yoshihiro if (!ret) 710a3633fe7SShimoda, Yoshihiro dev_info(&pdev->dev, "Use DMA when tx\n"); 7110243c536SShimoda, Yoshihiro else 7120243c536SShimoda, Yoshihiro return ret; 713a3633fe7SShimoda, Yoshihiro } 714a3633fe7SShimoda, Yoshihiro } 715a3633fe7SShimoda, Yoshihiro 7160243c536SShimoda, Yoshihiro return 0; 7170243c536SShimoda, Yoshihiro } 7180243c536SShimoda, Yoshihiro 719fd4a319bSGrant Likely static void rspi_release_dma(struct rspi_data *rspi) 720a3633fe7SShimoda, Yoshihiro { 721a3633fe7SShimoda, Yoshihiro if (rspi->chan_tx) 722a3633fe7SShimoda, Yoshihiro dma_release_channel(rspi->chan_tx); 723a3633fe7SShimoda, Yoshihiro if (rspi->chan_rx) 724a3633fe7SShimoda, Yoshihiro dma_release_channel(rspi->chan_rx); 725a3633fe7SShimoda, Yoshihiro } 726a3633fe7SShimoda, Yoshihiro 727fd4a319bSGrant Likely static int rspi_remove(struct platform_device *pdev) 7280b2182ddSShimoda, Yoshihiro { 7299d3405dbSAxel Lin struct rspi_data *rspi = spi_master_get(platform_get_drvdata(pdev)); 7300b2182ddSShimoda, Yoshihiro 7310b2182ddSShimoda, Yoshihiro spi_unregister_master(rspi->master); 732a3633fe7SShimoda, Yoshihiro rspi_release_dma(rspi); 7330b2182ddSShimoda, Yoshihiro free_irq(platform_get_irq(pdev, 0), rspi); 7340b2182ddSShimoda, Yoshihiro clk_put(rspi->clk); 7350b2182ddSShimoda, Yoshihiro iounmap(rspi->addr); 7360b2182ddSShimoda, Yoshihiro spi_master_put(rspi->master); 7370b2182ddSShimoda, Yoshihiro 7380b2182ddSShimoda, Yoshihiro return 0; 7390b2182ddSShimoda, Yoshihiro } 7400b2182ddSShimoda, Yoshihiro 741fd4a319bSGrant Likely static int rspi_probe(struct platform_device *pdev) 7420b2182ddSShimoda, Yoshihiro { 7430b2182ddSShimoda, Yoshihiro struct resource *res; 7440b2182ddSShimoda, Yoshihiro struct spi_master *master; 7450b2182ddSShimoda, Yoshihiro struct rspi_data *rspi; 7460b2182ddSShimoda, Yoshihiro int ret, irq; 7470b2182ddSShimoda, Yoshihiro char clk_name[16]; 7480b2182ddSShimoda, Yoshihiro 7490b2182ddSShimoda, Yoshihiro /* get base addr */ 7500b2182ddSShimoda, Yoshihiro res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 7510b2182ddSShimoda, Yoshihiro if (unlikely(res == NULL)) { 7520b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "invalid resource\n"); 7530b2182ddSShimoda, Yoshihiro return -EINVAL; 7540b2182ddSShimoda, Yoshihiro } 7550b2182ddSShimoda, Yoshihiro 7560b2182ddSShimoda, Yoshihiro irq = platform_get_irq(pdev, 0); 7570b2182ddSShimoda, Yoshihiro if (irq < 0) { 7580b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "platform_get_irq error\n"); 7590b2182ddSShimoda, Yoshihiro return -ENODEV; 7600b2182ddSShimoda, Yoshihiro } 7610b2182ddSShimoda, Yoshihiro 7620b2182ddSShimoda, Yoshihiro master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 7630b2182ddSShimoda, Yoshihiro if (master == NULL) { 7640b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "spi_alloc_master error.\n"); 7650b2182ddSShimoda, Yoshihiro return -ENOMEM; 7660b2182ddSShimoda, Yoshihiro } 7670b2182ddSShimoda, Yoshihiro 7680b2182ddSShimoda, Yoshihiro rspi = spi_master_get_devdata(master); 76924b5a82cSJingoo Han platform_set_drvdata(pdev, rspi); 7700b2182ddSShimoda, Yoshihiro 7710b2182ddSShimoda, Yoshihiro rspi->master = master; 7720b2182ddSShimoda, Yoshihiro rspi->addr = ioremap(res->start, resource_size(res)); 7730b2182ddSShimoda, Yoshihiro if (rspi->addr == NULL) { 7740b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "ioremap error.\n"); 7750b2182ddSShimoda, Yoshihiro ret = -ENOMEM; 7760b2182ddSShimoda, Yoshihiro goto error1; 7770b2182ddSShimoda, Yoshihiro } 7780b2182ddSShimoda, Yoshihiro 7790b2182ddSShimoda, Yoshihiro snprintf(clk_name, sizeof(clk_name), "rspi%d", pdev->id); 7800b2182ddSShimoda, Yoshihiro rspi->clk = clk_get(&pdev->dev, clk_name); 7810b2182ddSShimoda, Yoshihiro if (IS_ERR(rspi->clk)) { 7820b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "cannot get clock\n"); 7830b2182ddSShimoda, Yoshihiro ret = PTR_ERR(rspi->clk); 7840b2182ddSShimoda, Yoshihiro goto error2; 7850b2182ddSShimoda, Yoshihiro } 7860b2182ddSShimoda, Yoshihiro clk_enable(rspi->clk); 7870b2182ddSShimoda, Yoshihiro 7880b2182ddSShimoda, Yoshihiro INIT_LIST_HEAD(&rspi->queue); 7890b2182ddSShimoda, Yoshihiro spin_lock_init(&rspi->lock); 7900b2182ddSShimoda, Yoshihiro INIT_WORK(&rspi->ws, rspi_work); 7910b2182ddSShimoda, Yoshihiro init_waitqueue_head(&rspi->wait); 7920b2182ddSShimoda, Yoshihiro 7930b2182ddSShimoda, Yoshihiro master->num_chipselect = 2; 7940b2182ddSShimoda, Yoshihiro master->bus_num = pdev->id; 7950b2182ddSShimoda, Yoshihiro master->setup = rspi_setup; 7960b2182ddSShimoda, Yoshihiro master->transfer = rspi_transfer; 7970b2182ddSShimoda, Yoshihiro master->cleanup = rspi_cleanup; 7980b2182ddSShimoda, Yoshihiro 7990b2182ddSShimoda, Yoshihiro ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi); 8000b2182ddSShimoda, Yoshihiro if (ret < 0) { 8010b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "request_irq error\n"); 8020b2182ddSShimoda, Yoshihiro goto error3; 8030b2182ddSShimoda, Yoshihiro } 8040b2182ddSShimoda, Yoshihiro 805a3633fe7SShimoda, Yoshihiro rspi->irq = irq; 8060243c536SShimoda, Yoshihiro ret = rspi_request_dma(rspi, pdev); 8070243c536SShimoda, Yoshihiro if (ret < 0) { 8080243c536SShimoda, Yoshihiro dev_err(&pdev->dev, "rspi_request_dma failed.\n"); 8090243c536SShimoda, Yoshihiro goto error4; 8100243c536SShimoda, Yoshihiro } 811a3633fe7SShimoda, Yoshihiro 8120b2182ddSShimoda, Yoshihiro ret = spi_register_master(master); 8130b2182ddSShimoda, Yoshihiro if (ret < 0) { 8140b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "spi_register_master error.\n"); 8150b2182ddSShimoda, Yoshihiro goto error4; 8160b2182ddSShimoda, Yoshihiro } 8170b2182ddSShimoda, Yoshihiro 8180b2182ddSShimoda, Yoshihiro dev_info(&pdev->dev, "probed\n"); 8190b2182ddSShimoda, Yoshihiro 8200b2182ddSShimoda, Yoshihiro return 0; 8210b2182ddSShimoda, Yoshihiro 8220b2182ddSShimoda, Yoshihiro error4: 823a3633fe7SShimoda, Yoshihiro rspi_release_dma(rspi); 8240b2182ddSShimoda, Yoshihiro free_irq(irq, rspi); 8250b2182ddSShimoda, Yoshihiro error3: 8260b2182ddSShimoda, Yoshihiro clk_put(rspi->clk); 8270b2182ddSShimoda, Yoshihiro error2: 8280b2182ddSShimoda, Yoshihiro iounmap(rspi->addr); 8290b2182ddSShimoda, Yoshihiro error1: 8300b2182ddSShimoda, Yoshihiro spi_master_put(master); 8310b2182ddSShimoda, Yoshihiro 8320b2182ddSShimoda, Yoshihiro return ret; 8330b2182ddSShimoda, Yoshihiro } 8340b2182ddSShimoda, Yoshihiro 8350b2182ddSShimoda, Yoshihiro static struct platform_driver rspi_driver = { 8360b2182ddSShimoda, Yoshihiro .probe = rspi_probe, 837fd4a319bSGrant Likely .remove = rspi_remove, 8380b2182ddSShimoda, Yoshihiro .driver = { 8390b2182ddSShimoda, Yoshihiro .name = "rspi", 8400b2182ddSShimoda, Yoshihiro .owner = THIS_MODULE, 8410b2182ddSShimoda, Yoshihiro }, 8420b2182ddSShimoda, Yoshihiro }; 8430b2182ddSShimoda, Yoshihiro module_platform_driver(rspi_driver); 8440b2182ddSShimoda, Yoshihiro 8450b2182ddSShimoda, Yoshihiro MODULE_DESCRIPTION("Renesas RSPI bus driver"); 8460b2182ddSShimoda, Yoshihiro MODULE_LICENSE("GPL v2"); 8470b2182ddSShimoda, Yoshihiro MODULE_AUTHOR("Yoshihiro Shimoda"); 8480b2182ddSShimoda, Yoshihiro MODULE_ALIAS("platform:rspi"); 849