10b2182ddSShimoda, Yoshihiro /* 20b2182ddSShimoda, Yoshihiro * SH RSPI driver 30b2182ddSShimoda, Yoshihiro * 493722206SGeert Uytterhoeven * Copyright (C) 2012, 2013 Renesas Solutions Corp. 5880c6d11SGeert Uytterhoeven * Copyright (C) 2014 Glider bvba 60b2182ddSShimoda, Yoshihiro * 70b2182ddSShimoda, Yoshihiro * Based on spi-sh.c: 80b2182ddSShimoda, Yoshihiro * Copyright (C) 2011 Renesas Solutions Corp. 90b2182ddSShimoda, Yoshihiro * 100b2182ddSShimoda, Yoshihiro * This program is free software; you can redistribute it and/or modify 110b2182ddSShimoda, Yoshihiro * it under the terms of the GNU General Public License as published by 120b2182ddSShimoda, Yoshihiro * the Free Software Foundation; version 2 of the License. 130b2182ddSShimoda, Yoshihiro * 140b2182ddSShimoda, Yoshihiro * This program is distributed in the hope that it will be useful, 150b2182ddSShimoda, Yoshihiro * but WITHOUT ANY WARRANTY; without even the implied warranty of 160b2182ddSShimoda, Yoshihiro * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 170b2182ddSShimoda, Yoshihiro * GNU General Public License for more details. 180b2182ddSShimoda, Yoshihiro * 190b2182ddSShimoda, Yoshihiro * You should have received a copy of the GNU General Public License 200b2182ddSShimoda, Yoshihiro * along with this program; if not, write to the Free Software 210b2182ddSShimoda, Yoshihiro * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 220b2182ddSShimoda, Yoshihiro * 230b2182ddSShimoda, Yoshihiro */ 240b2182ddSShimoda, Yoshihiro 250b2182ddSShimoda, Yoshihiro #include <linux/module.h> 260b2182ddSShimoda, Yoshihiro #include <linux/kernel.h> 270b2182ddSShimoda, Yoshihiro #include <linux/sched.h> 280b2182ddSShimoda, Yoshihiro #include <linux/errno.h> 290b2182ddSShimoda, Yoshihiro #include <linux/interrupt.h> 300b2182ddSShimoda, Yoshihiro #include <linux/platform_device.h> 310b2182ddSShimoda, Yoshihiro #include <linux/io.h> 320b2182ddSShimoda, Yoshihiro #include <linux/clk.h> 33a3633fe7SShimoda, Yoshihiro #include <linux/dmaengine.h> 34a3633fe7SShimoda, Yoshihiro #include <linux/dma-mapping.h> 35426ef76dSGeert Uytterhoeven #include <linux/of_device.h> 36490c9774SGeert Uytterhoeven #include <linux/pm_runtime.h> 37a3633fe7SShimoda, Yoshihiro #include <linux/sh_dma.h> 380b2182ddSShimoda, Yoshihiro #include <linux/spi/spi.h> 39a3633fe7SShimoda, Yoshihiro #include <linux/spi/rspi.h> 400b2182ddSShimoda, Yoshihiro 416ab4865bSGeert Uytterhoeven #define RSPI_SPCR 0x00 /* Control Register */ 426ab4865bSGeert Uytterhoeven #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ 436ab4865bSGeert Uytterhoeven #define RSPI_SPPCR 0x02 /* Pin Control Register */ 446ab4865bSGeert Uytterhoeven #define RSPI_SPSR 0x03 /* Status Register */ 456ab4865bSGeert Uytterhoeven #define RSPI_SPDR 0x04 /* Data Register */ 466ab4865bSGeert Uytterhoeven #define RSPI_SPSCR 0x08 /* Sequence Control Register */ 476ab4865bSGeert Uytterhoeven #define RSPI_SPSSR 0x09 /* Sequence Status Register */ 486ab4865bSGeert Uytterhoeven #define RSPI_SPBR 0x0a /* Bit Rate Register */ 496ab4865bSGeert Uytterhoeven #define RSPI_SPDCR 0x0b /* Data Control Register */ 506ab4865bSGeert Uytterhoeven #define RSPI_SPCKD 0x0c /* Clock Delay Register */ 516ab4865bSGeert Uytterhoeven #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ 526ab4865bSGeert Uytterhoeven #define RSPI_SPND 0x0e /* Next-Access Delay Register */ 53862d357fSGeert Uytterhoeven #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ 546ab4865bSGeert Uytterhoeven #define RSPI_SPCMD0 0x10 /* Command Register 0 */ 556ab4865bSGeert Uytterhoeven #define RSPI_SPCMD1 0x12 /* Command Register 1 */ 566ab4865bSGeert Uytterhoeven #define RSPI_SPCMD2 0x14 /* Command Register 2 */ 576ab4865bSGeert Uytterhoeven #define RSPI_SPCMD3 0x16 /* Command Register 3 */ 586ab4865bSGeert Uytterhoeven #define RSPI_SPCMD4 0x18 /* Command Register 4 */ 596ab4865bSGeert Uytterhoeven #define RSPI_SPCMD5 0x1a /* Command Register 5 */ 606ab4865bSGeert Uytterhoeven #define RSPI_SPCMD6 0x1c /* Command Register 6 */ 616ab4865bSGeert Uytterhoeven #define RSPI_SPCMD7 0x1e /* Command Register 7 */ 62880c6d11SGeert Uytterhoeven #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) 63880c6d11SGeert Uytterhoeven #define RSPI_NUM_SPCMD 8 64880c6d11SGeert Uytterhoeven #define RSPI_RZ_NUM_SPCMD 4 65880c6d11SGeert Uytterhoeven #define QSPI_NUM_SPCMD 4 66862d357fSGeert Uytterhoeven 67862d357fSGeert Uytterhoeven /* RSPI on RZ only */ 686ab4865bSGeert Uytterhoeven #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ 696ab4865bSGeert Uytterhoeven #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ 700b2182ddSShimoda, Yoshihiro 71862d357fSGeert Uytterhoeven /* QSPI only */ 72fbe5072bSGeert Uytterhoeven #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ 73fbe5072bSGeert Uytterhoeven #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ 74fbe5072bSGeert Uytterhoeven #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ 75fbe5072bSGeert Uytterhoeven #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ 76fbe5072bSGeert Uytterhoeven #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ 77fbe5072bSGeert Uytterhoeven #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ 78880c6d11SGeert Uytterhoeven #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) 795ce0ba88SHiep Cao Minh 806ab4865bSGeert Uytterhoeven /* SPCR - Control Register */ 816ab4865bSGeert Uytterhoeven #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ 826ab4865bSGeert Uytterhoeven #define SPCR_SPE 0x40 /* Function Enable */ 836ab4865bSGeert Uytterhoeven #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ 846ab4865bSGeert Uytterhoeven #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ 856ab4865bSGeert Uytterhoeven #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ 866ab4865bSGeert Uytterhoeven #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ 876ab4865bSGeert Uytterhoeven /* RSPI on SH only */ 886ab4865bSGeert Uytterhoeven #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ 896ab4865bSGeert Uytterhoeven #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ 90fbe5072bSGeert Uytterhoeven /* QSPI on R-Car M2 only */ 91fbe5072bSGeert Uytterhoeven #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ 92fbe5072bSGeert Uytterhoeven #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ 930b2182ddSShimoda, Yoshihiro 946ab4865bSGeert Uytterhoeven /* SSLP - Slave Select Polarity Register */ 956ab4865bSGeert Uytterhoeven #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ 966ab4865bSGeert Uytterhoeven #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ 970b2182ddSShimoda, Yoshihiro 986ab4865bSGeert Uytterhoeven /* SPPCR - Pin Control Register */ 996ab4865bSGeert Uytterhoeven #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ 1006ab4865bSGeert Uytterhoeven #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ 1010b2182ddSShimoda, Yoshihiro #define SPPCR_SPOM 0x04 1026ab4865bSGeert Uytterhoeven #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ 1036ab4865bSGeert Uytterhoeven #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ 1040b2182ddSShimoda, Yoshihiro 105fbe5072bSGeert Uytterhoeven #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ 106fbe5072bSGeert Uytterhoeven #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ 107fbe5072bSGeert Uytterhoeven 1086ab4865bSGeert Uytterhoeven /* SPSR - Status Register */ 1096ab4865bSGeert Uytterhoeven #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ 1106ab4865bSGeert Uytterhoeven #define SPSR_TEND 0x40 /* Transmit End */ 1116ab4865bSGeert Uytterhoeven #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ 1126ab4865bSGeert Uytterhoeven #define SPSR_PERF 0x08 /* Parity Error Flag */ 1136ab4865bSGeert Uytterhoeven #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ 1146ab4865bSGeert Uytterhoeven #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ 115862d357fSGeert Uytterhoeven #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ 1160b2182ddSShimoda, Yoshihiro 1176ab4865bSGeert Uytterhoeven /* SPSCR - Sequence Control Register */ 1186ab4865bSGeert Uytterhoeven #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ 1190b2182ddSShimoda, Yoshihiro 1206ab4865bSGeert Uytterhoeven /* SPSSR - Sequence Status Register */ 1216ab4865bSGeert Uytterhoeven #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ 1226ab4865bSGeert Uytterhoeven #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ 1230b2182ddSShimoda, Yoshihiro 1246ab4865bSGeert Uytterhoeven /* SPDCR - Data Control Register */ 1256ab4865bSGeert Uytterhoeven #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ 1266ab4865bSGeert Uytterhoeven #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ 1276ab4865bSGeert Uytterhoeven #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ 1286ab4865bSGeert Uytterhoeven #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) 1296ab4865bSGeert Uytterhoeven #define SPDCR_SPLWORD SPDCR_SPLW1 1306ab4865bSGeert Uytterhoeven #define SPDCR_SPLBYTE SPDCR_SPLW0 1316ab4865bSGeert Uytterhoeven #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ 132862d357fSGeert Uytterhoeven #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ 1330b2182ddSShimoda, Yoshihiro #define SPDCR_SLSEL1 0x08 1340b2182ddSShimoda, Yoshihiro #define SPDCR_SLSEL0 0x04 135862d357fSGeert Uytterhoeven #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ 1360b2182ddSShimoda, Yoshihiro #define SPDCR_SPFC1 0x02 1370b2182ddSShimoda, Yoshihiro #define SPDCR_SPFC0 0x01 138862d357fSGeert Uytterhoeven #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ 1390b2182ddSShimoda, Yoshihiro 1406ab4865bSGeert Uytterhoeven /* SPCKD - Clock Delay Register */ 1416ab4865bSGeert Uytterhoeven #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ 1420b2182ddSShimoda, Yoshihiro 1436ab4865bSGeert Uytterhoeven /* SSLND - Slave Select Negation Delay Register */ 1446ab4865bSGeert Uytterhoeven #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ 1450b2182ddSShimoda, Yoshihiro 1466ab4865bSGeert Uytterhoeven /* SPND - Next-Access Delay Register */ 1476ab4865bSGeert Uytterhoeven #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ 1480b2182ddSShimoda, Yoshihiro 1496ab4865bSGeert Uytterhoeven /* SPCR2 - Control Register 2 */ 1506ab4865bSGeert Uytterhoeven #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ 1516ab4865bSGeert Uytterhoeven #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ 1526ab4865bSGeert Uytterhoeven #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ 1536ab4865bSGeert Uytterhoeven #define SPCR2_SPPE 0x01 /* Parity Enable */ 1540b2182ddSShimoda, Yoshihiro 1556ab4865bSGeert Uytterhoeven /* SPCMDn - Command Registers */ 1566ab4865bSGeert Uytterhoeven #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ 1576ab4865bSGeert Uytterhoeven #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ 1586ab4865bSGeert Uytterhoeven #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ 1596ab4865bSGeert Uytterhoeven #define SPCMD_LSBF 0x1000 /* LSB First */ 1606ab4865bSGeert Uytterhoeven #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ 1610b2182ddSShimoda, Yoshihiro #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 162880c6d11SGeert Uytterhoeven #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ 1635ce0ba88SHiep Cao Minh #define SPCMD_SPB_16BIT 0x0100 1640b2182ddSShimoda, Yoshihiro #define SPCMD_SPB_20BIT 0x0000 1650b2182ddSShimoda, Yoshihiro #define SPCMD_SPB_24BIT 0x0100 1660b2182ddSShimoda, Yoshihiro #define SPCMD_SPB_32BIT 0x0200 1676ab4865bSGeert Uytterhoeven #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ 168fbe5072bSGeert Uytterhoeven #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ 169fbe5072bSGeert Uytterhoeven #define SPCMD_SPIMOD1 0x0040 170fbe5072bSGeert Uytterhoeven #define SPCMD_SPIMOD0 0x0020 171fbe5072bSGeert Uytterhoeven #define SPCMD_SPIMOD_SINGLE 0 172fbe5072bSGeert Uytterhoeven #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 173fbe5072bSGeert Uytterhoeven #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 174fbe5072bSGeert Uytterhoeven #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ 1756ab4865bSGeert Uytterhoeven #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ 1766ab4865bSGeert Uytterhoeven #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ 1776ab4865bSGeert Uytterhoeven #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ 1786ab4865bSGeert Uytterhoeven #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ 1790b2182ddSShimoda, Yoshihiro 1806ab4865bSGeert Uytterhoeven /* SPBFCR - Buffer Control Register */ 181862d357fSGeert Uytterhoeven #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ 182862d357fSGeert Uytterhoeven #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ 1836ab4865bSGeert Uytterhoeven #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 1846ab4865bSGeert Uytterhoeven #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 1855ce0ba88SHiep Cao Minh 1862aae80b2SGeert Uytterhoeven #define DUMMY_DATA 0x00 1872aae80b2SGeert Uytterhoeven 1880b2182ddSShimoda, Yoshihiro struct rspi_data { 1890b2182ddSShimoda, Yoshihiro void __iomem *addr; 1900b2182ddSShimoda, Yoshihiro u32 max_speed_hz; 1910b2182ddSShimoda, Yoshihiro struct spi_master *master; 1920b2182ddSShimoda, Yoshihiro wait_queue_head_t wait; 1930b2182ddSShimoda, Yoshihiro struct clk *clk; 194348e5153SGeert Uytterhoeven u16 spcmd; 19506a7a3cfSGeert Uytterhoeven u8 spsr; 19606a7a3cfSGeert Uytterhoeven u8 sppcr; 19793722206SGeert Uytterhoeven int rx_irq, tx_irq; 1985ce0ba88SHiep Cao Minh const struct spi_ops *ops; 199a3633fe7SShimoda, Yoshihiro 200a3633fe7SShimoda, Yoshihiro /* for dmaengine */ 201a3633fe7SShimoda, Yoshihiro struct dma_chan *chan_tx; 202a3633fe7SShimoda, Yoshihiro struct dma_chan *chan_rx; 203a3633fe7SShimoda, Yoshihiro 204a3633fe7SShimoda, Yoshihiro unsigned dma_width_16bit:1; 205a3633fe7SShimoda, Yoshihiro unsigned dma_callbacked:1; 20674da7686SGeert Uytterhoeven unsigned byte_access:1; 2070b2182ddSShimoda, Yoshihiro }; 2080b2182ddSShimoda, Yoshihiro 209baf588f4SGeert Uytterhoeven static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) 2100b2182ddSShimoda, Yoshihiro { 2110b2182ddSShimoda, Yoshihiro iowrite8(data, rspi->addr + offset); 2120b2182ddSShimoda, Yoshihiro } 2130b2182ddSShimoda, Yoshihiro 214baf588f4SGeert Uytterhoeven static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) 2150b2182ddSShimoda, Yoshihiro { 2160b2182ddSShimoda, Yoshihiro iowrite16(data, rspi->addr + offset); 2170b2182ddSShimoda, Yoshihiro } 2180b2182ddSShimoda, Yoshihiro 219baf588f4SGeert Uytterhoeven static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) 2205ce0ba88SHiep Cao Minh { 2215ce0ba88SHiep Cao Minh iowrite32(data, rspi->addr + offset); 2225ce0ba88SHiep Cao Minh } 2235ce0ba88SHiep Cao Minh 224baf588f4SGeert Uytterhoeven static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) 2250b2182ddSShimoda, Yoshihiro { 2260b2182ddSShimoda, Yoshihiro return ioread8(rspi->addr + offset); 2270b2182ddSShimoda, Yoshihiro } 2280b2182ddSShimoda, Yoshihiro 229baf588f4SGeert Uytterhoeven static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) 2300b2182ddSShimoda, Yoshihiro { 2310b2182ddSShimoda, Yoshihiro return ioread16(rspi->addr + offset); 2320b2182ddSShimoda, Yoshihiro } 2330b2182ddSShimoda, Yoshihiro 23474da7686SGeert Uytterhoeven static void rspi_write_data(const struct rspi_data *rspi, u16 data) 23574da7686SGeert Uytterhoeven { 23674da7686SGeert Uytterhoeven if (rspi->byte_access) 23774da7686SGeert Uytterhoeven rspi_write8(rspi, data, RSPI_SPDR); 23874da7686SGeert Uytterhoeven else /* 16 bit */ 23974da7686SGeert Uytterhoeven rspi_write16(rspi, data, RSPI_SPDR); 24074da7686SGeert Uytterhoeven } 24174da7686SGeert Uytterhoeven 24274da7686SGeert Uytterhoeven static u16 rspi_read_data(const struct rspi_data *rspi) 24374da7686SGeert Uytterhoeven { 24474da7686SGeert Uytterhoeven if (rspi->byte_access) 24574da7686SGeert Uytterhoeven return rspi_read8(rspi, RSPI_SPDR); 24674da7686SGeert Uytterhoeven else /* 16 bit */ 24774da7686SGeert Uytterhoeven return rspi_read16(rspi, RSPI_SPDR); 24874da7686SGeert Uytterhoeven } 24974da7686SGeert Uytterhoeven 2505ce0ba88SHiep Cao Minh /* optional functions */ 2515ce0ba88SHiep Cao Minh struct spi_ops { 25274da7686SGeert Uytterhoeven int (*set_config_register)(struct rspi_data *rspi, int access_size); 253eb557f75SGeert Uytterhoeven int (*transfer_one)(struct spi_master *master, struct spi_device *spi, 254eb557f75SGeert Uytterhoeven struct spi_transfer *xfer); 255880c6d11SGeert Uytterhoeven u16 mode_bits; 2565ce0ba88SHiep Cao Minh }; 2575ce0ba88SHiep Cao Minh 2585ce0ba88SHiep Cao Minh /* 259862d357fSGeert Uytterhoeven * functions for RSPI on legacy SH 2605ce0ba88SHiep Cao Minh */ 26174da7686SGeert Uytterhoeven static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 2620b2182ddSShimoda, Yoshihiro { 2635ce0ba88SHiep Cao Minh int spbr; 2640b2182ddSShimoda, Yoshihiro 26506a7a3cfSGeert Uytterhoeven /* Sets output mode, MOSI signal, and (optionally) loopback */ 26606a7a3cfSGeert Uytterhoeven rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 2670b2182ddSShimoda, Yoshihiro 2685ce0ba88SHiep Cao Minh /* Sets transfer bit rate */ 2693beb61dbSGeert Uytterhoeven spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2703beb61dbSGeert Uytterhoeven 2 * rspi->max_speed_hz) - 1; 2715ce0ba88SHiep Cao Minh rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 2725ce0ba88SHiep Cao Minh 27374da7686SGeert Uytterhoeven /* Disable dummy transmission, set 16-bit word access, 1 frame */ 27474da7686SGeert Uytterhoeven rspi_write8(rspi, 0, RSPI_SPDCR); 27574da7686SGeert Uytterhoeven rspi->byte_access = 0; 2765ce0ba88SHiep Cao Minh 2775ce0ba88SHiep Cao Minh /* Sets RSPCK, SSL, next-access delay value */ 2785ce0ba88SHiep Cao Minh rspi_write8(rspi, 0x00, RSPI_SPCKD); 2795ce0ba88SHiep Cao Minh rspi_write8(rspi, 0x00, RSPI_SSLND); 2805ce0ba88SHiep Cao Minh rspi_write8(rspi, 0x00, RSPI_SPND); 2815ce0ba88SHiep Cao Minh 2825ce0ba88SHiep Cao Minh /* Sets parity, interrupt mask */ 2835ce0ba88SHiep Cao Minh rspi_write8(rspi, 0x00, RSPI_SPCR2); 2845ce0ba88SHiep Cao Minh 2855ce0ba88SHiep Cao Minh /* Sets SPCMD */ 286880c6d11SGeert Uytterhoeven rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 287880c6d11SGeert Uytterhoeven rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 2885ce0ba88SHiep Cao Minh 2895ce0ba88SHiep Cao Minh /* Sets RSPI mode */ 2905ce0ba88SHiep Cao Minh rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 2915ce0ba88SHiep Cao Minh 2925ce0ba88SHiep Cao Minh return 0; 2930b2182ddSShimoda, Yoshihiro } 2940b2182ddSShimoda, Yoshihiro 2955ce0ba88SHiep Cao Minh /* 296862d357fSGeert Uytterhoeven * functions for RSPI on RZ 297862d357fSGeert Uytterhoeven */ 298862d357fSGeert Uytterhoeven static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) 299862d357fSGeert Uytterhoeven { 300862d357fSGeert Uytterhoeven int spbr; 301862d357fSGeert Uytterhoeven 30206a7a3cfSGeert Uytterhoeven /* Sets output mode, MOSI signal, and (optionally) loopback */ 30306a7a3cfSGeert Uytterhoeven rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 304862d357fSGeert Uytterhoeven 305862d357fSGeert Uytterhoeven /* Sets transfer bit rate */ 3063beb61dbSGeert Uytterhoeven spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 3073beb61dbSGeert Uytterhoeven 2 * rspi->max_speed_hz) - 1; 308862d357fSGeert Uytterhoeven rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 309862d357fSGeert Uytterhoeven 310862d357fSGeert Uytterhoeven /* Disable dummy transmission, set byte access */ 311862d357fSGeert Uytterhoeven rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); 312862d357fSGeert Uytterhoeven rspi->byte_access = 1; 313862d357fSGeert Uytterhoeven 314862d357fSGeert Uytterhoeven /* Sets RSPCK, SSL, next-access delay value */ 315862d357fSGeert Uytterhoeven rspi_write8(rspi, 0x00, RSPI_SPCKD); 316862d357fSGeert Uytterhoeven rspi_write8(rspi, 0x00, RSPI_SSLND); 317862d357fSGeert Uytterhoeven rspi_write8(rspi, 0x00, RSPI_SPND); 318862d357fSGeert Uytterhoeven 319862d357fSGeert Uytterhoeven /* Sets SPCMD */ 320862d357fSGeert Uytterhoeven rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 321862d357fSGeert Uytterhoeven rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 322862d357fSGeert Uytterhoeven 323862d357fSGeert Uytterhoeven /* Sets RSPI mode */ 324862d357fSGeert Uytterhoeven rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 325862d357fSGeert Uytterhoeven 326862d357fSGeert Uytterhoeven return 0; 327862d357fSGeert Uytterhoeven } 328862d357fSGeert Uytterhoeven 329862d357fSGeert Uytterhoeven /* 3305ce0ba88SHiep Cao Minh * functions for QSPI 3315ce0ba88SHiep Cao Minh */ 33274da7686SGeert Uytterhoeven static int qspi_set_config_register(struct rspi_data *rspi, int access_size) 3335ce0ba88SHiep Cao Minh { 3345ce0ba88SHiep Cao Minh int spbr; 3355ce0ba88SHiep Cao Minh 33606a7a3cfSGeert Uytterhoeven /* Sets output mode, MOSI signal, and (optionally) loopback */ 33706a7a3cfSGeert Uytterhoeven rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 3385ce0ba88SHiep Cao Minh 3395ce0ba88SHiep Cao Minh /* Sets transfer bit rate */ 3403beb61dbSGeert Uytterhoeven spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz); 3415ce0ba88SHiep Cao Minh rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 3425ce0ba88SHiep Cao Minh 34374da7686SGeert Uytterhoeven /* Disable dummy transmission, set byte access */ 34474da7686SGeert Uytterhoeven rspi_write8(rspi, 0, RSPI_SPDCR); 34574da7686SGeert Uytterhoeven rspi->byte_access = 1; 3465ce0ba88SHiep Cao Minh 3475ce0ba88SHiep Cao Minh /* Sets RSPCK, SSL, next-access delay value */ 3485ce0ba88SHiep Cao Minh rspi_write8(rspi, 0x00, RSPI_SPCKD); 3495ce0ba88SHiep Cao Minh rspi_write8(rspi, 0x00, RSPI_SSLND); 3505ce0ba88SHiep Cao Minh rspi_write8(rspi, 0x00, RSPI_SPND); 3515ce0ba88SHiep Cao Minh 3525ce0ba88SHiep Cao Minh /* Data Length Setting */ 3535ce0ba88SHiep Cao Minh if (access_size == 8) 354880c6d11SGeert Uytterhoeven rspi->spcmd |= SPCMD_SPB_8BIT; 3555ce0ba88SHiep Cao Minh else if (access_size == 16) 356880c6d11SGeert Uytterhoeven rspi->spcmd |= SPCMD_SPB_16BIT; 3578e1c8096SLaurent Pinchart else 358880c6d11SGeert Uytterhoeven rspi->spcmd |= SPCMD_SPB_32BIT; 3595ce0ba88SHiep Cao Minh 360880c6d11SGeert Uytterhoeven rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; 3615ce0ba88SHiep Cao Minh 3625ce0ba88SHiep Cao Minh /* Resets transfer data length */ 3635ce0ba88SHiep Cao Minh rspi_write32(rspi, 0, QSPI_SPBMUL0); 3645ce0ba88SHiep Cao Minh 3655ce0ba88SHiep Cao Minh /* Resets transmit and receive buffer */ 3665ce0ba88SHiep Cao Minh rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 3675ce0ba88SHiep Cao Minh /* Sets buffer to allow normal operation */ 3685ce0ba88SHiep Cao Minh rspi_write8(rspi, 0x00, QSPI_SPBFCR); 3695ce0ba88SHiep Cao Minh 3705ce0ba88SHiep Cao Minh /* Sets SPCMD */ 371880c6d11SGeert Uytterhoeven rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 3725ce0ba88SHiep Cao Minh 373880c6d11SGeert Uytterhoeven /* Enables SPI function in master mode */ 3745ce0ba88SHiep Cao Minh rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); 3755ce0ba88SHiep Cao Minh 3765ce0ba88SHiep Cao Minh return 0; 3775ce0ba88SHiep Cao Minh } 3785ce0ba88SHiep Cao Minh 3795ce0ba88SHiep Cao Minh #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) 3805ce0ba88SHiep Cao Minh 381baf588f4SGeert Uytterhoeven static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) 3820b2182ddSShimoda, Yoshihiro { 3830b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); 3840b2182ddSShimoda, Yoshihiro } 3850b2182ddSShimoda, Yoshihiro 386baf588f4SGeert Uytterhoeven static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) 3870b2182ddSShimoda, Yoshihiro { 3880b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); 3890b2182ddSShimoda, Yoshihiro } 3900b2182ddSShimoda, Yoshihiro 3910b2182ddSShimoda, Yoshihiro static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, 3920b2182ddSShimoda, Yoshihiro u8 enable_bit) 3930b2182ddSShimoda, Yoshihiro { 3940b2182ddSShimoda, Yoshihiro int ret; 3950b2182ddSShimoda, Yoshihiro 3960b2182ddSShimoda, Yoshihiro rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 3975dd1ad23SGeert Uytterhoeven if (rspi->spsr & wait_mask) 3985dd1ad23SGeert Uytterhoeven return 0; 3995dd1ad23SGeert Uytterhoeven 4000b2182ddSShimoda, Yoshihiro rspi_enable_irq(rspi, enable_bit); 4010b2182ddSShimoda, Yoshihiro ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 4020b2182ddSShimoda, Yoshihiro if (ret == 0 && !(rspi->spsr & wait_mask)) 4030b2182ddSShimoda, Yoshihiro return -ETIMEDOUT; 4040b2182ddSShimoda, Yoshihiro 4050b2182ddSShimoda, Yoshihiro return 0; 4060b2182ddSShimoda, Yoshihiro } 4070b2182ddSShimoda, Yoshihiro 40835301c99SGeert Uytterhoeven static int rspi_data_out(struct rspi_data *rspi, u8 data) 40935301c99SGeert Uytterhoeven { 41035301c99SGeert Uytterhoeven if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { 41135301c99SGeert Uytterhoeven dev_err(&rspi->master->dev, "transmit timeout\n"); 41235301c99SGeert Uytterhoeven return -ETIMEDOUT; 41335301c99SGeert Uytterhoeven } 41435301c99SGeert Uytterhoeven rspi_write_data(rspi, data); 41535301c99SGeert Uytterhoeven return 0; 41635301c99SGeert Uytterhoeven } 41735301c99SGeert Uytterhoeven 41835301c99SGeert Uytterhoeven static int rspi_data_in(struct rspi_data *rspi) 41935301c99SGeert Uytterhoeven { 42035301c99SGeert Uytterhoeven u8 data; 42135301c99SGeert Uytterhoeven 42235301c99SGeert Uytterhoeven if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { 42335301c99SGeert Uytterhoeven dev_err(&rspi->master->dev, "receive timeout\n"); 42435301c99SGeert Uytterhoeven return -ETIMEDOUT; 42535301c99SGeert Uytterhoeven } 42635301c99SGeert Uytterhoeven data = rspi_read_data(rspi); 42735301c99SGeert Uytterhoeven return data; 42835301c99SGeert Uytterhoeven } 42935301c99SGeert Uytterhoeven 43035301c99SGeert Uytterhoeven static int rspi_data_out_in(struct rspi_data *rspi, u8 data) 43135301c99SGeert Uytterhoeven { 43235301c99SGeert Uytterhoeven int ret; 43335301c99SGeert Uytterhoeven 43435301c99SGeert Uytterhoeven ret = rspi_data_out(rspi, data); 43535301c99SGeert Uytterhoeven if (ret < 0) 43635301c99SGeert Uytterhoeven return ret; 43735301c99SGeert Uytterhoeven 43835301c99SGeert Uytterhoeven return rspi_data_in(rspi); 43935301c99SGeert Uytterhoeven } 44035301c99SGeert Uytterhoeven 441a3633fe7SShimoda, Yoshihiro static void rspi_dma_complete(void *arg) 4420b2182ddSShimoda, Yoshihiro { 443a3633fe7SShimoda, Yoshihiro struct rspi_data *rspi = arg; 444a3633fe7SShimoda, Yoshihiro 445a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked = 1; 446a3633fe7SShimoda, Yoshihiro wake_up_interruptible(&rspi->wait); 447a3633fe7SShimoda, Yoshihiro } 448a3633fe7SShimoda, Yoshihiro 449c132f094SGeert Uytterhoeven static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, 450c132f094SGeert Uytterhoeven unsigned len, struct dma_chan *chan, 451a3633fe7SShimoda, Yoshihiro enum dma_transfer_direction dir) 452a3633fe7SShimoda, Yoshihiro { 453a3633fe7SShimoda, Yoshihiro sg_init_table(sg, 1); 454a3633fe7SShimoda, Yoshihiro sg_set_buf(sg, buf, len); 455a3633fe7SShimoda, Yoshihiro sg_dma_len(sg) = len; 456a3633fe7SShimoda, Yoshihiro return dma_map_sg(chan->device->dev, sg, 1, dir); 457a3633fe7SShimoda, Yoshihiro } 458a3633fe7SShimoda, Yoshihiro 459a3633fe7SShimoda, Yoshihiro static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, 460a3633fe7SShimoda, Yoshihiro enum dma_transfer_direction dir) 461a3633fe7SShimoda, Yoshihiro { 462a3633fe7SShimoda, Yoshihiro dma_unmap_sg(chan->device->dev, sg, 1, dir); 463a3633fe7SShimoda, Yoshihiro } 464a3633fe7SShimoda, Yoshihiro 465a3633fe7SShimoda, Yoshihiro static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) 466a3633fe7SShimoda, Yoshihiro { 467a3633fe7SShimoda, Yoshihiro u16 *dst = buf; 468a3633fe7SShimoda, Yoshihiro const u8 *src = data; 469a3633fe7SShimoda, Yoshihiro 470a3633fe7SShimoda, Yoshihiro while (len) { 471a3633fe7SShimoda, Yoshihiro *dst++ = (u16)(*src++); 472a3633fe7SShimoda, Yoshihiro len--; 473a3633fe7SShimoda, Yoshihiro } 474a3633fe7SShimoda, Yoshihiro } 475a3633fe7SShimoda, Yoshihiro 476a3633fe7SShimoda, Yoshihiro static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) 477a3633fe7SShimoda, Yoshihiro { 478a3633fe7SShimoda, Yoshihiro u8 *dst = buf; 479a3633fe7SShimoda, Yoshihiro const u16 *src = data; 480a3633fe7SShimoda, Yoshihiro 481a3633fe7SShimoda, Yoshihiro while (len) { 482a3633fe7SShimoda, Yoshihiro *dst++ = (u8)*src++; 483a3633fe7SShimoda, Yoshihiro len--; 484a3633fe7SShimoda, Yoshihiro } 485a3633fe7SShimoda, Yoshihiro } 486a3633fe7SShimoda, Yoshihiro 487a3633fe7SShimoda, Yoshihiro static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) 488a3633fe7SShimoda, Yoshihiro { 489a3633fe7SShimoda, Yoshihiro struct scatterlist sg; 490c132f094SGeert Uytterhoeven const void *buf = NULL; 491a3633fe7SShimoda, Yoshihiro struct dma_async_tx_descriptor *desc; 49293722206SGeert Uytterhoeven unsigned int len; 493a3633fe7SShimoda, Yoshihiro int ret = 0; 494a3633fe7SShimoda, Yoshihiro 495a3633fe7SShimoda, Yoshihiro if (rspi->dma_width_16bit) { 496c132f094SGeert Uytterhoeven void *tmp; 497a3633fe7SShimoda, Yoshihiro /* 498a3633fe7SShimoda, Yoshihiro * If DMAC bus width is 16-bit, the driver allocates a dummy 499a3633fe7SShimoda, Yoshihiro * buffer. And, the driver converts original data into the 500a3633fe7SShimoda, Yoshihiro * DMAC data as the following format: 501a3633fe7SShimoda, Yoshihiro * original data: 1st byte, 2nd byte ... 502a3633fe7SShimoda, Yoshihiro * DMAC data: 1st byte, dummy, 2nd byte, dummy ... 503a3633fe7SShimoda, Yoshihiro */ 504a3633fe7SShimoda, Yoshihiro len = t->len * 2; 505c132f094SGeert Uytterhoeven tmp = kmalloc(len, GFP_KERNEL); 506c132f094SGeert Uytterhoeven if (!tmp) 507a3633fe7SShimoda, Yoshihiro return -ENOMEM; 508c132f094SGeert Uytterhoeven rspi_memory_to_8bit(tmp, t->tx_buf, t->len); 509c132f094SGeert Uytterhoeven buf = tmp; 510a3633fe7SShimoda, Yoshihiro } else { 511a3633fe7SShimoda, Yoshihiro len = t->len; 512c132f094SGeert Uytterhoeven buf = t->tx_buf; 513a3633fe7SShimoda, Yoshihiro } 514a3633fe7SShimoda, Yoshihiro 515a3633fe7SShimoda, Yoshihiro if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { 516a3633fe7SShimoda, Yoshihiro ret = -EFAULT; 517a3633fe7SShimoda, Yoshihiro goto end_nomap; 518a3633fe7SShimoda, Yoshihiro } 519a3633fe7SShimoda, Yoshihiro desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, 520a3633fe7SShimoda, Yoshihiro DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 521a3633fe7SShimoda, Yoshihiro if (!desc) { 522a3633fe7SShimoda, Yoshihiro ret = -EIO; 523a3633fe7SShimoda, Yoshihiro goto end; 524a3633fe7SShimoda, Yoshihiro } 525a3633fe7SShimoda, Yoshihiro 526a3633fe7SShimoda, Yoshihiro /* 527a3633fe7SShimoda, Yoshihiro * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 528a3633fe7SShimoda, Yoshihiro * called. So, this driver disables the IRQ while DMA transfer. 529a3633fe7SShimoda, Yoshihiro */ 53093722206SGeert Uytterhoeven disable_irq(rspi->tx_irq); 531a3633fe7SShimoda, Yoshihiro 532a3633fe7SShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); 533a3633fe7SShimoda, Yoshihiro rspi_enable_irq(rspi, SPCR_SPTIE); 534a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked = 0; 535a3633fe7SShimoda, Yoshihiro 536a3633fe7SShimoda, Yoshihiro desc->callback = rspi_dma_complete; 537a3633fe7SShimoda, Yoshihiro desc->callback_param = rspi; 538a3633fe7SShimoda, Yoshihiro dmaengine_submit(desc); 539a3633fe7SShimoda, Yoshihiro dma_async_issue_pending(rspi->chan_tx); 540a3633fe7SShimoda, Yoshihiro 541a3633fe7SShimoda, Yoshihiro ret = wait_event_interruptible_timeout(rspi->wait, 542a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked, HZ); 543a3633fe7SShimoda, Yoshihiro if (ret > 0 && rspi->dma_callbacked) 544a3633fe7SShimoda, Yoshihiro ret = 0; 545a3633fe7SShimoda, Yoshihiro else if (!ret) 546a3633fe7SShimoda, Yoshihiro ret = -ETIMEDOUT; 547a3633fe7SShimoda, Yoshihiro rspi_disable_irq(rspi, SPCR_SPTIE); 548a3633fe7SShimoda, Yoshihiro 54993722206SGeert Uytterhoeven enable_irq(rspi->tx_irq); 550a3633fe7SShimoda, Yoshihiro 551a3633fe7SShimoda, Yoshihiro end: 552a3633fe7SShimoda, Yoshihiro rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); 553a3633fe7SShimoda, Yoshihiro end_nomap: 554a3633fe7SShimoda, Yoshihiro if (rspi->dma_width_16bit) 555a3633fe7SShimoda, Yoshihiro kfree(buf); 556a3633fe7SShimoda, Yoshihiro 557a3633fe7SShimoda, Yoshihiro return ret; 558a3633fe7SShimoda, Yoshihiro } 559a3633fe7SShimoda, Yoshihiro 560baf588f4SGeert Uytterhoeven static void rspi_receive_init(const struct rspi_data *rspi) 561a3633fe7SShimoda, Yoshihiro { 56297b95c11SGeert Uytterhoeven u8 spsr; 5630b2182ddSShimoda, Yoshihiro 5640b2182ddSShimoda, Yoshihiro spsr = rspi_read8(rspi, RSPI_SPSR); 5650b2182ddSShimoda, Yoshihiro if (spsr & SPSR_SPRF) 56674da7686SGeert Uytterhoeven rspi_read_data(rspi); /* dummy read */ 5670b2182ddSShimoda, Yoshihiro if (spsr & SPSR_OVRF) 5680b2182ddSShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 569df900e67SGeert Uytterhoeven RSPI_SPSR); 570a3633fe7SShimoda, Yoshihiro } 571a3633fe7SShimoda, Yoshihiro 572862d357fSGeert Uytterhoeven static void rspi_rz_receive_init(const struct rspi_data *rspi) 573862d357fSGeert Uytterhoeven { 574862d357fSGeert Uytterhoeven rspi_receive_init(rspi); 575862d357fSGeert Uytterhoeven rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); 576862d357fSGeert Uytterhoeven rspi_write8(rspi, 0, RSPI_SPBFCR); 577862d357fSGeert Uytterhoeven } 578862d357fSGeert Uytterhoeven 579baf588f4SGeert Uytterhoeven static void qspi_receive_init(const struct rspi_data *rspi) 580cb52c673SHiep Cao Minh { 58197b95c11SGeert Uytterhoeven u8 spsr; 582cb52c673SHiep Cao Minh 583cb52c673SHiep Cao Minh spsr = rspi_read8(rspi, RSPI_SPSR); 584cb52c673SHiep Cao Minh if (spsr & SPSR_SPRF) 58574da7686SGeert Uytterhoeven rspi_read_data(rspi); /* dummy read */ 586cb52c673SHiep Cao Minh rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 587340a15e6SGeert Uytterhoeven rspi_write8(rspi, 0, QSPI_SPBFCR); 588cb52c673SHiep Cao Minh } 589cb52c673SHiep Cao Minh 590a3633fe7SShimoda, Yoshihiro static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) 591a3633fe7SShimoda, Yoshihiro { 592a3633fe7SShimoda, Yoshihiro struct scatterlist sg, sg_dummy; 593a3633fe7SShimoda, Yoshihiro void *dummy = NULL, *rx_buf = NULL; 594a3633fe7SShimoda, Yoshihiro struct dma_async_tx_descriptor *desc, *desc_dummy; 59593722206SGeert Uytterhoeven unsigned int len; 596a3633fe7SShimoda, Yoshihiro int ret = 0; 597a3633fe7SShimoda, Yoshihiro 598a3633fe7SShimoda, Yoshihiro if (rspi->dma_width_16bit) { 599a3633fe7SShimoda, Yoshihiro /* 600a3633fe7SShimoda, Yoshihiro * If DMAC bus width is 16-bit, the driver allocates a dummy 601a3633fe7SShimoda, Yoshihiro * buffer. And, finally the driver converts the DMAC data into 602a3633fe7SShimoda, Yoshihiro * actual data as the following format: 603a3633fe7SShimoda, Yoshihiro * DMAC data: 1st byte, dummy, 2nd byte, dummy ... 604a3633fe7SShimoda, Yoshihiro * actual data: 1st byte, 2nd byte ... 605a3633fe7SShimoda, Yoshihiro */ 606a3633fe7SShimoda, Yoshihiro len = t->len * 2; 607a3633fe7SShimoda, Yoshihiro rx_buf = kmalloc(len, GFP_KERNEL); 608a3633fe7SShimoda, Yoshihiro if (!rx_buf) 609a3633fe7SShimoda, Yoshihiro return -ENOMEM; 610a3633fe7SShimoda, Yoshihiro } else { 611a3633fe7SShimoda, Yoshihiro len = t->len; 612a3633fe7SShimoda, Yoshihiro rx_buf = t->rx_buf; 613a3633fe7SShimoda, Yoshihiro } 614a3633fe7SShimoda, Yoshihiro 615a3633fe7SShimoda, Yoshihiro /* prepare dummy transfer to generate SPI clocks */ 616a3633fe7SShimoda, Yoshihiro dummy = kzalloc(len, GFP_KERNEL); 617a3633fe7SShimoda, Yoshihiro if (!dummy) { 618a3633fe7SShimoda, Yoshihiro ret = -ENOMEM; 619a3633fe7SShimoda, Yoshihiro goto end_nomap; 620a3633fe7SShimoda, Yoshihiro } 621a3633fe7SShimoda, Yoshihiro if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, 622a3633fe7SShimoda, Yoshihiro DMA_TO_DEVICE)) { 623a3633fe7SShimoda, Yoshihiro ret = -EFAULT; 624a3633fe7SShimoda, Yoshihiro goto end_nomap; 625a3633fe7SShimoda, Yoshihiro } 626a3633fe7SShimoda, Yoshihiro desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, 627a3633fe7SShimoda, Yoshihiro DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 628a3633fe7SShimoda, Yoshihiro if (!desc_dummy) { 629a3633fe7SShimoda, Yoshihiro ret = -EIO; 630a3633fe7SShimoda, Yoshihiro goto end_dummy_mapped; 631a3633fe7SShimoda, Yoshihiro } 632a3633fe7SShimoda, Yoshihiro 633a3633fe7SShimoda, Yoshihiro /* prepare receive transfer */ 634a3633fe7SShimoda, Yoshihiro if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, 635a3633fe7SShimoda, Yoshihiro DMA_FROM_DEVICE)) { 636a3633fe7SShimoda, Yoshihiro ret = -EFAULT; 637a3633fe7SShimoda, Yoshihiro goto end_dummy_mapped; 638a3633fe7SShimoda, Yoshihiro 639a3633fe7SShimoda, Yoshihiro } 640a3633fe7SShimoda, Yoshihiro desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, 641a3633fe7SShimoda, Yoshihiro DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 642a3633fe7SShimoda, Yoshihiro if (!desc) { 643a3633fe7SShimoda, Yoshihiro ret = -EIO; 644a3633fe7SShimoda, Yoshihiro goto end; 645a3633fe7SShimoda, Yoshihiro } 646a3633fe7SShimoda, Yoshihiro 647a3633fe7SShimoda, Yoshihiro rspi_receive_init(rspi); 648a3633fe7SShimoda, Yoshihiro 649a3633fe7SShimoda, Yoshihiro /* 650a3633fe7SShimoda, Yoshihiro * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be 651a3633fe7SShimoda, Yoshihiro * called. So, this driver disables the IRQ while DMA transfer. 652a3633fe7SShimoda, Yoshihiro */ 65393722206SGeert Uytterhoeven disable_irq(rspi->tx_irq); 65493722206SGeert Uytterhoeven if (rspi->rx_irq != rspi->tx_irq) 65593722206SGeert Uytterhoeven disable_irq(rspi->rx_irq); 656a3633fe7SShimoda, Yoshihiro 657a3633fe7SShimoda, Yoshihiro rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); 658a3633fe7SShimoda, Yoshihiro rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 659a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked = 0; 660a3633fe7SShimoda, Yoshihiro 661a3633fe7SShimoda, Yoshihiro desc->callback = rspi_dma_complete; 662a3633fe7SShimoda, Yoshihiro desc->callback_param = rspi; 663a3633fe7SShimoda, Yoshihiro dmaengine_submit(desc); 664a3633fe7SShimoda, Yoshihiro dma_async_issue_pending(rspi->chan_rx); 665a3633fe7SShimoda, Yoshihiro 666a3633fe7SShimoda, Yoshihiro desc_dummy->callback = NULL; /* No callback */ 667a3633fe7SShimoda, Yoshihiro dmaengine_submit(desc_dummy); 668a3633fe7SShimoda, Yoshihiro dma_async_issue_pending(rspi->chan_tx); 669a3633fe7SShimoda, Yoshihiro 670a3633fe7SShimoda, Yoshihiro ret = wait_event_interruptible_timeout(rspi->wait, 671a3633fe7SShimoda, Yoshihiro rspi->dma_callbacked, HZ); 672a3633fe7SShimoda, Yoshihiro if (ret > 0 && rspi->dma_callbacked) 673a3633fe7SShimoda, Yoshihiro ret = 0; 674a3633fe7SShimoda, Yoshihiro else if (!ret) 675a3633fe7SShimoda, Yoshihiro ret = -ETIMEDOUT; 676a3633fe7SShimoda, Yoshihiro rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); 677a3633fe7SShimoda, Yoshihiro 67893722206SGeert Uytterhoeven enable_irq(rspi->tx_irq); 67993722206SGeert Uytterhoeven if (rspi->rx_irq != rspi->tx_irq) 68093722206SGeert Uytterhoeven enable_irq(rspi->rx_irq); 681a3633fe7SShimoda, Yoshihiro 682a3633fe7SShimoda, Yoshihiro end: 683a3633fe7SShimoda, Yoshihiro rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); 684a3633fe7SShimoda, Yoshihiro end_dummy_mapped: 685a3633fe7SShimoda, Yoshihiro rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); 686a3633fe7SShimoda, Yoshihiro end_nomap: 687a3633fe7SShimoda, Yoshihiro if (rspi->dma_width_16bit) { 688a3633fe7SShimoda, Yoshihiro if (!ret) 689a3633fe7SShimoda, Yoshihiro rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); 690a3633fe7SShimoda, Yoshihiro kfree(rx_buf); 691a3633fe7SShimoda, Yoshihiro } 692a3633fe7SShimoda, Yoshihiro kfree(dummy); 693a3633fe7SShimoda, Yoshihiro 694a3633fe7SShimoda, Yoshihiro return ret; 695a3633fe7SShimoda, Yoshihiro } 696a3633fe7SShimoda, Yoshihiro 697baf588f4SGeert Uytterhoeven static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) 698a3633fe7SShimoda, Yoshihiro { 699a3633fe7SShimoda, Yoshihiro if (t->tx_buf && rspi->chan_tx) 700a3633fe7SShimoda, Yoshihiro return 1; 701a3633fe7SShimoda, Yoshihiro /* If the module receives data by DMAC, it also needs TX DMAC */ 702a3633fe7SShimoda, Yoshihiro if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) 703a3633fe7SShimoda, Yoshihiro return 1; 704a3633fe7SShimoda, Yoshihiro 705a3633fe7SShimoda, Yoshihiro return 0; 706a3633fe7SShimoda, Yoshihiro } 707a3633fe7SShimoda, Yoshihiro 7088449fd76SGeert Uytterhoeven static int rspi_transfer_out_in(struct rspi_data *rspi, 7098449fd76SGeert Uytterhoeven struct spi_transfer *xfer) 7108449fd76SGeert Uytterhoeven { 7118449fd76SGeert Uytterhoeven int remain = xfer->len, ret; 7128449fd76SGeert Uytterhoeven const u8 *tx_buf = xfer->tx_buf; 7138449fd76SGeert Uytterhoeven u8 *rx_buf = xfer->rx_buf; 7148449fd76SGeert Uytterhoeven u8 spcr, data; 7158449fd76SGeert Uytterhoeven 7168449fd76SGeert Uytterhoeven rspi_receive_init(rspi); 7178449fd76SGeert Uytterhoeven 7188449fd76SGeert Uytterhoeven spcr = rspi_read8(rspi, RSPI_SPCR); 7198449fd76SGeert Uytterhoeven if (rx_buf) 7208449fd76SGeert Uytterhoeven spcr &= ~SPCR_TXMD; 7218449fd76SGeert Uytterhoeven else 7228449fd76SGeert Uytterhoeven spcr |= SPCR_TXMD; 7238449fd76SGeert Uytterhoeven rspi_write8(rspi, spcr, RSPI_SPCR); 7248449fd76SGeert Uytterhoeven 7258449fd76SGeert Uytterhoeven while (remain > 0) { 7268449fd76SGeert Uytterhoeven data = tx_buf ? *tx_buf++ : DUMMY_DATA; 7278449fd76SGeert Uytterhoeven ret = rspi_data_out(rspi, data); 7288449fd76SGeert Uytterhoeven if (ret < 0) 7298449fd76SGeert Uytterhoeven return ret; 7308449fd76SGeert Uytterhoeven if (rx_buf) { 7318449fd76SGeert Uytterhoeven ret = rspi_data_in(rspi); 7328449fd76SGeert Uytterhoeven if (ret < 0) 7338449fd76SGeert Uytterhoeven return ret; 7348449fd76SGeert Uytterhoeven *rx_buf++ = ret; 7358449fd76SGeert Uytterhoeven } 7368449fd76SGeert Uytterhoeven remain--; 7378449fd76SGeert Uytterhoeven } 7388449fd76SGeert Uytterhoeven 7398449fd76SGeert Uytterhoeven /* Wait for the last transmission */ 7408449fd76SGeert Uytterhoeven rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 7418449fd76SGeert Uytterhoeven 7428449fd76SGeert Uytterhoeven return 0; 7438449fd76SGeert Uytterhoeven } 7448449fd76SGeert Uytterhoeven 74579d23495SGeert Uytterhoeven static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, 74679d23495SGeert Uytterhoeven struct spi_transfer *xfer) 7470b2182ddSShimoda, Yoshihiro { 74879d23495SGeert Uytterhoeven struct rspi_data *rspi = spi_master_get_devdata(master); 7498449fd76SGeert Uytterhoeven int ret; 7508449fd76SGeert Uytterhoeven 7518449fd76SGeert Uytterhoeven if (!rspi_is_dma(rspi, xfer)) 7528449fd76SGeert Uytterhoeven return rspi_transfer_out_in(rspi, xfer); 7530b2182ddSShimoda, Yoshihiro 75479d23495SGeert Uytterhoeven if (xfer->tx_buf) { 75579d23495SGeert Uytterhoeven ret = rspi_send_dma(rspi, xfer); 7560b2182ddSShimoda, Yoshihiro if (ret < 0) 75779d23495SGeert Uytterhoeven return ret; 7580b2182ddSShimoda, Yoshihiro } 7598449fd76SGeert Uytterhoeven if (xfer->rx_buf) 7608449fd76SGeert Uytterhoeven return rspi_receive_dma(rspi, xfer); 7618449fd76SGeert Uytterhoeven 7628449fd76SGeert Uytterhoeven return 0; 7630b2182ddSShimoda, Yoshihiro } 7640b2182ddSShimoda, Yoshihiro 765862d357fSGeert Uytterhoeven static int rspi_rz_transfer_out_in(struct rspi_data *rspi, 766862d357fSGeert Uytterhoeven struct spi_transfer *xfer) 767862d357fSGeert Uytterhoeven { 768862d357fSGeert Uytterhoeven int remain = xfer->len, ret; 769862d357fSGeert Uytterhoeven const u8 *tx_buf = xfer->tx_buf; 770862d357fSGeert Uytterhoeven u8 *rx_buf = xfer->rx_buf; 771862d357fSGeert Uytterhoeven u8 data; 772862d357fSGeert Uytterhoeven 773862d357fSGeert Uytterhoeven rspi_rz_receive_init(rspi); 774862d357fSGeert Uytterhoeven 775862d357fSGeert Uytterhoeven while (remain > 0) { 776862d357fSGeert Uytterhoeven data = tx_buf ? *tx_buf++ : DUMMY_DATA; 777862d357fSGeert Uytterhoeven ret = rspi_data_out_in(rspi, data); 778862d357fSGeert Uytterhoeven if (ret < 0) 779862d357fSGeert Uytterhoeven return ret; 780862d357fSGeert Uytterhoeven if (rx_buf) 781862d357fSGeert Uytterhoeven *rx_buf++ = ret; 782862d357fSGeert Uytterhoeven remain--; 783862d357fSGeert Uytterhoeven } 784862d357fSGeert Uytterhoeven 785862d357fSGeert Uytterhoeven /* Wait for the last transmission */ 786862d357fSGeert Uytterhoeven rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 787862d357fSGeert Uytterhoeven 788862d357fSGeert Uytterhoeven return 0; 789862d357fSGeert Uytterhoeven } 790862d357fSGeert Uytterhoeven 791862d357fSGeert Uytterhoeven static int rspi_rz_transfer_one(struct spi_master *master, 792862d357fSGeert Uytterhoeven struct spi_device *spi, 793862d357fSGeert Uytterhoeven struct spi_transfer *xfer) 794862d357fSGeert Uytterhoeven { 795862d357fSGeert Uytterhoeven struct rspi_data *rspi = spi_master_get_devdata(master); 796862d357fSGeert Uytterhoeven 797862d357fSGeert Uytterhoeven return rspi_rz_transfer_out_in(rspi, xfer); 798862d357fSGeert Uytterhoeven } 799862d357fSGeert Uytterhoeven 800340a15e6SGeert Uytterhoeven static int qspi_transfer_out_in(struct rspi_data *rspi, 801340a15e6SGeert Uytterhoeven struct spi_transfer *xfer) 802340a15e6SGeert Uytterhoeven { 803340a15e6SGeert Uytterhoeven int remain = xfer->len, ret; 804340a15e6SGeert Uytterhoeven const u8 *tx_buf = xfer->tx_buf; 805340a15e6SGeert Uytterhoeven u8 *rx_buf = xfer->rx_buf; 806340a15e6SGeert Uytterhoeven u8 data; 807340a15e6SGeert Uytterhoeven 808340a15e6SGeert Uytterhoeven qspi_receive_init(rspi); 809340a15e6SGeert Uytterhoeven 810340a15e6SGeert Uytterhoeven while (remain > 0) { 811340a15e6SGeert Uytterhoeven data = tx_buf ? *tx_buf++ : DUMMY_DATA; 812340a15e6SGeert Uytterhoeven ret = rspi_data_out_in(rspi, data); 813340a15e6SGeert Uytterhoeven if (ret < 0) 814340a15e6SGeert Uytterhoeven return ret; 815340a15e6SGeert Uytterhoeven if (rx_buf) 816340a15e6SGeert Uytterhoeven *rx_buf++ = ret; 817340a15e6SGeert Uytterhoeven remain--; 818340a15e6SGeert Uytterhoeven } 819340a15e6SGeert Uytterhoeven 820340a15e6SGeert Uytterhoeven /* Wait for the last transmission */ 821340a15e6SGeert Uytterhoeven rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 822340a15e6SGeert Uytterhoeven 823340a15e6SGeert Uytterhoeven return 0; 824340a15e6SGeert Uytterhoeven } 825340a15e6SGeert Uytterhoeven 826880c6d11SGeert Uytterhoeven static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) 827880c6d11SGeert Uytterhoeven { 828880c6d11SGeert Uytterhoeven const u8 *buf = xfer->tx_buf; 829880c6d11SGeert Uytterhoeven unsigned int i; 830880c6d11SGeert Uytterhoeven int ret; 831880c6d11SGeert Uytterhoeven 832880c6d11SGeert Uytterhoeven for (i = 0; i < xfer->len; i++) { 833880c6d11SGeert Uytterhoeven ret = rspi_data_out(rspi, *buf++); 834880c6d11SGeert Uytterhoeven if (ret < 0) 835880c6d11SGeert Uytterhoeven return ret; 836880c6d11SGeert Uytterhoeven } 837880c6d11SGeert Uytterhoeven 838880c6d11SGeert Uytterhoeven /* Wait for the last transmission */ 839880c6d11SGeert Uytterhoeven rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 840880c6d11SGeert Uytterhoeven 841880c6d11SGeert Uytterhoeven return 0; 842880c6d11SGeert Uytterhoeven } 843880c6d11SGeert Uytterhoeven 844880c6d11SGeert Uytterhoeven static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) 845880c6d11SGeert Uytterhoeven { 846880c6d11SGeert Uytterhoeven u8 *buf = xfer->rx_buf; 847880c6d11SGeert Uytterhoeven unsigned int i; 848880c6d11SGeert Uytterhoeven int ret; 849880c6d11SGeert Uytterhoeven 850880c6d11SGeert Uytterhoeven for (i = 0; i < xfer->len; i++) { 851880c6d11SGeert Uytterhoeven ret = rspi_data_in(rspi); 852880c6d11SGeert Uytterhoeven if (ret < 0) 853880c6d11SGeert Uytterhoeven return ret; 854880c6d11SGeert Uytterhoeven *buf++ = ret; 855880c6d11SGeert Uytterhoeven } 856880c6d11SGeert Uytterhoeven 857880c6d11SGeert Uytterhoeven return 0; 858880c6d11SGeert Uytterhoeven } 859880c6d11SGeert Uytterhoeven 860eb557f75SGeert Uytterhoeven static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, 861eb557f75SGeert Uytterhoeven struct spi_transfer *xfer) 862eb557f75SGeert Uytterhoeven { 863eb557f75SGeert Uytterhoeven struct rspi_data *rspi = spi_master_get_devdata(master); 864eb557f75SGeert Uytterhoeven 865ba824d49SGeert Uytterhoeven if (spi->mode & SPI_LOOP) { 866ba824d49SGeert Uytterhoeven return qspi_transfer_out_in(rspi, xfer); 867ba824d49SGeert Uytterhoeven } else if (xfer->tx_buf && xfer->tx_nbits > SPI_NBITS_SINGLE) { 868880c6d11SGeert Uytterhoeven /* Quad or Dual SPI Write */ 869880c6d11SGeert Uytterhoeven return qspi_transfer_out(rspi, xfer); 870880c6d11SGeert Uytterhoeven } else if (xfer->rx_buf && xfer->rx_nbits > SPI_NBITS_SINGLE) { 871880c6d11SGeert Uytterhoeven /* Quad or Dual SPI Read */ 872880c6d11SGeert Uytterhoeven return qspi_transfer_in(rspi, xfer); 873880c6d11SGeert Uytterhoeven } else { 874880c6d11SGeert Uytterhoeven /* Single SPI Transfer */ 875340a15e6SGeert Uytterhoeven return qspi_transfer_out_in(rspi, xfer); 876eb557f75SGeert Uytterhoeven } 877880c6d11SGeert Uytterhoeven } 878eb557f75SGeert Uytterhoeven 8790b2182ddSShimoda, Yoshihiro static int rspi_setup(struct spi_device *spi) 8800b2182ddSShimoda, Yoshihiro { 8810b2182ddSShimoda, Yoshihiro struct rspi_data *rspi = spi_master_get_devdata(spi->master); 8820b2182ddSShimoda, Yoshihiro 8830b2182ddSShimoda, Yoshihiro rspi->max_speed_hz = spi->max_speed_hz; 8840b2182ddSShimoda, Yoshihiro 885348e5153SGeert Uytterhoeven rspi->spcmd = SPCMD_SSLKP; 886348e5153SGeert Uytterhoeven if (spi->mode & SPI_CPOL) 887348e5153SGeert Uytterhoeven rspi->spcmd |= SPCMD_CPOL; 888348e5153SGeert Uytterhoeven if (spi->mode & SPI_CPHA) 889348e5153SGeert Uytterhoeven rspi->spcmd |= SPCMD_CPHA; 890348e5153SGeert Uytterhoeven 89106a7a3cfSGeert Uytterhoeven /* CMOS output mode and MOSI signal from previous transfer */ 89206a7a3cfSGeert Uytterhoeven rspi->sppcr = 0; 89306a7a3cfSGeert Uytterhoeven if (spi->mode & SPI_LOOP) 89406a7a3cfSGeert Uytterhoeven rspi->sppcr |= SPPCR_SPLP; 89506a7a3cfSGeert Uytterhoeven 8965ce0ba88SHiep Cao Minh set_config_register(rspi, 8); 8970b2182ddSShimoda, Yoshihiro 8980b2182ddSShimoda, Yoshihiro return 0; 8990b2182ddSShimoda, Yoshihiro } 9000b2182ddSShimoda, Yoshihiro 901880c6d11SGeert Uytterhoeven static u16 qspi_transfer_mode(const struct spi_transfer *xfer) 902880c6d11SGeert Uytterhoeven { 903880c6d11SGeert Uytterhoeven if (xfer->tx_buf) 904880c6d11SGeert Uytterhoeven switch (xfer->tx_nbits) { 905880c6d11SGeert Uytterhoeven case SPI_NBITS_QUAD: 906880c6d11SGeert Uytterhoeven return SPCMD_SPIMOD_QUAD; 907880c6d11SGeert Uytterhoeven case SPI_NBITS_DUAL: 908880c6d11SGeert Uytterhoeven return SPCMD_SPIMOD_DUAL; 909880c6d11SGeert Uytterhoeven default: 910880c6d11SGeert Uytterhoeven return 0; 911880c6d11SGeert Uytterhoeven } 912880c6d11SGeert Uytterhoeven if (xfer->rx_buf) 913880c6d11SGeert Uytterhoeven switch (xfer->rx_nbits) { 914880c6d11SGeert Uytterhoeven case SPI_NBITS_QUAD: 915880c6d11SGeert Uytterhoeven return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; 916880c6d11SGeert Uytterhoeven case SPI_NBITS_DUAL: 917880c6d11SGeert Uytterhoeven return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; 918880c6d11SGeert Uytterhoeven default: 919880c6d11SGeert Uytterhoeven return 0; 920880c6d11SGeert Uytterhoeven } 921880c6d11SGeert Uytterhoeven 922880c6d11SGeert Uytterhoeven return 0; 923880c6d11SGeert Uytterhoeven } 924880c6d11SGeert Uytterhoeven 925880c6d11SGeert Uytterhoeven static int qspi_setup_sequencer(struct rspi_data *rspi, 926880c6d11SGeert Uytterhoeven const struct spi_message *msg) 927880c6d11SGeert Uytterhoeven { 928880c6d11SGeert Uytterhoeven const struct spi_transfer *xfer; 929880c6d11SGeert Uytterhoeven unsigned int i = 0, len = 0; 930880c6d11SGeert Uytterhoeven u16 current_mode = 0xffff, mode; 931880c6d11SGeert Uytterhoeven 932880c6d11SGeert Uytterhoeven list_for_each_entry(xfer, &msg->transfers, transfer_list) { 933880c6d11SGeert Uytterhoeven mode = qspi_transfer_mode(xfer); 934880c6d11SGeert Uytterhoeven if (mode == current_mode) { 935880c6d11SGeert Uytterhoeven len += xfer->len; 936880c6d11SGeert Uytterhoeven continue; 937880c6d11SGeert Uytterhoeven } 938880c6d11SGeert Uytterhoeven 939880c6d11SGeert Uytterhoeven /* Transfer mode change */ 940880c6d11SGeert Uytterhoeven if (i) { 941880c6d11SGeert Uytterhoeven /* Set transfer data length of previous transfer */ 942880c6d11SGeert Uytterhoeven rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 943880c6d11SGeert Uytterhoeven } 944880c6d11SGeert Uytterhoeven 945880c6d11SGeert Uytterhoeven if (i >= QSPI_NUM_SPCMD) { 946880c6d11SGeert Uytterhoeven dev_err(&msg->spi->dev, 947880c6d11SGeert Uytterhoeven "Too many different transfer modes"); 948880c6d11SGeert Uytterhoeven return -EINVAL; 949880c6d11SGeert Uytterhoeven } 950880c6d11SGeert Uytterhoeven 951880c6d11SGeert Uytterhoeven /* Program transfer mode for this transfer */ 952880c6d11SGeert Uytterhoeven rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); 953880c6d11SGeert Uytterhoeven current_mode = mode; 954880c6d11SGeert Uytterhoeven len = xfer->len; 955880c6d11SGeert Uytterhoeven i++; 956880c6d11SGeert Uytterhoeven } 957880c6d11SGeert Uytterhoeven if (i) { 958880c6d11SGeert Uytterhoeven /* Set final transfer data length and sequence length */ 959880c6d11SGeert Uytterhoeven rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 960880c6d11SGeert Uytterhoeven rspi_write8(rspi, i - 1, RSPI_SPSCR); 961880c6d11SGeert Uytterhoeven } 962880c6d11SGeert Uytterhoeven 963880c6d11SGeert Uytterhoeven return 0; 964880c6d11SGeert Uytterhoeven } 965880c6d11SGeert Uytterhoeven 96679d23495SGeert Uytterhoeven static int rspi_prepare_message(struct spi_master *master, 967880c6d11SGeert Uytterhoeven struct spi_message *msg) 96879d23495SGeert Uytterhoeven { 96979d23495SGeert Uytterhoeven struct rspi_data *rspi = spi_master_get_devdata(master); 970880c6d11SGeert Uytterhoeven int ret; 9710b2182ddSShimoda, Yoshihiro 972880c6d11SGeert Uytterhoeven if (msg->spi->mode & 973880c6d11SGeert Uytterhoeven (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { 974880c6d11SGeert Uytterhoeven /* Setup sequencer for messages with multiple transfer modes */ 975880c6d11SGeert Uytterhoeven ret = qspi_setup_sequencer(rspi, msg); 976880c6d11SGeert Uytterhoeven if (ret < 0) 977880c6d11SGeert Uytterhoeven return ret; 978880c6d11SGeert Uytterhoeven } 979880c6d11SGeert Uytterhoeven 980880c6d11SGeert Uytterhoeven /* Enable SPI function in master mode */ 98179d23495SGeert Uytterhoeven rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); 9820b2182ddSShimoda, Yoshihiro return 0; 9830b2182ddSShimoda, Yoshihiro } 9840b2182ddSShimoda, Yoshihiro 98579d23495SGeert Uytterhoeven static int rspi_unprepare_message(struct spi_master *master, 986880c6d11SGeert Uytterhoeven struct spi_message *msg) 9870b2182ddSShimoda, Yoshihiro { 98879d23495SGeert Uytterhoeven struct rspi_data *rspi = spi_master_get_devdata(master); 98979d23495SGeert Uytterhoeven 990880c6d11SGeert Uytterhoeven /* Disable SPI function */ 99179d23495SGeert Uytterhoeven rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 992880c6d11SGeert Uytterhoeven 993880c6d11SGeert Uytterhoeven /* Reset sequencer for Single SPI Transfers */ 994880c6d11SGeert Uytterhoeven rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 995880c6d11SGeert Uytterhoeven rspi_write8(rspi, 0, RSPI_SPSCR); 99679d23495SGeert Uytterhoeven return 0; 9970b2182ddSShimoda, Yoshihiro } 9980b2182ddSShimoda, Yoshihiro 99993722206SGeert Uytterhoeven static irqreturn_t rspi_irq_mux(int irq, void *_sr) 10000b2182ddSShimoda, Yoshihiro { 1001c132f094SGeert Uytterhoeven struct rspi_data *rspi = _sr; 100297b95c11SGeert Uytterhoeven u8 spsr; 10030b2182ddSShimoda, Yoshihiro irqreturn_t ret = IRQ_NONE; 100497b95c11SGeert Uytterhoeven u8 disable_irq = 0; 10050b2182ddSShimoda, Yoshihiro 10060b2182ddSShimoda, Yoshihiro rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 10070b2182ddSShimoda, Yoshihiro if (spsr & SPSR_SPRF) 10080b2182ddSShimoda, Yoshihiro disable_irq |= SPCR_SPRIE; 10090b2182ddSShimoda, Yoshihiro if (spsr & SPSR_SPTEF) 10100b2182ddSShimoda, Yoshihiro disable_irq |= SPCR_SPTIE; 10110b2182ddSShimoda, Yoshihiro 10120b2182ddSShimoda, Yoshihiro if (disable_irq) { 10130b2182ddSShimoda, Yoshihiro ret = IRQ_HANDLED; 10140b2182ddSShimoda, Yoshihiro rspi_disable_irq(rspi, disable_irq); 10150b2182ddSShimoda, Yoshihiro wake_up(&rspi->wait); 10160b2182ddSShimoda, Yoshihiro } 10170b2182ddSShimoda, Yoshihiro 10180b2182ddSShimoda, Yoshihiro return ret; 10190b2182ddSShimoda, Yoshihiro } 10200b2182ddSShimoda, Yoshihiro 102193722206SGeert Uytterhoeven static irqreturn_t rspi_irq_rx(int irq, void *_sr) 102293722206SGeert Uytterhoeven { 102393722206SGeert Uytterhoeven struct rspi_data *rspi = _sr; 102493722206SGeert Uytterhoeven u8 spsr; 102593722206SGeert Uytterhoeven 102693722206SGeert Uytterhoeven rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 102793722206SGeert Uytterhoeven if (spsr & SPSR_SPRF) { 102893722206SGeert Uytterhoeven rspi_disable_irq(rspi, SPCR_SPRIE); 102993722206SGeert Uytterhoeven wake_up(&rspi->wait); 103093722206SGeert Uytterhoeven return IRQ_HANDLED; 103193722206SGeert Uytterhoeven } 103293722206SGeert Uytterhoeven 103393722206SGeert Uytterhoeven return 0; 103493722206SGeert Uytterhoeven } 103593722206SGeert Uytterhoeven 103693722206SGeert Uytterhoeven static irqreturn_t rspi_irq_tx(int irq, void *_sr) 103793722206SGeert Uytterhoeven { 103893722206SGeert Uytterhoeven struct rspi_data *rspi = _sr; 103993722206SGeert Uytterhoeven u8 spsr; 104093722206SGeert Uytterhoeven 104193722206SGeert Uytterhoeven rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 104293722206SGeert Uytterhoeven if (spsr & SPSR_SPTEF) { 104393722206SGeert Uytterhoeven rspi_disable_irq(rspi, SPCR_SPTIE); 104493722206SGeert Uytterhoeven wake_up(&rspi->wait); 104593722206SGeert Uytterhoeven return IRQ_HANDLED; 104693722206SGeert Uytterhoeven } 104793722206SGeert Uytterhoeven 104893722206SGeert Uytterhoeven return 0; 104993722206SGeert Uytterhoeven } 105093722206SGeert Uytterhoeven 1051fd4a319bSGrant Likely static int rspi_request_dma(struct rspi_data *rspi, 1052a3633fe7SShimoda, Yoshihiro struct platform_device *pdev) 1053a3633fe7SShimoda, Yoshihiro { 1054baf588f4SGeert Uytterhoeven const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); 1055e2b05099SGuennadi Liakhovetski struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1056a3633fe7SShimoda, Yoshihiro dma_cap_mask_t mask; 10570243c536SShimoda, Yoshihiro struct dma_slave_config cfg; 10580243c536SShimoda, Yoshihiro int ret; 1059a3633fe7SShimoda, Yoshihiro 1060e2b05099SGuennadi Liakhovetski if (!res || !rspi_pd) 10610243c536SShimoda, Yoshihiro return 0; /* The driver assumes no error. */ 1062a3633fe7SShimoda, Yoshihiro 1063a3633fe7SShimoda, Yoshihiro rspi->dma_width_16bit = rspi_pd->dma_width_16bit; 1064a3633fe7SShimoda, Yoshihiro 1065a3633fe7SShimoda, Yoshihiro /* If the module receives data by DMAC, it also needs TX DMAC */ 1066a3633fe7SShimoda, Yoshihiro if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { 1067a3633fe7SShimoda, Yoshihiro dma_cap_zero(mask); 1068a3633fe7SShimoda, Yoshihiro dma_cap_set(DMA_SLAVE, mask); 10690243c536SShimoda, Yoshihiro rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, 10700243c536SShimoda, Yoshihiro (void *)rspi_pd->dma_rx_id); 10710243c536SShimoda, Yoshihiro if (rspi->chan_rx) { 10720243c536SShimoda, Yoshihiro cfg.slave_id = rspi_pd->dma_rx_id; 10730243c536SShimoda, Yoshihiro cfg.direction = DMA_DEV_TO_MEM; 1074e2b05099SGuennadi Liakhovetski cfg.dst_addr = 0; 1075e2b05099SGuennadi Liakhovetski cfg.src_addr = res->start + RSPI_SPDR; 10760243c536SShimoda, Yoshihiro ret = dmaengine_slave_config(rspi->chan_rx, &cfg); 10770243c536SShimoda, Yoshihiro if (!ret) 1078a3633fe7SShimoda, Yoshihiro dev_info(&pdev->dev, "Use DMA when rx.\n"); 10790243c536SShimoda, Yoshihiro else 10800243c536SShimoda, Yoshihiro return ret; 10810243c536SShimoda, Yoshihiro } 1082a3633fe7SShimoda, Yoshihiro } 1083a3633fe7SShimoda, Yoshihiro if (rspi_pd->dma_tx_id) { 1084a3633fe7SShimoda, Yoshihiro dma_cap_zero(mask); 1085a3633fe7SShimoda, Yoshihiro dma_cap_set(DMA_SLAVE, mask); 10860243c536SShimoda, Yoshihiro rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, 10870243c536SShimoda, Yoshihiro (void *)rspi_pd->dma_tx_id); 10880243c536SShimoda, Yoshihiro if (rspi->chan_tx) { 10890243c536SShimoda, Yoshihiro cfg.slave_id = rspi_pd->dma_tx_id; 10900243c536SShimoda, Yoshihiro cfg.direction = DMA_MEM_TO_DEV; 1091e2b05099SGuennadi Liakhovetski cfg.dst_addr = res->start + RSPI_SPDR; 1092e2b05099SGuennadi Liakhovetski cfg.src_addr = 0; 10930243c536SShimoda, Yoshihiro ret = dmaengine_slave_config(rspi->chan_tx, &cfg); 10940243c536SShimoda, Yoshihiro if (!ret) 1095a3633fe7SShimoda, Yoshihiro dev_info(&pdev->dev, "Use DMA when tx\n"); 10960243c536SShimoda, Yoshihiro else 10970243c536SShimoda, Yoshihiro return ret; 1098a3633fe7SShimoda, Yoshihiro } 1099a3633fe7SShimoda, Yoshihiro } 1100a3633fe7SShimoda, Yoshihiro 11010243c536SShimoda, Yoshihiro return 0; 11020243c536SShimoda, Yoshihiro } 11030243c536SShimoda, Yoshihiro 1104fd4a319bSGrant Likely static void rspi_release_dma(struct rspi_data *rspi) 1105a3633fe7SShimoda, Yoshihiro { 1106a3633fe7SShimoda, Yoshihiro if (rspi->chan_tx) 1107a3633fe7SShimoda, Yoshihiro dma_release_channel(rspi->chan_tx); 1108a3633fe7SShimoda, Yoshihiro if (rspi->chan_rx) 1109a3633fe7SShimoda, Yoshihiro dma_release_channel(rspi->chan_rx); 1110a3633fe7SShimoda, Yoshihiro } 1111a3633fe7SShimoda, Yoshihiro 1112fd4a319bSGrant Likely static int rspi_remove(struct platform_device *pdev) 11130b2182ddSShimoda, Yoshihiro { 11145ffbe2d9SLaurent Pinchart struct rspi_data *rspi = platform_get_drvdata(pdev); 11150b2182ddSShimoda, Yoshihiro 1116a3633fe7SShimoda, Yoshihiro rspi_release_dma(rspi); 1117490c9774SGeert Uytterhoeven pm_runtime_disable(&pdev->dev); 11180b2182ddSShimoda, Yoshihiro 11190b2182ddSShimoda, Yoshihiro return 0; 11200b2182ddSShimoda, Yoshihiro } 11210b2182ddSShimoda, Yoshihiro 1122426ef76dSGeert Uytterhoeven static const struct spi_ops rspi_ops = { 1123426ef76dSGeert Uytterhoeven .set_config_register = rspi_set_config_register, 1124426ef76dSGeert Uytterhoeven .transfer_one = rspi_transfer_one, 1125880c6d11SGeert Uytterhoeven .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 1126426ef76dSGeert Uytterhoeven }; 1127426ef76dSGeert Uytterhoeven 1128426ef76dSGeert Uytterhoeven static const struct spi_ops rspi_rz_ops = { 1129426ef76dSGeert Uytterhoeven .set_config_register = rspi_rz_set_config_register, 1130426ef76dSGeert Uytterhoeven .transfer_one = rspi_rz_transfer_one, 1131880c6d11SGeert Uytterhoeven .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 1132426ef76dSGeert Uytterhoeven }; 1133426ef76dSGeert Uytterhoeven 1134426ef76dSGeert Uytterhoeven static const struct spi_ops qspi_ops = { 1135426ef76dSGeert Uytterhoeven .set_config_register = qspi_set_config_register, 1136426ef76dSGeert Uytterhoeven .transfer_one = qspi_transfer_one, 1137880c6d11SGeert Uytterhoeven .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | 1138880c6d11SGeert Uytterhoeven SPI_TX_DUAL | SPI_TX_QUAD | 1139880c6d11SGeert Uytterhoeven SPI_RX_DUAL | SPI_RX_QUAD, 1140426ef76dSGeert Uytterhoeven }; 1141426ef76dSGeert Uytterhoeven 1142426ef76dSGeert Uytterhoeven #ifdef CONFIG_OF 1143426ef76dSGeert Uytterhoeven static const struct of_device_id rspi_of_match[] = { 1144426ef76dSGeert Uytterhoeven /* RSPI on legacy SH */ 1145426ef76dSGeert Uytterhoeven { .compatible = "renesas,rspi", .data = &rspi_ops }, 1146426ef76dSGeert Uytterhoeven /* RSPI on RZ/A1H */ 1147426ef76dSGeert Uytterhoeven { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, 1148426ef76dSGeert Uytterhoeven /* QSPI on R-Car Gen2 */ 1149426ef76dSGeert Uytterhoeven { .compatible = "renesas,qspi", .data = &qspi_ops }, 1150426ef76dSGeert Uytterhoeven { /* sentinel */ } 1151426ef76dSGeert Uytterhoeven }; 1152426ef76dSGeert Uytterhoeven 1153426ef76dSGeert Uytterhoeven MODULE_DEVICE_TABLE(of, rspi_of_match); 1154426ef76dSGeert Uytterhoeven 1155426ef76dSGeert Uytterhoeven static int rspi_parse_dt(struct device *dev, struct spi_master *master) 1156426ef76dSGeert Uytterhoeven { 1157426ef76dSGeert Uytterhoeven u32 num_cs; 1158426ef76dSGeert Uytterhoeven int error; 1159426ef76dSGeert Uytterhoeven 1160426ef76dSGeert Uytterhoeven /* Parse DT properties */ 1161426ef76dSGeert Uytterhoeven error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); 1162426ef76dSGeert Uytterhoeven if (error) { 1163426ef76dSGeert Uytterhoeven dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); 1164426ef76dSGeert Uytterhoeven return error; 1165426ef76dSGeert Uytterhoeven } 1166426ef76dSGeert Uytterhoeven 1167426ef76dSGeert Uytterhoeven master->num_chipselect = num_cs; 1168426ef76dSGeert Uytterhoeven return 0; 1169426ef76dSGeert Uytterhoeven } 1170426ef76dSGeert Uytterhoeven #else 117164b67defSShimoda, Yoshihiro #define rspi_of_match NULL 1172426ef76dSGeert Uytterhoeven static inline int rspi_parse_dt(struct device *dev, struct spi_master *master) 1173426ef76dSGeert Uytterhoeven { 1174426ef76dSGeert Uytterhoeven return -EINVAL; 1175426ef76dSGeert Uytterhoeven } 1176426ef76dSGeert Uytterhoeven #endif /* CONFIG_OF */ 1177426ef76dSGeert Uytterhoeven 117893722206SGeert Uytterhoeven static int rspi_request_irq(struct device *dev, unsigned int irq, 117993722206SGeert Uytterhoeven irq_handler_t handler, const char *suffix, 118093722206SGeert Uytterhoeven void *dev_id) 118193722206SGeert Uytterhoeven { 118293722206SGeert Uytterhoeven const char *base = dev_name(dev); 118393722206SGeert Uytterhoeven size_t len = strlen(base) + strlen(suffix) + 2; 118493722206SGeert Uytterhoeven char *name = devm_kzalloc(dev, len, GFP_KERNEL); 118593722206SGeert Uytterhoeven if (!name) 118693722206SGeert Uytterhoeven return -ENOMEM; 118793722206SGeert Uytterhoeven snprintf(name, len, "%s:%s", base, suffix); 118893722206SGeert Uytterhoeven return devm_request_irq(dev, irq, handler, 0, name, dev_id); 118993722206SGeert Uytterhoeven } 119093722206SGeert Uytterhoeven 1191fd4a319bSGrant Likely static int rspi_probe(struct platform_device *pdev) 11920b2182ddSShimoda, Yoshihiro { 11930b2182ddSShimoda, Yoshihiro struct resource *res; 11940b2182ddSShimoda, Yoshihiro struct spi_master *master; 11950b2182ddSShimoda, Yoshihiro struct rspi_data *rspi; 119693722206SGeert Uytterhoeven int ret; 1197426ef76dSGeert Uytterhoeven const struct of_device_id *of_id; 1198426ef76dSGeert Uytterhoeven const struct rspi_plat_data *rspi_pd; 11995ce0ba88SHiep Cao Minh const struct spi_ops *ops; 12000b2182ddSShimoda, Yoshihiro 12010b2182ddSShimoda, Yoshihiro master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 12020b2182ddSShimoda, Yoshihiro if (master == NULL) { 12030b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "spi_alloc_master error.\n"); 12040b2182ddSShimoda, Yoshihiro return -ENOMEM; 12050b2182ddSShimoda, Yoshihiro } 12060b2182ddSShimoda, Yoshihiro 1207426ef76dSGeert Uytterhoeven of_id = of_match_device(rspi_of_match, &pdev->dev); 1208426ef76dSGeert Uytterhoeven if (of_id) { 1209426ef76dSGeert Uytterhoeven ops = of_id->data; 1210426ef76dSGeert Uytterhoeven ret = rspi_parse_dt(&pdev->dev, master); 1211426ef76dSGeert Uytterhoeven if (ret) 1212426ef76dSGeert Uytterhoeven goto error1; 1213426ef76dSGeert Uytterhoeven } else { 1214426ef76dSGeert Uytterhoeven ops = (struct spi_ops *)pdev->id_entry->driver_data; 1215426ef76dSGeert Uytterhoeven rspi_pd = dev_get_platdata(&pdev->dev); 1216426ef76dSGeert Uytterhoeven if (rspi_pd && rspi_pd->num_chipselect) 1217426ef76dSGeert Uytterhoeven master->num_chipselect = rspi_pd->num_chipselect; 1218426ef76dSGeert Uytterhoeven else 1219426ef76dSGeert Uytterhoeven master->num_chipselect = 2; /* default */ 1220426ef76dSGeert Uytterhoeven }; 1221426ef76dSGeert Uytterhoeven 1222426ef76dSGeert Uytterhoeven /* ops parameter check */ 1223426ef76dSGeert Uytterhoeven if (!ops->set_config_register) { 1224426ef76dSGeert Uytterhoeven dev_err(&pdev->dev, "there is no set_config_register\n"); 1225426ef76dSGeert Uytterhoeven ret = -ENODEV; 1226426ef76dSGeert Uytterhoeven goto error1; 1227426ef76dSGeert Uytterhoeven } 1228426ef76dSGeert Uytterhoeven 12290b2182ddSShimoda, Yoshihiro rspi = spi_master_get_devdata(master); 123024b5a82cSJingoo Han platform_set_drvdata(pdev, rspi); 12315ce0ba88SHiep Cao Minh rspi->ops = ops; 12320b2182ddSShimoda, Yoshihiro rspi->master = master; 12335d79e9acSLaurent Pinchart 12345d79e9acSLaurent Pinchart res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 12355d79e9acSLaurent Pinchart rspi->addr = devm_ioremap_resource(&pdev->dev, res); 12365d79e9acSLaurent Pinchart if (IS_ERR(rspi->addr)) { 12375d79e9acSLaurent Pinchart ret = PTR_ERR(rspi->addr); 12380b2182ddSShimoda, Yoshihiro goto error1; 12390b2182ddSShimoda, Yoshihiro } 12400b2182ddSShimoda, Yoshihiro 124129f397b7SGeert Uytterhoeven rspi->clk = devm_clk_get(&pdev->dev, NULL); 12420b2182ddSShimoda, Yoshihiro if (IS_ERR(rspi->clk)) { 12430b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "cannot get clock\n"); 12440b2182ddSShimoda, Yoshihiro ret = PTR_ERR(rspi->clk); 12455d79e9acSLaurent Pinchart goto error1; 12460b2182ddSShimoda, Yoshihiro } 124717fe0d9aSGeert Uytterhoeven 1248490c9774SGeert Uytterhoeven pm_runtime_enable(&pdev->dev); 12490b2182ddSShimoda, Yoshihiro 12500b2182ddSShimoda, Yoshihiro init_waitqueue_head(&rspi->wait); 12510b2182ddSShimoda, Yoshihiro 12520b2182ddSShimoda, Yoshihiro master->bus_num = pdev->id; 12530b2182ddSShimoda, Yoshihiro master->setup = rspi_setup; 1254490c9774SGeert Uytterhoeven master->auto_runtime_pm = true; 1255eb557f75SGeert Uytterhoeven master->transfer_one = ops->transfer_one; 125679d23495SGeert Uytterhoeven master->prepare_message = rspi_prepare_message; 125779d23495SGeert Uytterhoeven master->unprepare_message = rspi_unprepare_message; 1258880c6d11SGeert Uytterhoeven master->mode_bits = ops->mode_bits; 1259426ef76dSGeert Uytterhoeven master->dev.of_node = pdev->dev.of_node; 12600b2182ddSShimoda, Yoshihiro 126193722206SGeert Uytterhoeven ret = platform_get_irq_byname(pdev, "rx"); 126293722206SGeert Uytterhoeven if (ret < 0) { 126393722206SGeert Uytterhoeven ret = platform_get_irq_byname(pdev, "mux"); 126493722206SGeert Uytterhoeven if (ret < 0) 126593722206SGeert Uytterhoeven ret = platform_get_irq(pdev, 0); 126693722206SGeert Uytterhoeven if (ret >= 0) 126793722206SGeert Uytterhoeven rspi->rx_irq = rspi->tx_irq = ret; 126893722206SGeert Uytterhoeven } else { 126993722206SGeert Uytterhoeven rspi->rx_irq = ret; 127093722206SGeert Uytterhoeven ret = platform_get_irq_byname(pdev, "tx"); 127193722206SGeert Uytterhoeven if (ret >= 0) 127293722206SGeert Uytterhoeven rspi->tx_irq = ret; 127393722206SGeert Uytterhoeven } 127493722206SGeert Uytterhoeven if (ret < 0) { 127593722206SGeert Uytterhoeven dev_err(&pdev->dev, "platform_get_irq error\n"); 127693722206SGeert Uytterhoeven goto error2; 127793722206SGeert Uytterhoeven } 127893722206SGeert Uytterhoeven 127993722206SGeert Uytterhoeven if (rspi->rx_irq == rspi->tx_irq) { 128093722206SGeert Uytterhoeven /* Single multiplexed interrupt */ 128193722206SGeert Uytterhoeven ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, 128293722206SGeert Uytterhoeven "mux", rspi); 128393722206SGeert Uytterhoeven } else { 128493722206SGeert Uytterhoeven /* Multi-interrupt mode, only SPRI and SPTI are used */ 128593722206SGeert Uytterhoeven ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, 128693722206SGeert Uytterhoeven "rx", rspi); 128793722206SGeert Uytterhoeven if (!ret) 128893722206SGeert Uytterhoeven ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, 128993722206SGeert Uytterhoeven rspi_irq_tx, "tx", rspi); 129093722206SGeert Uytterhoeven } 12910b2182ddSShimoda, Yoshihiro if (ret < 0) { 12920b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "request_irq error\n"); 1293fcb4ed74SGeert Uytterhoeven goto error2; 12940b2182ddSShimoda, Yoshihiro } 12950b2182ddSShimoda, Yoshihiro 12960243c536SShimoda, Yoshihiro ret = rspi_request_dma(rspi, pdev); 12970243c536SShimoda, Yoshihiro if (ret < 0) { 12980243c536SShimoda, Yoshihiro dev_err(&pdev->dev, "rspi_request_dma failed.\n"); 1299fcb4ed74SGeert Uytterhoeven goto error3; 13000243c536SShimoda, Yoshihiro } 1301a3633fe7SShimoda, Yoshihiro 13029e03d05eSJingoo Han ret = devm_spi_register_master(&pdev->dev, master); 13030b2182ddSShimoda, Yoshihiro if (ret < 0) { 13040b2182ddSShimoda, Yoshihiro dev_err(&pdev->dev, "spi_register_master error.\n"); 1305fcb4ed74SGeert Uytterhoeven goto error3; 13060b2182ddSShimoda, Yoshihiro } 13070b2182ddSShimoda, Yoshihiro 13080b2182ddSShimoda, Yoshihiro dev_info(&pdev->dev, "probed\n"); 13090b2182ddSShimoda, Yoshihiro 13100b2182ddSShimoda, Yoshihiro return 0; 13110b2182ddSShimoda, Yoshihiro 1312fcb4ed74SGeert Uytterhoeven error3: 13135d79e9acSLaurent Pinchart rspi_release_dma(rspi); 1314fcb4ed74SGeert Uytterhoeven error2: 1315490c9774SGeert Uytterhoeven pm_runtime_disable(&pdev->dev); 13160b2182ddSShimoda, Yoshihiro error1: 13170b2182ddSShimoda, Yoshihiro spi_master_put(master); 13180b2182ddSShimoda, Yoshihiro 13190b2182ddSShimoda, Yoshihiro return ret; 13200b2182ddSShimoda, Yoshihiro } 13210b2182ddSShimoda, Yoshihiro 13225ce0ba88SHiep Cao Minh static struct platform_device_id spi_driver_ids[] = { 13235ce0ba88SHiep Cao Minh { "rspi", (kernel_ulong_t)&rspi_ops }, 1324862d357fSGeert Uytterhoeven { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, 13255ce0ba88SHiep Cao Minh { "qspi", (kernel_ulong_t)&qspi_ops }, 13265ce0ba88SHiep Cao Minh {}, 13275ce0ba88SHiep Cao Minh }; 13285ce0ba88SHiep Cao Minh 13295ce0ba88SHiep Cao Minh MODULE_DEVICE_TABLE(platform, spi_driver_ids); 13305ce0ba88SHiep Cao Minh 13310b2182ddSShimoda, Yoshihiro static struct platform_driver rspi_driver = { 13320b2182ddSShimoda, Yoshihiro .probe = rspi_probe, 1333fd4a319bSGrant Likely .remove = rspi_remove, 13345ce0ba88SHiep Cao Minh .id_table = spi_driver_ids, 13350b2182ddSShimoda, Yoshihiro .driver = { 13365ce0ba88SHiep Cao Minh .name = "renesas_spi", 13370b2182ddSShimoda, Yoshihiro .owner = THIS_MODULE, 1338426ef76dSGeert Uytterhoeven .of_match_table = of_match_ptr(rspi_of_match), 13390b2182ddSShimoda, Yoshihiro }, 13400b2182ddSShimoda, Yoshihiro }; 13410b2182ddSShimoda, Yoshihiro module_platform_driver(rspi_driver); 13420b2182ddSShimoda, Yoshihiro 13430b2182ddSShimoda, Yoshihiro MODULE_DESCRIPTION("Renesas RSPI bus driver"); 13440b2182ddSShimoda, Yoshihiro MODULE_LICENSE("GPL v2"); 13450b2182ddSShimoda, Yoshihiro MODULE_AUTHOR("Yoshihiro Shimoda"); 13460b2182ddSShimoda, Yoshihiro MODULE_ALIAS("platform:rspi"); 1347