1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Addy Ke <addy.ke@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/spi/spi.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/scatterlist.h> 17 18 #define DRIVER_NAME "rockchip-spi" 19 20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ 21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg) 22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ 23 writel_relaxed(readl_relaxed(reg) | (bits), reg) 24 25 /* SPI register offsets */ 26 #define ROCKCHIP_SPI_CTRLR0 0x0000 27 #define ROCKCHIP_SPI_CTRLR1 0x0004 28 #define ROCKCHIP_SPI_SSIENR 0x0008 29 #define ROCKCHIP_SPI_SER 0x000c 30 #define ROCKCHIP_SPI_BAUDR 0x0010 31 #define ROCKCHIP_SPI_TXFTLR 0x0014 32 #define ROCKCHIP_SPI_RXFTLR 0x0018 33 #define ROCKCHIP_SPI_TXFLR 0x001c 34 #define ROCKCHIP_SPI_RXFLR 0x0020 35 #define ROCKCHIP_SPI_SR 0x0024 36 #define ROCKCHIP_SPI_IPR 0x0028 37 #define ROCKCHIP_SPI_IMR 0x002c 38 #define ROCKCHIP_SPI_ISR 0x0030 39 #define ROCKCHIP_SPI_RISR 0x0034 40 #define ROCKCHIP_SPI_ICR 0x0038 41 #define ROCKCHIP_SPI_DMACR 0x003c 42 #define ROCKCHIP_SPI_DMATDLR 0x0040 43 #define ROCKCHIP_SPI_DMARDLR 0x0044 44 #define ROCKCHIP_SPI_VERSION 0x0048 45 #define ROCKCHIP_SPI_TXDR 0x0400 46 #define ROCKCHIP_SPI_RXDR 0x0800 47 48 /* Bit fields in CTRLR0 */ 49 #define CR0_DFS_OFFSET 0 50 #define CR0_DFS_4BIT 0x0 51 #define CR0_DFS_8BIT 0x1 52 #define CR0_DFS_16BIT 0x2 53 54 #define CR0_CFS_OFFSET 2 55 56 #define CR0_SCPH_OFFSET 6 57 58 #define CR0_SCPOL_OFFSET 7 59 60 #define CR0_CSM_OFFSET 8 61 #define CR0_CSM_KEEP 0x0 62 /* ss_n be high for half sclk_out cycles */ 63 #define CR0_CSM_HALF 0X1 64 /* ss_n be high for one sclk_out cycle */ 65 #define CR0_CSM_ONE 0x2 66 67 /* ss_n to sclk_out delay */ 68 #define CR0_SSD_OFFSET 10 69 /* 70 * The period between ss_n active and 71 * sclk_out active is half sclk_out cycles 72 */ 73 #define CR0_SSD_HALF 0x0 74 /* 75 * The period between ss_n active and 76 * sclk_out active is one sclk_out cycle 77 */ 78 #define CR0_SSD_ONE 0x1 79 80 #define CR0_EM_OFFSET 11 81 #define CR0_EM_LITTLE 0x0 82 #define CR0_EM_BIG 0x1 83 84 #define CR0_FBM_OFFSET 12 85 #define CR0_FBM_MSB 0x0 86 #define CR0_FBM_LSB 0x1 87 88 #define CR0_BHT_OFFSET 13 89 #define CR0_BHT_16BIT 0x0 90 #define CR0_BHT_8BIT 0x1 91 92 #define CR0_RSD_OFFSET 14 93 #define CR0_RSD_MAX 0x3 94 95 #define CR0_FRF_OFFSET 16 96 #define CR0_FRF_SPI 0x0 97 #define CR0_FRF_SSP 0x1 98 #define CR0_FRF_MICROWIRE 0x2 99 100 #define CR0_XFM_OFFSET 18 101 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) 102 #define CR0_XFM_TR 0x0 103 #define CR0_XFM_TO 0x1 104 #define CR0_XFM_RO 0x2 105 106 #define CR0_OPM_OFFSET 20 107 #define CR0_OPM_MASTER 0x0 108 #define CR0_OPM_SLAVE 0x1 109 110 #define CR0_SOI_OFFSET 23 111 112 #define CR0_MTM_OFFSET 0x21 113 114 /* Bit fields in SER, 2bit */ 115 #define SER_MASK 0x3 116 117 /* Bit fields in BAUDR */ 118 #define BAUDR_SCKDV_MIN 2 119 #define BAUDR_SCKDV_MAX 65534 120 121 /* Bit fields in SR, 6bit */ 122 #define SR_MASK 0x3f 123 #define SR_BUSY (1 << 0) 124 #define SR_TF_FULL (1 << 1) 125 #define SR_TF_EMPTY (1 << 2) 126 #define SR_RF_EMPTY (1 << 3) 127 #define SR_RF_FULL (1 << 4) 128 #define SR_SLAVE_TX_BUSY (1 << 5) 129 130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ 131 #define INT_MASK 0x1f 132 #define INT_TF_EMPTY (1 << 0) 133 #define INT_TF_OVERFLOW (1 << 1) 134 #define INT_RF_UNDERFLOW (1 << 2) 135 #define INT_RF_OVERFLOW (1 << 3) 136 #define INT_RF_FULL (1 << 4) 137 #define INT_CS_INACTIVE (1 << 6) 138 139 /* Bit fields in ICR, 4bit */ 140 #define ICR_MASK 0x0f 141 #define ICR_ALL (1 << 0) 142 #define ICR_RF_UNDERFLOW (1 << 1) 143 #define ICR_RF_OVERFLOW (1 << 2) 144 #define ICR_TF_OVERFLOW (1 << 3) 145 146 /* Bit fields in DMACR */ 147 #define RF_DMA_EN (1 << 0) 148 #define TF_DMA_EN (1 << 1) 149 150 /* Driver state flags */ 151 #define RXDMA (1 << 0) 152 #define TXDMA (1 << 1) 153 154 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ 155 #define MAX_SCLK_OUT 50000000U 156 157 /* 158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, 159 * the controller seems to hang when given 0x10000, so stick with this for now. 160 */ 161 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff 162 163 /* 2 for native cs, 2 for cs-gpio */ 164 #define ROCKCHIP_SPI_MAX_CS_NUM 4 165 #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002 166 #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002 167 168 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000 169 170 struct rockchip_spi { 171 struct device *dev; 172 173 struct clk *spiclk; 174 struct clk *apb_pclk; 175 176 void __iomem *regs; 177 dma_addr_t dma_addr_rx; 178 dma_addr_t dma_addr_tx; 179 180 const void *tx; 181 void *rx; 182 unsigned int tx_left; 183 unsigned int rx_left; 184 185 atomic_t state; 186 187 /*depth of the FIFO buffer */ 188 u32 fifo_len; 189 /* frequency of spiclk */ 190 u32 freq; 191 192 u8 n_bytes; 193 u8 rsd; 194 195 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; 196 197 bool slave_abort; 198 bool cs_inactive; /* spi slave tansmition stop when cs inactive */ 199 bool cs_high_supported; /* native CS supports active-high polarity */ 200 201 struct spi_transfer *xfer; /* Store xfer temporarily */ 202 }; 203 204 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) 205 { 206 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); 207 } 208 209 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode) 210 { 211 unsigned long timeout = jiffies + msecs_to_jiffies(5); 212 213 do { 214 if (slave_mode) { 215 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) && 216 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))) 217 return; 218 } else { 219 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) 220 return; 221 } 222 } while (!time_after(jiffies, timeout)); 223 224 dev_warn(rs->dev, "spi controller is in busy state!\n"); 225 } 226 227 static u32 get_fifo_len(struct rockchip_spi *rs) 228 { 229 u32 ver; 230 231 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION); 232 233 switch (ver) { 234 case ROCKCHIP_SPI_VER2_TYPE1: 235 case ROCKCHIP_SPI_VER2_TYPE2: 236 return 64; 237 default: 238 return 32; 239 } 240 } 241 242 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 243 { 244 struct spi_controller *ctlr = spi->controller; 245 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 246 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable; 247 248 /* Return immediately for no-op */ 249 if (cs_asserted == rs->cs_asserted[spi->chip_select]) 250 return; 251 252 if (cs_asserted) { 253 /* Keep things powered as long as CS is asserted */ 254 pm_runtime_get_sync(rs->dev); 255 256 if (spi->cs_gpiod) 257 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); 258 else 259 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select)); 260 } else { 261 if (spi->cs_gpiod) 262 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); 263 else 264 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select)); 265 266 /* Drop reference from when we first asserted CS */ 267 pm_runtime_put(rs->dev); 268 } 269 270 rs->cs_asserted[spi->chip_select] = cs_asserted; 271 } 272 273 static void rockchip_spi_handle_err(struct spi_controller *ctlr, 274 struct spi_message *msg) 275 { 276 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 277 278 /* stop running spi transfer 279 * this also flushes both rx and tx fifos 280 */ 281 spi_enable_chip(rs, false); 282 283 /* make sure all interrupts are masked and status cleared */ 284 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 285 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 286 287 if (atomic_read(&rs->state) & TXDMA) 288 dmaengine_terminate_async(ctlr->dma_tx); 289 290 if (atomic_read(&rs->state) & RXDMA) 291 dmaengine_terminate_async(ctlr->dma_rx); 292 } 293 294 static void rockchip_spi_pio_writer(struct rockchip_spi *rs) 295 { 296 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); 297 u32 words = min(rs->tx_left, tx_free); 298 299 rs->tx_left -= words; 300 for (; words; words--) { 301 u32 txw; 302 303 if (rs->n_bytes == 1) 304 txw = *(u8 *)rs->tx; 305 else 306 txw = *(u16 *)rs->tx; 307 308 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); 309 rs->tx += rs->n_bytes; 310 } 311 } 312 313 static void rockchip_spi_pio_reader(struct rockchip_spi *rs) 314 { 315 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 316 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0; 317 318 /* the hardware doesn't allow us to change fifo threshold 319 * level while spi is enabled, so instead make sure to leave 320 * enough words in the rx fifo to get the last interrupt 321 * exactly when all words have been received 322 */ 323 if (rx_left) { 324 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1; 325 326 if (rx_left < ftl) { 327 rx_left = ftl; 328 words = rs->rx_left - rx_left; 329 } 330 } 331 332 rs->rx_left = rx_left; 333 for (; words; words--) { 334 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 335 336 if (!rs->rx) 337 continue; 338 339 if (rs->n_bytes == 1) 340 *(u8 *)rs->rx = (u8)rxw; 341 else 342 *(u16 *)rs->rx = (u16)rxw; 343 rs->rx += rs->n_bytes; 344 } 345 } 346 347 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) 348 { 349 struct spi_controller *ctlr = dev_id; 350 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 351 352 /* When int_cs_inactive comes, spi slave abort */ 353 if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) { 354 ctlr->slave_abort(ctlr); 355 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 356 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 357 358 return IRQ_HANDLED; 359 } 360 361 if (rs->tx_left) 362 rockchip_spi_pio_writer(rs); 363 364 rockchip_spi_pio_reader(rs); 365 if (!rs->rx_left) { 366 spi_enable_chip(rs, false); 367 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 368 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 369 spi_finalize_current_transfer(ctlr); 370 } 371 372 return IRQ_HANDLED; 373 } 374 375 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, 376 struct spi_controller *ctlr, 377 struct spi_transfer *xfer) 378 { 379 rs->tx = xfer->tx_buf; 380 rs->rx = xfer->rx_buf; 381 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0; 382 rs->rx_left = xfer->len / rs->n_bytes; 383 384 if (rs->cs_inactive) 385 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR); 386 else 387 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR); 388 spi_enable_chip(rs, true); 389 390 if (rs->tx_left) 391 rockchip_spi_pio_writer(rs); 392 393 /* 1 means the transfer is in progress */ 394 return 1; 395 } 396 397 static void rockchip_spi_dma_rxcb(void *data) 398 { 399 struct spi_controller *ctlr = data; 400 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 401 int state = atomic_fetch_andnot(RXDMA, &rs->state); 402 403 if (state & TXDMA && !rs->slave_abort) 404 return; 405 406 if (rs->cs_inactive) 407 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 408 409 spi_enable_chip(rs, false); 410 spi_finalize_current_transfer(ctlr); 411 } 412 413 static void rockchip_spi_dma_txcb(void *data) 414 { 415 struct spi_controller *ctlr = data; 416 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 417 int state = atomic_fetch_andnot(TXDMA, &rs->state); 418 419 if (state & RXDMA && !rs->slave_abort) 420 return; 421 422 /* Wait until the FIFO data completely. */ 423 wait_for_tx_idle(rs, ctlr->slave); 424 425 spi_enable_chip(rs, false); 426 spi_finalize_current_transfer(ctlr); 427 } 428 429 static u32 rockchip_spi_calc_burst_size(u32 data_len) 430 { 431 u32 i; 432 433 /* burst size: 1, 2, 4, 8 */ 434 for (i = 1; i < 8; i <<= 1) { 435 if (data_len & i) 436 break; 437 } 438 439 return i; 440 } 441 442 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, 443 struct spi_controller *ctlr, struct spi_transfer *xfer) 444 { 445 struct dma_async_tx_descriptor *rxdesc, *txdesc; 446 447 atomic_set(&rs->state, 0); 448 449 rs->tx = xfer->tx_buf; 450 rs->rx = xfer->rx_buf; 451 452 rxdesc = NULL; 453 if (xfer->rx_buf) { 454 struct dma_slave_config rxconf = { 455 .direction = DMA_DEV_TO_MEM, 456 .src_addr = rs->dma_addr_rx, 457 .src_addr_width = rs->n_bytes, 458 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes), 459 }; 460 461 dmaengine_slave_config(ctlr->dma_rx, &rxconf); 462 463 rxdesc = dmaengine_prep_slave_sg( 464 ctlr->dma_rx, 465 xfer->rx_sg.sgl, xfer->rx_sg.nents, 466 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 467 if (!rxdesc) 468 return -EINVAL; 469 470 rxdesc->callback = rockchip_spi_dma_rxcb; 471 rxdesc->callback_param = ctlr; 472 } 473 474 txdesc = NULL; 475 if (xfer->tx_buf) { 476 struct dma_slave_config txconf = { 477 .direction = DMA_MEM_TO_DEV, 478 .dst_addr = rs->dma_addr_tx, 479 .dst_addr_width = rs->n_bytes, 480 .dst_maxburst = rs->fifo_len / 4, 481 }; 482 483 dmaengine_slave_config(ctlr->dma_tx, &txconf); 484 485 txdesc = dmaengine_prep_slave_sg( 486 ctlr->dma_tx, 487 xfer->tx_sg.sgl, xfer->tx_sg.nents, 488 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 489 if (!txdesc) { 490 if (rxdesc) 491 dmaengine_terminate_sync(ctlr->dma_rx); 492 return -EINVAL; 493 } 494 495 txdesc->callback = rockchip_spi_dma_txcb; 496 txdesc->callback_param = ctlr; 497 } 498 499 /* rx must be started before tx due to spi instinct */ 500 if (rxdesc) { 501 atomic_or(RXDMA, &rs->state); 502 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc); 503 dma_async_issue_pending(ctlr->dma_rx); 504 } 505 506 if (rs->cs_inactive) 507 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR); 508 509 spi_enable_chip(rs, true); 510 511 if (txdesc) { 512 atomic_or(TXDMA, &rs->state); 513 dmaengine_submit(txdesc); 514 dma_async_issue_pending(ctlr->dma_tx); 515 } 516 517 /* 1 means the transfer is in progress */ 518 return 1; 519 } 520 521 static int rockchip_spi_config(struct rockchip_spi *rs, 522 struct spi_device *spi, struct spi_transfer *xfer, 523 bool use_dma, bool slave_mode) 524 { 525 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET 526 | CR0_BHT_8BIT << CR0_BHT_OFFSET 527 | CR0_SSD_ONE << CR0_SSD_OFFSET 528 | CR0_EM_BIG << CR0_EM_OFFSET; 529 u32 cr1; 530 u32 dmacr = 0; 531 532 if (slave_mode) 533 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET; 534 rs->slave_abort = false; 535 536 cr0 |= rs->rsd << CR0_RSD_OFFSET; 537 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; 538 if (spi->mode & SPI_LSB_FIRST) 539 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; 540 if (spi->mode & SPI_CS_HIGH) 541 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET; 542 543 if (xfer->rx_buf && xfer->tx_buf) 544 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; 545 else if (xfer->rx_buf) 546 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; 547 else if (use_dma) 548 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; 549 550 switch (xfer->bits_per_word) { 551 case 4: 552 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; 553 cr1 = xfer->len - 1; 554 break; 555 case 8: 556 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; 557 cr1 = xfer->len - 1; 558 break; 559 case 16: 560 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; 561 cr1 = xfer->len / 2 - 1; 562 break; 563 default: 564 /* we only whitelist 4, 8 and 16 bit words in 565 * ctlr->bits_per_word_mask, so this shouldn't 566 * happen 567 */ 568 dev_err(rs->dev, "unknown bits per word: %d\n", 569 xfer->bits_per_word); 570 return -EINVAL; 571 } 572 573 if (use_dma) { 574 if (xfer->tx_buf) 575 dmacr |= TF_DMA_EN; 576 if (xfer->rx_buf) 577 dmacr |= RF_DMA_EN; 578 } 579 580 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 581 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); 582 583 /* unfortunately setting the fifo threshold level to generate an 584 * interrupt exactly when the fifo is full doesn't seem to work, 585 * so we need the strict inequality here 586 */ 587 if ((xfer->len / rs->n_bytes) < rs->fifo_len) 588 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 589 else 590 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 591 592 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR); 593 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1, 594 rs->regs + ROCKCHIP_SPI_DMARDLR); 595 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); 596 597 /* the hardware only supports an even clock divisor, so 598 * round divisor = spiclk / speed up to nearest even number 599 * so that the resulting speed is <= the requested speed 600 */ 601 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz), 602 rs->regs + ROCKCHIP_SPI_BAUDR); 603 604 return 0; 605 } 606 607 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) 608 { 609 return ROCKCHIP_SPI_MAX_TRANLEN; 610 } 611 612 static int rockchip_spi_slave_abort(struct spi_controller *ctlr) 613 { 614 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 615 u32 rx_fifo_left; 616 struct dma_tx_state state; 617 enum dma_status status; 618 619 /* Get current dma rx point */ 620 if (atomic_read(&rs->state) & RXDMA) { 621 dmaengine_pause(ctlr->dma_rx); 622 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state); 623 if (status == DMA_ERROR) { 624 rs->rx = rs->xfer->rx_buf; 625 rs->xfer->len = 0; 626 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 627 for (; rx_fifo_left; rx_fifo_left--) 628 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 629 goto out; 630 } else { 631 rs->rx += rs->xfer->len - rs->n_bytes * state.residue; 632 } 633 } 634 635 /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */ 636 if (rs->rx) { 637 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 638 for (; rx_fifo_left; rx_fifo_left--) { 639 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 640 641 if (rs->n_bytes == 1) 642 *(u8 *)rs->rx = (u8)rxw; 643 else 644 *(u16 *)rs->rx = (u16)rxw; 645 rs->rx += rs->n_bytes; 646 } 647 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf); 648 } 649 650 out: 651 if (atomic_read(&rs->state) & RXDMA) 652 dmaengine_terminate_sync(ctlr->dma_rx); 653 if (atomic_read(&rs->state) & TXDMA) 654 dmaengine_terminate_sync(ctlr->dma_tx); 655 atomic_set(&rs->state, 0); 656 spi_enable_chip(rs, false); 657 rs->slave_abort = true; 658 spi_finalize_current_transfer(ctlr); 659 660 return 0; 661 } 662 663 static int rockchip_spi_transfer_one( 664 struct spi_controller *ctlr, 665 struct spi_device *spi, 666 struct spi_transfer *xfer) 667 { 668 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 669 int ret; 670 bool use_dma; 671 672 /* Zero length transfers won't trigger an interrupt on completion */ 673 if (!xfer->len) { 674 spi_finalize_current_transfer(ctlr); 675 return 1; 676 } 677 678 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && 679 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 680 681 if (!xfer->tx_buf && !xfer->rx_buf) { 682 dev_err(rs->dev, "No buffer for transfer\n"); 683 return -EINVAL; 684 } 685 686 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { 687 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); 688 return -EINVAL; 689 } 690 691 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2; 692 rs->xfer = xfer; 693 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false; 694 695 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave); 696 if (ret) 697 return ret; 698 699 if (use_dma) 700 return rockchip_spi_prepare_dma(rs, ctlr, xfer); 701 702 return rockchip_spi_prepare_irq(rs, ctlr, xfer); 703 } 704 705 static bool rockchip_spi_can_dma(struct spi_controller *ctlr, 706 struct spi_device *spi, 707 struct spi_transfer *xfer) 708 { 709 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 710 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2; 711 712 /* if the numbor of spi words to transfer is less than the fifo 713 * length we can just fill the fifo and wait for a single irq, 714 * so don't bother setting up dma 715 */ 716 return xfer->len / bytes_per_word >= rs->fifo_len; 717 } 718 719 static int rockchip_spi_setup(struct spi_device *spi) 720 { 721 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller); 722 u32 cr0; 723 724 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) { 725 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); 726 return -EINVAL; 727 } 728 729 pm_runtime_get_sync(rs->dev); 730 731 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0); 732 733 cr0 &= ~(0x3 << CR0_SCPH_OFFSET); 734 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET); 735 if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1) 736 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET; 737 else if (spi->chip_select <= 1) 738 cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET); 739 740 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 741 742 pm_runtime_put(rs->dev); 743 744 return 0; 745 } 746 747 static int rockchip_spi_probe(struct platform_device *pdev) 748 { 749 int ret; 750 struct rockchip_spi *rs; 751 struct spi_controller *ctlr; 752 struct resource *mem; 753 struct device_node *np = pdev->dev.of_node; 754 u32 rsd_nsecs, num_cs; 755 bool slave_mode; 756 757 slave_mode = of_property_read_bool(np, "spi-slave"); 758 759 if (slave_mode) 760 ctlr = spi_alloc_slave(&pdev->dev, 761 sizeof(struct rockchip_spi)); 762 else 763 ctlr = spi_alloc_master(&pdev->dev, 764 sizeof(struct rockchip_spi)); 765 766 if (!ctlr) 767 return -ENOMEM; 768 769 platform_set_drvdata(pdev, ctlr); 770 771 rs = spi_controller_get_devdata(ctlr); 772 ctlr->slave = slave_mode; 773 774 /* Get basic io resource and map it */ 775 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 776 rs->regs = devm_ioremap_resource(&pdev->dev, mem); 777 if (IS_ERR(rs->regs)) { 778 ret = PTR_ERR(rs->regs); 779 goto err_put_ctlr; 780 } 781 782 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 783 if (IS_ERR(rs->apb_pclk)) { 784 dev_err(&pdev->dev, "Failed to get apb_pclk\n"); 785 ret = PTR_ERR(rs->apb_pclk); 786 goto err_put_ctlr; 787 } 788 789 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); 790 if (IS_ERR(rs->spiclk)) { 791 dev_err(&pdev->dev, "Failed to get spi_pclk\n"); 792 ret = PTR_ERR(rs->spiclk); 793 goto err_put_ctlr; 794 } 795 796 ret = clk_prepare_enable(rs->apb_pclk); 797 if (ret < 0) { 798 dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); 799 goto err_put_ctlr; 800 } 801 802 ret = clk_prepare_enable(rs->spiclk); 803 if (ret < 0) { 804 dev_err(&pdev->dev, "Failed to enable spi_clk\n"); 805 goto err_disable_apbclk; 806 } 807 808 spi_enable_chip(rs, false); 809 810 ret = platform_get_irq(pdev, 0); 811 if (ret < 0) 812 goto err_disable_spiclk; 813 814 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL, 815 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr); 816 if (ret) 817 goto err_disable_spiclk; 818 819 rs->dev = &pdev->dev; 820 rs->freq = clk_get_rate(rs->spiclk); 821 822 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", 823 &rsd_nsecs)) { 824 /* rx sample delay is expressed in parent clock cycles (max 3) */ 825 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), 826 1000000000 >> 8); 827 if (!rsd) { 828 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n", 829 rs->freq, rsd_nsecs); 830 } else if (rsd > CR0_RSD_MAX) { 831 rsd = CR0_RSD_MAX; 832 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n", 833 rs->freq, rsd_nsecs, 834 CR0_RSD_MAX * 1000000000U / rs->freq); 835 } 836 rs->rsd = rsd; 837 } 838 839 rs->fifo_len = get_fifo_len(rs); 840 if (!rs->fifo_len) { 841 dev_err(&pdev->dev, "Failed to get fifo length\n"); 842 ret = -EINVAL; 843 goto err_disable_spiclk; 844 } 845 846 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT); 847 pm_runtime_use_autosuspend(&pdev->dev); 848 pm_runtime_set_active(&pdev->dev); 849 pm_runtime_enable(&pdev->dev); 850 851 ctlr->auto_runtime_pm = true; 852 ctlr->bus_num = pdev->id; 853 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST; 854 if (slave_mode) { 855 ctlr->mode_bits |= SPI_NO_CS; 856 ctlr->slave_abort = rockchip_spi_slave_abort; 857 } else { 858 ctlr->flags = SPI_MASTER_GPIO_SS; 859 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM; 860 /* 861 * rk spi0 has two native cs, spi1..5 one cs only 862 * if num-cs is missing in the dts, default to 1 863 */ 864 if (of_property_read_u32(np, "num-cs", &num_cs)) 865 num_cs = 1; 866 ctlr->num_chipselect = num_cs; 867 ctlr->use_gpio_descriptors = true; 868 } 869 ctlr->dev.of_node = pdev->dev.of_node; 870 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4); 871 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; 872 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); 873 874 ctlr->setup = rockchip_spi_setup; 875 ctlr->set_cs = rockchip_spi_set_cs; 876 ctlr->transfer_one = rockchip_spi_transfer_one; 877 ctlr->max_transfer_size = rockchip_spi_max_transfer_size; 878 ctlr->handle_err = rockchip_spi_handle_err; 879 880 ctlr->dma_tx = dma_request_chan(rs->dev, "tx"); 881 if (IS_ERR(ctlr->dma_tx)) { 882 /* Check tx to see if we need defer probing driver */ 883 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) { 884 ret = -EPROBE_DEFER; 885 goto err_disable_pm_runtime; 886 } 887 dev_warn(rs->dev, "Failed to request TX DMA channel\n"); 888 ctlr->dma_tx = NULL; 889 } 890 891 ctlr->dma_rx = dma_request_chan(rs->dev, "rx"); 892 if (IS_ERR(ctlr->dma_rx)) { 893 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) { 894 ret = -EPROBE_DEFER; 895 goto err_free_dma_tx; 896 } 897 dev_warn(rs->dev, "Failed to request RX DMA channel\n"); 898 ctlr->dma_rx = NULL; 899 } 900 901 if (ctlr->dma_tx && ctlr->dma_rx) { 902 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR; 903 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR; 904 ctlr->can_dma = rockchip_spi_can_dma; 905 } 906 907 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) { 908 case ROCKCHIP_SPI_VER2_TYPE2: 909 rs->cs_high_supported = true; 910 ctlr->mode_bits |= SPI_CS_HIGH; 911 if (ctlr->can_dma && slave_mode) 912 rs->cs_inactive = true; 913 else 914 rs->cs_inactive = false; 915 break; 916 default: 917 rs->cs_inactive = false; 918 break; 919 } 920 921 ret = devm_spi_register_controller(&pdev->dev, ctlr); 922 if (ret < 0) { 923 dev_err(&pdev->dev, "Failed to register controller\n"); 924 goto err_free_dma_rx; 925 } 926 927 return 0; 928 929 err_free_dma_rx: 930 if (ctlr->dma_rx) 931 dma_release_channel(ctlr->dma_rx); 932 err_free_dma_tx: 933 if (ctlr->dma_tx) 934 dma_release_channel(ctlr->dma_tx); 935 err_disable_pm_runtime: 936 pm_runtime_disable(&pdev->dev); 937 err_disable_spiclk: 938 clk_disable_unprepare(rs->spiclk); 939 err_disable_apbclk: 940 clk_disable_unprepare(rs->apb_pclk); 941 err_put_ctlr: 942 spi_controller_put(ctlr); 943 944 return ret; 945 } 946 947 static int rockchip_spi_remove(struct platform_device *pdev) 948 { 949 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev)); 950 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 951 952 pm_runtime_get_sync(&pdev->dev); 953 954 clk_disable_unprepare(rs->spiclk); 955 clk_disable_unprepare(rs->apb_pclk); 956 957 pm_runtime_put_noidle(&pdev->dev); 958 pm_runtime_disable(&pdev->dev); 959 pm_runtime_set_suspended(&pdev->dev); 960 961 if (ctlr->dma_tx) 962 dma_release_channel(ctlr->dma_tx); 963 if (ctlr->dma_rx) 964 dma_release_channel(ctlr->dma_rx); 965 966 spi_controller_put(ctlr); 967 968 return 0; 969 } 970 971 #ifdef CONFIG_PM_SLEEP 972 static int rockchip_spi_suspend(struct device *dev) 973 { 974 int ret; 975 struct spi_controller *ctlr = dev_get_drvdata(dev); 976 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 977 978 ret = spi_controller_suspend(ctlr); 979 if (ret < 0) 980 return ret; 981 982 clk_disable_unprepare(rs->spiclk); 983 clk_disable_unprepare(rs->apb_pclk); 984 985 pinctrl_pm_select_sleep_state(dev); 986 987 return 0; 988 } 989 990 static int rockchip_spi_resume(struct device *dev) 991 { 992 int ret; 993 struct spi_controller *ctlr = dev_get_drvdata(dev); 994 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 995 996 pinctrl_pm_select_default_state(dev); 997 998 ret = clk_prepare_enable(rs->apb_pclk); 999 if (ret < 0) 1000 return ret; 1001 1002 ret = clk_prepare_enable(rs->spiclk); 1003 if (ret < 0) 1004 clk_disable_unprepare(rs->apb_pclk); 1005 1006 ret = spi_controller_resume(ctlr); 1007 if (ret < 0) { 1008 clk_disable_unprepare(rs->spiclk); 1009 clk_disable_unprepare(rs->apb_pclk); 1010 } 1011 1012 return 0; 1013 } 1014 #endif /* CONFIG_PM_SLEEP */ 1015 1016 #ifdef CONFIG_PM 1017 static int rockchip_spi_runtime_suspend(struct device *dev) 1018 { 1019 struct spi_controller *ctlr = dev_get_drvdata(dev); 1020 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 1021 1022 clk_disable_unprepare(rs->spiclk); 1023 clk_disable_unprepare(rs->apb_pclk); 1024 1025 return 0; 1026 } 1027 1028 static int rockchip_spi_runtime_resume(struct device *dev) 1029 { 1030 int ret; 1031 struct spi_controller *ctlr = dev_get_drvdata(dev); 1032 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 1033 1034 ret = clk_prepare_enable(rs->apb_pclk); 1035 if (ret < 0) 1036 return ret; 1037 1038 ret = clk_prepare_enable(rs->spiclk); 1039 if (ret < 0) 1040 clk_disable_unprepare(rs->apb_pclk); 1041 1042 return 0; 1043 } 1044 #endif /* CONFIG_PM */ 1045 1046 static const struct dev_pm_ops rockchip_spi_pm = { 1047 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) 1048 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, 1049 rockchip_spi_runtime_resume, NULL) 1050 }; 1051 1052 static const struct of_device_id rockchip_spi_dt_match[] = { 1053 { .compatible = "rockchip,px30-spi", }, 1054 { .compatible = "rockchip,rk3036-spi", }, 1055 { .compatible = "rockchip,rk3066-spi", }, 1056 { .compatible = "rockchip,rk3188-spi", }, 1057 { .compatible = "rockchip,rk3228-spi", }, 1058 { .compatible = "rockchip,rk3288-spi", }, 1059 { .compatible = "rockchip,rk3308-spi", }, 1060 { .compatible = "rockchip,rk3328-spi", }, 1061 { .compatible = "rockchip,rk3368-spi", }, 1062 { .compatible = "rockchip,rk3399-spi", }, 1063 { .compatible = "rockchip,rv1108-spi", }, 1064 { .compatible = "rockchip,rv1126-spi", }, 1065 { }, 1066 }; 1067 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 1068 1069 static struct platform_driver rockchip_spi_driver = { 1070 .driver = { 1071 .name = DRIVER_NAME, 1072 .pm = &rockchip_spi_pm, 1073 .of_match_table = of_match_ptr(rockchip_spi_dt_match), 1074 }, 1075 .probe = rockchip_spi_probe, 1076 .remove = rockchip_spi_remove, 1077 }; 1078 1079 module_platform_driver(rockchip_spi_driver); 1080 1081 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 1082 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); 1083 MODULE_LICENSE("GPL v2"); 1084