1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Addy Ke <addy.ke@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/spi/spi.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/scatterlist.h> 17 18 #define DRIVER_NAME "rockchip-spi" 19 20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ 21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg) 22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ 23 writel_relaxed(readl_relaxed(reg) | (bits), reg) 24 25 /* SPI register offsets */ 26 #define ROCKCHIP_SPI_CTRLR0 0x0000 27 #define ROCKCHIP_SPI_CTRLR1 0x0004 28 #define ROCKCHIP_SPI_SSIENR 0x0008 29 #define ROCKCHIP_SPI_SER 0x000c 30 #define ROCKCHIP_SPI_BAUDR 0x0010 31 #define ROCKCHIP_SPI_TXFTLR 0x0014 32 #define ROCKCHIP_SPI_RXFTLR 0x0018 33 #define ROCKCHIP_SPI_TXFLR 0x001c 34 #define ROCKCHIP_SPI_RXFLR 0x0020 35 #define ROCKCHIP_SPI_SR 0x0024 36 #define ROCKCHIP_SPI_IPR 0x0028 37 #define ROCKCHIP_SPI_IMR 0x002c 38 #define ROCKCHIP_SPI_ISR 0x0030 39 #define ROCKCHIP_SPI_RISR 0x0034 40 #define ROCKCHIP_SPI_ICR 0x0038 41 #define ROCKCHIP_SPI_DMACR 0x003c 42 #define ROCKCHIP_SPI_DMATDLR 0x0040 43 #define ROCKCHIP_SPI_DMARDLR 0x0044 44 #define ROCKCHIP_SPI_VERSION 0x0048 45 #define ROCKCHIP_SPI_TXDR 0x0400 46 #define ROCKCHIP_SPI_RXDR 0x0800 47 48 /* Bit fields in CTRLR0 */ 49 #define CR0_DFS_OFFSET 0 50 #define CR0_DFS_4BIT 0x0 51 #define CR0_DFS_8BIT 0x1 52 #define CR0_DFS_16BIT 0x2 53 54 #define CR0_CFS_OFFSET 2 55 56 #define CR0_SCPH_OFFSET 6 57 58 #define CR0_SCPOL_OFFSET 7 59 60 #define CR0_CSM_OFFSET 8 61 #define CR0_CSM_KEEP 0x0 62 /* ss_n be high for half sclk_out cycles */ 63 #define CR0_CSM_HALF 0X1 64 /* ss_n be high for one sclk_out cycle */ 65 #define CR0_CSM_ONE 0x2 66 67 /* ss_n to sclk_out delay */ 68 #define CR0_SSD_OFFSET 10 69 /* 70 * The period between ss_n active and 71 * sclk_out active is half sclk_out cycles 72 */ 73 #define CR0_SSD_HALF 0x0 74 /* 75 * The period between ss_n active and 76 * sclk_out active is one sclk_out cycle 77 */ 78 #define CR0_SSD_ONE 0x1 79 80 #define CR0_EM_OFFSET 11 81 #define CR0_EM_LITTLE 0x0 82 #define CR0_EM_BIG 0x1 83 84 #define CR0_FBM_OFFSET 12 85 #define CR0_FBM_MSB 0x0 86 #define CR0_FBM_LSB 0x1 87 88 #define CR0_BHT_OFFSET 13 89 #define CR0_BHT_16BIT 0x0 90 #define CR0_BHT_8BIT 0x1 91 92 #define CR0_RSD_OFFSET 14 93 #define CR0_RSD_MAX 0x3 94 95 #define CR0_FRF_OFFSET 16 96 #define CR0_FRF_SPI 0x0 97 #define CR0_FRF_SSP 0x1 98 #define CR0_FRF_MICROWIRE 0x2 99 100 #define CR0_XFM_OFFSET 18 101 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) 102 #define CR0_XFM_TR 0x0 103 #define CR0_XFM_TO 0x1 104 #define CR0_XFM_RO 0x2 105 106 #define CR0_OPM_OFFSET 20 107 #define CR0_OPM_MASTER 0x0 108 #define CR0_OPM_SLAVE 0x1 109 110 #define CR0_SOI_OFFSET 23 111 112 #define CR0_MTM_OFFSET 0x21 113 114 /* Bit fields in SER, 2bit */ 115 #define SER_MASK 0x3 116 117 /* Bit fields in BAUDR */ 118 #define BAUDR_SCKDV_MIN 2 119 #define BAUDR_SCKDV_MAX 65534 120 121 /* Bit fields in SR, 6bit */ 122 #define SR_MASK 0x3f 123 #define SR_BUSY (1 << 0) 124 #define SR_TF_FULL (1 << 1) 125 #define SR_TF_EMPTY (1 << 2) 126 #define SR_RF_EMPTY (1 << 3) 127 #define SR_RF_FULL (1 << 4) 128 #define SR_SLAVE_TX_BUSY (1 << 5) 129 130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ 131 #define INT_MASK 0x1f 132 #define INT_TF_EMPTY (1 << 0) 133 #define INT_TF_OVERFLOW (1 << 1) 134 #define INT_RF_UNDERFLOW (1 << 2) 135 #define INT_RF_OVERFLOW (1 << 3) 136 #define INT_RF_FULL (1 << 4) 137 #define INT_CS_INACTIVE (1 << 6) 138 139 /* Bit fields in ICR, 4bit */ 140 #define ICR_MASK 0x0f 141 #define ICR_ALL (1 << 0) 142 #define ICR_RF_UNDERFLOW (1 << 1) 143 #define ICR_RF_OVERFLOW (1 << 2) 144 #define ICR_TF_OVERFLOW (1 << 3) 145 146 /* Bit fields in DMACR */ 147 #define RF_DMA_EN (1 << 0) 148 #define TF_DMA_EN (1 << 1) 149 150 /* Driver state flags */ 151 #define RXDMA (1 << 0) 152 #define TXDMA (1 << 1) 153 154 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ 155 #define MAX_SCLK_OUT 50000000U 156 157 /* 158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, 159 * the controller seems to hang when given 0x10000, so stick with this for now. 160 */ 161 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff 162 163 /* 2 for native cs, 2 for cs-gpio */ 164 #define ROCKCHIP_SPI_MAX_CS_NUM 4 165 #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002 166 #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002 167 168 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000 169 170 struct rockchip_spi { 171 struct device *dev; 172 173 struct clk *spiclk; 174 struct clk *apb_pclk; 175 176 void __iomem *regs; 177 dma_addr_t dma_addr_rx; 178 dma_addr_t dma_addr_tx; 179 180 const void *tx; 181 void *rx; 182 unsigned int tx_left; 183 unsigned int rx_left; 184 185 atomic_t state; 186 187 /*depth of the FIFO buffer */ 188 u32 fifo_len; 189 /* frequency of spiclk */ 190 u32 freq; 191 192 u8 n_bytes; 193 u8 rsd; 194 195 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; 196 197 bool slave_abort; 198 bool cs_inactive; /* spi slave tansmition stop when cs inactive */ 199 struct spi_transfer *xfer; /* Store xfer temporarily */ 200 }; 201 202 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) 203 { 204 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); 205 } 206 207 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode) 208 { 209 unsigned long timeout = jiffies + msecs_to_jiffies(5); 210 211 do { 212 if (slave_mode) { 213 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) && 214 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))) 215 return; 216 } else { 217 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) 218 return; 219 } 220 } while (!time_after(jiffies, timeout)); 221 222 dev_warn(rs->dev, "spi controller is in busy state!\n"); 223 } 224 225 static u32 get_fifo_len(struct rockchip_spi *rs) 226 { 227 u32 ver; 228 229 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION); 230 231 switch (ver) { 232 case ROCKCHIP_SPI_VER2_TYPE1: 233 case ROCKCHIP_SPI_VER2_TYPE2: 234 return 64; 235 default: 236 return 32; 237 } 238 } 239 240 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 241 { 242 struct spi_controller *ctlr = spi->controller; 243 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 244 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable; 245 246 /* Return immediately for no-op */ 247 if (cs_asserted == rs->cs_asserted[spi->chip_select]) 248 return; 249 250 if (cs_asserted) { 251 /* Keep things powered as long as CS is asserted */ 252 pm_runtime_get_sync(rs->dev); 253 254 if (spi->cs_gpiod) 255 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); 256 else 257 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select)); 258 } else { 259 if (spi->cs_gpiod) 260 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); 261 else 262 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select)); 263 264 /* Drop reference from when we first asserted CS */ 265 pm_runtime_put(rs->dev); 266 } 267 268 rs->cs_asserted[spi->chip_select] = cs_asserted; 269 } 270 271 static void rockchip_spi_handle_err(struct spi_controller *ctlr, 272 struct spi_message *msg) 273 { 274 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 275 276 /* stop running spi transfer 277 * this also flushes both rx and tx fifos 278 */ 279 spi_enable_chip(rs, false); 280 281 /* make sure all interrupts are masked and status cleared */ 282 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 283 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 284 285 if (atomic_read(&rs->state) & TXDMA) 286 dmaengine_terminate_async(ctlr->dma_tx); 287 288 if (atomic_read(&rs->state) & RXDMA) 289 dmaengine_terminate_async(ctlr->dma_rx); 290 } 291 292 static void rockchip_spi_pio_writer(struct rockchip_spi *rs) 293 { 294 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); 295 u32 words = min(rs->tx_left, tx_free); 296 297 rs->tx_left -= words; 298 for (; words; words--) { 299 u32 txw; 300 301 if (rs->n_bytes == 1) 302 txw = *(u8 *)rs->tx; 303 else 304 txw = *(u16 *)rs->tx; 305 306 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); 307 rs->tx += rs->n_bytes; 308 } 309 } 310 311 static void rockchip_spi_pio_reader(struct rockchip_spi *rs) 312 { 313 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 314 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0; 315 316 /* the hardware doesn't allow us to change fifo threshold 317 * level while spi is enabled, so instead make sure to leave 318 * enough words in the rx fifo to get the last interrupt 319 * exactly when all words have been received 320 */ 321 if (rx_left) { 322 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1; 323 324 if (rx_left < ftl) { 325 rx_left = ftl; 326 words = rs->rx_left - rx_left; 327 } 328 } 329 330 rs->rx_left = rx_left; 331 for (; words; words--) { 332 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 333 334 if (!rs->rx) 335 continue; 336 337 if (rs->n_bytes == 1) 338 *(u8 *)rs->rx = (u8)rxw; 339 else 340 *(u16 *)rs->rx = (u16)rxw; 341 rs->rx += rs->n_bytes; 342 } 343 } 344 345 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) 346 { 347 struct spi_controller *ctlr = dev_id; 348 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 349 350 /* When int_cs_inactive comes, spi slave abort */ 351 if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) { 352 ctlr->slave_abort(ctlr); 353 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 354 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 355 356 return IRQ_HANDLED; 357 } 358 359 if (rs->tx_left) 360 rockchip_spi_pio_writer(rs); 361 362 rockchip_spi_pio_reader(rs); 363 if (!rs->rx_left) { 364 spi_enable_chip(rs, false); 365 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 366 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 367 spi_finalize_current_transfer(ctlr); 368 } 369 370 return IRQ_HANDLED; 371 } 372 373 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, 374 struct spi_controller *ctlr, 375 struct spi_transfer *xfer) 376 { 377 rs->tx = xfer->tx_buf; 378 rs->rx = xfer->rx_buf; 379 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0; 380 rs->rx_left = xfer->len / rs->n_bytes; 381 382 if (rs->cs_inactive) 383 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR); 384 else 385 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR); 386 spi_enable_chip(rs, true); 387 388 if (rs->tx_left) 389 rockchip_spi_pio_writer(rs); 390 391 /* 1 means the transfer is in progress */ 392 return 1; 393 } 394 395 static void rockchip_spi_dma_rxcb(void *data) 396 { 397 struct spi_controller *ctlr = data; 398 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 399 int state = atomic_fetch_andnot(RXDMA, &rs->state); 400 401 if (state & TXDMA && !rs->slave_abort) 402 return; 403 404 if (rs->cs_inactive) 405 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 406 407 spi_enable_chip(rs, false); 408 spi_finalize_current_transfer(ctlr); 409 } 410 411 static void rockchip_spi_dma_txcb(void *data) 412 { 413 struct spi_controller *ctlr = data; 414 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 415 int state = atomic_fetch_andnot(TXDMA, &rs->state); 416 417 if (state & RXDMA && !rs->slave_abort) 418 return; 419 420 /* Wait until the FIFO data completely. */ 421 wait_for_tx_idle(rs, ctlr->slave); 422 423 spi_enable_chip(rs, false); 424 spi_finalize_current_transfer(ctlr); 425 } 426 427 static u32 rockchip_spi_calc_burst_size(u32 data_len) 428 { 429 u32 i; 430 431 /* burst size: 1, 2, 4, 8 */ 432 for (i = 1; i < 8; i <<= 1) { 433 if (data_len & i) 434 break; 435 } 436 437 return i; 438 } 439 440 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, 441 struct spi_controller *ctlr, struct spi_transfer *xfer) 442 { 443 struct dma_async_tx_descriptor *rxdesc, *txdesc; 444 445 atomic_set(&rs->state, 0); 446 447 rs->tx = xfer->tx_buf; 448 rs->rx = xfer->rx_buf; 449 450 rxdesc = NULL; 451 if (xfer->rx_buf) { 452 struct dma_slave_config rxconf = { 453 .direction = DMA_DEV_TO_MEM, 454 .src_addr = rs->dma_addr_rx, 455 .src_addr_width = rs->n_bytes, 456 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes), 457 }; 458 459 dmaengine_slave_config(ctlr->dma_rx, &rxconf); 460 461 rxdesc = dmaengine_prep_slave_sg( 462 ctlr->dma_rx, 463 xfer->rx_sg.sgl, xfer->rx_sg.nents, 464 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 465 if (!rxdesc) 466 return -EINVAL; 467 468 rxdesc->callback = rockchip_spi_dma_rxcb; 469 rxdesc->callback_param = ctlr; 470 } 471 472 txdesc = NULL; 473 if (xfer->tx_buf) { 474 struct dma_slave_config txconf = { 475 .direction = DMA_MEM_TO_DEV, 476 .dst_addr = rs->dma_addr_tx, 477 .dst_addr_width = rs->n_bytes, 478 .dst_maxburst = rs->fifo_len / 4, 479 }; 480 481 dmaengine_slave_config(ctlr->dma_tx, &txconf); 482 483 txdesc = dmaengine_prep_slave_sg( 484 ctlr->dma_tx, 485 xfer->tx_sg.sgl, xfer->tx_sg.nents, 486 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 487 if (!txdesc) { 488 if (rxdesc) 489 dmaengine_terminate_sync(ctlr->dma_rx); 490 return -EINVAL; 491 } 492 493 txdesc->callback = rockchip_spi_dma_txcb; 494 txdesc->callback_param = ctlr; 495 } 496 497 /* rx must be started before tx due to spi instinct */ 498 if (rxdesc) { 499 atomic_or(RXDMA, &rs->state); 500 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc); 501 dma_async_issue_pending(ctlr->dma_rx); 502 } 503 504 if (rs->cs_inactive) 505 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR); 506 507 spi_enable_chip(rs, true); 508 509 if (txdesc) { 510 atomic_or(TXDMA, &rs->state); 511 dmaengine_submit(txdesc); 512 dma_async_issue_pending(ctlr->dma_tx); 513 } 514 515 /* 1 means the transfer is in progress */ 516 return 1; 517 } 518 519 static int rockchip_spi_config(struct rockchip_spi *rs, 520 struct spi_device *spi, struct spi_transfer *xfer, 521 bool use_dma, bool slave_mode) 522 { 523 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET 524 | CR0_BHT_8BIT << CR0_BHT_OFFSET 525 | CR0_SSD_ONE << CR0_SSD_OFFSET 526 | CR0_EM_BIG << CR0_EM_OFFSET; 527 u32 cr1; 528 u32 dmacr = 0; 529 530 if (slave_mode) 531 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET; 532 rs->slave_abort = false; 533 534 cr0 |= rs->rsd << CR0_RSD_OFFSET; 535 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; 536 if (spi->mode & SPI_LSB_FIRST) 537 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; 538 if (spi->mode & SPI_CS_HIGH) 539 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET; 540 541 if (xfer->rx_buf && xfer->tx_buf) 542 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; 543 else if (xfer->rx_buf) 544 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; 545 else if (use_dma) 546 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; 547 548 switch (xfer->bits_per_word) { 549 case 4: 550 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; 551 cr1 = xfer->len - 1; 552 break; 553 case 8: 554 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; 555 cr1 = xfer->len - 1; 556 break; 557 case 16: 558 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; 559 cr1 = xfer->len / 2 - 1; 560 break; 561 default: 562 /* we only whitelist 4, 8 and 16 bit words in 563 * ctlr->bits_per_word_mask, so this shouldn't 564 * happen 565 */ 566 dev_err(rs->dev, "unknown bits per word: %d\n", 567 xfer->bits_per_word); 568 return -EINVAL; 569 } 570 571 if (use_dma) { 572 if (xfer->tx_buf) 573 dmacr |= TF_DMA_EN; 574 if (xfer->rx_buf) 575 dmacr |= RF_DMA_EN; 576 } 577 578 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 579 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); 580 581 /* unfortunately setting the fifo threshold level to generate an 582 * interrupt exactly when the fifo is full doesn't seem to work, 583 * so we need the strict inequality here 584 */ 585 if ((xfer->len / rs->n_bytes) < rs->fifo_len) 586 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 587 else 588 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 589 590 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR); 591 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1, 592 rs->regs + ROCKCHIP_SPI_DMARDLR); 593 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); 594 595 /* the hardware only supports an even clock divisor, so 596 * round divisor = spiclk / speed up to nearest even number 597 * so that the resulting speed is <= the requested speed 598 */ 599 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz), 600 rs->regs + ROCKCHIP_SPI_BAUDR); 601 602 return 0; 603 } 604 605 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) 606 { 607 return ROCKCHIP_SPI_MAX_TRANLEN; 608 } 609 610 static int rockchip_spi_slave_abort(struct spi_controller *ctlr) 611 { 612 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 613 u32 rx_fifo_left; 614 struct dma_tx_state state; 615 enum dma_status status; 616 617 /* Get current dma rx point */ 618 if (atomic_read(&rs->state) & RXDMA) { 619 dmaengine_pause(ctlr->dma_rx); 620 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state); 621 if (status == DMA_ERROR) { 622 rs->rx = rs->xfer->rx_buf; 623 rs->xfer->len = 0; 624 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 625 for (; rx_fifo_left; rx_fifo_left--) 626 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 627 goto out; 628 } else { 629 rs->rx += rs->xfer->len - rs->n_bytes * state.residue; 630 } 631 } 632 633 /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */ 634 if (rs->rx) { 635 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 636 for (; rx_fifo_left; rx_fifo_left--) { 637 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 638 639 if (rs->n_bytes == 1) 640 *(u8 *)rs->rx = (u8)rxw; 641 else 642 *(u16 *)rs->rx = (u16)rxw; 643 rs->rx += rs->n_bytes; 644 } 645 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf); 646 } 647 648 out: 649 if (atomic_read(&rs->state) & RXDMA) 650 dmaengine_terminate_sync(ctlr->dma_rx); 651 if (atomic_read(&rs->state) & TXDMA) 652 dmaengine_terminate_sync(ctlr->dma_tx); 653 atomic_set(&rs->state, 0); 654 spi_enable_chip(rs, false); 655 rs->slave_abort = true; 656 spi_finalize_current_transfer(ctlr); 657 658 return 0; 659 } 660 661 static int rockchip_spi_transfer_one( 662 struct spi_controller *ctlr, 663 struct spi_device *spi, 664 struct spi_transfer *xfer) 665 { 666 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 667 int ret; 668 bool use_dma; 669 670 /* Zero length transfers won't trigger an interrupt on completion */ 671 if (!xfer->len) { 672 spi_finalize_current_transfer(ctlr); 673 return 1; 674 } 675 676 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && 677 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 678 679 if (!xfer->tx_buf && !xfer->rx_buf) { 680 dev_err(rs->dev, "No buffer for transfer\n"); 681 return -EINVAL; 682 } 683 684 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { 685 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); 686 return -EINVAL; 687 } 688 689 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2; 690 rs->xfer = xfer; 691 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false; 692 693 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave); 694 if (ret) 695 return ret; 696 697 if (use_dma) 698 return rockchip_spi_prepare_dma(rs, ctlr, xfer); 699 700 return rockchip_spi_prepare_irq(rs, ctlr, xfer); 701 } 702 703 static bool rockchip_spi_can_dma(struct spi_controller *ctlr, 704 struct spi_device *spi, 705 struct spi_transfer *xfer) 706 { 707 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 708 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2; 709 710 /* if the numbor of spi words to transfer is less than the fifo 711 * length we can just fill the fifo and wait for a single irq, 712 * so don't bother setting up dma 713 */ 714 return xfer->len / bytes_per_word >= rs->fifo_len; 715 } 716 717 static int rockchip_spi_setup(struct spi_device *spi) 718 { 719 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller); 720 u32 cr0; 721 722 pm_runtime_get_sync(rs->dev); 723 724 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0); 725 726 cr0 &= ~(0x3 << CR0_SCPH_OFFSET); 727 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET); 728 if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1) 729 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET; 730 else if (spi->chip_select <= 1) 731 cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET); 732 733 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 734 735 pm_runtime_put(rs->dev); 736 737 return 0; 738 } 739 740 static int rockchip_spi_probe(struct platform_device *pdev) 741 { 742 int ret; 743 struct rockchip_spi *rs; 744 struct spi_controller *ctlr; 745 struct resource *mem; 746 struct device_node *np = pdev->dev.of_node; 747 u32 rsd_nsecs, num_cs; 748 bool slave_mode; 749 750 slave_mode = of_property_read_bool(np, "spi-slave"); 751 752 if (slave_mode) 753 ctlr = spi_alloc_slave(&pdev->dev, 754 sizeof(struct rockchip_spi)); 755 else 756 ctlr = spi_alloc_master(&pdev->dev, 757 sizeof(struct rockchip_spi)); 758 759 if (!ctlr) 760 return -ENOMEM; 761 762 platform_set_drvdata(pdev, ctlr); 763 764 rs = spi_controller_get_devdata(ctlr); 765 ctlr->slave = slave_mode; 766 767 /* Get basic io resource and map it */ 768 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 769 rs->regs = devm_ioremap_resource(&pdev->dev, mem); 770 if (IS_ERR(rs->regs)) { 771 ret = PTR_ERR(rs->regs); 772 goto err_put_ctlr; 773 } 774 775 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 776 if (IS_ERR(rs->apb_pclk)) { 777 dev_err(&pdev->dev, "Failed to get apb_pclk\n"); 778 ret = PTR_ERR(rs->apb_pclk); 779 goto err_put_ctlr; 780 } 781 782 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); 783 if (IS_ERR(rs->spiclk)) { 784 dev_err(&pdev->dev, "Failed to get spi_pclk\n"); 785 ret = PTR_ERR(rs->spiclk); 786 goto err_put_ctlr; 787 } 788 789 ret = clk_prepare_enable(rs->apb_pclk); 790 if (ret < 0) { 791 dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); 792 goto err_put_ctlr; 793 } 794 795 ret = clk_prepare_enable(rs->spiclk); 796 if (ret < 0) { 797 dev_err(&pdev->dev, "Failed to enable spi_clk\n"); 798 goto err_disable_apbclk; 799 } 800 801 spi_enable_chip(rs, false); 802 803 ret = platform_get_irq(pdev, 0); 804 if (ret < 0) 805 goto err_disable_spiclk; 806 807 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL, 808 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr); 809 if (ret) 810 goto err_disable_spiclk; 811 812 rs->dev = &pdev->dev; 813 rs->freq = clk_get_rate(rs->spiclk); 814 815 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", 816 &rsd_nsecs)) { 817 /* rx sample delay is expressed in parent clock cycles (max 3) */ 818 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), 819 1000000000 >> 8); 820 if (!rsd) { 821 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n", 822 rs->freq, rsd_nsecs); 823 } else if (rsd > CR0_RSD_MAX) { 824 rsd = CR0_RSD_MAX; 825 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n", 826 rs->freq, rsd_nsecs, 827 CR0_RSD_MAX * 1000000000U / rs->freq); 828 } 829 rs->rsd = rsd; 830 } 831 832 rs->fifo_len = get_fifo_len(rs); 833 if (!rs->fifo_len) { 834 dev_err(&pdev->dev, "Failed to get fifo length\n"); 835 ret = -EINVAL; 836 goto err_disable_spiclk; 837 } 838 839 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT); 840 pm_runtime_use_autosuspend(&pdev->dev); 841 pm_runtime_set_active(&pdev->dev); 842 pm_runtime_enable(&pdev->dev); 843 844 ctlr->auto_runtime_pm = true; 845 ctlr->bus_num = pdev->id; 846 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST; 847 if (slave_mode) { 848 ctlr->mode_bits |= SPI_NO_CS; 849 ctlr->slave_abort = rockchip_spi_slave_abort; 850 } else { 851 ctlr->flags = SPI_MASTER_GPIO_SS; 852 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM; 853 /* 854 * rk spi0 has two native cs, spi1..5 one cs only 855 * if num-cs is missing in the dts, default to 1 856 */ 857 if (of_property_read_u32(np, "num-cs", &num_cs)) 858 num_cs = 1; 859 ctlr->num_chipselect = num_cs; 860 ctlr->use_gpio_descriptors = true; 861 } 862 ctlr->dev.of_node = pdev->dev.of_node; 863 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4); 864 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; 865 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); 866 867 ctlr->setup = rockchip_spi_setup; 868 ctlr->set_cs = rockchip_spi_set_cs; 869 ctlr->transfer_one = rockchip_spi_transfer_one; 870 ctlr->max_transfer_size = rockchip_spi_max_transfer_size; 871 ctlr->handle_err = rockchip_spi_handle_err; 872 873 ctlr->dma_tx = dma_request_chan(rs->dev, "tx"); 874 if (IS_ERR(ctlr->dma_tx)) { 875 /* Check tx to see if we need defer probing driver */ 876 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) { 877 ret = -EPROBE_DEFER; 878 goto err_disable_pm_runtime; 879 } 880 dev_warn(rs->dev, "Failed to request TX DMA channel\n"); 881 ctlr->dma_tx = NULL; 882 } 883 884 ctlr->dma_rx = dma_request_chan(rs->dev, "rx"); 885 if (IS_ERR(ctlr->dma_rx)) { 886 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) { 887 ret = -EPROBE_DEFER; 888 goto err_free_dma_tx; 889 } 890 dev_warn(rs->dev, "Failed to request RX DMA channel\n"); 891 ctlr->dma_rx = NULL; 892 } 893 894 if (ctlr->dma_tx && ctlr->dma_rx) { 895 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR; 896 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR; 897 ctlr->can_dma = rockchip_spi_can_dma; 898 } 899 900 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) { 901 case ROCKCHIP_SPI_VER2_TYPE2: 902 ctlr->mode_bits |= SPI_CS_HIGH; 903 if (ctlr->can_dma && slave_mode) 904 rs->cs_inactive = true; 905 else 906 rs->cs_inactive = false; 907 break; 908 default: 909 rs->cs_inactive = false; 910 break; 911 } 912 913 ret = devm_spi_register_controller(&pdev->dev, ctlr); 914 if (ret < 0) { 915 dev_err(&pdev->dev, "Failed to register controller\n"); 916 goto err_free_dma_rx; 917 } 918 919 return 0; 920 921 err_free_dma_rx: 922 if (ctlr->dma_rx) 923 dma_release_channel(ctlr->dma_rx); 924 err_free_dma_tx: 925 if (ctlr->dma_tx) 926 dma_release_channel(ctlr->dma_tx); 927 err_disable_pm_runtime: 928 pm_runtime_disable(&pdev->dev); 929 err_disable_spiclk: 930 clk_disable_unprepare(rs->spiclk); 931 err_disable_apbclk: 932 clk_disable_unprepare(rs->apb_pclk); 933 err_put_ctlr: 934 spi_controller_put(ctlr); 935 936 return ret; 937 } 938 939 static int rockchip_spi_remove(struct platform_device *pdev) 940 { 941 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev)); 942 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 943 944 pm_runtime_get_sync(&pdev->dev); 945 946 clk_disable_unprepare(rs->spiclk); 947 clk_disable_unprepare(rs->apb_pclk); 948 949 pm_runtime_put_noidle(&pdev->dev); 950 pm_runtime_disable(&pdev->dev); 951 pm_runtime_set_suspended(&pdev->dev); 952 953 if (ctlr->dma_tx) 954 dma_release_channel(ctlr->dma_tx); 955 if (ctlr->dma_rx) 956 dma_release_channel(ctlr->dma_rx); 957 958 spi_controller_put(ctlr); 959 960 return 0; 961 } 962 963 #ifdef CONFIG_PM_SLEEP 964 static int rockchip_spi_suspend(struct device *dev) 965 { 966 int ret; 967 struct spi_controller *ctlr = dev_get_drvdata(dev); 968 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 969 970 ret = spi_controller_suspend(ctlr); 971 if (ret < 0) 972 return ret; 973 974 clk_disable_unprepare(rs->spiclk); 975 clk_disable_unprepare(rs->apb_pclk); 976 977 pinctrl_pm_select_sleep_state(dev); 978 979 return 0; 980 } 981 982 static int rockchip_spi_resume(struct device *dev) 983 { 984 int ret; 985 struct spi_controller *ctlr = dev_get_drvdata(dev); 986 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 987 988 pinctrl_pm_select_default_state(dev); 989 990 ret = clk_prepare_enable(rs->apb_pclk); 991 if (ret < 0) 992 return ret; 993 994 ret = clk_prepare_enable(rs->spiclk); 995 if (ret < 0) 996 clk_disable_unprepare(rs->apb_pclk); 997 998 ret = spi_controller_resume(ctlr); 999 if (ret < 0) { 1000 clk_disable_unprepare(rs->spiclk); 1001 clk_disable_unprepare(rs->apb_pclk); 1002 } 1003 1004 return 0; 1005 } 1006 #endif /* CONFIG_PM_SLEEP */ 1007 1008 #ifdef CONFIG_PM 1009 static int rockchip_spi_runtime_suspend(struct device *dev) 1010 { 1011 struct spi_controller *ctlr = dev_get_drvdata(dev); 1012 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 1013 1014 clk_disable_unprepare(rs->spiclk); 1015 clk_disable_unprepare(rs->apb_pclk); 1016 1017 return 0; 1018 } 1019 1020 static int rockchip_spi_runtime_resume(struct device *dev) 1021 { 1022 int ret; 1023 struct spi_controller *ctlr = dev_get_drvdata(dev); 1024 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 1025 1026 ret = clk_prepare_enable(rs->apb_pclk); 1027 if (ret < 0) 1028 return ret; 1029 1030 ret = clk_prepare_enable(rs->spiclk); 1031 if (ret < 0) 1032 clk_disable_unprepare(rs->apb_pclk); 1033 1034 return 0; 1035 } 1036 #endif /* CONFIG_PM */ 1037 1038 static const struct dev_pm_ops rockchip_spi_pm = { 1039 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) 1040 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, 1041 rockchip_spi_runtime_resume, NULL) 1042 }; 1043 1044 static const struct of_device_id rockchip_spi_dt_match[] = { 1045 { .compatible = "rockchip,px30-spi", }, 1046 { .compatible = "rockchip,rk3036-spi", }, 1047 { .compatible = "rockchip,rk3066-spi", }, 1048 { .compatible = "rockchip,rk3188-spi", }, 1049 { .compatible = "rockchip,rk3228-spi", }, 1050 { .compatible = "rockchip,rk3288-spi", }, 1051 { .compatible = "rockchip,rk3308-spi", }, 1052 { .compatible = "rockchip,rk3328-spi", }, 1053 { .compatible = "rockchip,rk3368-spi", }, 1054 { .compatible = "rockchip,rk3399-spi", }, 1055 { .compatible = "rockchip,rv1108-spi", }, 1056 { .compatible = "rockchip,rv1126-spi", }, 1057 { }, 1058 }; 1059 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 1060 1061 static struct platform_driver rockchip_spi_driver = { 1062 .driver = { 1063 .name = DRIVER_NAME, 1064 .pm = &rockchip_spi_pm, 1065 .of_match_table = of_match_ptr(rockchip_spi_dt_match), 1066 }, 1067 .probe = rockchip_spi_probe, 1068 .remove = rockchip_spi_remove, 1069 }; 1070 1071 module_platform_driver(rockchip_spi_driver); 1072 1073 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 1074 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); 1075 MODULE_LICENSE("GPL v2"); 1076