1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Addy Ke <addy.ke@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/spi/spi.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/scatterlist.h> 17 18 #define DRIVER_NAME "rockchip-spi" 19 20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ 21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg) 22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ 23 writel_relaxed(readl_relaxed(reg) | (bits), reg) 24 25 /* SPI register offsets */ 26 #define ROCKCHIP_SPI_CTRLR0 0x0000 27 #define ROCKCHIP_SPI_CTRLR1 0x0004 28 #define ROCKCHIP_SPI_SSIENR 0x0008 29 #define ROCKCHIP_SPI_SER 0x000c 30 #define ROCKCHIP_SPI_BAUDR 0x0010 31 #define ROCKCHIP_SPI_TXFTLR 0x0014 32 #define ROCKCHIP_SPI_RXFTLR 0x0018 33 #define ROCKCHIP_SPI_TXFLR 0x001c 34 #define ROCKCHIP_SPI_RXFLR 0x0020 35 #define ROCKCHIP_SPI_SR 0x0024 36 #define ROCKCHIP_SPI_IPR 0x0028 37 #define ROCKCHIP_SPI_IMR 0x002c 38 #define ROCKCHIP_SPI_ISR 0x0030 39 #define ROCKCHIP_SPI_RISR 0x0034 40 #define ROCKCHIP_SPI_ICR 0x0038 41 #define ROCKCHIP_SPI_DMACR 0x003c 42 #define ROCKCHIP_SPI_DMATDLR 0x0040 43 #define ROCKCHIP_SPI_DMARDLR 0x0044 44 #define ROCKCHIP_SPI_TXDR 0x0400 45 #define ROCKCHIP_SPI_RXDR 0x0800 46 47 /* Bit fields in CTRLR0 */ 48 #define CR0_DFS_OFFSET 0 49 #define CR0_DFS_4BIT 0x0 50 #define CR0_DFS_8BIT 0x1 51 #define CR0_DFS_16BIT 0x2 52 53 #define CR0_CFS_OFFSET 2 54 55 #define CR0_SCPH_OFFSET 6 56 57 #define CR0_SCPOL_OFFSET 7 58 59 #define CR0_CSM_OFFSET 8 60 #define CR0_CSM_KEEP 0x0 61 /* ss_n be high for half sclk_out cycles */ 62 #define CR0_CSM_HALF 0X1 63 /* ss_n be high for one sclk_out cycle */ 64 #define CR0_CSM_ONE 0x2 65 66 /* ss_n to sclk_out delay */ 67 #define CR0_SSD_OFFSET 10 68 /* 69 * The period between ss_n active and 70 * sclk_out active is half sclk_out cycles 71 */ 72 #define CR0_SSD_HALF 0x0 73 /* 74 * The period between ss_n active and 75 * sclk_out active is one sclk_out cycle 76 */ 77 #define CR0_SSD_ONE 0x1 78 79 #define CR0_EM_OFFSET 11 80 #define CR0_EM_LITTLE 0x0 81 #define CR0_EM_BIG 0x1 82 83 #define CR0_FBM_OFFSET 12 84 #define CR0_FBM_MSB 0x0 85 #define CR0_FBM_LSB 0x1 86 87 #define CR0_BHT_OFFSET 13 88 #define CR0_BHT_16BIT 0x0 89 #define CR0_BHT_8BIT 0x1 90 91 #define CR0_RSD_OFFSET 14 92 #define CR0_RSD_MAX 0x3 93 94 #define CR0_FRF_OFFSET 16 95 #define CR0_FRF_SPI 0x0 96 #define CR0_FRF_SSP 0x1 97 #define CR0_FRF_MICROWIRE 0x2 98 99 #define CR0_XFM_OFFSET 18 100 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) 101 #define CR0_XFM_TR 0x0 102 #define CR0_XFM_TO 0x1 103 #define CR0_XFM_RO 0x2 104 105 #define CR0_OPM_OFFSET 20 106 #define CR0_OPM_MASTER 0x0 107 #define CR0_OPM_SLAVE 0x1 108 109 #define CR0_MTM_OFFSET 0x21 110 111 /* Bit fields in SER, 2bit */ 112 #define SER_MASK 0x3 113 114 /* Bit fields in BAUDR */ 115 #define BAUDR_SCKDV_MIN 2 116 #define BAUDR_SCKDV_MAX 65534 117 118 /* Bit fields in SR, 5bit */ 119 #define SR_MASK 0x1f 120 #define SR_BUSY (1 << 0) 121 #define SR_TF_FULL (1 << 1) 122 #define SR_TF_EMPTY (1 << 2) 123 #define SR_RF_EMPTY (1 << 3) 124 #define SR_RF_FULL (1 << 4) 125 126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ 127 #define INT_MASK 0x1f 128 #define INT_TF_EMPTY (1 << 0) 129 #define INT_TF_OVERFLOW (1 << 1) 130 #define INT_RF_UNDERFLOW (1 << 2) 131 #define INT_RF_OVERFLOW (1 << 3) 132 #define INT_RF_FULL (1 << 4) 133 134 /* Bit fields in ICR, 4bit */ 135 #define ICR_MASK 0x0f 136 #define ICR_ALL (1 << 0) 137 #define ICR_RF_UNDERFLOW (1 << 1) 138 #define ICR_RF_OVERFLOW (1 << 2) 139 #define ICR_TF_OVERFLOW (1 << 3) 140 141 /* Bit fields in DMACR */ 142 #define RF_DMA_EN (1 << 0) 143 #define TF_DMA_EN (1 << 1) 144 145 /* Driver state flags */ 146 #define RXDMA (1 << 0) 147 #define TXDMA (1 << 1) 148 149 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ 150 #define MAX_SCLK_OUT 50000000U 151 152 /* 153 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, 154 * the controller seems to hang when given 0x10000, so stick with this for now. 155 */ 156 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff 157 158 #define ROCKCHIP_SPI_MAX_CS_NUM 2 159 160 struct rockchip_spi { 161 struct device *dev; 162 163 struct clk *spiclk; 164 struct clk *apb_pclk; 165 166 void __iomem *regs; 167 dma_addr_t dma_addr_rx; 168 dma_addr_t dma_addr_tx; 169 170 const void *tx; 171 void *rx; 172 unsigned int tx_left; 173 unsigned int rx_left; 174 175 atomic_t state; 176 177 /*depth of the FIFO buffer */ 178 u32 fifo_len; 179 /* frequency of spiclk */ 180 u32 freq; 181 182 u8 n_bytes; 183 u8 rsd; 184 185 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; 186 187 bool slave_abort; 188 }; 189 190 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) 191 { 192 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); 193 } 194 195 static inline void wait_for_idle(struct rockchip_spi *rs) 196 { 197 unsigned long timeout = jiffies + msecs_to_jiffies(5); 198 199 do { 200 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) 201 return; 202 } while (!time_after(jiffies, timeout)); 203 204 dev_warn(rs->dev, "spi controller is in busy state!\n"); 205 } 206 207 static u32 get_fifo_len(struct rockchip_spi *rs) 208 { 209 u32 fifo; 210 211 for (fifo = 2; fifo < 32; fifo++) { 212 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); 213 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) 214 break; 215 } 216 217 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); 218 219 return (fifo == 31) ? 0 : fifo; 220 } 221 222 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 223 { 224 struct spi_controller *ctlr = spi->controller; 225 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 226 bool cs_asserted = !enable; 227 228 /* Return immediately for no-op */ 229 if (cs_asserted == rs->cs_asserted[spi->chip_select]) 230 return; 231 232 if (cs_asserted) { 233 /* Keep things powered as long as CS is asserted */ 234 pm_runtime_get_sync(rs->dev); 235 236 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 237 BIT(spi->chip_select)); 238 } else { 239 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 240 BIT(spi->chip_select)); 241 242 /* Drop reference from when we first asserted CS */ 243 pm_runtime_put(rs->dev); 244 } 245 246 rs->cs_asserted[spi->chip_select] = cs_asserted; 247 } 248 249 static void rockchip_spi_handle_err(struct spi_controller *ctlr, 250 struct spi_message *msg) 251 { 252 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 253 254 /* stop running spi transfer 255 * this also flushes both rx and tx fifos 256 */ 257 spi_enable_chip(rs, false); 258 259 /* make sure all interrupts are masked */ 260 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 261 262 if (atomic_read(&rs->state) & TXDMA) 263 dmaengine_terminate_async(ctlr->dma_tx); 264 265 if (atomic_read(&rs->state) & RXDMA) 266 dmaengine_terminate_async(ctlr->dma_rx); 267 } 268 269 static void rockchip_spi_pio_writer(struct rockchip_spi *rs) 270 { 271 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); 272 u32 words = min(rs->tx_left, tx_free); 273 274 rs->tx_left -= words; 275 for (; words; words--) { 276 u32 txw; 277 278 if (rs->n_bytes == 1) 279 txw = *(u8 *)rs->tx; 280 else 281 txw = *(u16 *)rs->tx; 282 283 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); 284 rs->tx += rs->n_bytes; 285 } 286 } 287 288 static void rockchip_spi_pio_reader(struct rockchip_spi *rs) 289 { 290 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 291 u32 rx_left = rs->rx_left - words; 292 293 /* the hardware doesn't allow us to change fifo threshold 294 * level while spi is enabled, so instead make sure to leave 295 * enough words in the rx fifo to get the last interrupt 296 * exactly when all words have been received 297 */ 298 if (rx_left) { 299 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1; 300 301 if (rx_left < ftl) { 302 rx_left = ftl; 303 words = rs->rx_left - rx_left; 304 } 305 } 306 307 rs->rx_left = rx_left; 308 for (; words; words--) { 309 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 310 311 if (!rs->rx) 312 continue; 313 314 if (rs->n_bytes == 1) 315 *(u8 *)rs->rx = (u8)rxw; 316 else 317 *(u16 *)rs->rx = (u16)rxw; 318 rs->rx += rs->n_bytes; 319 } 320 } 321 322 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) 323 { 324 struct spi_controller *ctlr = dev_id; 325 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 326 327 if (rs->tx_left) 328 rockchip_spi_pio_writer(rs); 329 330 rockchip_spi_pio_reader(rs); 331 if (!rs->rx_left) { 332 spi_enable_chip(rs, false); 333 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 334 spi_finalize_current_transfer(ctlr); 335 } 336 337 return IRQ_HANDLED; 338 } 339 340 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, 341 struct spi_transfer *xfer) 342 { 343 rs->tx = xfer->tx_buf; 344 rs->rx = xfer->rx_buf; 345 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0; 346 rs->rx_left = xfer->len / rs->n_bytes; 347 348 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR); 349 spi_enable_chip(rs, true); 350 351 if (rs->tx_left) 352 rockchip_spi_pio_writer(rs); 353 354 /* 1 means the transfer is in progress */ 355 return 1; 356 } 357 358 static void rockchip_spi_dma_rxcb(void *data) 359 { 360 struct spi_controller *ctlr = data; 361 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 362 int state = atomic_fetch_andnot(RXDMA, &rs->state); 363 364 if (state & TXDMA && !rs->slave_abort) 365 return; 366 367 spi_enable_chip(rs, false); 368 spi_finalize_current_transfer(ctlr); 369 } 370 371 static void rockchip_spi_dma_txcb(void *data) 372 { 373 struct spi_controller *ctlr = data; 374 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 375 int state = atomic_fetch_andnot(TXDMA, &rs->state); 376 377 if (state & RXDMA && !rs->slave_abort) 378 return; 379 380 /* Wait until the FIFO data completely. */ 381 wait_for_idle(rs); 382 383 spi_enable_chip(rs, false); 384 spi_finalize_current_transfer(ctlr); 385 } 386 387 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, 388 struct spi_controller *ctlr, struct spi_transfer *xfer) 389 { 390 struct dma_async_tx_descriptor *rxdesc, *txdesc; 391 392 atomic_set(&rs->state, 0); 393 394 rxdesc = NULL; 395 if (xfer->rx_buf) { 396 struct dma_slave_config rxconf = { 397 .direction = DMA_DEV_TO_MEM, 398 .src_addr = rs->dma_addr_rx, 399 .src_addr_width = rs->n_bytes, 400 .src_maxburst = 1, 401 }; 402 403 dmaengine_slave_config(ctlr->dma_rx, &rxconf); 404 405 rxdesc = dmaengine_prep_slave_sg( 406 ctlr->dma_rx, 407 xfer->rx_sg.sgl, xfer->rx_sg.nents, 408 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 409 if (!rxdesc) 410 return -EINVAL; 411 412 rxdesc->callback = rockchip_spi_dma_rxcb; 413 rxdesc->callback_param = ctlr; 414 } 415 416 txdesc = NULL; 417 if (xfer->tx_buf) { 418 struct dma_slave_config txconf = { 419 .direction = DMA_MEM_TO_DEV, 420 .dst_addr = rs->dma_addr_tx, 421 .dst_addr_width = rs->n_bytes, 422 .dst_maxburst = rs->fifo_len / 4, 423 }; 424 425 dmaengine_slave_config(ctlr->dma_tx, &txconf); 426 427 txdesc = dmaengine_prep_slave_sg( 428 ctlr->dma_tx, 429 xfer->tx_sg.sgl, xfer->tx_sg.nents, 430 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 431 if (!txdesc) { 432 if (rxdesc) 433 dmaengine_terminate_sync(ctlr->dma_rx); 434 return -EINVAL; 435 } 436 437 txdesc->callback = rockchip_spi_dma_txcb; 438 txdesc->callback_param = ctlr; 439 } 440 441 /* rx must be started before tx due to spi instinct */ 442 if (rxdesc) { 443 atomic_or(RXDMA, &rs->state); 444 dmaengine_submit(rxdesc); 445 dma_async_issue_pending(ctlr->dma_rx); 446 } 447 448 spi_enable_chip(rs, true); 449 450 if (txdesc) { 451 atomic_or(TXDMA, &rs->state); 452 dmaengine_submit(txdesc); 453 dma_async_issue_pending(ctlr->dma_tx); 454 } 455 456 /* 1 means the transfer is in progress */ 457 return 1; 458 } 459 460 static void rockchip_spi_config(struct rockchip_spi *rs, 461 struct spi_device *spi, struct spi_transfer *xfer, 462 bool use_dma, bool slave_mode) 463 { 464 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET 465 | CR0_BHT_8BIT << CR0_BHT_OFFSET 466 | CR0_SSD_ONE << CR0_SSD_OFFSET 467 | CR0_EM_BIG << CR0_EM_OFFSET; 468 u32 cr1; 469 u32 dmacr = 0; 470 471 if (slave_mode) 472 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET; 473 rs->slave_abort = false; 474 475 cr0 |= rs->rsd << CR0_RSD_OFFSET; 476 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; 477 if (spi->mode & SPI_LSB_FIRST) 478 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; 479 480 if (xfer->rx_buf && xfer->tx_buf) 481 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; 482 else if (xfer->rx_buf) 483 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; 484 else if (use_dma) 485 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; 486 487 switch (xfer->bits_per_word) { 488 case 4: 489 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; 490 cr1 = xfer->len - 1; 491 break; 492 case 8: 493 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; 494 cr1 = xfer->len - 1; 495 break; 496 case 16: 497 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; 498 cr1 = xfer->len / 2 - 1; 499 break; 500 default: 501 /* we only whitelist 4, 8 and 16 bit words in 502 * ctlr->bits_per_word_mask, so this shouldn't 503 * happen 504 */ 505 unreachable(); 506 } 507 508 if (use_dma) { 509 if (xfer->tx_buf) 510 dmacr |= TF_DMA_EN; 511 if (xfer->rx_buf) 512 dmacr |= RF_DMA_EN; 513 } 514 515 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 516 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); 517 518 /* unfortunately setting the fifo threshold level to generate an 519 * interrupt exactly when the fifo is full doesn't seem to work, 520 * so we need the strict inequality here 521 */ 522 if (xfer->len < rs->fifo_len) 523 writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 524 else 525 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 526 527 writel_relaxed(rs->fifo_len / 2, rs->regs + ROCKCHIP_SPI_DMATDLR); 528 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); 529 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); 530 531 /* the hardware only supports an even clock divisor, so 532 * round divisor = spiclk / speed up to nearest even number 533 * so that the resulting speed is <= the requested speed 534 */ 535 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz), 536 rs->regs + ROCKCHIP_SPI_BAUDR); 537 } 538 539 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) 540 { 541 return ROCKCHIP_SPI_MAX_TRANLEN; 542 } 543 544 static int rockchip_spi_slave_abort(struct spi_controller *ctlr) 545 { 546 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 547 548 rs->slave_abort = true; 549 complete(&ctlr->xfer_completion); 550 551 return 0; 552 } 553 554 static int rockchip_spi_transfer_one( 555 struct spi_controller *ctlr, 556 struct spi_device *spi, 557 struct spi_transfer *xfer) 558 { 559 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 560 bool use_dma; 561 562 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && 563 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 564 565 if (!xfer->tx_buf && !xfer->rx_buf) { 566 dev_err(rs->dev, "No buffer for transfer\n"); 567 return -EINVAL; 568 } 569 570 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { 571 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); 572 return -EINVAL; 573 } 574 575 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2; 576 577 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false; 578 579 rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave); 580 581 if (use_dma) 582 return rockchip_spi_prepare_dma(rs, ctlr, xfer); 583 584 return rockchip_spi_prepare_irq(rs, xfer); 585 } 586 587 static bool rockchip_spi_can_dma(struct spi_controller *ctlr, 588 struct spi_device *spi, 589 struct spi_transfer *xfer) 590 { 591 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 592 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2; 593 594 /* if the numbor of spi words to transfer is less than the fifo 595 * length we can just fill the fifo and wait for a single irq, 596 * so don't bother setting up dma 597 */ 598 return xfer->len / bytes_per_word >= rs->fifo_len; 599 } 600 601 static int rockchip_spi_probe(struct platform_device *pdev) 602 { 603 int ret; 604 struct rockchip_spi *rs; 605 struct spi_controller *ctlr; 606 struct resource *mem; 607 struct device_node *np = pdev->dev.of_node; 608 u32 rsd_nsecs; 609 bool slave_mode; 610 611 slave_mode = of_property_read_bool(np, "spi-slave"); 612 613 if (slave_mode) 614 ctlr = spi_alloc_slave(&pdev->dev, 615 sizeof(struct rockchip_spi)); 616 else 617 ctlr = spi_alloc_master(&pdev->dev, 618 sizeof(struct rockchip_spi)); 619 620 if (!ctlr) 621 return -ENOMEM; 622 623 platform_set_drvdata(pdev, ctlr); 624 625 rs = spi_controller_get_devdata(ctlr); 626 ctlr->slave = slave_mode; 627 628 /* Get basic io resource and map it */ 629 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 630 rs->regs = devm_ioremap_resource(&pdev->dev, mem); 631 if (IS_ERR(rs->regs)) { 632 ret = PTR_ERR(rs->regs); 633 goto err_put_ctlr; 634 } 635 636 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 637 if (IS_ERR(rs->apb_pclk)) { 638 dev_err(&pdev->dev, "Failed to get apb_pclk\n"); 639 ret = PTR_ERR(rs->apb_pclk); 640 goto err_put_ctlr; 641 } 642 643 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); 644 if (IS_ERR(rs->spiclk)) { 645 dev_err(&pdev->dev, "Failed to get spi_pclk\n"); 646 ret = PTR_ERR(rs->spiclk); 647 goto err_put_ctlr; 648 } 649 650 ret = clk_prepare_enable(rs->apb_pclk); 651 if (ret < 0) { 652 dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); 653 goto err_put_ctlr; 654 } 655 656 ret = clk_prepare_enable(rs->spiclk); 657 if (ret < 0) { 658 dev_err(&pdev->dev, "Failed to enable spi_clk\n"); 659 goto err_disable_apbclk; 660 } 661 662 spi_enable_chip(rs, false); 663 664 ret = platform_get_irq(pdev, 0); 665 if (ret < 0) 666 goto err_disable_spiclk; 667 668 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL, 669 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr); 670 if (ret) 671 goto err_disable_spiclk; 672 673 rs->dev = &pdev->dev; 674 rs->freq = clk_get_rate(rs->spiclk); 675 676 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", 677 &rsd_nsecs)) { 678 /* rx sample delay is expressed in parent clock cycles (max 3) */ 679 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), 680 1000000000 >> 8); 681 if (!rsd) { 682 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n", 683 rs->freq, rsd_nsecs); 684 } else if (rsd > CR0_RSD_MAX) { 685 rsd = CR0_RSD_MAX; 686 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n", 687 rs->freq, rsd_nsecs, 688 CR0_RSD_MAX * 1000000000U / rs->freq); 689 } 690 rs->rsd = rsd; 691 } 692 693 rs->fifo_len = get_fifo_len(rs); 694 if (!rs->fifo_len) { 695 dev_err(&pdev->dev, "Failed to get fifo length\n"); 696 ret = -EINVAL; 697 goto err_disable_spiclk; 698 } 699 700 pm_runtime_set_active(&pdev->dev); 701 pm_runtime_enable(&pdev->dev); 702 703 ctlr->auto_runtime_pm = true; 704 ctlr->bus_num = pdev->id; 705 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST; 706 if (slave_mode) { 707 ctlr->mode_bits |= SPI_NO_CS; 708 ctlr->slave_abort = rockchip_spi_slave_abort; 709 } else { 710 ctlr->flags = SPI_MASTER_GPIO_SS; 711 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM; 712 /* 713 * rk spi0 has two native cs, spi1..5 one cs only 714 * if num-cs is missing in the dts, default to 1 715 */ 716 if (of_property_read_u16(np, "num-cs", &ctlr->num_chipselect)) 717 ctlr->num_chipselect = 1; 718 ctlr->use_gpio_descriptors = true; 719 } 720 ctlr->dev.of_node = pdev->dev.of_node; 721 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4); 722 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; 723 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); 724 725 ctlr->set_cs = rockchip_spi_set_cs; 726 ctlr->transfer_one = rockchip_spi_transfer_one; 727 ctlr->max_transfer_size = rockchip_spi_max_transfer_size; 728 ctlr->handle_err = rockchip_spi_handle_err; 729 730 ctlr->dma_tx = dma_request_chan(rs->dev, "tx"); 731 if (IS_ERR(ctlr->dma_tx)) { 732 /* Check tx to see if we need defer probing driver */ 733 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) { 734 ret = -EPROBE_DEFER; 735 goto err_disable_pm_runtime; 736 } 737 dev_warn(rs->dev, "Failed to request TX DMA channel\n"); 738 ctlr->dma_tx = NULL; 739 } 740 741 ctlr->dma_rx = dma_request_chan(rs->dev, "rx"); 742 if (IS_ERR(ctlr->dma_rx)) { 743 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) { 744 ret = -EPROBE_DEFER; 745 goto err_free_dma_tx; 746 } 747 dev_warn(rs->dev, "Failed to request RX DMA channel\n"); 748 ctlr->dma_rx = NULL; 749 } 750 751 if (ctlr->dma_tx && ctlr->dma_rx) { 752 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR; 753 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR; 754 ctlr->can_dma = rockchip_spi_can_dma; 755 } 756 757 ret = devm_spi_register_controller(&pdev->dev, ctlr); 758 if (ret < 0) { 759 dev_err(&pdev->dev, "Failed to register controller\n"); 760 goto err_free_dma_rx; 761 } 762 763 return 0; 764 765 err_free_dma_rx: 766 if (ctlr->dma_rx) 767 dma_release_channel(ctlr->dma_rx); 768 err_free_dma_tx: 769 if (ctlr->dma_tx) 770 dma_release_channel(ctlr->dma_tx); 771 err_disable_pm_runtime: 772 pm_runtime_disable(&pdev->dev); 773 err_disable_spiclk: 774 clk_disable_unprepare(rs->spiclk); 775 err_disable_apbclk: 776 clk_disable_unprepare(rs->apb_pclk); 777 err_put_ctlr: 778 spi_controller_put(ctlr); 779 780 return ret; 781 } 782 783 static int rockchip_spi_remove(struct platform_device *pdev) 784 { 785 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev)); 786 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 787 788 pm_runtime_get_sync(&pdev->dev); 789 790 clk_disable_unprepare(rs->spiclk); 791 clk_disable_unprepare(rs->apb_pclk); 792 793 pm_runtime_put_noidle(&pdev->dev); 794 pm_runtime_disable(&pdev->dev); 795 pm_runtime_set_suspended(&pdev->dev); 796 797 if (ctlr->dma_tx) 798 dma_release_channel(ctlr->dma_tx); 799 if (ctlr->dma_rx) 800 dma_release_channel(ctlr->dma_rx); 801 802 spi_controller_put(ctlr); 803 804 return 0; 805 } 806 807 #ifdef CONFIG_PM_SLEEP 808 static int rockchip_spi_suspend(struct device *dev) 809 { 810 int ret; 811 struct spi_controller *ctlr = dev_get_drvdata(dev); 812 813 ret = spi_controller_suspend(ctlr); 814 if (ret < 0) 815 return ret; 816 817 ret = pm_runtime_force_suspend(dev); 818 if (ret < 0) 819 return ret; 820 821 pinctrl_pm_select_sleep_state(dev); 822 823 return 0; 824 } 825 826 static int rockchip_spi_resume(struct device *dev) 827 { 828 int ret; 829 struct spi_controller *ctlr = dev_get_drvdata(dev); 830 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 831 832 pinctrl_pm_select_default_state(dev); 833 834 ret = pm_runtime_force_resume(dev); 835 if (ret < 0) 836 return ret; 837 838 ret = spi_controller_resume(ctlr); 839 if (ret < 0) { 840 clk_disable_unprepare(rs->spiclk); 841 clk_disable_unprepare(rs->apb_pclk); 842 } 843 844 return 0; 845 } 846 #endif /* CONFIG_PM_SLEEP */ 847 848 #ifdef CONFIG_PM 849 static int rockchip_spi_runtime_suspend(struct device *dev) 850 { 851 struct spi_controller *ctlr = dev_get_drvdata(dev); 852 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 853 854 clk_disable_unprepare(rs->spiclk); 855 clk_disable_unprepare(rs->apb_pclk); 856 857 return 0; 858 } 859 860 static int rockchip_spi_runtime_resume(struct device *dev) 861 { 862 int ret; 863 struct spi_controller *ctlr = dev_get_drvdata(dev); 864 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 865 866 ret = clk_prepare_enable(rs->apb_pclk); 867 if (ret < 0) 868 return ret; 869 870 ret = clk_prepare_enable(rs->spiclk); 871 if (ret < 0) 872 clk_disable_unprepare(rs->apb_pclk); 873 874 return 0; 875 } 876 #endif /* CONFIG_PM */ 877 878 static const struct dev_pm_ops rockchip_spi_pm = { 879 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) 880 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, 881 rockchip_spi_runtime_resume, NULL) 882 }; 883 884 static const struct of_device_id rockchip_spi_dt_match[] = { 885 { .compatible = "rockchip,px30-spi", }, 886 { .compatible = "rockchip,rk3036-spi", }, 887 { .compatible = "rockchip,rk3066-spi", }, 888 { .compatible = "rockchip,rk3188-spi", }, 889 { .compatible = "rockchip,rk3228-spi", }, 890 { .compatible = "rockchip,rk3288-spi", }, 891 { .compatible = "rockchip,rk3308-spi", }, 892 { .compatible = "rockchip,rk3328-spi", }, 893 { .compatible = "rockchip,rk3368-spi", }, 894 { .compatible = "rockchip,rk3399-spi", }, 895 { .compatible = "rockchip,rv1108-spi", }, 896 { }, 897 }; 898 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 899 900 static struct platform_driver rockchip_spi_driver = { 901 .driver = { 902 .name = DRIVER_NAME, 903 .pm = &rockchip_spi_pm, 904 .of_match_table = of_match_ptr(rockchip_spi_dt_match), 905 }, 906 .probe = rockchip_spi_probe, 907 .remove = rockchip_spi_remove, 908 }; 909 910 module_platform_driver(rockchip_spi_driver); 911 912 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 913 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); 914 MODULE_LICENSE("GPL v2"); 915