1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/list.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/spi/spi.h> 18 #include <linux/dmaengine.h> 19 #include <linux/dma-mapping.h> 20 21 #define QUP_CONFIG 0x0000 22 #define QUP_STATE 0x0004 23 #define QUP_IO_M_MODES 0x0008 24 #define QUP_SW_RESET 0x000c 25 #define QUP_OPERATIONAL 0x0018 26 #define QUP_ERROR_FLAGS 0x001c 27 #define QUP_ERROR_FLAGS_EN 0x0020 28 #define QUP_OPERATIONAL_MASK 0x0028 29 #define QUP_HW_VERSION 0x0030 30 #define QUP_MX_OUTPUT_CNT 0x0100 31 #define QUP_OUTPUT_FIFO 0x0110 32 #define QUP_MX_WRITE_CNT 0x0150 33 #define QUP_MX_INPUT_CNT 0x0200 34 #define QUP_MX_READ_CNT 0x0208 35 #define QUP_INPUT_FIFO 0x0218 36 37 #define SPI_CONFIG 0x0300 38 #define SPI_IO_CONTROL 0x0304 39 #define SPI_ERROR_FLAGS 0x0308 40 #define SPI_ERROR_FLAGS_EN 0x030c 41 42 /* QUP_CONFIG fields */ 43 #define QUP_CONFIG_SPI_MODE (1 << 8) 44 #define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13) 45 #define QUP_CONFIG_NO_INPUT BIT(7) 46 #define QUP_CONFIG_NO_OUTPUT BIT(6) 47 #define QUP_CONFIG_N 0x001f 48 49 /* QUP_STATE fields */ 50 #define QUP_STATE_VALID BIT(2) 51 #define QUP_STATE_RESET 0 52 #define QUP_STATE_RUN 1 53 #define QUP_STATE_PAUSE 3 54 #define QUP_STATE_MASK 3 55 #define QUP_STATE_CLEAR 2 56 57 #define QUP_HW_VERSION_2_1_1 0x20010001 58 59 /* QUP_IO_M_MODES fields */ 60 #define QUP_IO_M_PACK_EN BIT(15) 61 #define QUP_IO_M_UNPACK_EN BIT(14) 62 #define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12 63 #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10 64 #define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT) 65 #define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT) 66 67 #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0) 68 #define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2) 69 #define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5) 70 #define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7) 71 72 #define QUP_IO_M_MODE_FIFO 0 73 #define QUP_IO_M_MODE_BLOCK 1 74 #define QUP_IO_M_MODE_DMOV 2 75 #define QUP_IO_M_MODE_BAM 3 76 77 /* QUP_OPERATIONAL fields */ 78 #define QUP_OP_IN_BLOCK_READ_REQ BIT(13) 79 #define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12) 80 #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11) 81 #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10) 82 #define QUP_OP_IN_SERVICE_FLAG BIT(9) 83 #define QUP_OP_OUT_SERVICE_FLAG BIT(8) 84 #define QUP_OP_IN_FIFO_FULL BIT(7) 85 #define QUP_OP_OUT_FIFO_FULL BIT(6) 86 #define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5) 87 #define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4) 88 89 /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */ 90 #define QUP_ERROR_OUTPUT_OVER_RUN BIT(5) 91 #define QUP_ERROR_INPUT_UNDER_RUN BIT(4) 92 #define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3) 93 #define QUP_ERROR_INPUT_OVER_RUN BIT(2) 94 95 /* SPI_CONFIG fields */ 96 #define SPI_CONFIG_HS_MODE BIT(10) 97 #define SPI_CONFIG_INPUT_FIRST BIT(9) 98 #define SPI_CONFIG_LOOPBACK BIT(8) 99 100 /* SPI_IO_CONTROL fields */ 101 #define SPI_IO_C_FORCE_CS BIT(11) 102 #define SPI_IO_C_CLK_IDLE_HIGH BIT(10) 103 #define SPI_IO_C_MX_CS_MODE BIT(8) 104 #define SPI_IO_C_CS_N_POLARITY_0 BIT(4) 105 #define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2) 106 #define SPI_IO_C_CS_SELECT_MASK 0x000c 107 #define SPI_IO_C_TRISTATE_CS BIT(1) 108 #define SPI_IO_C_NO_TRI_STATE BIT(0) 109 110 /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */ 111 #define SPI_ERROR_CLK_OVER_RUN BIT(1) 112 #define SPI_ERROR_CLK_UNDER_RUN BIT(0) 113 114 #define SPI_NUM_CHIPSELECTS 4 115 116 #define SPI_MAX_XFER (SZ_64K - 64) 117 118 /* high speed mode is when bus rate is greater then 26MHz */ 119 #define SPI_HS_MIN_RATE 26000000 120 #define SPI_MAX_RATE 50000000 121 122 #define SPI_DELAY_THRESHOLD 1 123 #define SPI_DELAY_RETRY 10 124 125 struct spi_qup { 126 void __iomem *base; 127 struct device *dev; 128 struct clk *cclk; /* core clock */ 129 struct clk *iclk; /* interface clock */ 130 int irq; 131 spinlock_t lock; 132 133 int in_fifo_sz; 134 int out_fifo_sz; 135 int in_blk_sz; 136 int out_blk_sz; 137 138 struct spi_transfer *xfer; 139 struct completion done; 140 int error; 141 int w_size; /* bytes per SPI word */ 142 int n_words; 143 int tx_bytes; 144 int rx_bytes; 145 const u8 *tx_buf; 146 u8 *rx_buf; 147 int qup_v1; 148 149 int mode; 150 struct dma_slave_config rx_conf; 151 struct dma_slave_config tx_conf; 152 }; 153 154 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer); 155 156 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) 157 { 158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); 159 160 return (opflag & flag) != 0; 161 } 162 163 static inline bool spi_qup_is_dma_xfer(int mode) 164 { 165 if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM) 166 return true; 167 168 return false; 169 } 170 171 /* get's the transaction size length */ 172 static inline unsigned int spi_qup_len(struct spi_qup *controller) 173 { 174 return controller->n_words * controller->w_size; 175 } 176 177 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) 178 { 179 u32 opstate = readl_relaxed(controller->base + QUP_STATE); 180 181 return opstate & QUP_STATE_VALID; 182 } 183 184 static int spi_qup_set_state(struct spi_qup *controller, u32 state) 185 { 186 unsigned long loop; 187 u32 cur_state; 188 189 loop = 0; 190 while (!spi_qup_is_valid_state(controller)) { 191 192 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); 193 194 if (++loop > SPI_DELAY_RETRY) 195 return -EIO; 196 } 197 198 if (loop) 199 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", 200 loop, state); 201 202 cur_state = readl_relaxed(controller->base + QUP_STATE); 203 /* 204 * Per spec: for PAUSE_STATE to RESET_STATE, two writes 205 * of (b10) are required 206 */ 207 if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) && 208 (state == QUP_STATE_RESET)) { 209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); 210 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); 211 } else { 212 cur_state &= ~QUP_STATE_MASK; 213 cur_state |= state; 214 writel_relaxed(cur_state, controller->base + QUP_STATE); 215 } 216 217 loop = 0; 218 while (!spi_qup_is_valid_state(controller)) { 219 220 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); 221 222 if (++loop > SPI_DELAY_RETRY) 223 return -EIO; 224 } 225 226 return 0; 227 } 228 229 static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words) 230 { 231 u8 *rx_buf = controller->rx_buf; 232 int i, shift, num_bytes; 233 u32 word; 234 235 for (; num_words; num_words--) { 236 237 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); 238 239 num_bytes = min_t(int, spi_qup_len(controller) - 240 controller->rx_bytes, 241 controller->w_size); 242 243 if (!rx_buf) { 244 controller->rx_bytes += num_bytes; 245 continue; 246 } 247 248 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { 249 /* 250 * The data format depends on bytes per SPI word: 251 * 4 bytes: 0x12345678 252 * 2 bytes: 0x00001234 253 * 1 byte : 0x00000012 254 */ 255 shift = BITS_PER_BYTE; 256 shift *= (controller->w_size - i - 1); 257 rx_buf[controller->rx_bytes] = word >> shift; 258 } 259 } 260 } 261 262 static void spi_qup_read(struct spi_qup *controller, u32 *opflags) 263 { 264 u32 remainder, words_per_block, num_words; 265 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; 266 267 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, 268 controller->w_size); 269 words_per_block = controller->in_blk_sz >> 2; 270 271 do { 272 /* ACK by clearing service flag */ 273 writel_relaxed(QUP_OP_IN_SERVICE_FLAG, 274 controller->base + QUP_OPERATIONAL); 275 276 if (!remainder) 277 goto exit; 278 279 if (is_block_mode) { 280 num_words = (remainder > words_per_block) ? 281 words_per_block : remainder; 282 } else { 283 if (!spi_qup_is_flag_set(controller, 284 QUP_OP_IN_FIFO_NOT_EMPTY)) 285 break; 286 287 num_words = 1; 288 } 289 290 /* read up to the maximum transfer size available */ 291 spi_qup_read_from_fifo(controller, num_words); 292 293 remainder -= num_words; 294 295 /* if block mode, check to see if next block is available */ 296 if (is_block_mode && !spi_qup_is_flag_set(controller, 297 QUP_OP_IN_BLOCK_READ_REQ)) 298 break; 299 300 } while (remainder); 301 302 /* 303 * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block 304 * reads, it has to be cleared again at the very end. However, be sure 305 * to refresh opflags value because MAX_INPUT_DONE_FLAG may now be 306 * present and this is used to determine if transaction is complete 307 */ 308 exit: 309 if (!remainder) { 310 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); 311 if (is_block_mode && *opflags & QUP_OP_MAX_INPUT_DONE_FLAG) 312 writel_relaxed(QUP_OP_IN_SERVICE_FLAG, 313 controller->base + QUP_OPERATIONAL); 314 } 315 } 316 317 static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words) 318 { 319 const u8 *tx_buf = controller->tx_buf; 320 int i, num_bytes; 321 u32 word, data; 322 323 for (; num_words; num_words--) { 324 word = 0; 325 326 num_bytes = min_t(int, spi_qup_len(controller) - 327 controller->tx_bytes, 328 controller->w_size); 329 if (tx_buf) 330 for (i = 0; i < num_bytes; i++) { 331 data = tx_buf[controller->tx_bytes + i]; 332 word |= data << (BITS_PER_BYTE * (3 - i)); 333 } 334 335 controller->tx_bytes += num_bytes; 336 337 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); 338 } 339 } 340 341 static void spi_qup_dma_done(void *data) 342 { 343 struct spi_qup *qup = data; 344 345 complete(&qup->done); 346 } 347 348 static void spi_qup_write(struct spi_qup *controller) 349 { 350 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; 351 u32 remainder, words_per_block, num_words; 352 353 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, 354 controller->w_size); 355 words_per_block = controller->out_blk_sz >> 2; 356 357 do { 358 /* ACK by clearing service flag */ 359 writel_relaxed(QUP_OP_OUT_SERVICE_FLAG, 360 controller->base + QUP_OPERATIONAL); 361 362 /* make sure the interrupt is valid */ 363 if (!remainder) 364 return; 365 366 if (is_block_mode) { 367 num_words = (remainder > words_per_block) ? 368 words_per_block : remainder; 369 } else { 370 if (spi_qup_is_flag_set(controller, 371 QUP_OP_OUT_FIFO_FULL)) 372 break; 373 374 num_words = 1; 375 } 376 377 spi_qup_write_to_fifo(controller, num_words); 378 379 remainder -= num_words; 380 381 /* if block mode, check to see if next block is available */ 382 if (is_block_mode && !spi_qup_is_flag_set(controller, 383 QUP_OP_OUT_BLOCK_WRITE_REQ)) 384 break; 385 386 } while (remainder); 387 } 388 389 static int spi_qup_prep_sg(struct spi_master *master, struct scatterlist *sgl, 390 unsigned int nents, enum dma_transfer_direction dir, 391 dma_async_tx_callback callback) 392 { 393 struct spi_qup *qup = spi_master_get_devdata(master); 394 unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE; 395 struct dma_async_tx_descriptor *desc; 396 struct dma_chan *chan; 397 dma_cookie_t cookie; 398 399 if (dir == DMA_MEM_TO_DEV) 400 chan = master->dma_tx; 401 else 402 chan = master->dma_rx; 403 404 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); 405 if (IS_ERR_OR_NULL(desc)) 406 return desc ? PTR_ERR(desc) : -EINVAL; 407 408 desc->callback = callback; 409 desc->callback_param = qup; 410 411 cookie = dmaengine_submit(desc); 412 413 return dma_submit_error(cookie); 414 } 415 416 static void spi_qup_dma_terminate(struct spi_master *master, 417 struct spi_transfer *xfer) 418 { 419 if (xfer->tx_buf) 420 dmaengine_terminate_all(master->dma_tx); 421 if (xfer->rx_buf) 422 dmaengine_terminate_all(master->dma_rx); 423 } 424 425 static u32 spi_qup_sgl_get_nents_len(struct scatterlist *sgl, u32 max, 426 u32 *nents) 427 { 428 struct scatterlist *sg; 429 u32 total = 0; 430 431 for (sg = sgl; sg; sg = sg_next(sg)) { 432 unsigned int len = sg_dma_len(sg); 433 434 /* check for overflow as well as limit */ 435 if (((total + len) < total) || ((total + len) > max)) 436 break; 437 438 total += len; 439 (*nents)++; 440 } 441 442 return total; 443 } 444 445 static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer, 446 unsigned long timeout) 447 { 448 dma_async_tx_callback rx_done = NULL, tx_done = NULL; 449 struct spi_master *master = spi->master; 450 struct spi_qup *qup = spi_master_get_devdata(master); 451 struct scatterlist *tx_sgl, *rx_sgl; 452 int ret; 453 454 if (xfer->rx_buf) 455 rx_done = spi_qup_dma_done; 456 else if (xfer->tx_buf) 457 tx_done = spi_qup_dma_done; 458 459 rx_sgl = xfer->rx_sg.sgl; 460 tx_sgl = xfer->tx_sg.sgl; 461 462 do { 463 u32 rx_nents = 0, tx_nents = 0; 464 465 if (rx_sgl) 466 qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl, 467 SPI_MAX_XFER, &rx_nents) / qup->w_size; 468 if (tx_sgl) 469 qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl, 470 SPI_MAX_XFER, &tx_nents) / qup->w_size; 471 if (!qup->n_words) 472 return -EIO; 473 474 ret = spi_qup_io_config(spi, xfer); 475 if (ret) 476 return ret; 477 478 /* before issuing the descriptors, set the QUP to run */ 479 ret = spi_qup_set_state(qup, QUP_STATE_RUN); 480 if (ret) { 481 dev_warn(qup->dev, "cannot set RUN state\n"); 482 return ret; 483 } 484 if (rx_sgl) { 485 ret = spi_qup_prep_sg(master, rx_sgl, rx_nents, 486 DMA_DEV_TO_MEM, rx_done); 487 if (ret) 488 return ret; 489 dma_async_issue_pending(master->dma_rx); 490 } 491 492 if (tx_sgl) { 493 ret = spi_qup_prep_sg(master, tx_sgl, tx_nents, 494 DMA_MEM_TO_DEV, tx_done); 495 if (ret) 496 return ret; 497 498 dma_async_issue_pending(master->dma_tx); 499 } 500 501 if (!wait_for_completion_timeout(&qup->done, timeout)) 502 return -ETIMEDOUT; 503 504 for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl)) 505 ; 506 for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl)) 507 ; 508 509 } while (rx_sgl || tx_sgl); 510 511 return 0; 512 } 513 514 static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer, 515 unsigned long timeout) 516 { 517 struct spi_master *master = spi->master; 518 struct spi_qup *qup = spi_master_get_devdata(master); 519 int ret, n_words, iterations, offset = 0; 520 521 n_words = qup->n_words; 522 iterations = n_words / SPI_MAX_XFER; /* round down */ 523 qup->rx_buf = xfer->rx_buf; 524 qup->tx_buf = xfer->tx_buf; 525 526 do { 527 if (iterations) 528 qup->n_words = SPI_MAX_XFER; 529 else 530 qup->n_words = n_words % SPI_MAX_XFER; 531 532 if (qup->tx_buf && offset) 533 qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER; 534 535 if (qup->rx_buf && offset) 536 qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER; 537 538 /* 539 * if the transaction is small enough, we need 540 * to fallback to FIFO mode 541 */ 542 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32))) 543 qup->mode = QUP_IO_M_MODE_FIFO; 544 545 ret = spi_qup_io_config(spi, xfer); 546 if (ret) 547 return ret; 548 549 ret = spi_qup_set_state(qup, QUP_STATE_RUN); 550 if (ret) { 551 dev_warn(qup->dev, "cannot set RUN state\n"); 552 return ret; 553 } 554 555 ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); 556 if (ret) { 557 dev_warn(qup->dev, "cannot set PAUSE state\n"); 558 return ret; 559 } 560 561 if (qup->mode == QUP_IO_M_MODE_FIFO) 562 spi_qup_write(qup); 563 564 ret = spi_qup_set_state(qup, QUP_STATE_RUN); 565 if (ret) { 566 dev_warn(qup->dev, "cannot set RUN state\n"); 567 return ret; 568 } 569 570 if (!wait_for_completion_timeout(&qup->done, timeout)) 571 return -ETIMEDOUT; 572 573 offset++; 574 } while (iterations--); 575 576 return 0; 577 } 578 579 static bool spi_qup_data_pending(struct spi_qup *controller) 580 { 581 unsigned int remainder_tx, remainder_rx; 582 583 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) - 584 controller->tx_bytes, controller->w_size); 585 586 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) - 587 controller->rx_bytes, controller->w_size); 588 589 return remainder_tx || remainder_rx; 590 } 591 592 static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) 593 { 594 struct spi_qup *controller = dev_id; 595 u32 opflags, qup_err, spi_err; 596 unsigned long flags; 597 int error = 0; 598 599 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); 600 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); 601 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); 602 603 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); 604 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); 605 606 if (qup_err) { 607 if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN) 608 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); 609 if (qup_err & QUP_ERROR_INPUT_UNDER_RUN) 610 dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); 611 if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN) 612 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); 613 if (qup_err & QUP_ERROR_INPUT_OVER_RUN) 614 dev_warn(controller->dev, "INPUT_OVER_RUN\n"); 615 616 error = -EIO; 617 } 618 619 if (spi_err) { 620 if (spi_err & SPI_ERROR_CLK_OVER_RUN) 621 dev_warn(controller->dev, "CLK_OVER_RUN\n"); 622 if (spi_err & SPI_ERROR_CLK_UNDER_RUN) 623 dev_warn(controller->dev, "CLK_UNDER_RUN\n"); 624 625 error = -EIO; 626 } 627 628 spin_lock_irqsave(&controller->lock, flags); 629 if (!controller->error) 630 controller->error = error; 631 spin_unlock_irqrestore(&controller->lock, flags); 632 633 if (spi_qup_is_dma_xfer(controller->mode)) { 634 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); 635 } else { 636 if (opflags & QUP_OP_IN_SERVICE_FLAG) 637 spi_qup_read(controller, &opflags); 638 639 if (opflags & QUP_OP_OUT_SERVICE_FLAG) 640 spi_qup_write(controller); 641 642 if (!spi_qup_data_pending(controller)) 643 complete(&controller->done); 644 } 645 646 if (error) 647 complete(&controller->done); 648 649 if (opflags & QUP_OP_MAX_INPUT_DONE_FLAG) { 650 if (!spi_qup_is_dma_xfer(controller->mode)) { 651 if (spi_qup_data_pending(controller)) 652 return IRQ_HANDLED; 653 } 654 complete(&controller->done); 655 } 656 657 return IRQ_HANDLED; 658 } 659 660 /* set clock freq ... bits per word, determine mode */ 661 static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer) 662 { 663 struct spi_qup *controller = spi_master_get_devdata(spi->master); 664 int ret; 665 666 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { 667 dev_err(controller->dev, "too big size for loopback %d > %d\n", 668 xfer->len, controller->in_fifo_sz); 669 return -EIO; 670 } 671 672 ret = clk_set_rate(controller->cclk, xfer->speed_hz); 673 if (ret) { 674 dev_err(controller->dev, "fail to set frequency %d", 675 xfer->speed_hz); 676 return -EIO; 677 } 678 679 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); 680 controller->n_words = xfer->len / controller->w_size; 681 682 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) 683 controller->mode = QUP_IO_M_MODE_FIFO; 684 else if (spi->master->can_dma && 685 spi->master->can_dma(spi->master, spi, xfer) && 686 spi->master->cur_msg_mapped) 687 controller->mode = QUP_IO_M_MODE_BAM; 688 else 689 controller->mode = QUP_IO_M_MODE_BLOCK; 690 691 return 0; 692 } 693 694 /* prep qup for another spi transaction of specific type */ 695 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) 696 { 697 struct spi_qup *controller = spi_master_get_devdata(spi->master); 698 u32 config, iomode, control; 699 unsigned long flags; 700 701 spin_lock_irqsave(&controller->lock, flags); 702 controller->xfer = xfer; 703 controller->error = 0; 704 controller->rx_bytes = 0; 705 controller->tx_bytes = 0; 706 spin_unlock_irqrestore(&controller->lock, flags); 707 708 709 if (spi_qup_set_state(controller, QUP_STATE_RESET)) { 710 dev_err(controller->dev, "cannot set RESET state\n"); 711 return -EIO; 712 } 713 714 switch (controller->mode) { 715 case QUP_IO_M_MODE_FIFO: 716 writel_relaxed(controller->n_words, 717 controller->base + QUP_MX_READ_CNT); 718 writel_relaxed(controller->n_words, 719 controller->base + QUP_MX_WRITE_CNT); 720 /* must be zero for FIFO */ 721 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); 722 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); 723 break; 724 case QUP_IO_M_MODE_BAM: 725 writel_relaxed(controller->n_words, 726 controller->base + QUP_MX_INPUT_CNT); 727 writel_relaxed(controller->n_words, 728 controller->base + QUP_MX_OUTPUT_CNT); 729 /* must be zero for BLOCK and BAM */ 730 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); 731 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); 732 733 if (!controller->qup_v1) { 734 void __iomem *input_cnt; 735 736 input_cnt = controller->base + QUP_MX_INPUT_CNT; 737 /* 738 * for DMA transfers, both QUP_MX_INPUT_CNT and 739 * QUP_MX_OUTPUT_CNT must be zero to all cases but one. 740 * That case is a non-balanced transfer when there is 741 * only a rx_buf. 742 */ 743 if (xfer->tx_buf) 744 writel_relaxed(0, input_cnt); 745 else 746 writel_relaxed(controller->n_words, input_cnt); 747 748 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); 749 } 750 break; 751 case QUP_IO_M_MODE_BLOCK: 752 reinit_completion(&controller->done); 753 writel_relaxed(controller->n_words, 754 controller->base + QUP_MX_INPUT_CNT); 755 writel_relaxed(controller->n_words, 756 controller->base + QUP_MX_OUTPUT_CNT); 757 /* must be zero for BLOCK and BAM */ 758 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); 759 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); 760 break; 761 default: 762 dev_err(controller->dev, "unknown mode = %d\n", 763 controller->mode); 764 return -EIO; 765 } 766 767 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); 768 /* Set input and output transfer mode */ 769 iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK); 770 771 if (!spi_qup_is_dma_xfer(controller->mode)) 772 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN); 773 else 774 iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN; 775 776 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); 777 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); 778 779 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); 780 781 control = readl_relaxed(controller->base + SPI_IO_CONTROL); 782 783 if (spi->mode & SPI_CPOL) 784 control |= SPI_IO_C_CLK_IDLE_HIGH; 785 else 786 control &= ~SPI_IO_C_CLK_IDLE_HIGH; 787 788 writel_relaxed(control, controller->base + SPI_IO_CONTROL); 789 790 config = readl_relaxed(controller->base + SPI_CONFIG); 791 792 if (spi->mode & SPI_LOOP) 793 config |= SPI_CONFIG_LOOPBACK; 794 else 795 config &= ~SPI_CONFIG_LOOPBACK; 796 797 if (spi->mode & SPI_CPHA) 798 config &= ~SPI_CONFIG_INPUT_FIRST; 799 else 800 config |= SPI_CONFIG_INPUT_FIRST; 801 802 /* 803 * HS_MODE improves signal stability for spi-clk high rates, 804 * but is invalid in loop back mode. 805 */ 806 if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP)) 807 config |= SPI_CONFIG_HS_MODE; 808 else 809 config &= ~SPI_CONFIG_HS_MODE; 810 811 writel_relaxed(config, controller->base + SPI_CONFIG); 812 813 config = readl_relaxed(controller->base + QUP_CONFIG); 814 config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N); 815 config |= xfer->bits_per_word - 1; 816 config |= QUP_CONFIG_SPI_MODE; 817 818 if (spi_qup_is_dma_xfer(controller->mode)) { 819 if (!xfer->tx_buf) 820 config |= QUP_CONFIG_NO_OUTPUT; 821 if (!xfer->rx_buf) 822 config |= QUP_CONFIG_NO_INPUT; 823 } 824 825 writel_relaxed(config, controller->base + QUP_CONFIG); 826 827 /* only write to OPERATIONAL_MASK when register is present */ 828 if (!controller->qup_v1) { 829 u32 mask = 0; 830 831 /* 832 * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO 833 * status change in BAM mode 834 */ 835 836 if (spi_qup_is_dma_xfer(controller->mode)) 837 mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG; 838 839 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); 840 } 841 842 return 0; 843 } 844 845 static int spi_qup_transfer_one(struct spi_master *master, 846 struct spi_device *spi, 847 struct spi_transfer *xfer) 848 { 849 struct spi_qup *controller = spi_master_get_devdata(master); 850 unsigned long timeout, flags; 851 int ret = -EIO; 852 853 ret = spi_qup_io_prep(spi, xfer); 854 if (ret) 855 return ret; 856 857 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); 858 timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER, 859 xfer->len) * 8, timeout); 860 timeout = 100 * msecs_to_jiffies(timeout); 861 862 reinit_completion(&controller->done); 863 864 spin_lock_irqsave(&controller->lock, flags); 865 controller->xfer = xfer; 866 controller->error = 0; 867 controller->rx_bytes = 0; 868 controller->tx_bytes = 0; 869 spin_unlock_irqrestore(&controller->lock, flags); 870 871 if (spi_qup_is_dma_xfer(controller->mode)) 872 ret = spi_qup_do_dma(spi, xfer, timeout); 873 else 874 ret = spi_qup_do_pio(spi, xfer, timeout); 875 876 spi_qup_set_state(controller, QUP_STATE_RESET); 877 spin_lock_irqsave(&controller->lock, flags); 878 if (!ret) 879 ret = controller->error; 880 spin_unlock_irqrestore(&controller->lock, flags); 881 882 if (ret && spi_qup_is_dma_xfer(controller->mode)) 883 spi_qup_dma_terminate(master, xfer); 884 885 return ret; 886 } 887 888 static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi, 889 struct spi_transfer *xfer) 890 { 891 struct spi_qup *qup = spi_master_get_devdata(master); 892 size_t dma_align = dma_get_cache_alignment(); 893 int n_words; 894 895 if (xfer->rx_buf) { 896 if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) || 897 IS_ERR_OR_NULL(master->dma_rx)) 898 return false; 899 if (qup->qup_v1 && (xfer->len % qup->in_blk_sz)) 900 return false; 901 } 902 903 if (xfer->tx_buf) { 904 if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) || 905 IS_ERR_OR_NULL(master->dma_tx)) 906 return false; 907 if (qup->qup_v1 && (xfer->len % qup->out_blk_sz)) 908 return false; 909 } 910 911 n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8); 912 if (n_words <= (qup->in_fifo_sz / sizeof(u32))) 913 return false; 914 915 return true; 916 } 917 918 static void spi_qup_release_dma(struct spi_master *master) 919 { 920 if (!IS_ERR_OR_NULL(master->dma_rx)) 921 dma_release_channel(master->dma_rx); 922 if (!IS_ERR_OR_NULL(master->dma_tx)) 923 dma_release_channel(master->dma_tx); 924 } 925 926 static int spi_qup_init_dma(struct spi_master *master, resource_size_t base) 927 { 928 struct spi_qup *spi = spi_master_get_devdata(master); 929 struct dma_slave_config *rx_conf = &spi->rx_conf, 930 *tx_conf = &spi->tx_conf; 931 struct device *dev = spi->dev; 932 int ret; 933 934 /* allocate dma resources, if available */ 935 master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); 936 if (IS_ERR(master->dma_rx)) 937 return PTR_ERR(master->dma_rx); 938 939 master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); 940 if (IS_ERR(master->dma_tx)) { 941 ret = PTR_ERR(master->dma_tx); 942 goto err_tx; 943 } 944 945 /* set DMA parameters */ 946 rx_conf->direction = DMA_DEV_TO_MEM; 947 rx_conf->device_fc = 1; 948 rx_conf->src_addr = base + QUP_INPUT_FIFO; 949 rx_conf->src_maxburst = spi->in_blk_sz; 950 951 tx_conf->direction = DMA_MEM_TO_DEV; 952 tx_conf->device_fc = 1; 953 tx_conf->dst_addr = base + QUP_OUTPUT_FIFO; 954 tx_conf->dst_maxburst = spi->out_blk_sz; 955 956 ret = dmaengine_slave_config(master->dma_rx, rx_conf); 957 if (ret) { 958 dev_err(dev, "failed to configure RX channel\n"); 959 goto err; 960 } 961 962 ret = dmaengine_slave_config(master->dma_tx, tx_conf); 963 if (ret) { 964 dev_err(dev, "failed to configure TX channel\n"); 965 goto err; 966 } 967 968 return 0; 969 970 err: 971 dma_release_channel(master->dma_tx); 972 err_tx: 973 dma_release_channel(master->dma_rx); 974 return ret; 975 } 976 977 static void spi_qup_set_cs(struct spi_device *spi, bool val) 978 { 979 struct spi_qup *controller; 980 u32 spi_ioc; 981 u32 spi_ioc_orig; 982 983 controller = spi_master_get_devdata(spi->master); 984 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); 985 spi_ioc_orig = spi_ioc; 986 if (!val) 987 spi_ioc |= SPI_IO_C_FORCE_CS; 988 else 989 spi_ioc &= ~SPI_IO_C_FORCE_CS; 990 991 if (spi_ioc != spi_ioc_orig) 992 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); 993 } 994 995 static int spi_qup_probe(struct platform_device *pdev) 996 { 997 struct spi_master *master; 998 struct clk *iclk, *cclk; 999 struct spi_qup *controller; 1000 struct resource *res; 1001 struct device *dev; 1002 void __iomem *base; 1003 u32 max_freq, iomode, num_cs; 1004 int ret, irq, size; 1005 1006 dev = &pdev->dev; 1007 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1008 base = devm_ioremap_resource(dev, res); 1009 if (IS_ERR(base)) 1010 return PTR_ERR(base); 1011 1012 irq = platform_get_irq(pdev, 0); 1013 if (irq < 0) 1014 return irq; 1015 1016 cclk = devm_clk_get(dev, "core"); 1017 if (IS_ERR(cclk)) 1018 return PTR_ERR(cclk); 1019 1020 iclk = devm_clk_get(dev, "iface"); 1021 if (IS_ERR(iclk)) 1022 return PTR_ERR(iclk); 1023 1024 /* This is optional parameter */ 1025 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) 1026 max_freq = SPI_MAX_RATE; 1027 1028 if (!max_freq || max_freq > SPI_MAX_RATE) { 1029 dev_err(dev, "invalid clock frequency %d\n", max_freq); 1030 return -ENXIO; 1031 } 1032 1033 ret = clk_prepare_enable(cclk); 1034 if (ret) { 1035 dev_err(dev, "cannot enable core clock\n"); 1036 return ret; 1037 } 1038 1039 ret = clk_prepare_enable(iclk); 1040 if (ret) { 1041 clk_disable_unprepare(cclk); 1042 dev_err(dev, "cannot enable iface clock\n"); 1043 return ret; 1044 } 1045 1046 master = spi_alloc_master(dev, sizeof(struct spi_qup)); 1047 if (!master) { 1048 clk_disable_unprepare(cclk); 1049 clk_disable_unprepare(iclk); 1050 dev_err(dev, "cannot allocate master\n"); 1051 return -ENOMEM; 1052 } 1053 1054 /* use num-cs unless not present or out of range */ 1055 if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) || 1056 num_cs > SPI_NUM_CHIPSELECTS) 1057 master->num_chipselect = SPI_NUM_CHIPSELECTS; 1058 else 1059 master->num_chipselect = num_cs; 1060 1061 master->bus_num = pdev->id; 1062 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1063 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1064 master->max_speed_hz = max_freq; 1065 master->transfer_one = spi_qup_transfer_one; 1066 master->dev.of_node = pdev->dev.of_node; 1067 master->auto_runtime_pm = true; 1068 master->dma_alignment = dma_get_cache_alignment(); 1069 master->max_dma_len = SPI_MAX_XFER; 1070 1071 platform_set_drvdata(pdev, master); 1072 1073 controller = spi_master_get_devdata(master); 1074 1075 controller->dev = dev; 1076 controller->base = base; 1077 controller->iclk = iclk; 1078 controller->cclk = cclk; 1079 controller->irq = irq; 1080 1081 ret = spi_qup_init_dma(master, res->start); 1082 if (ret == -EPROBE_DEFER) 1083 goto error; 1084 else if (!ret) 1085 master->can_dma = spi_qup_can_dma; 1086 1087 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev); 1088 1089 if (!controller->qup_v1) 1090 master->set_cs = spi_qup_set_cs; 1091 1092 spin_lock_init(&controller->lock); 1093 init_completion(&controller->done); 1094 1095 iomode = readl_relaxed(base + QUP_IO_M_MODES); 1096 1097 size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode); 1098 if (size) 1099 controller->out_blk_sz = size * 16; 1100 else 1101 controller->out_blk_sz = 4; 1102 1103 size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode); 1104 if (size) 1105 controller->in_blk_sz = size * 16; 1106 else 1107 controller->in_blk_sz = 4; 1108 1109 size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode); 1110 controller->out_fifo_sz = controller->out_blk_sz * (2 << size); 1111 1112 size = QUP_IO_M_INPUT_FIFO_SIZE(iomode); 1113 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); 1114 1115 dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", 1116 controller->in_blk_sz, controller->in_fifo_sz, 1117 controller->out_blk_sz, controller->out_fifo_sz); 1118 1119 writel_relaxed(1, base + QUP_SW_RESET); 1120 1121 ret = spi_qup_set_state(controller, QUP_STATE_RESET); 1122 if (ret) { 1123 dev_err(dev, "cannot set RESET state\n"); 1124 goto error_dma; 1125 } 1126 1127 writel_relaxed(0, base + QUP_OPERATIONAL); 1128 writel_relaxed(0, base + QUP_IO_M_MODES); 1129 1130 if (!controller->qup_v1) 1131 writel_relaxed(0, base + QUP_OPERATIONAL_MASK); 1132 1133 writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN, 1134 base + SPI_ERROR_FLAGS_EN); 1135 1136 /* if earlier version of the QUP, disable INPUT_OVERRUN */ 1137 if (controller->qup_v1) 1138 writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN | 1139 QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN, 1140 base + QUP_ERROR_FLAGS_EN); 1141 1142 writel_relaxed(0, base + SPI_CONFIG); 1143 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); 1144 1145 ret = devm_request_irq(dev, irq, spi_qup_qup_irq, 1146 IRQF_TRIGGER_HIGH, pdev->name, controller); 1147 if (ret) 1148 goto error_dma; 1149 1150 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); 1151 pm_runtime_use_autosuspend(dev); 1152 pm_runtime_set_active(dev); 1153 pm_runtime_enable(dev); 1154 1155 ret = devm_spi_register_master(dev, master); 1156 if (ret) 1157 goto disable_pm; 1158 1159 return 0; 1160 1161 disable_pm: 1162 pm_runtime_disable(&pdev->dev); 1163 error_dma: 1164 spi_qup_release_dma(master); 1165 error: 1166 clk_disable_unprepare(cclk); 1167 clk_disable_unprepare(iclk); 1168 spi_master_put(master); 1169 return ret; 1170 } 1171 1172 #ifdef CONFIG_PM 1173 static int spi_qup_pm_suspend_runtime(struct device *device) 1174 { 1175 struct spi_master *master = dev_get_drvdata(device); 1176 struct spi_qup *controller = spi_master_get_devdata(master); 1177 u32 config; 1178 1179 /* Enable clocks auto gaiting */ 1180 config = readl(controller->base + QUP_CONFIG); 1181 config |= QUP_CONFIG_CLOCK_AUTO_GATE; 1182 writel_relaxed(config, controller->base + QUP_CONFIG); 1183 1184 clk_disable_unprepare(controller->cclk); 1185 clk_disable_unprepare(controller->iclk); 1186 1187 return 0; 1188 } 1189 1190 static int spi_qup_pm_resume_runtime(struct device *device) 1191 { 1192 struct spi_master *master = dev_get_drvdata(device); 1193 struct spi_qup *controller = spi_master_get_devdata(master); 1194 u32 config; 1195 int ret; 1196 1197 ret = clk_prepare_enable(controller->iclk); 1198 if (ret) 1199 return ret; 1200 1201 ret = clk_prepare_enable(controller->cclk); 1202 if (ret) 1203 return ret; 1204 1205 /* Disable clocks auto gaiting */ 1206 config = readl_relaxed(controller->base + QUP_CONFIG); 1207 config &= ~QUP_CONFIG_CLOCK_AUTO_GATE; 1208 writel_relaxed(config, controller->base + QUP_CONFIG); 1209 return 0; 1210 } 1211 #endif /* CONFIG_PM */ 1212 1213 #ifdef CONFIG_PM_SLEEP 1214 static int spi_qup_suspend(struct device *device) 1215 { 1216 struct spi_master *master = dev_get_drvdata(device); 1217 struct spi_qup *controller = spi_master_get_devdata(master); 1218 int ret; 1219 1220 ret = spi_master_suspend(master); 1221 if (ret) 1222 return ret; 1223 1224 ret = spi_qup_set_state(controller, QUP_STATE_RESET); 1225 if (ret) 1226 return ret; 1227 1228 if (!pm_runtime_suspended(device)) { 1229 clk_disable_unprepare(controller->cclk); 1230 clk_disable_unprepare(controller->iclk); 1231 } 1232 return 0; 1233 } 1234 1235 static int spi_qup_resume(struct device *device) 1236 { 1237 struct spi_master *master = dev_get_drvdata(device); 1238 struct spi_qup *controller = spi_master_get_devdata(master); 1239 int ret; 1240 1241 ret = clk_prepare_enable(controller->iclk); 1242 if (ret) 1243 return ret; 1244 1245 ret = clk_prepare_enable(controller->cclk); 1246 if (ret) 1247 return ret; 1248 1249 ret = spi_qup_set_state(controller, QUP_STATE_RESET); 1250 if (ret) 1251 return ret; 1252 1253 return spi_master_resume(master); 1254 } 1255 #endif /* CONFIG_PM_SLEEP */ 1256 1257 static int spi_qup_remove(struct platform_device *pdev) 1258 { 1259 struct spi_master *master = dev_get_drvdata(&pdev->dev); 1260 struct spi_qup *controller = spi_master_get_devdata(master); 1261 int ret; 1262 1263 ret = pm_runtime_get_sync(&pdev->dev); 1264 if (ret < 0) 1265 return ret; 1266 1267 ret = spi_qup_set_state(controller, QUP_STATE_RESET); 1268 if (ret) 1269 return ret; 1270 1271 spi_qup_release_dma(master); 1272 1273 clk_disable_unprepare(controller->cclk); 1274 clk_disable_unprepare(controller->iclk); 1275 1276 pm_runtime_put_noidle(&pdev->dev); 1277 pm_runtime_disable(&pdev->dev); 1278 1279 return 0; 1280 } 1281 1282 static const struct of_device_id spi_qup_dt_match[] = { 1283 { .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, }, 1284 { .compatible = "qcom,spi-qup-v2.1.1", }, 1285 { .compatible = "qcom,spi-qup-v2.2.1", }, 1286 { } 1287 }; 1288 MODULE_DEVICE_TABLE(of, spi_qup_dt_match); 1289 1290 static const struct dev_pm_ops spi_qup_dev_pm_ops = { 1291 SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume) 1292 SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime, 1293 spi_qup_pm_resume_runtime, 1294 NULL) 1295 }; 1296 1297 static struct platform_driver spi_qup_driver = { 1298 .driver = { 1299 .name = "spi_qup", 1300 .pm = &spi_qup_dev_pm_ops, 1301 .of_match_table = spi_qup_dt_match, 1302 }, 1303 .probe = spi_qup_probe, 1304 .remove = spi_qup_remove, 1305 }; 1306 module_platform_driver(spi_qup_driver); 1307 1308 MODULE_LICENSE("GPL v2"); 1309 MODULE_ALIAS("platform:spi_qup"); 1310