1 /* 2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3 * Copyright (C) 2013, Intel Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/ioport.h> 21 #include <linux/errno.h> 22 #include <linux/err.h> 23 #include <linux/interrupt.h> 24 #include <linux/kernel.h> 25 #include <linux/pci.h> 26 #include <linux/platform_device.h> 27 #include <linux/spi/pxa2xx_spi.h> 28 #include <linux/spi/spi.h> 29 #include <linux/delay.h> 30 #include <linux/gpio.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/clk.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/acpi.h> 36 37 #include "spi-pxa2xx.h" 38 39 MODULE_AUTHOR("Stephen Street"); 40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 41 MODULE_LICENSE("GPL"); 42 MODULE_ALIAS("platform:pxa2xx-spi"); 43 44 #define TIMOUT_DFLT 1000 45 46 /* 47 * for testing SSCR1 changes that require SSP restart, basically 48 * everything except the service and interrupt enables, the pxa270 developer 49 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 50 * list, but the PXA255 dev man says all bits without really meaning the 51 * service and interrupt enables 52 */ 53 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 54 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 55 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 56 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 57 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 59 60 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 61 | QUARK_X1000_SSCR1_EFWR \ 62 | QUARK_X1000_SSCR1_RFT \ 63 | QUARK_X1000_SSCR1_TFT \ 64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 65 66 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 67 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 68 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 69 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 70 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ 71 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 72 73 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 74 #define LPSS_CS_CONTROL_SW_MODE BIT(0) 75 #define LPSS_CS_CONTROL_CS_HIGH BIT(1) 76 #define LPSS_CAPS_CS_EN_SHIFT 9 77 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) 78 79 struct lpss_config { 80 /* LPSS offset from drv_data->ioaddr */ 81 unsigned offset; 82 /* Register offsets from drv_data->lpss_base or -1 */ 83 int reg_general; 84 int reg_ssp; 85 int reg_cs_ctrl; 86 int reg_capabilities; 87 /* FIFO thresholds */ 88 u32 rx_threshold; 89 u32 tx_threshold_lo; 90 u32 tx_threshold_hi; 91 /* Chip select control */ 92 unsigned cs_sel_shift; 93 unsigned cs_sel_mask; 94 unsigned cs_num; 95 }; 96 97 /* Keep these sorted with enum pxa_ssp_type */ 98 static const struct lpss_config lpss_platforms[] = { 99 { /* LPSS_LPT_SSP */ 100 .offset = 0x800, 101 .reg_general = 0x08, 102 .reg_ssp = 0x0c, 103 .reg_cs_ctrl = 0x18, 104 .reg_capabilities = -1, 105 .rx_threshold = 64, 106 .tx_threshold_lo = 160, 107 .tx_threshold_hi = 224, 108 }, 109 { /* LPSS_BYT_SSP */ 110 .offset = 0x400, 111 .reg_general = 0x08, 112 .reg_ssp = 0x0c, 113 .reg_cs_ctrl = 0x18, 114 .reg_capabilities = -1, 115 .rx_threshold = 64, 116 .tx_threshold_lo = 160, 117 .tx_threshold_hi = 224, 118 }, 119 { /* LPSS_BSW_SSP */ 120 .offset = 0x400, 121 .reg_general = 0x08, 122 .reg_ssp = 0x0c, 123 .reg_cs_ctrl = 0x18, 124 .reg_capabilities = -1, 125 .rx_threshold = 64, 126 .tx_threshold_lo = 160, 127 .tx_threshold_hi = 224, 128 .cs_sel_shift = 2, 129 .cs_sel_mask = 1 << 2, 130 .cs_num = 2, 131 }, 132 { /* LPSS_SPT_SSP */ 133 .offset = 0x200, 134 .reg_general = -1, 135 .reg_ssp = 0x20, 136 .reg_cs_ctrl = 0x24, 137 .reg_capabilities = -1, 138 .rx_threshold = 1, 139 .tx_threshold_lo = 32, 140 .tx_threshold_hi = 56, 141 }, 142 { /* LPSS_BXT_SSP */ 143 .offset = 0x200, 144 .reg_general = -1, 145 .reg_ssp = 0x20, 146 .reg_cs_ctrl = 0x24, 147 .reg_capabilities = 0xfc, 148 .rx_threshold = 1, 149 .tx_threshold_lo = 16, 150 .tx_threshold_hi = 48, 151 .cs_sel_shift = 8, 152 .cs_sel_mask = 3 << 8, 153 }, 154 { /* LPSS_CNL_SSP */ 155 .offset = 0x200, 156 .reg_general = -1, 157 .reg_ssp = 0x20, 158 .reg_cs_ctrl = 0x24, 159 .reg_capabilities = 0xfc, 160 .rx_threshold = 1, 161 .tx_threshold_lo = 32, 162 .tx_threshold_hi = 56, 163 .cs_sel_shift = 8, 164 .cs_sel_mask = 3 << 8, 165 }, 166 }; 167 168 static inline const struct lpss_config 169 *lpss_get_config(const struct driver_data *drv_data) 170 { 171 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; 172 } 173 174 static bool is_lpss_ssp(const struct driver_data *drv_data) 175 { 176 switch (drv_data->ssp_type) { 177 case LPSS_LPT_SSP: 178 case LPSS_BYT_SSP: 179 case LPSS_BSW_SSP: 180 case LPSS_SPT_SSP: 181 case LPSS_BXT_SSP: 182 case LPSS_CNL_SSP: 183 return true; 184 default: 185 return false; 186 } 187 } 188 189 static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 190 { 191 return drv_data->ssp_type == QUARK_X1000_SSP; 192 } 193 194 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 195 { 196 switch (drv_data->ssp_type) { 197 case QUARK_X1000_SSP: 198 return QUARK_X1000_SSCR1_CHANGE_MASK; 199 case CE4100_SSP: 200 return CE4100_SSCR1_CHANGE_MASK; 201 default: 202 return SSCR1_CHANGE_MASK; 203 } 204 } 205 206 static u32 207 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 208 { 209 switch (drv_data->ssp_type) { 210 case QUARK_X1000_SSP: 211 return RX_THRESH_QUARK_X1000_DFLT; 212 case CE4100_SSP: 213 return RX_THRESH_CE4100_DFLT; 214 default: 215 return RX_THRESH_DFLT; 216 } 217 } 218 219 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 220 { 221 u32 mask; 222 223 switch (drv_data->ssp_type) { 224 case QUARK_X1000_SSP: 225 mask = QUARK_X1000_SSSR_TFL_MASK; 226 break; 227 case CE4100_SSP: 228 mask = CE4100_SSSR_TFL_MASK; 229 break; 230 default: 231 mask = SSSR_TFL_MASK; 232 break; 233 } 234 235 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; 236 } 237 238 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 239 u32 *sccr1_reg) 240 { 241 u32 mask; 242 243 switch (drv_data->ssp_type) { 244 case QUARK_X1000_SSP: 245 mask = QUARK_X1000_SSCR1_RFT; 246 break; 247 case CE4100_SSP: 248 mask = CE4100_SSCR1_RFT; 249 break; 250 default: 251 mask = SSCR1_RFT; 252 break; 253 } 254 *sccr1_reg &= ~mask; 255 } 256 257 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 258 u32 *sccr1_reg, u32 threshold) 259 { 260 switch (drv_data->ssp_type) { 261 case QUARK_X1000_SSP: 262 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 263 break; 264 case CE4100_SSP: 265 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); 266 break; 267 default: 268 *sccr1_reg |= SSCR1_RxTresh(threshold); 269 break; 270 } 271 } 272 273 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 274 u32 clk_div, u8 bits) 275 { 276 switch (drv_data->ssp_type) { 277 case QUARK_X1000_SSP: 278 return clk_div 279 | QUARK_X1000_SSCR0_Motorola 280 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) 281 | SSCR0_SSE; 282 default: 283 return clk_div 284 | SSCR0_Motorola 285 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 286 | SSCR0_SSE 287 | (bits > 16 ? SSCR0_EDSS : 0); 288 } 289 } 290 291 /* 292 * Read and write LPSS SSP private registers. Caller must first check that 293 * is_lpss_ssp() returns true before these can be called. 294 */ 295 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 296 { 297 WARN_ON(!drv_data->lpss_base); 298 return readl(drv_data->lpss_base + offset); 299 } 300 301 static void __lpss_ssp_write_priv(struct driver_data *drv_data, 302 unsigned offset, u32 value) 303 { 304 WARN_ON(!drv_data->lpss_base); 305 writel(value, drv_data->lpss_base + offset); 306 } 307 308 /* 309 * lpss_ssp_setup - perform LPSS SSP specific setup 310 * @drv_data: pointer to the driver private data 311 * 312 * Perform LPSS SSP specific setup. This function must be called first if 313 * one is going to use LPSS SSP private registers. 314 */ 315 static void lpss_ssp_setup(struct driver_data *drv_data) 316 { 317 const struct lpss_config *config; 318 u32 value; 319 320 config = lpss_get_config(drv_data); 321 drv_data->lpss_base = drv_data->ioaddr + config->offset; 322 323 /* Enable software chip select control */ 324 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 325 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); 326 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; 327 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 328 329 /* Enable multiblock DMA transfers */ 330 if (drv_data->master_info->enable_dma) { 331 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); 332 333 if (config->reg_general >= 0) { 334 value = __lpss_ssp_read_priv(drv_data, 335 config->reg_general); 336 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; 337 __lpss_ssp_write_priv(drv_data, 338 config->reg_general, value); 339 } 340 } 341 } 342 343 static void lpss_ssp_select_cs(struct driver_data *drv_data, 344 const struct lpss_config *config) 345 { 346 u32 value, cs; 347 348 if (!config->cs_sel_mask) 349 return; 350 351 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 352 353 cs = drv_data->master->cur_msg->spi->chip_select; 354 cs <<= config->cs_sel_shift; 355 if (cs != (value & config->cs_sel_mask)) { 356 /* 357 * When switching another chip select output active the 358 * output must be selected first and wait 2 ssp_clk cycles 359 * before changing state to active. Otherwise a short 360 * glitch will occur on the previous chip select since 361 * output select is latched but state control is not. 362 */ 363 value &= ~config->cs_sel_mask; 364 value |= cs; 365 __lpss_ssp_write_priv(drv_data, 366 config->reg_cs_ctrl, value); 367 ndelay(1000000000 / 368 (drv_data->master->max_speed_hz / 2)); 369 } 370 } 371 372 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) 373 { 374 const struct lpss_config *config; 375 u32 value; 376 377 config = lpss_get_config(drv_data); 378 379 if (enable) 380 lpss_ssp_select_cs(drv_data, config); 381 382 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 383 if (enable) 384 value &= ~LPSS_CS_CONTROL_CS_HIGH; 385 else 386 value |= LPSS_CS_CONTROL_CS_HIGH; 387 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 388 } 389 390 static void cs_assert(struct driver_data *drv_data) 391 { 392 struct chip_data *chip = 393 spi_get_ctldata(drv_data->master->cur_msg->spi); 394 395 if (drv_data->ssp_type == CE4100_SSP) { 396 pxa2xx_spi_write(drv_data, SSSR, chip->frm); 397 return; 398 } 399 400 if (chip->cs_control) { 401 chip->cs_control(PXA2XX_CS_ASSERT); 402 return; 403 } 404 405 if (gpio_is_valid(chip->gpio_cs)) { 406 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 407 return; 408 } 409 410 if (is_lpss_ssp(drv_data)) 411 lpss_ssp_cs_control(drv_data, true); 412 } 413 414 static void cs_deassert(struct driver_data *drv_data) 415 { 416 struct chip_data *chip = 417 spi_get_ctldata(drv_data->master->cur_msg->spi); 418 419 if (drv_data->ssp_type == CE4100_SSP) 420 return; 421 422 if (chip->cs_control) { 423 chip->cs_control(PXA2XX_CS_DEASSERT); 424 return; 425 } 426 427 if (gpio_is_valid(chip->gpio_cs)) { 428 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 429 return; 430 } 431 432 if (is_lpss_ssp(drv_data)) 433 lpss_ssp_cs_control(drv_data, false); 434 } 435 436 int pxa2xx_spi_flush(struct driver_data *drv_data) 437 { 438 unsigned long limit = loops_per_jiffy << 1; 439 440 do { 441 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 442 pxa2xx_spi_read(drv_data, SSDR); 443 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 444 write_SSSR_CS(drv_data, SSSR_ROR); 445 446 return limit; 447 } 448 449 static int null_writer(struct driver_data *drv_data) 450 { 451 u8 n_bytes = drv_data->n_bytes; 452 453 if (pxa2xx_spi_txfifo_full(drv_data) 454 || (drv_data->tx == drv_data->tx_end)) 455 return 0; 456 457 pxa2xx_spi_write(drv_data, SSDR, 0); 458 drv_data->tx += n_bytes; 459 460 return 1; 461 } 462 463 static int null_reader(struct driver_data *drv_data) 464 { 465 u8 n_bytes = drv_data->n_bytes; 466 467 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 468 && (drv_data->rx < drv_data->rx_end)) { 469 pxa2xx_spi_read(drv_data, SSDR); 470 drv_data->rx += n_bytes; 471 } 472 473 return drv_data->rx == drv_data->rx_end; 474 } 475 476 static int u8_writer(struct driver_data *drv_data) 477 { 478 if (pxa2xx_spi_txfifo_full(drv_data) 479 || (drv_data->tx == drv_data->tx_end)) 480 return 0; 481 482 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 483 ++drv_data->tx; 484 485 return 1; 486 } 487 488 static int u8_reader(struct driver_data *drv_data) 489 { 490 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 491 && (drv_data->rx < drv_data->rx_end)) { 492 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 493 ++drv_data->rx; 494 } 495 496 return drv_data->rx == drv_data->rx_end; 497 } 498 499 static int u16_writer(struct driver_data *drv_data) 500 { 501 if (pxa2xx_spi_txfifo_full(drv_data) 502 || (drv_data->tx == drv_data->tx_end)) 503 return 0; 504 505 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 506 drv_data->tx += 2; 507 508 return 1; 509 } 510 511 static int u16_reader(struct driver_data *drv_data) 512 { 513 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 514 && (drv_data->rx < drv_data->rx_end)) { 515 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 516 drv_data->rx += 2; 517 } 518 519 return drv_data->rx == drv_data->rx_end; 520 } 521 522 static int u32_writer(struct driver_data *drv_data) 523 { 524 if (pxa2xx_spi_txfifo_full(drv_data) 525 || (drv_data->tx == drv_data->tx_end)) 526 return 0; 527 528 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 529 drv_data->tx += 4; 530 531 return 1; 532 } 533 534 static int u32_reader(struct driver_data *drv_data) 535 { 536 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 537 && (drv_data->rx < drv_data->rx_end)) { 538 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 539 drv_data->rx += 4; 540 } 541 542 return drv_data->rx == drv_data->rx_end; 543 } 544 545 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 546 { 547 struct spi_message *msg = drv_data->master->cur_msg; 548 struct spi_transfer *trans = drv_data->cur_transfer; 549 550 /* Move to next transfer */ 551 if (trans->transfer_list.next != &msg->transfers) { 552 drv_data->cur_transfer = 553 list_entry(trans->transfer_list.next, 554 struct spi_transfer, 555 transfer_list); 556 return RUNNING_STATE; 557 } else 558 return DONE_STATE; 559 } 560 561 /* caller already set message->status; dma and pio irqs are blocked */ 562 static void giveback(struct driver_data *drv_data) 563 { 564 struct spi_transfer* last_transfer; 565 struct spi_message *msg; 566 unsigned long timeout; 567 568 msg = drv_data->master->cur_msg; 569 drv_data->cur_transfer = NULL; 570 571 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, 572 transfer_list); 573 574 /* Delay if requested before any change in chip select */ 575 if (last_transfer->delay_usecs) 576 udelay(last_transfer->delay_usecs); 577 578 /* Wait until SSP becomes idle before deasserting the CS */ 579 timeout = jiffies + msecs_to_jiffies(10); 580 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && 581 !time_after(jiffies, timeout)) 582 cpu_relax(); 583 584 /* Drop chip select UNLESS cs_change is true or we are returning 585 * a message with an error, or next message is for another chip 586 */ 587 if (!last_transfer->cs_change) 588 cs_deassert(drv_data); 589 else { 590 struct spi_message *next_msg; 591 592 /* Holding of cs was hinted, but we need to make sure 593 * the next message is for the same chip. Don't waste 594 * time with the following tests unless this was hinted. 595 * 596 * We cannot postpone this until pump_messages, because 597 * after calling msg->complete (below) the driver that 598 * sent the current message could be unloaded, which 599 * could invalidate the cs_control() callback... 600 */ 601 602 /* get a pointer to the next message, if any */ 603 next_msg = spi_get_next_queued_message(drv_data->master); 604 605 /* see if the next and current messages point 606 * to the same chip 607 */ 608 if ((next_msg && next_msg->spi != msg->spi) || 609 msg->state == ERROR_STATE) 610 cs_deassert(drv_data); 611 } 612 613 spi_finalize_current_message(drv_data->master); 614 } 615 616 static void reset_sccr1(struct driver_data *drv_data) 617 { 618 struct chip_data *chip = 619 spi_get_ctldata(drv_data->master->cur_msg->spi); 620 u32 sccr1_reg; 621 622 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; 623 switch (drv_data->ssp_type) { 624 case QUARK_X1000_SSP: 625 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT; 626 break; 627 case CE4100_SSP: 628 sccr1_reg &= ~CE4100_SSCR1_RFT; 629 break; 630 default: 631 sccr1_reg &= ~SSCR1_RFT; 632 break; 633 } 634 sccr1_reg |= chip->threshold; 635 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 636 } 637 638 static void int_error_stop(struct driver_data *drv_data, const char* msg) 639 { 640 /* Stop and reset SSP */ 641 write_SSSR_CS(drv_data, drv_data->clear_sr); 642 reset_sccr1(drv_data); 643 if (!pxa25x_ssp_comp(drv_data)) 644 pxa2xx_spi_write(drv_data, SSTO, 0); 645 pxa2xx_spi_flush(drv_data); 646 pxa2xx_spi_write(drv_data, SSCR0, 647 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 648 649 dev_err(&drv_data->pdev->dev, "%s\n", msg); 650 651 drv_data->master->cur_msg->state = ERROR_STATE; 652 tasklet_schedule(&drv_data->pump_transfers); 653 } 654 655 static void int_transfer_complete(struct driver_data *drv_data) 656 { 657 /* Clear and disable interrupts */ 658 write_SSSR_CS(drv_data, drv_data->clear_sr); 659 reset_sccr1(drv_data); 660 if (!pxa25x_ssp_comp(drv_data)) 661 pxa2xx_spi_write(drv_data, SSTO, 0); 662 663 /* Update total byte transferred return count actual bytes read */ 664 drv_data->master->cur_msg->actual_length += drv_data->len - 665 (drv_data->rx_end - drv_data->rx); 666 667 /* Transfer delays and chip select release are 668 * handled in pump_transfers or giveback 669 */ 670 671 /* Move to next transfer */ 672 drv_data->master->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 673 674 /* Schedule transfer tasklet */ 675 tasklet_schedule(&drv_data->pump_transfers); 676 } 677 678 static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 679 { 680 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? 681 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 682 683 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; 684 685 if (irq_status & SSSR_ROR) { 686 int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 687 return IRQ_HANDLED; 688 } 689 690 if (irq_status & SSSR_TINT) { 691 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 692 if (drv_data->read(drv_data)) { 693 int_transfer_complete(drv_data); 694 return IRQ_HANDLED; 695 } 696 } 697 698 /* Drain rx fifo, Fill tx fifo and prevent overruns */ 699 do { 700 if (drv_data->read(drv_data)) { 701 int_transfer_complete(drv_data); 702 return IRQ_HANDLED; 703 } 704 } while (drv_data->write(drv_data)); 705 706 if (drv_data->read(drv_data)) { 707 int_transfer_complete(drv_data); 708 return IRQ_HANDLED; 709 } 710 711 if (drv_data->tx == drv_data->tx_end) { 712 u32 bytes_left; 713 u32 sccr1_reg; 714 715 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 716 sccr1_reg &= ~SSCR1_TIE; 717 718 /* 719 * PXA25x_SSP has no timeout, set up rx threshould for the 720 * remaining RX bytes. 721 */ 722 if (pxa25x_ssp_comp(drv_data)) { 723 u32 rx_thre; 724 725 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 726 727 bytes_left = drv_data->rx_end - drv_data->rx; 728 switch (drv_data->n_bytes) { 729 case 4: 730 bytes_left >>= 1; 731 case 2: 732 bytes_left >>= 1; 733 } 734 735 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 736 if (rx_thre > bytes_left) 737 rx_thre = bytes_left; 738 739 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 740 } 741 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 742 } 743 744 /* We did something */ 745 return IRQ_HANDLED; 746 } 747 748 static void handle_bad_msg(struct driver_data *drv_data) 749 { 750 pxa2xx_spi_write(drv_data, SSCR0, 751 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 752 pxa2xx_spi_write(drv_data, SSCR1, 753 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1); 754 if (!pxa25x_ssp_comp(drv_data)) 755 pxa2xx_spi_write(drv_data, SSTO, 0); 756 write_SSSR_CS(drv_data, drv_data->clear_sr); 757 758 dev_err(&drv_data->pdev->dev, 759 "bad message state in interrupt handler\n"); 760 } 761 762 static irqreturn_t ssp_int(int irq, void *dev_id) 763 { 764 struct driver_data *drv_data = dev_id; 765 u32 sccr1_reg; 766 u32 mask = drv_data->mask_sr; 767 u32 status; 768 769 /* 770 * The IRQ might be shared with other peripherals so we must first 771 * check that are we RPM suspended or not. If we are we assume that 772 * the IRQ was not for us (we shouldn't be RPM suspended when the 773 * interrupt is enabled). 774 */ 775 if (pm_runtime_suspended(&drv_data->pdev->dev)) 776 return IRQ_NONE; 777 778 /* 779 * If the device is not yet in RPM suspended state and we get an 780 * interrupt that is meant for another device, check if status bits 781 * are all set to one. That means that the device is already 782 * powered off. 783 */ 784 status = pxa2xx_spi_read(drv_data, SSSR); 785 if (status == ~0) 786 return IRQ_NONE; 787 788 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 789 790 /* Ignore possible writes if we don't need to write */ 791 if (!(sccr1_reg & SSCR1_TIE)) 792 mask &= ~SSSR_TFS; 793 794 /* Ignore RX timeout interrupt if it is disabled */ 795 if (!(sccr1_reg & SSCR1_TINTE)) 796 mask &= ~SSSR_TINT; 797 798 if (!(status & mask)) 799 return IRQ_NONE; 800 801 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); 802 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 803 804 if (!drv_data->master->cur_msg) { 805 handle_bad_msg(drv_data); 806 /* Never fail */ 807 return IRQ_HANDLED; 808 } 809 810 return drv_data->transfer_handler(drv_data); 811 } 812 813 /* 814 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply 815 * input frequency by fractions of 2^24. It also has a divider by 5. 816 * 817 * There are formulas to get baud rate value for given input frequency and 818 * divider parameters, such as DDS_CLK_RATE and SCR: 819 * 820 * Fsys = 200MHz 821 * 822 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) 823 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) 824 * 825 * DDS_CLK_RATE either 2^n or 2^n / 5. 826 * SCR is in range 0 .. 255 827 * 828 * Divisor = 5^i * 2^j * 2 * k 829 * i = [0, 1] i = 1 iff j = 0 or j > 3 830 * j = [0, 23] j = 0 iff i = 1 831 * k = [1, 256] 832 * Special case: j = 0, i = 1: Divisor = 2 / 5 833 * 834 * Accordingly to the specification the recommended values for DDS_CLK_RATE 835 * are: 836 * Case 1: 2^n, n = [0, 23] 837 * Case 2: 2^24 * 2 / 5 (0x666666) 838 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) 839 * 840 * In all cases the lowest possible value is better. 841 * 842 * The function calculates parameters for all cases and chooses the one closest 843 * to the asked baud rate. 844 */ 845 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 846 { 847 unsigned long xtal = 200000000; 848 unsigned long fref = xtal / 2; /* mandatory division by 2, 849 see (2) */ 850 /* case 3 */ 851 unsigned long fref1 = fref / 2; /* case 1 */ 852 unsigned long fref2 = fref * 2 / 5; /* case 2 */ 853 unsigned long scale; 854 unsigned long q, q1, q2; 855 long r, r1, r2; 856 u32 mul; 857 858 /* Case 1 */ 859 860 /* Set initial value for DDS_CLK_RATE */ 861 mul = (1 << 24) >> 1; 862 863 /* Calculate initial quot */ 864 q1 = DIV_ROUND_UP(fref1, rate); 865 866 /* Scale q1 if it's too big */ 867 if (q1 > 256) { 868 /* Scale q1 to range [1, 512] */ 869 scale = fls_long(q1 - 1); 870 if (scale > 9) { 871 q1 >>= scale - 9; 872 mul >>= scale - 9; 873 } 874 875 /* Round the result if we have a remainder */ 876 q1 += q1 & 1; 877 } 878 879 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ 880 scale = __ffs(q1); 881 q1 >>= scale; 882 mul >>= scale; 883 884 /* Get the remainder */ 885 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); 886 887 /* Case 2 */ 888 889 q2 = DIV_ROUND_UP(fref2, rate); 890 r2 = abs(fref2 / q2 - rate); 891 892 /* 893 * Choose the best between two: less remainder we have the better. We 894 * can't go case 2 if q2 is greater than 256 since SCR register can 895 * hold only values 0 .. 255. 896 */ 897 if (r2 >= r1 || q2 > 256) { 898 /* case 1 is better */ 899 r = r1; 900 q = q1; 901 } else { 902 /* case 2 is better */ 903 r = r2; 904 q = q2; 905 mul = (1 << 24) * 2 / 5; 906 } 907 908 /* Check case 3 only if the divisor is big enough */ 909 if (fref / rate >= 80) { 910 u64 fssp; 911 u32 m; 912 913 /* Calculate initial quot */ 914 q1 = DIV_ROUND_UP(fref, rate); 915 m = (1 << 24) / q1; 916 917 /* Get the remainder */ 918 fssp = (u64)fref * m; 919 do_div(fssp, 1 << 24); 920 r1 = abs(fssp - rate); 921 922 /* Choose this one if it suits better */ 923 if (r1 < r) { 924 /* case 3 is better */ 925 q = 1; 926 mul = m; 927 } 928 } 929 930 *dds = mul; 931 return q - 1; 932 } 933 934 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 935 { 936 unsigned long ssp_clk = drv_data->master->max_speed_hz; 937 const struct ssp_device *ssp = drv_data->ssp; 938 939 rate = min_t(int, ssp_clk, rate); 940 941 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 942 return (ssp_clk / (2 * rate) - 1) & 0xff; 943 else 944 return (ssp_clk / rate - 1) & 0xfff; 945 } 946 947 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 948 int rate) 949 { 950 struct chip_data *chip = 951 spi_get_ctldata(drv_data->master->cur_msg->spi); 952 unsigned int clk_div; 953 954 switch (drv_data->ssp_type) { 955 case QUARK_X1000_SSP: 956 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); 957 break; 958 default: 959 clk_div = ssp_get_clk_div(drv_data, rate); 960 break; 961 } 962 return clk_div << 8; 963 } 964 965 static bool pxa2xx_spi_can_dma(struct spi_master *master, 966 struct spi_device *spi, 967 struct spi_transfer *xfer) 968 { 969 struct chip_data *chip = spi_get_ctldata(spi); 970 971 return chip->enable_dma && 972 xfer->len <= MAX_DMA_LEN && 973 xfer->len >= chip->dma_burst_size; 974 } 975 976 static void pump_transfers(unsigned long data) 977 { 978 struct driver_data *drv_data = (struct driver_data *)data; 979 struct spi_master *master = drv_data->master; 980 struct spi_message *message = master->cur_msg; 981 struct chip_data *chip = spi_get_ctldata(message->spi); 982 u32 dma_thresh = chip->dma_threshold; 983 u32 dma_burst = chip->dma_burst_size; 984 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 985 struct spi_transfer *transfer; 986 struct spi_transfer *previous; 987 u32 clk_div; 988 u8 bits; 989 u32 speed; 990 u32 cr0; 991 u32 cr1; 992 int err; 993 int dma_mapped; 994 995 /* Get current state information */ 996 transfer = drv_data->cur_transfer; 997 998 /* Handle for abort */ 999 if (message->state == ERROR_STATE) { 1000 message->status = -EIO; 1001 giveback(drv_data); 1002 return; 1003 } 1004 1005 /* Handle end of message */ 1006 if (message->state == DONE_STATE) { 1007 message->status = 0; 1008 giveback(drv_data); 1009 return; 1010 } 1011 1012 /* Delay if requested at end of transfer before CS change */ 1013 if (message->state == RUNNING_STATE) { 1014 previous = list_entry(transfer->transfer_list.prev, 1015 struct spi_transfer, 1016 transfer_list); 1017 if (previous->delay_usecs) 1018 udelay(previous->delay_usecs); 1019 1020 /* Drop chip select only if cs_change is requested */ 1021 if (previous->cs_change) 1022 cs_deassert(drv_data); 1023 } 1024 1025 /* Check if we can DMA this transfer */ 1026 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { 1027 1028 /* reject already-mapped transfers; PIO won't always work */ 1029 if (message->is_dma_mapped 1030 || transfer->rx_dma || transfer->tx_dma) { 1031 dev_err(&drv_data->pdev->dev, 1032 "pump_transfers: mapped transfer length of " 1033 "%u is greater than %d\n", 1034 transfer->len, MAX_DMA_LEN); 1035 message->status = -EINVAL; 1036 giveback(drv_data); 1037 return; 1038 } 1039 1040 /* warn ... we force this to PIO mode */ 1041 dev_warn_ratelimited(&message->spi->dev, 1042 "pump_transfers: DMA disabled for transfer length %ld " 1043 "greater than %d\n", 1044 (long)drv_data->len, MAX_DMA_LEN); 1045 } 1046 1047 /* Setup the transfer state based on the type of transfer */ 1048 if (pxa2xx_spi_flush(drv_data) == 0) { 1049 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 1050 message->status = -EIO; 1051 giveback(drv_data); 1052 return; 1053 } 1054 drv_data->n_bytes = chip->n_bytes; 1055 drv_data->tx = (void *)transfer->tx_buf; 1056 drv_data->tx_end = drv_data->tx + transfer->len; 1057 drv_data->rx = transfer->rx_buf; 1058 drv_data->rx_end = drv_data->rx + transfer->len; 1059 drv_data->len = transfer->len; 1060 drv_data->write = drv_data->tx ? chip->write : null_writer; 1061 drv_data->read = drv_data->rx ? chip->read : null_reader; 1062 1063 /* Change speed and bit per word on a per transfer */ 1064 bits = transfer->bits_per_word; 1065 speed = transfer->speed_hz; 1066 1067 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); 1068 1069 if (bits <= 8) { 1070 drv_data->n_bytes = 1; 1071 drv_data->read = drv_data->read != null_reader ? 1072 u8_reader : null_reader; 1073 drv_data->write = drv_data->write != null_writer ? 1074 u8_writer : null_writer; 1075 } else if (bits <= 16) { 1076 drv_data->n_bytes = 2; 1077 drv_data->read = drv_data->read != null_reader ? 1078 u16_reader : null_reader; 1079 drv_data->write = drv_data->write != null_writer ? 1080 u16_writer : null_writer; 1081 } else if (bits <= 32) { 1082 drv_data->n_bytes = 4; 1083 drv_data->read = drv_data->read != null_reader ? 1084 u32_reader : null_reader; 1085 drv_data->write = drv_data->write != null_writer ? 1086 u32_writer : null_writer; 1087 } 1088 /* 1089 * if bits/word is changed in dma mode, then must check the 1090 * thresholds and burst also 1091 */ 1092 if (chip->enable_dma) { 1093 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 1094 message->spi, 1095 bits, &dma_burst, 1096 &dma_thresh)) 1097 dev_warn_ratelimited(&message->spi->dev, 1098 "pump_transfers: DMA burst size reduced to match bits_per_word\n"); 1099 } 1100 1101 message->state = RUNNING_STATE; 1102 1103 dma_mapped = master->can_dma && 1104 master->can_dma(master, message->spi, transfer) && 1105 master->cur_msg_mapped; 1106 if (dma_mapped) { 1107 1108 /* Ensure we have the correct interrupt handler */ 1109 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 1110 1111 err = pxa2xx_spi_dma_prepare(drv_data, dma_burst); 1112 if (err) { 1113 message->status = err; 1114 giveback(drv_data); 1115 return; 1116 } 1117 1118 /* Clear status and start DMA engine */ 1119 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 1120 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 1121 1122 pxa2xx_spi_dma_start(drv_data); 1123 } else { 1124 /* Ensure we have the correct interrupt handler */ 1125 drv_data->transfer_handler = interrupt_transfer; 1126 1127 /* Clear status */ 1128 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 1129 write_SSSR_CS(drv_data, drv_data->clear_sr); 1130 } 1131 1132 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1133 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 1134 if (!pxa25x_ssp_comp(drv_data)) 1135 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", 1136 master->max_speed_hz 1137 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), 1138 dma_mapped ? "DMA" : "PIO"); 1139 else 1140 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", 1141 master->max_speed_hz / 2 1142 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1143 dma_mapped ? "DMA" : "PIO"); 1144 1145 if (is_lpss_ssp(drv_data)) { 1146 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) 1147 != chip->lpss_rx_threshold) 1148 pxa2xx_spi_write(drv_data, SSIRF, 1149 chip->lpss_rx_threshold); 1150 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) 1151 != chip->lpss_tx_threshold) 1152 pxa2xx_spi_write(drv_data, SSITF, 1153 chip->lpss_tx_threshold); 1154 } 1155 1156 if (is_quark_x1000_ssp(drv_data) && 1157 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) 1158 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); 1159 1160 /* see if we need to reload the config registers */ 1161 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) 1162 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) 1163 != (cr1 & change_mask)) { 1164 /* stop the SSP, and update the other bits */ 1165 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); 1166 if (!pxa25x_ssp_comp(drv_data)) 1167 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1168 /* first set CR1 without interrupt and service enables */ 1169 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); 1170 /* restart the SSP */ 1171 pxa2xx_spi_write(drv_data, SSCR0, cr0); 1172 1173 } else { 1174 if (!pxa25x_ssp_comp(drv_data)) 1175 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1176 } 1177 1178 cs_assert(drv_data); 1179 1180 /* after chip select, release the data by enabling service 1181 * requests and interrupts, without changing any mode bits */ 1182 pxa2xx_spi_write(drv_data, SSCR1, cr1); 1183 } 1184 1185 static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 1186 struct spi_message *msg) 1187 { 1188 struct driver_data *drv_data = spi_master_get_devdata(master); 1189 1190 /* Initial message state*/ 1191 msg->state = START_STATE; 1192 drv_data->cur_transfer = list_entry(msg->transfers.next, 1193 struct spi_transfer, 1194 transfer_list); 1195 1196 /* Mark as busy and launch transfers */ 1197 tasklet_schedule(&drv_data->pump_transfers); 1198 return 0; 1199 } 1200 1201 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) 1202 { 1203 struct driver_data *drv_data = spi_master_get_devdata(master); 1204 1205 /* Disable the SSP now */ 1206 pxa2xx_spi_write(drv_data, SSCR0, 1207 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1208 1209 return 0; 1210 } 1211 1212 static int setup_cs(struct spi_device *spi, struct chip_data *chip, 1213 struct pxa2xx_spi_chip *chip_info) 1214 { 1215 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1216 int err = 0; 1217 1218 if (chip == NULL) 1219 return 0; 1220 1221 if (drv_data->cs_gpiods) { 1222 struct gpio_desc *gpiod; 1223 1224 gpiod = drv_data->cs_gpiods[spi->chip_select]; 1225 if (gpiod) { 1226 chip->gpio_cs = desc_to_gpio(gpiod); 1227 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1228 gpiod_set_value(gpiod, chip->gpio_cs_inverted); 1229 } 1230 1231 return 0; 1232 } 1233 1234 if (chip_info == NULL) 1235 return 0; 1236 1237 /* NOTE: setup() can be called multiple times, possibly with 1238 * different chip_info, release previously requested GPIO 1239 */ 1240 if (gpio_is_valid(chip->gpio_cs)) 1241 gpio_free(chip->gpio_cs); 1242 1243 /* If (*cs_control) is provided, ignore GPIO chip select */ 1244 if (chip_info->cs_control) { 1245 chip->cs_control = chip_info->cs_control; 1246 return 0; 1247 } 1248 1249 if (gpio_is_valid(chip_info->gpio_cs)) { 1250 err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1251 if (err) { 1252 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 1253 chip_info->gpio_cs); 1254 return err; 1255 } 1256 1257 chip->gpio_cs = chip_info->gpio_cs; 1258 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1259 1260 err = gpio_direction_output(chip->gpio_cs, 1261 !chip->gpio_cs_inverted); 1262 } 1263 1264 return err; 1265 } 1266 1267 static int setup(struct spi_device *spi) 1268 { 1269 struct pxa2xx_spi_chip *chip_info; 1270 struct chip_data *chip; 1271 const struct lpss_config *config; 1272 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1273 uint tx_thres, tx_hi_thres, rx_thres; 1274 1275 switch (drv_data->ssp_type) { 1276 case QUARK_X1000_SSP: 1277 tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1278 tx_hi_thres = 0; 1279 rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1280 break; 1281 case CE4100_SSP: 1282 tx_thres = TX_THRESH_CE4100_DFLT; 1283 tx_hi_thres = 0; 1284 rx_thres = RX_THRESH_CE4100_DFLT; 1285 break; 1286 case LPSS_LPT_SSP: 1287 case LPSS_BYT_SSP: 1288 case LPSS_BSW_SSP: 1289 case LPSS_SPT_SSP: 1290 case LPSS_BXT_SSP: 1291 case LPSS_CNL_SSP: 1292 config = lpss_get_config(drv_data); 1293 tx_thres = config->tx_threshold_lo; 1294 tx_hi_thres = config->tx_threshold_hi; 1295 rx_thres = config->rx_threshold; 1296 break; 1297 default: 1298 tx_thres = TX_THRESH_DFLT; 1299 tx_hi_thres = 0; 1300 rx_thres = RX_THRESH_DFLT; 1301 break; 1302 } 1303 1304 /* Only alloc on first setup */ 1305 chip = spi_get_ctldata(spi); 1306 if (!chip) { 1307 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1308 if (!chip) 1309 return -ENOMEM; 1310 1311 if (drv_data->ssp_type == CE4100_SSP) { 1312 if (spi->chip_select > 4) { 1313 dev_err(&spi->dev, 1314 "failed setup: cs number must not be > 4.\n"); 1315 kfree(chip); 1316 return -EINVAL; 1317 } 1318 1319 chip->frm = spi->chip_select; 1320 } else 1321 chip->gpio_cs = -1; 1322 chip->enable_dma = drv_data->master_info->enable_dma; 1323 chip->timeout = TIMOUT_DFLT; 1324 } 1325 1326 /* protocol drivers may change the chip settings, so... 1327 * if chip_info exists, use it */ 1328 chip_info = spi->controller_data; 1329 1330 /* chip_info isn't always needed */ 1331 chip->cr1 = 0; 1332 if (chip_info) { 1333 if (chip_info->timeout) 1334 chip->timeout = chip_info->timeout; 1335 if (chip_info->tx_threshold) 1336 tx_thres = chip_info->tx_threshold; 1337 if (chip_info->tx_hi_threshold) 1338 tx_hi_thres = chip_info->tx_hi_threshold; 1339 if (chip_info->rx_threshold) 1340 rx_thres = chip_info->rx_threshold; 1341 chip->dma_threshold = 0; 1342 if (chip_info->enable_loopback) 1343 chip->cr1 = SSCR1_LBM; 1344 } 1345 1346 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1347 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 1348 | SSITF_TxHiThresh(tx_hi_thres); 1349 1350 /* set dma burst and threshold outside of chip_info path so that if 1351 * chip_info goes away after setting chip->enable_dma, the 1352 * burst and threshold can still respond to changes in bits_per_word */ 1353 if (chip->enable_dma) { 1354 /* set up legal burst and threshold for dma */ 1355 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1356 spi->bits_per_word, 1357 &chip->dma_burst_size, 1358 &chip->dma_threshold)) { 1359 dev_warn(&spi->dev, 1360 "in setup: DMA burst size reduced to match bits_per_word\n"); 1361 } 1362 } 1363 1364 switch (drv_data->ssp_type) { 1365 case QUARK_X1000_SSP: 1366 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1367 & QUARK_X1000_SSCR1_RFT) 1368 | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1369 & QUARK_X1000_SSCR1_TFT); 1370 break; 1371 case CE4100_SSP: 1372 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | 1373 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); 1374 break; 1375 default: 1376 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1377 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1378 break; 1379 } 1380 1381 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1382 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1383 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1384 1385 if (spi->mode & SPI_LOOP) 1386 chip->cr1 |= SSCR1_LBM; 1387 1388 if (spi->bits_per_word <= 8) { 1389 chip->n_bytes = 1; 1390 chip->read = u8_reader; 1391 chip->write = u8_writer; 1392 } else if (spi->bits_per_word <= 16) { 1393 chip->n_bytes = 2; 1394 chip->read = u16_reader; 1395 chip->write = u16_writer; 1396 } else if (spi->bits_per_word <= 32) { 1397 chip->n_bytes = 4; 1398 chip->read = u32_reader; 1399 chip->write = u32_writer; 1400 } 1401 1402 spi_set_ctldata(spi, chip); 1403 1404 if (drv_data->ssp_type == CE4100_SSP) 1405 return 0; 1406 1407 return setup_cs(spi, chip, chip_info); 1408 } 1409 1410 static void cleanup(struct spi_device *spi) 1411 { 1412 struct chip_data *chip = spi_get_ctldata(spi); 1413 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1414 1415 if (!chip) 1416 return; 1417 1418 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && 1419 gpio_is_valid(chip->gpio_cs)) 1420 gpio_free(chip->gpio_cs); 1421 1422 kfree(chip); 1423 } 1424 1425 #ifdef CONFIG_PCI 1426 #ifdef CONFIG_ACPI 1427 1428 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1429 { "INT33C0", LPSS_LPT_SSP }, 1430 { "INT33C1", LPSS_LPT_SSP }, 1431 { "INT3430", LPSS_LPT_SSP }, 1432 { "INT3431", LPSS_LPT_SSP }, 1433 { "80860F0E", LPSS_BYT_SSP }, 1434 { "8086228E", LPSS_BSW_SSP }, 1435 { }, 1436 }; 1437 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1438 1439 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1440 { 1441 unsigned int devid; 1442 int port_id = -1; 1443 1444 if (adev && adev->pnp.unique_id && 1445 !kstrtouint(adev->pnp.unique_id, 0, &devid)) 1446 port_id = devid; 1447 return port_id; 1448 } 1449 #else /* !CONFIG_ACPI */ 1450 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1451 { 1452 return -1; 1453 } 1454 #endif 1455 1456 /* 1457 * PCI IDs of compound devices that integrate both host controller and private 1458 * integrated DMA engine. Please note these are not used in module 1459 * autoloading and probing in this module but matching the LPSS SSP type. 1460 */ 1461 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { 1462 /* SPT-LP */ 1463 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, 1464 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, 1465 /* SPT-H */ 1466 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, 1467 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, 1468 /* KBL-H */ 1469 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, 1470 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, 1471 /* BXT A-Step */ 1472 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, 1473 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, 1474 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, 1475 /* BXT B-Step */ 1476 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, 1477 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, 1478 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, 1479 /* GLK */ 1480 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, 1481 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, 1482 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, 1483 /* APL */ 1484 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, 1485 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, 1486 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, 1487 /* CNL-LP */ 1488 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, 1489 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, 1490 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP }, 1491 /* CNL-H */ 1492 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP }, 1493 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP }, 1494 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP }, 1495 { }, 1496 }; 1497 1498 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) 1499 { 1500 struct device *dev = param; 1501 1502 if (dev != chan->device->dev->parent) 1503 return false; 1504 1505 return true; 1506 } 1507 1508 static struct pxa2xx_spi_master * 1509 pxa2xx_spi_init_pdata(struct platform_device *pdev) 1510 { 1511 struct pxa2xx_spi_master *pdata; 1512 struct acpi_device *adev; 1513 struct ssp_device *ssp; 1514 struct resource *res; 1515 const struct acpi_device_id *adev_id = NULL; 1516 const struct pci_device_id *pcidev_id = NULL; 1517 int type; 1518 1519 adev = ACPI_COMPANION(&pdev->dev); 1520 1521 if (dev_is_pci(pdev->dev.parent)) 1522 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, 1523 to_pci_dev(pdev->dev.parent)); 1524 else if (adev) 1525 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 1526 &pdev->dev); 1527 else 1528 return NULL; 1529 1530 if (adev_id) 1531 type = (int)adev_id->driver_data; 1532 else if (pcidev_id) 1533 type = (int)pcidev_id->driver_data; 1534 else 1535 return NULL; 1536 1537 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1538 if (!pdata) 1539 return NULL; 1540 1541 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1542 if (!res) 1543 return NULL; 1544 1545 ssp = &pdata->ssp; 1546 1547 ssp->phys_base = res->start; 1548 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1549 if (IS_ERR(ssp->mmio_base)) 1550 return NULL; 1551 1552 if (pcidev_id) { 1553 pdata->tx_param = pdev->dev.parent; 1554 pdata->rx_param = pdev->dev.parent; 1555 pdata->dma_filter = pxa2xx_spi_idma_filter; 1556 } 1557 1558 ssp->clk = devm_clk_get(&pdev->dev, NULL); 1559 ssp->irq = platform_get_irq(pdev, 0); 1560 ssp->type = type; 1561 ssp->pdev = pdev; 1562 ssp->port_id = pxa2xx_spi_get_port_id(adev); 1563 1564 pdata->num_chipselect = 1; 1565 pdata->enable_dma = true; 1566 1567 return pdata; 1568 } 1569 1570 #else /* !CONFIG_PCI */ 1571 static inline struct pxa2xx_spi_master * 1572 pxa2xx_spi_init_pdata(struct platform_device *pdev) 1573 { 1574 return NULL; 1575 } 1576 #endif 1577 1578 static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs) 1579 { 1580 struct driver_data *drv_data = spi_master_get_devdata(master); 1581 1582 if (has_acpi_companion(&drv_data->pdev->dev)) { 1583 switch (drv_data->ssp_type) { 1584 /* 1585 * For Atoms the ACPI DeviceSelection used by the Windows 1586 * driver starts from 1 instead of 0 so translate it here 1587 * to match what Linux expects. 1588 */ 1589 case LPSS_BYT_SSP: 1590 case LPSS_BSW_SSP: 1591 return cs - 1; 1592 1593 default: 1594 break; 1595 } 1596 } 1597 1598 return cs; 1599 } 1600 1601 static int pxa2xx_spi_probe(struct platform_device *pdev) 1602 { 1603 struct device *dev = &pdev->dev; 1604 struct pxa2xx_spi_master *platform_info; 1605 struct spi_master *master; 1606 struct driver_data *drv_data; 1607 struct ssp_device *ssp; 1608 const struct lpss_config *config; 1609 int status, count; 1610 u32 tmp; 1611 1612 platform_info = dev_get_platdata(dev); 1613 if (!platform_info) { 1614 platform_info = pxa2xx_spi_init_pdata(pdev); 1615 if (!platform_info) { 1616 dev_err(&pdev->dev, "missing platform data\n"); 1617 return -ENODEV; 1618 } 1619 } 1620 1621 ssp = pxa_ssp_request(pdev->id, pdev->name); 1622 if (!ssp) 1623 ssp = &platform_info->ssp; 1624 1625 if (!ssp->mmio_base) { 1626 dev_err(&pdev->dev, "failed to get ssp\n"); 1627 return -ENODEV; 1628 } 1629 1630 master = spi_alloc_master(dev, sizeof(struct driver_data)); 1631 if (!master) { 1632 dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1633 pxa_ssp_free(ssp); 1634 return -ENOMEM; 1635 } 1636 drv_data = spi_master_get_devdata(master); 1637 drv_data->master = master; 1638 drv_data->master_info = platform_info; 1639 drv_data->pdev = pdev; 1640 drv_data->ssp = ssp; 1641 1642 master->dev.of_node = pdev->dev.of_node; 1643 /* the spi->mode bits understood by this driver: */ 1644 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1645 1646 master->bus_num = ssp->port_id; 1647 master->dma_alignment = DMA_ALIGNMENT; 1648 master->cleanup = cleanup; 1649 master->setup = setup; 1650 master->transfer_one_message = pxa2xx_spi_transfer_one_message; 1651 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1652 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs; 1653 master->auto_runtime_pm = true; 1654 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; 1655 1656 drv_data->ssp_type = ssp->type; 1657 1658 drv_data->ioaddr = ssp->mmio_base; 1659 drv_data->ssdr_physical = ssp->phys_base + SSDR; 1660 if (pxa25x_ssp_comp(drv_data)) { 1661 switch (drv_data->ssp_type) { 1662 case QUARK_X1000_SSP: 1663 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1664 break; 1665 default: 1666 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1667 break; 1668 } 1669 1670 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1671 drv_data->dma_cr1 = 0; 1672 drv_data->clear_sr = SSSR_ROR; 1673 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1674 } else { 1675 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1676 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1677 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1678 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1679 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1680 } 1681 1682 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1683 drv_data); 1684 if (status < 0) { 1685 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1686 goto out_error_master_alloc; 1687 } 1688 1689 /* Setup DMA if requested */ 1690 if (platform_info->enable_dma) { 1691 status = pxa2xx_spi_dma_setup(drv_data); 1692 if (status) { 1693 dev_dbg(dev, "no DMA channels available, using PIO\n"); 1694 platform_info->enable_dma = false; 1695 } else { 1696 master->can_dma = pxa2xx_spi_can_dma; 1697 } 1698 } 1699 1700 /* Enable SOC clock */ 1701 clk_prepare_enable(ssp->clk); 1702 1703 master->max_speed_hz = clk_get_rate(ssp->clk); 1704 1705 /* Load default SSP configuration */ 1706 pxa2xx_spi_write(drv_data, SSCR0, 0); 1707 switch (drv_data->ssp_type) { 1708 case QUARK_X1000_SSP: 1709 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | 1710 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1711 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1712 1713 /* using the Motorola SPI protocol and use 8 bit frame */ 1714 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); 1715 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1716 break; 1717 case CE4100_SSP: 1718 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | 1719 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); 1720 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1721 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1722 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1723 break; 1724 default: 1725 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1726 SSCR1_TxTresh(TX_THRESH_DFLT); 1727 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1728 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1729 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1730 break; 1731 } 1732 1733 if (!pxa25x_ssp_comp(drv_data)) 1734 pxa2xx_spi_write(drv_data, SSTO, 0); 1735 1736 if (!is_quark_x1000_ssp(drv_data)) 1737 pxa2xx_spi_write(drv_data, SSPSP, 0); 1738 1739 if (is_lpss_ssp(drv_data)) { 1740 lpss_ssp_setup(drv_data); 1741 config = lpss_get_config(drv_data); 1742 if (config->reg_capabilities >= 0) { 1743 tmp = __lpss_ssp_read_priv(drv_data, 1744 config->reg_capabilities); 1745 tmp &= LPSS_CAPS_CS_EN_MASK; 1746 tmp >>= LPSS_CAPS_CS_EN_SHIFT; 1747 platform_info->num_chipselect = ffz(tmp); 1748 } else if (config->cs_num) { 1749 platform_info->num_chipselect = config->cs_num; 1750 } 1751 } 1752 master->num_chipselect = platform_info->num_chipselect; 1753 1754 count = gpiod_count(&pdev->dev, "cs"); 1755 if (count > 0) { 1756 int i; 1757 1758 master->num_chipselect = max_t(int, count, 1759 master->num_chipselect); 1760 1761 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev, 1762 master->num_chipselect, sizeof(struct gpio_desc *), 1763 GFP_KERNEL); 1764 if (!drv_data->cs_gpiods) { 1765 status = -ENOMEM; 1766 goto out_error_clock_enabled; 1767 } 1768 1769 for (i = 0; i < master->num_chipselect; i++) { 1770 struct gpio_desc *gpiod; 1771 1772 gpiod = devm_gpiod_get_index(dev, "cs", i, 1773 GPIOD_OUT_HIGH); 1774 if (IS_ERR(gpiod)) { 1775 /* Means use native chip select */ 1776 if (PTR_ERR(gpiod) == -ENOENT) 1777 continue; 1778 1779 status = (int)PTR_ERR(gpiod); 1780 goto out_error_clock_enabled; 1781 } else { 1782 drv_data->cs_gpiods[i] = gpiod; 1783 } 1784 } 1785 } 1786 1787 tasklet_init(&drv_data->pump_transfers, pump_transfers, 1788 (unsigned long)drv_data); 1789 1790 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1791 pm_runtime_use_autosuspend(&pdev->dev); 1792 pm_runtime_set_active(&pdev->dev); 1793 pm_runtime_enable(&pdev->dev); 1794 1795 /* Register with the SPI framework */ 1796 platform_set_drvdata(pdev, drv_data); 1797 status = devm_spi_register_master(&pdev->dev, master); 1798 if (status != 0) { 1799 dev_err(&pdev->dev, "problem registering spi master\n"); 1800 goto out_error_clock_enabled; 1801 } 1802 1803 return status; 1804 1805 out_error_clock_enabled: 1806 clk_disable_unprepare(ssp->clk); 1807 pxa2xx_spi_dma_release(drv_data); 1808 free_irq(ssp->irq, drv_data); 1809 1810 out_error_master_alloc: 1811 spi_master_put(master); 1812 pxa_ssp_free(ssp); 1813 return status; 1814 } 1815 1816 static int pxa2xx_spi_remove(struct platform_device *pdev) 1817 { 1818 struct driver_data *drv_data = platform_get_drvdata(pdev); 1819 struct ssp_device *ssp; 1820 1821 if (!drv_data) 1822 return 0; 1823 ssp = drv_data->ssp; 1824 1825 pm_runtime_get_sync(&pdev->dev); 1826 1827 /* Disable the SSP at the peripheral and SOC level */ 1828 pxa2xx_spi_write(drv_data, SSCR0, 0); 1829 clk_disable_unprepare(ssp->clk); 1830 1831 /* Release DMA */ 1832 if (drv_data->master_info->enable_dma) 1833 pxa2xx_spi_dma_release(drv_data); 1834 1835 pm_runtime_put_noidle(&pdev->dev); 1836 pm_runtime_disable(&pdev->dev); 1837 1838 /* Release IRQ */ 1839 free_irq(ssp->irq, drv_data); 1840 1841 /* Release SSP */ 1842 pxa_ssp_free(ssp); 1843 1844 return 0; 1845 } 1846 1847 static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1848 { 1849 int status = 0; 1850 1851 if ((status = pxa2xx_spi_remove(pdev)) != 0) 1852 dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1853 } 1854 1855 #ifdef CONFIG_PM_SLEEP 1856 static int pxa2xx_spi_suspend(struct device *dev) 1857 { 1858 struct driver_data *drv_data = dev_get_drvdata(dev); 1859 struct ssp_device *ssp = drv_data->ssp; 1860 int status; 1861 1862 status = spi_master_suspend(drv_data->master); 1863 if (status != 0) 1864 return status; 1865 pxa2xx_spi_write(drv_data, SSCR0, 0); 1866 1867 if (!pm_runtime_suspended(dev)) 1868 clk_disable_unprepare(ssp->clk); 1869 1870 return 0; 1871 } 1872 1873 static int pxa2xx_spi_resume(struct device *dev) 1874 { 1875 struct driver_data *drv_data = dev_get_drvdata(dev); 1876 struct ssp_device *ssp = drv_data->ssp; 1877 int status; 1878 1879 /* Enable the SSP clock */ 1880 if (!pm_runtime_suspended(dev)) 1881 clk_prepare_enable(ssp->clk); 1882 1883 /* Restore LPSS private register bits */ 1884 if (is_lpss_ssp(drv_data)) 1885 lpss_ssp_setup(drv_data); 1886 1887 /* Start the queue running */ 1888 status = spi_master_resume(drv_data->master); 1889 if (status != 0) { 1890 dev_err(dev, "problem starting queue (%d)\n", status); 1891 return status; 1892 } 1893 1894 return 0; 1895 } 1896 #endif 1897 1898 #ifdef CONFIG_PM 1899 static int pxa2xx_spi_runtime_suspend(struct device *dev) 1900 { 1901 struct driver_data *drv_data = dev_get_drvdata(dev); 1902 1903 clk_disable_unprepare(drv_data->ssp->clk); 1904 return 0; 1905 } 1906 1907 static int pxa2xx_spi_runtime_resume(struct device *dev) 1908 { 1909 struct driver_data *drv_data = dev_get_drvdata(dev); 1910 1911 clk_prepare_enable(drv_data->ssp->clk); 1912 return 0; 1913 } 1914 #endif 1915 1916 static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1917 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1918 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 1919 pxa2xx_spi_runtime_resume, NULL) 1920 }; 1921 1922 static struct platform_driver driver = { 1923 .driver = { 1924 .name = "pxa2xx-spi", 1925 .pm = &pxa2xx_spi_pm_ops, 1926 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1927 }, 1928 .probe = pxa2xx_spi_probe, 1929 .remove = pxa2xx_spi_remove, 1930 .shutdown = pxa2xx_spi_shutdown, 1931 }; 1932 1933 static int __init pxa2xx_spi_init(void) 1934 { 1935 return platform_driver_register(&driver); 1936 } 1937 subsys_initcall(pxa2xx_spi_init); 1938 1939 static void __exit pxa2xx_spi_exit(void) 1940 { 1941 platform_driver_unregister(&driver); 1942 } 1943 module_exit(pxa2xx_spi_exit); 1944