1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 4 * Copyright (C) 2013, 2021 Intel Corporation 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/dmaengine.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/ioport.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/of.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/property.h> 27 #include <linux/slab.h> 28 29 #include <linux/spi/pxa2xx_spi.h> 30 #include <linux/spi/spi.h> 31 32 #include "spi-pxa2xx.h" 33 34 MODULE_AUTHOR("Stephen Street"); 35 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 36 MODULE_LICENSE("GPL"); 37 MODULE_ALIAS("platform:pxa2xx-spi"); 38 39 #define TIMOUT_DFLT 1000 40 41 /* 42 * For testing SSCR1 changes that require SSP restart, basically 43 * everything except the service and interrupt enables, the PXA270 developer 44 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 45 * list, but the PXA255 developer manual says all bits without really meaning 46 * the service and interrupt enables. 47 */ 48 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 49 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 50 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 51 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 52 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 53 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 54 55 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 56 | QUARK_X1000_SSCR1_EFWR \ 57 | QUARK_X1000_SSCR1_RFT \ 58 | QUARK_X1000_SSCR1_TFT \ 59 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 60 61 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 62 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 63 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 64 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 65 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ 66 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 67 68 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 69 #define LPSS_CS_CONTROL_SW_MODE BIT(0) 70 #define LPSS_CS_CONTROL_CS_HIGH BIT(1) 71 #define LPSS_CAPS_CS_EN_SHIFT 9 72 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) 73 74 #define LPSS_PRIV_CLOCK_GATE 0x38 75 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3 76 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3 77 78 struct lpss_config { 79 /* LPSS offset from drv_data->ioaddr */ 80 unsigned offset; 81 /* Register offsets from drv_data->lpss_base or -1 */ 82 int reg_general; 83 int reg_ssp; 84 int reg_cs_ctrl; 85 int reg_capabilities; 86 /* FIFO thresholds */ 87 u32 rx_threshold; 88 u32 tx_threshold_lo; 89 u32 tx_threshold_hi; 90 /* Chip select control */ 91 unsigned cs_sel_shift; 92 unsigned cs_sel_mask; 93 unsigned cs_num; 94 /* Quirks */ 95 unsigned cs_clk_stays_gated : 1; 96 }; 97 98 /* Keep these sorted with enum pxa_ssp_type */ 99 static const struct lpss_config lpss_platforms[] = { 100 { /* LPSS_LPT_SSP */ 101 .offset = 0x800, 102 .reg_general = 0x08, 103 .reg_ssp = 0x0c, 104 .reg_cs_ctrl = 0x18, 105 .reg_capabilities = -1, 106 .rx_threshold = 64, 107 .tx_threshold_lo = 160, 108 .tx_threshold_hi = 224, 109 }, 110 { /* LPSS_BYT_SSP */ 111 .offset = 0x400, 112 .reg_general = 0x08, 113 .reg_ssp = 0x0c, 114 .reg_cs_ctrl = 0x18, 115 .reg_capabilities = -1, 116 .rx_threshold = 64, 117 .tx_threshold_lo = 160, 118 .tx_threshold_hi = 224, 119 }, 120 { /* LPSS_BSW_SSP */ 121 .offset = 0x400, 122 .reg_general = 0x08, 123 .reg_ssp = 0x0c, 124 .reg_cs_ctrl = 0x18, 125 .reg_capabilities = -1, 126 .rx_threshold = 64, 127 .tx_threshold_lo = 160, 128 .tx_threshold_hi = 224, 129 .cs_sel_shift = 2, 130 .cs_sel_mask = 1 << 2, 131 .cs_num = 2, 132 }, 133 { /* LPSS_SPT_SSP */ 134 .offset = 0x200, 135 .reg_general = -1, 136 .reg_ssp = 0x20, 137 .reg_cs_ctrl = 0x24, 138 .reg_capabilities = -1, 139 .rx_threshold = 1, 140 .tx_threshold_lo = 32, 141 .tx_threshold_hi = 56, 142 }, 143 { /* LPSS_BXT_SSP */ 144 .offset = 0x200, 145 .reg_general = -1, 146 .reg_ssp = 0x20, 147 .reg_cs_ctrl = 0x24, 148 .reg_capabilities = 0xfc, 149 .rx_threshold = 1, 150 .tx_threshold_lo = 16, 151 .tx_threshold_hi = 48, 152 .cs_sel_shift = 8, 153 .cs_sel_mask = 3 << 8, 154 .cs_clk_stays_gated = true, 155 }, 156 { /* LPSS_CNL_SSP */ 157 .offset = 0x200, 158 .reg_general = -1, 159 .reg_ssp = 0x20, 160 .reg_cs_ctrl = 0x24, 161 .reg_capabilities = 0xfc, 162 .rx_threshold = 1, 163 .tx_threshold_lo = 32, 164 .tx_threshold_hi = 56, 165 .cs_sel_shift = 8, 166 .cs_sel_mask = 3 << 8, 167 .cs_clk_stays_gated = true, 168 }, 169 }; 170 171 static inline const struct lpss_config 172 *lpss_get_config(const struct driver_data *drv_data) 173 { 174 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; 175 } 176 177 static bool is_lpss_ssp(const struct driver_data *drv_data) 178 { 179 switch (drv_data->ssp_type) { 180 case LPSS_LPT_SSP: 181 case LPSS_BYT_SSP: 182 case LPSS_BSW_SSP: 183 case LPSS_SPT_SSP: 184 case LPSS_BXT_SSP: 185 case LPSS_CNL_SSP: 186 return true; 187 default: 188 return false; 189 } 190 } 191 192 static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 193 { 194 return drv_data->ssp_type == QUARK_X1000_SSP; 195 } 196 197 static bool is_mmp2_ssp(const struct driver_data *drv_data) 198 { 199 return drv_data->ssp_type == MMP2_SSP; 200 } 201 202 static bool is_mrfld_ssp(const struct driver_data *drv_data) 203 { 204 return drv_data->ssp_type == MRFLD_SSP; 205 } 206 207 static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value) 208 { 209 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value) 210 pxa2xx_spi_write(drv_data, reg, value & mask); 211 } 212 213 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 214 { 215 switch (drv_data->ssp_type) { 216 case QUARK_X1000_SSP: 217 return QUARK_X1000_SSCR1_CHANGE_MASK; 218 case CE4100_SSP: 219 return CE4100_SSCR1_CHANGE_MASK; 220 default: 221 return SSCR1_CHANGE_MASK; 222 } 223 } 224 225 static u32 226 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 227 { 228 switch (drv_data->ssp_type) { 229 case QUARK_X1000_SSP: 230 return RX_THRESH_QUARK_X1000_DFLT; 231 case CE4100_SSP: 232 return RX_THRESH_CE4100_DFLT; 233 default: 234 return RX_THRESH_DFLT; 235 } 236 } 237 238 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 239 { 240 u32 mask; 241 242 switch (drv_data->ssp_type) { 243 case QUARK_X1000_SSP: 244 mask = QUARK_X1000_SSSR_TFL_MASK; 245 break; 246 case CE4100_SSP: 247 mask = CE4100_SSSR_TFL_MASK; 248 break; 249 default: 250 mask = SSSR_TFL_MASK; 251 break; 252 } 253 254 return read_SSSR_bits(drv_data, mask) == mask; 255 } 256 257 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 258 u32 *sccr1_reg) 259 { 260 u32 mask; 261 262 switch (drv_data->ssp_type) { 263 case QUARK_X1000_SSP: 264 mask = QUARK_X1000_SSCR1_RFT; 265 break; 266 case CE4100_SSP: 267 mask = CE4100_SSCR1_RFT; 268 break; 269 default: 270 mask = SSCR1_RFT; 271 break; 272 } 273 *sccr1_reg &= ~mask; 274 } 275 276 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 277 u32 *sccr1_reg, u32 threshold) 278 { 279 switch (drv_data->ssp_type) { 280 case QUARK_X1000_SSP: 281 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 282 break; 283 case CE4100_SSP: 284 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); 285 break; 286 default: 287 *sccr1_reg |= SSCR1_RxTresh(threshold); 288 break; 289 } 290 } 291 292 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 293 u32 clk_div, u8 bits) 294 { 295 switch (drv_data->ssp_type) { 296 case QUARK_X1000_SSP: 297 return clk_div 298 | QUARK_X1000_SSCR0_Motorola 299 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits); 300 default: 301 return clk_div 302 | SSCR0_Motorola 303 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 304 | (bits > 16 ? SSCR0_EDSS : 0); 305 } 306 } 307 308 /* 309 * Read and write LPSS SSP private registers. Caller must first check that 310 * is_lpss_ssp() returns true before these can be called. 311 */ 312 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 313 { 314 WARN_ON(!drv_data->lpss_base); 315 return readl(drv_data->lpss_base + offset); 316 } 317 318 static void __lpss_ssp_write_priv(struct driver_data *drv_data, 319 unsigned offset, u32 value) 320 { 321 WARN_ON(!drv_data->lpss_base); 322 writel(value, drv_data->lpss_base + offset); 323 } 324 325 /* 326 * lpss_ssp_setup - perform LPSS SSP specific setup 327 * @drv_data: pointer to the driver private data 328 * 329 * Perform LPSS SSP specific setup. This function must be called first if 330 * one is going to use LPSS SSP private registers. 331 */ 332 static void lpss_ssp_setup(struct driver_data *drv_data) 333 { 334 const struct lpss_config *config; 335 u32 value; 336 337 config = lpss_get_config(drv_data); 338 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset; 339 340 /* Enable software chip select control */ 341 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 342 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); 343 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; 344 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 345 346 /* Enable multiblock DMA transfers */ 347 if (drv_data->controller_info->enable_dma) { 348 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); 349 350 if (config->reg_general >= 0) { 351 value = __lpss_ssp_read_priv(drv_data, 352 config->reg_general); 353 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; 354 __lpss_ssp_write_priv(drv_data, 355 config->reg_general, value); 356 } 357 } 358 } 359 360 static void lpss_ssp_select_cs(struct spi_device *spi, 361 const struct lpss_config *config) 362 { 363 struct driver_data *drv_data = 364 spi_controller_get_devdata(spi->controller); 365 u32 value, cs; 366 367 if (!config->cs_sel_mask) 368 return; 369 370 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 371 372 cs = spi->chip_select; 373 cs <<= config->cs_sel_shift; 374 if (cs != (value & config->cs_sel_mask)) { 375 /* 376 * When switching another chip select output active the 377 * output must be selected first and wait 2 ssp_clk cycles 378 * before changing state to active. Otherwise a short 379 * glitch will occur on the previous chip select since 380 * output select is latched but state control is not. 381 */ 382 value &= ~config->cs_sel_mask; 383 value |= cs; 384 __lpss_ssp_write_priv(drv_data, 385 config->reg_cs_ctrl, value); 386 ndelay(1000000000 / 387 (drv_data->controller->max_speed_hz / 2)); 388 } 389 } 390 391 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) 392 { 393 struct driver_data *drv_data = 394 spi_controller_get_devdata(spi->controller); 395 const struct lpss_config *config; 396 u32 value; 397 398 config = lpss_get_config(drv_data); 399 400 if (enable) 401 lpss_ssp_select_cs(spi, config); 402 403 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 404 if (enable) 405 value &= ~LPSS_CS_CONTROL_CS_HIGH; 406 else 407 value |= LPSS_CS_CONTROL_CS_HIGH; 408 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 409 if (config->cs_clk_stays_gated) { 410 u32 clkgate; 411 412 /* 413 * Changing CS alone when dynamic clock gating is on won't 414 * actually flip CS at that time. This ruins SPI transfers 415 * that specify delays, or have no data. Toggle the clock mode 416 * to force on briefly to poke the CS pin to move. 417 */ 418 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE); 419 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) | 420 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON; 421 422 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value); 423 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate); 424 } 425 } 426 427 static void cs_assert(struct spi_device *spi) 428 { 429 struct driver_data *drv_data = 430 spi_controller_get_devdata(spi->controller); 431 432 if (drv_data->ssp_type == CE4100_SSP) { 433 pxa2xx_spi_write(drv_data, SSSR, spi->chip_select); 434 return; 435 } 436 437 if (is_lpss_ssp(drv_data)) 438 lpss_ssp_cs_control(spi, true); 439 } 440 441 static void cs_deassert(struct spi_device *spi) 442 { 443 struct driver_data *drv_data = 444 spi_controller_get_devdata(spi->controller); 445 unsigned long timeout; 446 447 if (drv_data->ssp_type == CE4100_SSP) 448 return; 449 450 /* Wait until SSP becomes idle before deasserting the CS */ 451 timeout = jiffies + msecs_to_jiffies(10); 452 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && 453 !time_after(jiffies, timeout)) 454 cpu_relax(); 455 456 if (is_lpss_ssp(drv_data)) 457 lpss_ssp_cs_control(spi, false); 458 } 459 460 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) 461 { 462 if (level) 463 cs_deassert(spi); 464 else 465 cs_assert(spi); 466 } 467 468 int pxa2xx_spi_flush(struct driver_data *drv_data) 469 { 470 unsigned long limit = loops_per_jiffy << 1; 471 472 do { 473 while (read_SSSR_bits(drv_data, SSSR_RNE)) 474 pxa2xx_spi_read(drv_data, SSDR); 475 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 476 write_SSSR_CS(drv_data, SSSR_ROR); 477 478 return limit; 479 } 480 481 static void pxa2xx_spi_off(struct driver_data *drv_data) 482 { 483 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */ 484 if (is_mmp2_ssp(drv_data)) 485 return; 486 487 pxa_ssp_disable(drv_data->ssp); 488 } 489 490 static int null_writer(struct driver_data *drv_data) 491 { 492 u8 n_bytes = drv_data->n_bytes; 493 494 if (pxa2xx_spi_txfifo_full(drv_data) 495 || (drv_data->tx == drv_data->tx_end)) 496 return 0; 497 498 pxa2xx_spi_write(drv_data, SSDR, 0); 499 drv_data->tx += n_bytes; 500 501 return 1; 502 } 503 504 static int null_reader(struct driver_data *drv_data) 505 { 506 u8 n_bytes = drv_data->n_bytes; 507 508 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { 509 pxa2xx_spi_read(drv_data, SSDR); 510 drv_data->rx += n_bytes; 511 } 512 513 return drv_data->rx == drv_data->rx_end; 514 } 515 516 static int u8_writer(struct driver_data *drv_data) 517 { 518 if (pxa2xx_spi_txfifo_full(drv_data) 519 || (drv_data->tx == drv_data->tx_end)) 520 return 0; 521 522 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 523 ++drv_data->tx; 524 525 return 1; 526 } 527 528 static int u8_reader(struct driver_data *drv_data) 529 { 530 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { 531 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 532 ++drv_data->rx; 533 } 534 535 return drv_data->rx == drv_data->rx_end; 536 } 537 538 static int u16_writer(struct driver_data *drv_data) 539 { 540 if (pxa2xx_spi_txfifo_full(drv_data) 541 || (drv_data->tx == drv_data->tx_end)) 542 return 0; 543 544 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 545 drv_data->tx += 2; 546 547 return 1; 548 } 549 550 static int u16_reader(struct driver_data *drv_data) 551 { 552 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { 553 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 554 drv_data->rx += 2; 555 } 556 557 return drv_data->rx == drv_data->rx_end; 558 } 559 560 static int u32_writer(struct driver_data *drv_data) 561 { 562 if (pxa2xx_spi_txfifo_full(drv_data) 563 || (drv_data->tx == drv_data->tx_end)) 564 return 0; 565 566 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 567 drv_data->tx += 4; 568 569 return 1; 570 } 571 572 static int u32_reader(struct driver_data *drv_data) 573 { 574 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { 575 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 576 drv_data->rx += 4; 577 } 578 579 return drv_data->rx == drv_data->rx_end; 580 } 581 582 static void reset_sccr1(struct driver_data *drv_data) 583 { 584 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold; 585 struct chip_data *chip; 586 587 if (drv_data->controller->cur_msg) { 588 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); 589 threshold = chip->threshold; 590 } else { 591 threshold = 0; 592 } 593 594 switch (drv_data->ssp_type) { 595 case QUARK_X1000_SSP: 596 mask |= QUARK_X1000_SSCR1_RFT; 597 break; 598 case CE4100_SSP: 599 mask |= CE4100_SSCR1_RFT; 600 break; 601 default: 602 mask |= SSCR1_RFT; 603 break; 604 } 605 606 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold); 607 } 608 609 static void int_stop_and_reset(struct driver_data *drv_data) 610 { 611 /* Clear and disable interrupts */ 612 write_SSSR_CS(drv_data, drv_data->clear_sr); 613 reset_sccr1(drv_data); 614 if (pxa25x_ssp_comp(drv_data)) 615 return; 616 617 pxa2xx_spi_write(drv_data, SSTO, 0); 618 } 619 620 static void int_error_stop(struct driver_data *drv_data, const char *msg, int err) 621 { 622 int_stop_and_reset(drv_data); 623 pxa2xx_spi_flush(drv_data); 624 pxa2xx_spi_off(drv_data); 625 626 dev_err(drv_data->ssp->dev, "%s\n", msg); 627 628 drv_data->controller->cur_msg->status = err; 629 spi_finalize_current_transfer(drv_data->controller); 630 } 631 632 static void int_transfer_complete(struct driver_data *drv_data) 633 { 634 int_stop_and_reset(drv_data); 635 636 spi_finalize_current_transfer(drv_data->controller); 637 } 638 639 static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 640 { 641 u32 irq_status; 642 643 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr); 644 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE)) 645 irq_status &= ~SSSR_TFS; 646 647 if (irq_status & SSSR_ROR) { 648 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO); 649 return IRQ_HANDLED; 650 } 651 652 if (irq_status & SSSR_TUR) { 653 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO); 654 return IRQ_HANDLED; 655 } 656 657 if (irq_status & SSSR_TINT) { 658 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 659 if (drv_data->read(drv_data)) { 660 int_transfer_complete(drv_data); 661 return IRQ_HANDLED; 662 } 663 } 664 665 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */ 666 do { 667 if (drv_data->read(drv_data)) { 668 int_transfer_complete(drv_data); 669 return IRQ_HANDLED; 670 } 671 } while (drv_data->write(drv_data)); 672 673 if (drv_data->read(drv_data)) { 674 int_transfer_complete(drv_data); 675 return IRQ_HANDLED; 676 } 677 678 if (drv_data->tx == drv_data->tx_end) { 679 u32 bytes_left; 680 u32 sccr1_reg; 681 682 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 683 sccr1_reg &= ~SSCR1_TIE; 684 685 /* 686 * PXA25x_SSP has no timeout, set up Rx threshold for 687 * the remaining Rx bytes. 688 */ 689 if (pxa25x_ssp_comp(drv_data)) { 690 u32 rx_thre; 691 692 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 693 694 bytes_left = drv_data->rx_end - drv_data->rx; 695 switch (drv_data->n_bytes) { 696 case 4: 697 bytes_left >>= 2; 698 break; 699 case 2: 700 bytes_left >>= 1; 701 break; 702 } 703 704 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 705 if (rx_thre > bytes_left) 706 rx_thre = bytes_left; 707 708 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 709 } 710 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 711 } 712 713 /* We did something */ 714 return IRQ_HANDLED; 715 } 716 717 static void handle_bad_msg(struct driver_data *drv_data) 718 { 719 int_stop_and_reset(drv_data); 720 pxa2xx_spi_off(drv_data); 721 722 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n"); 723 } 724 725 static irqreturn_t ssp_int(int irq, void *dev_id) 726 { 727 struct driver_data *drv_data = dev_id; 728 u32 sccr1_reg; 729 u32 mask = drv_data->mask_sr; 730 u32 status; 731 732 /* 733 * The IRQ might be shared with other peripherals so we must first 734 * check that are we RPM suspended or not. If we are we assume that 735 * the IRQ was not for us (we shouldn't be RPM suspended when the 736 * interrupt is enabled). 737 */ 738 if (pm_runtime_suspended(drv_data->ssp->dev)) 739 return IRQ_NONE; 740 741 /* 742 * If the device is not yet in RPM suspended state and we get an 743 * interrupt that is meant for another device, check if status bits 744 * are all set to one. That means that the device is already 745 * powered off. 746 */ 747 status = pxa2xx_spi_read(drv_data, SSSR); 748 if (status == ~0) 749 return IRQ_NONE; 750 751 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 752 753 /* Ignore possible writes if we don't need to write */ 754 if (!(sccr1_reg & SSCR1_TIE)) 755 mask &= ~SSSR_TFS; 756 757 /* Ignore RX timeout interrupt if it is disabled */ 758 if (!(sccr1_reg & SSCR1_TINTE)) 759 mask &= ~SSSR_TINT; 760 761 if (!(status & mask)) 762 return IRQ_NONE; 763 764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); 765 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 766 767 if (!drv_data->controller->cur_msg) { 768 handle_bad_msg(drv_data); 769 /* Never fail */ 770 return IRQ_HANDLED; 771 } 772 773 return drv_data->transfer_handler(drv_data); 774 } 775 776 /* 777 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply 778 * input frequency by fractions of 2^24. It also has a divider by 5. 779 * 780 * There are formulas to get baud rate value for given input frequency and 781 * divider parameters, such as DDS_CLK_RATE and SCR: 782 * 783 * Fsys = 200MHz 784 * 785 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) 786 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) 787 * 788 * DDS_CLK_RATE either 2^n or 2^n / 5. 789 * SCR is in range 0 .. 255 790 * 791 * Divisor = 5^i * 2^j * 2 * k 792 * i = [0, 1] i = 1 iff j = 0 or j > 3 793 * j = [0, 23] j = 0 iff i = 1 794 * k = [1, 256] 795 * Special case: j = 0, i = 1: Divisor = 2 / 5 796 * 797 * Accordingly to the specification the recommended values for DDS_CLK_RATE 798 * are: 799 * Case 1: 2^n, n = [0, 23] 800 * Case 2: 2^24 * 2 / 5 (0x666666) 801 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) 802 * 803 * In all cases the lowest possible value is better. 804 * 805 * The function calculates parameters for all cases and chooses the one closest 806 * to the asked baud rate. 807 */ 808 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 809 { 810 unsigned long xtal = 200000000; 811 unsigned long fref = xtal / 2; /* mandatory division by 2, 812 see (2) */ 813 /* case 3 */ 814 unsigned long fref1 = fref / 2; /* case 1 */ 815 unsigned long fref2 = fref * 2 / 5; /* case 2 */ 816 unsigned long scale; 817 unsigned long q, q1, q2; 818 long r, r1, r2; 819 u32 mul; 820 821 /* Case 1 */ 822 823 /* Set initial value for DDS_CLK_RATE */ 824 mul = (1 << 24) >> 1; 825 826 /* Calculate initial quot */ 827 q1 = DIV_ROUND_UP(fref1, rate); 828 829 /* Scale q1 if it's too big */ 830 if (q1 > 256) { 831 /* Scale q1 to range [1, 512] */ 832 scale = fls_long(q1 - 1); 833 if (scale > 9) { 834 q1 >>= scale - 9; 835 mul >>= scale - 9; 836 } 837 838 /* Round the result if we have a remainder */ 839 q1 += q1 & 1; 840 } 841 842 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ 843 scale = __ffs(q1); 844 q1 >>= scale; 845 mul >>= scale; 846 847 /* Get the remainder */ 848 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); 849 850 /* Case 2 */ 851 852 q2 = DIV_ROUND_UP(fref2, rate); 853 r2 = abs(fref2 / q2 - rate); 854 855 /* 856 * Choose the best between two: less remainder we have the better. We 857 * can't go case 2 if q2 is greater than 256 since SCR register can 858 * hold only values 0 .. 255. 859 */ 860 if (r2 >= r1 || q2 > 256) { 861 /* case 1 is better */ 862 r = r1; 863 q = q1; 864 } else { 865 /* case 2 is better */ 866 r = r2; 867 q = q2; 868 mul = (1 << 24) * 2 / 5; 869 } 870 871 /* Check case 3 only if the divisor is big enough */ 872 if (fref / rate >= 80) { 873 u64 fssp; 874 u32 m; 875 876 /* Calculate initial quot */ 877 q1 = DIV_ROUND_UP(fref, rate); 878 m = (1 << 24) / q1; 879 880 /* Get the remainder */ 881 fssp = (u64)fref * m; 882 do_div(fssp, 1 << 24); 883 r1 = abs(fssp - rate); 884 885 /* Choose this one if it suits better */ 886 if (r1 < r) { 887 /* case 3 is better */ 888 q = 1; 889 mul = m; 890 } 891 } 892 893 *dds = mul; 894 return q - 1; 895 } 896 897 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 898 { 899 unsigned long ssp_clk = drv_data->controller->max_speed_hz; 900 const struct ssp_device *ssp = drv_data->ssp; 901 902 rate = min_t(int, ssp_clk, rate); 903 904 /* 905 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding 906 * that the SSP transmission rate can be greater than the device rate. 907 */ 908 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 909 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; 910 else 911 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; 912 } 913 914 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 915 int rate) 916 { 917 struct chip_data *chip = 918 spi_get_ctldata(drv_data->controller->cur_msg->spi); 919 unsigned int clk_div; 920 921 switch (drv_data->ssp_type) { 922 case QUARK_X1000_SSP: 923 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); 924 break; 925 default: 926 clk_div = ssp_get_clk_div(drv_data, rate); 927 break; 928 } 929 return clk_div << 8; 930 } 931 932 static bool pxa2xx_spi_can_dma(struct spi_controller *controller, 933 struct spi_device *spi, 934 struct spi_transfer *xfer) 935 { 936 struct chip_data *chip = spi_get_ctldata(spi); 937 938 return chip->enable_dma && 939 xfer->len <= MAX_DMA_LEN && 940 xfer->len >= chip->dma_burst_size; 941 } 942 943 static int pxa2xx_spi_transfer_one(struct spi_controller *controller, 944 struct spi_device *spi, 945 struct spi_transfer *transfer) 946 { 947 struct driver_data *drv_data = spi_controller_get_devdata(controller); 948 struct spi_message *message = controller->cur_msg; 949 struct chip_data *chip = spi_get_ctldata(spi); 950 u32 dma_thresh = chip->dma_threshold; 951 u32 dma_burst = chip->dma_burst_size; 952 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 953 u32 clk_div; 954 u8 bits; 955 u32 speed; 956 u32 cr0; 957 u32 cr1; 958 int err; 959 int dma_mapped; 960 961 /* Check if we can DMA this transfer */ 962 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { 963 964 /* Reject already-mapped transfers; PIO won't always work */ 965 if (message->is_dma_mapped 966 || transfer->rx_dma || transfer->tx_dma) { 967 dev_err(&spi->dev, 968 "Mapped transfer length of %u is greater than %d\n", 969 transfer->len, MAX_DMA_LEN); 970 return -EINVAL; 971 } 972 973 /* Warn ... we force this to PIO mode */ 974 dev_warn_ratelimited(&spi->dev, 975 "DMA disabled for transfer length %u greater than %d\n", 976 transfer->len, MAX_DMA_LEN); 977 } 978 979 /* Setup the transfer state based on the type of transfer */ 980 if (pxa2xx_spi_flush(drv_data) == 0) { 981 dev_err(&spi->dev, "Flush failed\n"); 982 return -EIO; 983 } 984 drv_data->tx = (void *)transfer->tx_buf; 985 drv_data->tx_end = drv_data->tx + transfer->len; 986 drv_data->rx = transfer->rx_buf; 987 drv_data->rx_end = drv_data->rx + transfer->len; 988 989 /* Change speed and bit per word on a per transfer */ 990 bits = transfer->bits_per_word; 991 speed = transfer->speed_hz; 992 993 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); 994 995 if (bits <= 8) { 996 drv_data->n_bytes = 1; 997 drv_data->read = drv_data->rx ? u8_reader : null_reader; 998 drv_data->write = drv_data->tx ? u8_writer : null_writer; 999 } else if (bits <= 16) { 1000 drv_data->n_bytes = 2; 1001 drv_data->read = drv_data->rx ? u16_reader : null_reader; 1002 drv_data->write = drv_data->tx ? u16_writer : null_writer; 1003 } else if (bits <= 32) { 1004 drv_data->n_bytes = 4; 1005 drv_data->read = drv_data->rx ? u32_reader : null_reader; 1006 drv_data->write = drv_data->tx ? u32_writer : null_writer; 1007 } 1008 /* 1009 * If bits per word is changed in DMA mode, then must check 1010 * the thresholds and burst also. 1011 */ 1012 if (chip->enable_dma) { 1013 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 1014 spi, 1015 bits, &dma_burst, 1016 &dma_thresh)) 1017 dev_warn_ratelimited(&spi->dev, 1018 "DMA burst size reduced to match bits_per_word\n"); 1019 } 1020 1021 dma_mapped = controller->can_dma && 1022 controller->can_dma(controller, spi, transfer) && 1023 controller->cur_msg_mapped; 1024 if (dma_mapped) { 1025 1026 /* Ensure we have the correct interrupt handler */ 1027 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 1028 1029 err = pxa2xx_spi_dma_prepare(drv_data, transfer); 1030 if (err) 1031 return err; 1032 1033 /* Clear status and start DMA engine */ 1034 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 1035 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 1036 1037 pxa2xx_spi_dma_start(drv_data); 1038 } else { 1039 /* Ensure we have the correct interrupt handler */ 1040 drv_data->transfer_handler = interrupt_transfer; 1041 1042 /* Clear status */ 1043 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 1044 write_SSSR_CS(drv_data, drv_data->clear_sr); 1045 } 1046 1047 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1048 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 1049 if (!pxa25x_ssp_comp(drv_data)) 1050 dev_dbg(&spi->dev, "%u Hz actual, %s\n", 1051 controller->max_speed_hz 1052 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), 1053 dma_mapped ? "DMA" : "PIO"); 1054 else 1055 dev_dbg(&spi->dev, "%u Hz actual, %s\n", 1056 controller->max_speed_hz / 2 1057 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1058 dma_mapped ? "DMA" : "PIO"); 1059 1060 if (is_lpss_ssp(drv_data)) { 1061 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold); 1062 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold); 1063 } 1064 1065 if (is_mrfld_ssp(drv_data)) { 1066 u32 mask = SFIFOTT_RFT | SFIFOTT_TFT; 1067 u32 thresh = 0; 1068 1069 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold); 1070 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold); 1071 1072 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh); 1073 } 1074 1075 if (is_quark_x1000_ssp(drv_data)) 1076 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate); 1077 1078 /* Stop the SSP */ 1079 if (!is_mmp2_ssp(drv_data)) 1080 pxa_ssp_disable(drv_data->ssp); 1081 1082 if (!pxa25x_ssp_comp(drv_data)) 1083 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1084 1085 /* First set CR1 without interrupt and service enables */ 1086 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1); 1087 1088 /* See if we need to reload the configuration registers */ 1089 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0); 1090 1091 /* Restart the SSP */ 1092 pxa_ssp_enable(drv_data->ssp); 1093 1094 if (is_mmp2_ssp(drv_data)) { 1095 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8; 1096 1097 if (tx_level) { 1098 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */ 1099 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level); 1100 if (tx_level > transfer->len) 1101 tx_level = transfer->len; 1102 drv_data->tx += tx_level; 1103 } 1104 } 1105 1106 if (spi_controller_is_slave(controller)) { 1107 while (drv_data->write(drv_data)) 1108 ; 1109 if (drv_data->gpiod_ready) { 1110 gpiod_set_value(drv_data->gpiod_ready, 1); 1111 udelay(1); 1112 gpiod_set_value(drv_data->gpiod_ready, 0); 1113 } 1114 } 1115 1116 /* 1117 * Release the data by enabling service requests and interrupts, 1118 * without changing any mode bits. 1119 */ 1120 pxa2xx_spi_write(drv_data, SSCR1, cr1); 1121 1122 return 1; 1123 } 1124 1125 static int pxa2xx_spi_slave_abort(struct spi_controller *controller) 1126 { 1127 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1128 1129 int_error_stop(drv_data, "transfer aborted", -EINTR); 1130 1131 return 0; 1132 } 1133 1134 static void pxa2xx_spi_handle_err(struct spi_controller *controller, 1135 struct spi_message *msg) 1136 { 1137 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1138 1139 int_stop_and_reset(drv_data); 1140 1141 /* Disable the SSP */ 1142 pxa2xx_spi_off(drv_data); 1143 1144 /* 1145 * Stop the DMA if running. Note DMA callback handler may have unset 1146 * the dma_running already, which is fine as stopping is not needed 1147 * then but we shouldn't rely this flag for anything else than 1148 * stopping. For instance to differentiate between PIO and DMA 1149 * transfers. 1150 */ 1151 if (atomic_read(&drv_data->dma_running)) 1152 pxa2xx_spi_dma_stop(drv_data); 1153 } 1154 1155 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller) 1156 { 1157 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1158 1159 /* Disable the SSP now */ 1160 pxa2xx_spi_off(drv_data); 1161 1162 return 0; 1163 } 1164 1165 static int setup(struct spi_device *spi) 1166 { 1167 struct pxa2xx_spi_chip *chip_info; 1168 struct chip_data *chip; 1169 const struct lpss_config *config; 1170 struct driver_data *drv_data = 1171 spi_controller_get_devdata(spi->controller); 1172 uint tx_thres, tx_hi_thres, rx_thres; 1173 1174 switch (drv_data->ssp_type) { 1175 case QUARK_X1000_SSP: 1176 tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1177 tx_hi_thres = 0; 1178 rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1179 break; 1180 case MRFLD_SSP: 1181 tx_thres = TX_THRESH_MRFLD_DFLT; 1182 tx_hi_thres = 0; 1183 rx_thres = RX_THRESH_MRFLD_DFLT; 1184 break; 1185 case CE4100_SSP: 1186 tx_thres = TX_THRESH_CE4100_DFLT; 1187 tx_hi_thres = 0; 1188 rx_thres = RX_THRESH_CE4100_DFLT; 1189 break; 1190 case LPSS_LPT_SSP: 1191 case LPSS_BYT_SSP: 1192 case LPSS_BSW_SSP: 1193 case LPSS_SPT_SSP: 1194 case LPSS_BXT_SSP: 1195 case LPSS_CNL_SSP: 1196 config = lpss_get_config(drv_data); 1197 tx_thres = config->tx_threshold_lo; 1198 tx_hi_thres = config->tx_threshold_hi; 1199 rx_thres = config->rx_threshold; 1200 break; 1201 default: 1202 tx_hi_thres = 0; 1203 if (spi_controller_is_slave(drv_data->controller)) { 1204 tx_thres = 1; 1205 rx_thres = 2; 1206 } else { 1207 tx_thres = TX_THRESH_DFLT; 1208 rx_thres = RX_THRESH_DFLT; 1209 } 1210 break; 1211 } 1212 1213 /* Only allocate on the first setup */ 1214 chip = spi_get_ctldata(spi); 1215 if (!chip) { 1216 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1217 if (!chip) 1218 return -ENOMEM; 1219 1220 if (drv_data->ssp_type == CE4100_SSP) { 1221 if (spi->chip_select > 4) { 1222 dev_err(&spi->dev, 1223 "failed setup: cs number must not be > 4.\n"); 1224 kfree(chip); 1225 return -EINVAL; 1226 } 1227 } 1228 chip->enable_dma = drv_data->controller_info->enable_dma; 1229 chip->timeout = TIMOUT_DFLT; 1230 } 1231 1232 /* 1233 * Protocol drivers may change the chip settings, so... 1234 * if chip_info exists, use it. 1235 */ 1236 chip_info = spi->controller_data; 1237 1238 /* chip_info isn't always needed */ 1239 if (chip_info) { 1240 if (chip_info->timeout) 1241 chip->timeout = chip_info->timeout; 1242 if (chip_info->tx_threshold) 1243 tx_thres = chip_info->tx_threshold; 1244 if (chip_info->tx_hi_threshold) 1245 tx_hi_thres = chip_info->tx_hi_threshold; 1246 if (chip_info->rx_threshold) 1247 rx_thres = chip_info->rx_threshold; 1248 chip->dma_threshold = 0; 1249 } 1250 1251 chip->cr1 = 0; 1252 if (spi_controller_is_slave(drv_data->controller)) { 1253 chip->cr1 |= SSCR1_SCFR; 1254 chip->cr1 |= SSCR1_SCLKDIR; 1255 chip->cr1 |= SSCR1_SFRMDIR; 1256 chip->cr1 |= SSCR1_SPH; 1257 } 1258 1259 if (is_lpss_ssp(drv_data)) { 1260 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1261 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | 1262 SSITF_TxHiThresh(tx_hi_thres); 1263 } 1264 1265 if (is_mrfld_ssp(drv_data)) { 1266 chip->lpss_rx_threshold = rx_thres; 1267 chip->lpss_tx_threshold = tx_thres; 1268 } 1269 1270 /* 1271 * Set DMA burst and threshold outside of chip_info path so that if 1272 * chip_info goes away after setting chip->enable_dma, the burst and 1273 * threshold can still respond to changes in bits_per_word. 1274 */ 1275 if (chip->enable_dma) { 1276 /* Set up legal burst and threshold for DMA */ 1277 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1278 spi->bits_per_word, 1279 &chip->dma_burst_size, 1280 &chip->dma_threshold)) { 1281 dev_warn(&spi->dev, 1282 "in setup: DMA burst size reduced to match bits_per_word\n"); 1283 } 1284 dev_dbg(&spi->dev, 1285 "in setup: DMA burst size set to %u\n", 1286 chip->dma_burst_size); 1287 } 1288 1289 switch (drv_data->ssp_type) { 1290 case QUARK_X1000_SSP: 1291 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1292 & QUARK_X1000_SSCR1_RFT) 1293 | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1294 & QUARK_X1000_SSCR1_TFT); 1295 break; 1296 case CE4100_SSP: 1297 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | 1298 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); 1299 break; 1300 default: 1301 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1302 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1303 break; 1304 } 1305 1306 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1307 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) | 1308 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0); 1309 1310 if (spi->mode & SPI_LOOP) 1311 chip->cr1 |= SSCR1_LBM; 1312 1313 spi_set_ctldata(spi, chip); 1314 1315 return 0; 1316 } 1317 1318 static void cleanup(struct spi_device *spi) 1319 { 1320 struct chip_data *chip = spi_get_ctldata(spi); 1321 1322 kfree(chip); 1323 } 1324 1325 #ifdef CONFIG_ACPI 1326 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1327 { "INT33C0", LPSS_LPT_SSP }, 1328 { "INT33C1", LPSS_LPT_SSP }, 1329 { "INT3430", LPSS_LPT_SSP }, 1330 { "INT3431", LPSS_LPT_SSP }, 1331 { "80860F0E", LPSS_BYT_SSP }, 1332 { "8086228E", LPSS_BSW_SSP }, 1333 { }, 1334 }; 1335 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1336 #endif 1337 1338 /* 1339 * PCI IDs of compound devices that integrate both host controller and private 1340 * integrated DMA engine. Please note these are not used in module 1341 * autoloading and probing in this module but matching the LPSS SSP type. 1342 */ 1343 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { 1344 /* SPT-LP */ 1345 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, 1346 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, 1347 /* SPT-H */ 1348 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, 1349 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, 1350 /* KBL-H */ 1351 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, 1352 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, 1353 /* CML-V */ 1354 { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP }, 1355 { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP }, 1356 /* BXT A-Step */ 1357 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, 1358 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, 1359 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, 1360 /* BXT B-Step */ 1361 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, 1362 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, 1363 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, 1364 /* GLK */ 1365 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, 1366 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, 1367 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, 1368 /* ICL-LP */ 1369 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP }, 1370 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP }, 1371 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP }, 1372 /* EHL */ 1373 { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP }, 1374 { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP }, 1375 { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP }, 1376 /* JSL */ 1377 { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP }, 1378 { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP }, 1379 { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP }, 1380 /* TGL-H */ 1381 { PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP }, 1382 { PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP }, 1383 { PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP }, 1384 { PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP }, 1385 /* ADL-P */ 1386 { PCI_VDEVICE(INTEL, 0x51aa), LPSS_CNL_SSP }, 1387 { PCI_VDEVICE(INTEL, 0x51ab), LPSS_CNL_SSP }, 1388 { PCI_VDEVICE(INTEL, 0x51fb), LPSS_CNL_SSP }, 1389 /* ADL-M */ 1390 { PCI_VDEVICE(INTEL, 0x54aa), LPSS_CNL_SSP }, 1391 { PCI_VDEVICE(INTEL, 0x54ab), LPSS_CNL_SSP }, 1392 { PCI_VDEVICE(INTEL, 0x54fb), LPSS_CNL_SSP }, 1393 /* APL */ 1394 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, 1395 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, 1396 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, 1397 /* RPL-S */ 1398 { PCI_VDEVICE(INTEL, 0x7a2a), LPSS_CNL_SSP }, 1399 { PCI_VDEVICE(INTEL, 0x7a2b), LPSS_CNL_SSP }, 1400 { PCI_VDEVICE(INTEL, 0x7a79), LPSS_CNL_SSP }, 1401 { PCI_VDEVICE(INTEL, 0x7a7b), LPSS_CNL_SSP }, 1402 /* ADL-S */ 1403 { PCI_VDEVICE(INTEL, 0x7aaa), LPSS_CNL_SSP }, 1404 { PCI_VDEVICE(INTEL, 0x7aab), LPSS_CNL_SSP }, 1405 { PCI_VDEVICE(INTEL, 0x7af9), LPSS_CNL_SSP }, 1406 { PCI_VDEVICE(INTEL, 0x7afb), LPSS_CNL_SSP }, 1407 /* MTL-P */ 1408 { PCI_VDEVICE(INTEL, 0x7e27), LPSS_CNL_SSP }, 1409 { PCI_VDEVICE(INTEL, 0x7e30), LPSS_CNL_SSP }, 1410 { PCI_VDEVICE(INTEL, 0x7e46), LPSS_CNL_SSP }, 1411 /* CNL-LP */ 1412 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, 1413 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, 1414 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP }, 1415 /* CNL-H */ 1416 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP }, 1417 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP }, 1418 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP }, 1419 /* CML-LP */ 1420 { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP }, 1421 { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP }, 1422 { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP }, 1423 /* CML-H */ 1424 { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP }, 1425 { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP }, 1426 { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP }, 1427 /* TGL-LP */ 1428 { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP }, 1429 { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP }, 1430 { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP }, 1431 { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP }, 1432 { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP }, 1433 { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP }, 1434 { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP }, 1435 { }, 1436 }; 1437 1438 static const struct of_device_id pxa2xx_spi_of_match[] = { 1439 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP }, 1440 {}, 1441 }; 1442 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match); 1443 1444 #ifdef CONFIG_PCI 1445 1446 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) 1447 { 1448 return param == chan->device->dev; 1449 } 1450 1451 #endif /* CONFIG_PCI */ 1452 1453 static struct pxa2xx_spi_controller * 1454 pxa2xx_spi_init_pdata(struct platform_device *pdev) 1455 { 1456 struct pxa2xx_spi_controller *pdata; 1457 struct device *dev = &pdev->dev; 1458 struct device *parent = dev->parent; 1459 struct ssp_device *ssp; 1460 struct resource *res; 1461 struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL; 1462 const struct pci_device_id *pcidev_id = NULL; 1463 enum pxa_ssp_type type; 1464 const void *match; 1465 int status; 1466 u64 uid; 1467 1468 if (pcidev) 1469 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev); 1470 1471 match = device_get_match_data(&pdev->dev); 1472 if (match) 1473 type = (enum pxa_ssp_type)match; 1474 else if (pcidev_id) 1475 type = (enum pxa_ssp_type)pcidev_id->driver_data; 1476 else 1477 return ERR_PTR(-EINVAL); 1478 1479 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1480 if (!pdata) 1481 return ERR_PTR(-ENOMEM); 1482 1483 ssp = &pdata->ssp; 1484 1485 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1486 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1487 if (IS_ERR(ssp->mmio_base)) 1488 return ERR_CAST(ssp->mmio_base); 1489 1490 ssp->phys_base = res->start; 1491 1492 #ifdef CONFIG_PCI 1493 if (pcidev_id) { 1494 pdata->tx_param = parent; 1495 pdata->rx_param = parent; 1496 pdata->dma_filter = pxa2xx_spi_idma_filter; 1497 } 1498 #endif 1499 1500 ssp->clk = devm_clk_get(&pdev->dev, NULL); 1501 if (IS_ERR(ssp->clk)) 1502 return ERR_CAST(ssp->clk); 1503 1504 ssp->irq = platform_get_irq(pdev, 0); 1505 if (ssp->irq < 0) 1506 return ERR_PTR(ssp->irq); 1507 1508 ssp->type = type; 1509 ssp->dev = &pdev->dev; 1510 1511 status = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &uid); 1512 if (status) 1513 ssp->port_id = -1; 1514 else 1515 ssp->port_id = uid; 1516 1517 pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave"); 1518 pdata->num_chipselect = 1; 1519 pdata->enable_dma = true; 1520 pdata->dma_burst_size = 1; 1521 1522 return pdata; 1523 } 1524 1525 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller, 1526 unsigned int cs) 1527 { 1528 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1529 1530 if (has_acpi_companion(drv_data->ssp->dev)) { 1531 switch (drv_data->ssp_type) { 1532 /* 1533 * For Atoms the ACPI DeviceSelection used by the Windows 1534 * driver starts from 1 instead of 0 so translate it here 1535 * to match what Linux expects. 1536 */ 1537 case LPSS_BYT_SSP: 1538 case LPSS_BSW_SSP: 1539 return cs - 1; 1540 1541 default: 1542 break; 1543 } 1544 } 1545 1546 return cs; 1547 } 1548 1549 static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi) 1550 { 1551 return MAX_DMA_LEN; 1552 } 1553 1554 static int pxa2xx_spi_probe(struct platform_device *pdev) 1555 { 1556 struct device *dev = &pdev->dev; 1557 struct pxa2xx_spi_controller *platform_info; 1558 struct spi_controller *controller; 1559 struct driver_data *drv_data; 1560 struct ssp_device *ssp; 1561 const struct lpss_config *config; 1562 int status; 1563 u32 tmp; 1564 1565 platform_info = dev_get_platdata(dev); 1566 if (!platform_info) { 1567 platform_info = pxa2xx_spi_init_pdata(pdev); 1568 if (IS_ERR(platform_info)) { 1569 dev_err(&pdev->dev, "missing platform data\n"); 1570 return PTR_ERR(platform_info); 1571 } 1572 } 1573 1574 ssp = pxa_ssp_request(pdev->id, pdev->name); 1575 if (!ssp) 1576 ssp = &platform_info->ssp; 1577 1578 if (!ssp->mmio_base) { 1579 dev_err(&pdev->dev, "failed to get SSP\n"); 1580 return -ENODEV; 1581 } 1582 1583 if (platform_info->is_slave) 1584 controller = devm_spi_alloc_slave(dev, sizeof(*drv_data)); 1585 else 1586 controller = devm_spi_alloc_master(dev, sizeof(*drv_data)); 1587 1588 if (!controller) { 1589 dev_err(&pdev->dev, "cannot alloc spi_controller\n"); 1590 status = -ENOMEM; 1591 goto out_error_controller_alloc; 1592 } 1593 drv_data = spi_controller_get_devdata(controller); 1594 drv_data->controller = controller; 1595 drv_data->controller_info = platform_info; 1596 drv_data->ssp = ssp; 1597 1598 device_set_node(&controller->dev, dev_fwnode(dev)); 1599 1600 /* The spi->mode bits understood by this driver: */ 1601 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1602 1603 controller->bus_num = ssp->port_id; 1604 controller->dma_alignment = DMA_ALIGNMENT; 1605 controller->cleanup = cleanup; 1606 controller->setup = setup; 1607 controller->set_cs = pxa2xx_spi_set_cs; 1608 controller->transfer_one = pxa2xx_spi_transfer_one; 1609 controller->slave_abort = pxa2xx_spi_slave_abort; 1610 controller->handle_err = pxa2xx_spi_handle_err; 1611 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1612 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; 1613 controller->auto_runtime_pm = true; 1614 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; 1615 1616 drv_data->ssp_type = ssp->type; 1617 1618 if (pxa25x_ssp_comp(drv_data)) { 1619 switch (drv_data->ssp_type) { 1620 case QUARK_X1000_SSP: 1621 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1622 break; 1623 default: 1624 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1625 break; 1626 } 1627 1628 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1629 drv_data->dma_cr1 = 0; 1630 drv_data->clear_sr = SSSR_ROR; 1631 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1632 } else { 1633 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1634 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1635 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1636 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1637 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS 1638 | SSSR_ROR | SSSR_TUR; 1639 } 1640 1641 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1642 drv_data); 1643 if (status < 0) { 1644 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1645 goto out_error_controller_alloc; 1646 } 1647 1648 /* Setup DMA if requested */ 1649 if (platform_info->enable_dma) { 1650 status = pxa2xx_spi_dma_setup(drv_data); 1651 if (status) { 1652 dev_warn(dev, "no DMA channels available, using PIO\n"); 1653 platform_info->enable_dma = false; 1654 } else { 1655 controller->can_dma = pxa2xx_spi_can_dma; 1656 controller->max_dma_len = MAX_DMA_LEN; 1657 controller->max_transfer_size = 1658 pxa2xx_spi_max_dma_transfer_size; 1659 } 1660 } 1661 1662 /* Enable SOC clock */ 1663 status = clk_prepare_enable(ssp->clk); 1664 if (status) 1665 goto out_error_dma_irq_alloc; 1666 1667 controller->max_speed_hz = clk_get_rate(ssp->clk); 1668 /* 1669 * Set minimum speed for all other platforms than Intel Quark which is 1670 * able do under 1 Hz transfers. 1671 */ 1672 if (!pxa25x_ssp_comp(drv_data)) 1673 controller->min_speed_hz = 1674 DIV_ROUND_UP(controller->max_speed_hz, 4096); 1675 else if (!is_quark_x1000_ssp(drv_data)) 1676 controller->min_speed_hz = 1677 DIV_ROUND_UP(controller->max_speed_hz, 512); 1678 1679 pxa_ssp_disable(ssp); 1680 1681 /* Load default SSP configuration */ 1682 switch (drv_data->ssp_type) { 1683 case QUARK_X1000_SSP: 1684 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | 1685 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1686 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1687 1688 /* Using the Motorola SPI protocol and use 8 bit frame */ 1689 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); 1690 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1691 break; 1692 case CE4100_SSP: 1693 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | 1694 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); 1695 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1696 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1697 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1698 break; 1699 default: 1700 1701 if (spi_controller_is_slave(controller)) { 1702 tmp = SSCR1_SCFR | 1703 SSCR1_SCLKDIR | 1704 SSCR1_SFRMDIR | 1705 SSCR1_RxTresh(2) | 1706 SSCR1_TxTresh(1) | 1707 SSCR1_SPH; 1708 } else { 1709 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1710 SSCR1_TxTresh(TX_THRESH_DFLT); 1711 } 1712 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1713 tmp = SSCR0_Motorola | SSCR0_DataSize(8); 1714 if (!spi_controller_is_slave(controller)) 1715 tmp |= SSCR0_SCR(2); 1716 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1717 break; 1718 } 1719 1720 if (!pxa25x_ssp_comp(drv_data)) 1721 pxa2xx_spi_write(drv_data, SSTO, 0); 1722 1723 if (!is_quark_x1000_ssp(drv_data)) 1724 pxa2xx_spi_write(drv_data, SSPSP, 0); 1725 1726 if (is_lpss_ssp(drv_data)) { 1727 lpss_ssp_setup(drv_data); 1728 config = lpss_get_config(drv_data); 1729 if (config->reg_capabilities >= 0) { 1730 tmp = __lpss_ssp_read_priv(drv_data, 1731 config->reg_capabilities); 1732 tmp &= LPSS_CAPS_CS_EN_MASK; 1733 tmp >>= LPSS_CAPS_CS_EN_SHIFT; 1734 platform_info->num_chipselect = ffz(tmp); 1735 } else if (config->cs_num) { 1736 platform_info->num_chipselect = config->cs_num; 1737 } 1738 } 1739 controller->num_chipselect = platform_info->num_chipselect; 1740 controller->use_gpio_descriptors = true; 1741 1742 if (platform_info->is_slave) { 1743 drv_data->gpiod_ready = devm_gpiod_get_optional(dev, 1744 "ready", GPIOD_OUT_LOW); 1745 if (IS_ERR(drv_data->gpiod_ready)) { 1746 status = PTR_ERR(drv_data->gpiod_ready); 1747 goto out_error_clock_enabled; 1748 } 1749 } 1750 1751 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1752 pm_runtime_use_autosuspend(&pdev->dev); 1753 pm_runtime_set_active(&pdev->dev); 1754 pm_runtime_enable(&pdev->dev); 1755 1756 /* Register with the SPI framework */ 1757 platform_set_drvdata(pdev, drv_data); 1758 status = spi_register_controller(controller); 1759 if (status) { 1760 dev_err(&pdev->dev, "problem registering SPI controller\n"); 1761 goto out_error_pm_runtime_enabled; 1762 } 1763 1764 return status; 1765 1766 out_error_pm_runtime_enabled: 1767 pm_runtime_disable(&pdev->dev); 1768 1769 out_error_clock_enabled: 1770 clk_disable_unprepare(ssp->clk); 1771 1772 out_error_dma_irq_alloc: 1773 pxa2xx_spi_dma_release(drv_data); 1774 free_irq(ssp->irq, drv_data); 1775 1776 out_error_controller_alloc: 1777 pxa_ssp_free(ssp); 1778 return status; 1779 } 1780 1781 static int pxa2xx_spi_remove(struct platform_device *pdev) 1782 { 1783 struct driver_data *drv_data = platform_get_drvdata(pdev); 1784 struct ssp_device *ssp = drv_data->ssp; 1785 1786 pm_runtime_get_sync(&pdev->dev); 1787 1788 spi_unregister_controller(drv_data->controller); 1789 1790 /* Disable the SSP at the peripheral and SOC level */ 1791 pxa_ssp_disable(ssp); 1792 clk_disable_unprepare(ssp->clk); 1793 1794 /* Release DMA */ 1795 if (drv_data->controller_info->enable_dma) 1796 pxa2xx_spi_dma_release(drv_data); 1797 1798 pm_runtime_put_noidle(&pdev->dev); 1799 pm_runtime_disable(&pdev->dev); 1800 1801 /* Release IRQ */ 1802 free_irq(ssp->irq, drv_data); 1803 1804 /* Release SSP */ 1805 pxa_ssp_free(ssp); 1806 1807 return 0; 1808 } 1809 1810 #ifdef CONFIG_PM_SLEEP 1811 static int pxa2xx_spi_suspend(struct device *dev) 1812 { 1813 struct driver_data *drv_data = dev_get_drvdata(dev); 1814 struct ssp_device *ssp = drv_data->ssp; 1815 int status; 1816 1817 status = spi_controller_suspend(drv_data->controller); 1818 if (status) 1819 return status; 1820 1821 pxa_ssp_disable(ssp); 1822 1823 if (!pm_runtime_suspended(dev)) 1824 clk_disable_unprepare(ssp->clk); 1825 1826 return 0; 1827 } 1828 1829 static int pxa2xx_spi_resume(struct device *dev) 1830 { 1831 struct driver_data *drv_data = dev_get_drvdata(dev); 1832 struct ssp_device *ssp = drv_data->ssp; 1833 int status; 1834 1835 /* Enable the SSP clock */ 1836 if (!pm_runtime_suspended(dev)) { 1837 status = clk_prepare_enable(ssp->clk); 1838 if (status) 1839 return status; 1840 } 1841 1842 /* Start the queue running */ 1843 return spi_controller_resume(drv_data->controller); 1844 } 1845 #endif 1846 1847 #ifdef CONFIG_PM 1848 static int pxa2xx_spi_runtime_suspend(struct device *dev) 1849 { 1850 struct driver_data *drv_data = dev_get_drvdata(dev); 1851 1852 clk_disable_unprepare(drv_data->ssp->clk); 1853 return 0; 1854 } 1855 1856 static int pxa2xx_spi_runtime_resume(struct device *dev) 1857 { 1858 struct driver_data *drv_data = dev_get_drvdata(dev); 1859 1860 return clk_prepare_enable(drv_data->ssp->clk); 1861 } 1862 #endif 1863 1864 static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1865 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1866 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 1867 pxa2xx_spi_runtime_resume, NULL) 1868 }; 1869 1870 static struct platform_driver driver = { 1871 .driver = { 1872 .name = "pxa2xx-spi", 1873 .pm = &pxa2xx_spi_pm_ops, 1874 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1875 .of_match_table = of_match_ptr(pxa2xx_spi_of_match), 1876 }, 1877 .probe = pxa2xx_spi_probe, 1878 .remove = pxa2xx_spi_remove, 1879 }; 1880 1881 static int __init pxa2xx_spi_init(void) 1882 { 1883 return platform_driver_register(&driver); 1884 } 1885 subsys_initcall(pxa2xx_spi_init); 1886 1887 static void __exit pxa2xx_spi_exit(void) 1888 { 1889 platform_driver_unregister(&driver); 1890 } 1891 module_exit(pxa2xx_spi_exit); 1892 1893 MODULE_SOFTDEP("pre: dw_dmac"); 1894