xref: /openbmc/linux/drivers/spi/spi-pxa2xx.c (revision a2cce7a9)
1 /*
2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3  * Copyright (C) 2013, Intel Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/ioport.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/spi/pxa2xx_spi.h>
27 #include <linux/spi/spi.h>
28 #include <linux/delay.h>
29 #include <linux/gpio.h>
30 #include <linux/slab.h>
31 #include <linux/clk.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/acpi.h>
34 
35 #include "spi-pxa2xx.h"
36 
37 MODULE_AUTHOR("Stephen Street");
38 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
39 MODULE_LICENSE("GPL");
40 MODULE_ALIAS("platform:pxa2xx-spi");
41 
42 #define TIMOUT_DFLT		1000
43 
44 /*
45  * for testing SSCR1 changes that require SSP restart, basically
46  * everything except the service and interrupt enables, the pxa270 developer
47  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
48  * list, but the PXA255 dev man says all bits without really meaning the
49  * service and interrupt enables
50  */
51 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
52 				| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
53 				| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
54 				| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
55 				| SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
56 				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
57 
58 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF	\
59 				| QUARK_X1000_SSCR1_EFWR	\
60 				| QUARK_X1000_SSCR1_RFT		\
61 				| QUARK_X1000_SSCR1_TFT		\
62 				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
63 
64 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
65 #define SPI_CS_CONTROL_SW_MODE	BIT(0)
66 #define SPI_CS_CONTROL_CS_HIGH	BIT(1)
67 
68 struct lpss_config {
69 	/* LPSS offset from drv_data->ioaddr */
70 	unsigned offset;
71 	/* Register offsets from drv_data->lpss_base or -1 */
72 	int reg_general;
73 	int reg_ssp;
74 	int reg_cs_ctrl;
75 	/* FIFO thresholds */
76 	u32 rx_threshold;
77 	u32 tx_threshold_lo;
78 	u32 tx_threshold_hi;
79 };
80 
81 /* Keep these sorted with enum pxa_ssp_type */
82 static const struct lpss_config lpss_platforms[] = {
83 	{	/* LPSS_LPT_SSP */
84 		.offset = 0x800,
85 		.reg_general = 0x08,
86 		.reg_ssp = 0x0c,
87 		.reg_cs_ctrl = 0x18,
88 		.rx_threshold = 64,
89 		.tx_threshold_lo = 160,
90 		.tx_threshold_hi = 224,
91 	},
92 	{	/* LPSS_BYT_SSP */
93 		.offset = 0x400,
94 		.reg_general = 0x08,
95 		.reg_ssp = 0x0c,
96 		.reg_cs_ctrl = 0x18,
97 		.rx_threshold = 64,
98 		.tx_threshold_lo = 160,
99 		.tx_threshold_hi = 224,
100 	},
101 	{	/* LPSS_SPT_SSP */
102 		.offset = 0x200,
103 		.reg_general = -1,
104 		.reg_ssp = 0x20,
105 		.reg_cs_ctrl = 0x24,
106 		.rx_threshold = 1,
107 		.tx_threshold_lo = 32,
108 		.tx_threshold_hi = 56,
109 	},
110 };
111 
112 static inline const struct lpss_config
113 *lpss_get_config(const struct driver_data *drv_data)
114 {
115 	return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
116 }
117 
118 static bool is_lpss_ssp(const struct driver_data *drv_data)
119 {
120 	switch (drv_data->ssp_type) {
121 	case LPSS_LPT_SSP:
122 	case LPSS_BYT_SSP:
123 	case LPSS_SPT_SSP:
124 		return true;
125 	default:
126 		return false;
127 	}
128 }
129 
130 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
131 {
132 	return drv_data->ssp_type == QUARK_X1000_SSP;
133 }
134 
135 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
136 {
137 	switch (drv_data->ssp_type) {
138 	case QUARK_X1000_SSP:
139 		return QUARK_X1000_SSCR1_CHANGE_MASK;
140 	default:
141 		return SSCR1_CHANGE_MASK;
142 	}
143 }
144 
145 static u32
146 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
147 {
148 	switch (drv_data->ssp_type) {
149 	case QUARK_X1000_SSP:
150 		return RX_THRESH_QUARK_X1000_DFLT;
151 	default:
152 		return RX_THRESH_DFLT;
153 	}
154 }
155 
156 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
157 {
158 	u32 mask;
159 
160 	switch (drv_data->ssp_type) {
161 	case QUARK_X1000_SSP:
162 		mask = QUARK_X1000_SSSR_TFL_MASK;
163 		break;
164 	default:
165 		mask = SSSR_TFL_MASK;
166 		break;
167 	}
168 
169 	return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
170 }
171 
172 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
173 				     u32 *sccr1_reg)
174 {
175 	u32 mask;
176 
177 	switch (drv_data->ssp_type) {
178 	case QUARK_X1000_SSP:
179 		mask = QUARK_X1000_SSCR1_RFT;
180 		break;
181 	default:
182 		mask = SSCR1_RFT;
183 		break;
184 	}
185 	*sccr1_reg &= ~mask;
186 }
187 
188 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
189 				   u32 *sccr1_reg, u32 threshold)
190 {
191 	switch (drv_data->ssp_type) {
192 	case QUARK_X1000_SSP:
193 		*sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
194 		break;
195 	default:
196 		*sccr1_reg |= SSCR1_RxTresh(threshold);
197 		break;
198 	}
199 }
200 
201 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
202 				  u32 clk_div, u8 bits)
203 {
204 	switch (drv_data->ssp_type) {
205 	case QUARK_X1000_SSP:
206 		return clk_div
207 			| QUARK_X1000_SSCR0_Motorola
208 			| QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
209 			| SSCR0_SSE;
210 	default:
211 		return clk_div
212 			| SSCR0_Motorola
213 			| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
214 			| SSCR0_SSE
215 			| (bits > 16 ? SSCR0_EDSS : 0);
216 	}
217 }
218 
219 /*
220  * Read and write LPSS SSP private registers. Caller must first check that
221  * is_lpss_ssp() returns true before these can be called.
222  */
223 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
224 {
225 	WARN_ON(!drv_data->lpss_base);
226 	return readl(drv_data->lpss_base + offset);
227 }
228 
229 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
230 				  unsigned offset, u32 value)
231 {
232 	WARN_ON(!drv_data->lpss_base);
233 	writel(value, drv_data->lpss_base + offset);
234 }
235 
236 /*
237  * lpss_ssp_setup - perform LPSS SSP specific setup
238  * @drv_data: pointer to the driver private data
239  *
240  * Perform LPSS SSP specific setup. This function must be called first if
241  * one is going to use LPSS SSP private registers.
242  */
243 static void lpss_ssp_setup(struct driver_data *drv_data)
244 {
245 	const struct lpss_config *config;
246 	u32 value;
247 
248 	config = lpss_get_config(drv_data);
249 	drv_data->lpss_base = drv_data->ioaddr + config->offset;
250 
251 	/* Enable software chip select control */
252 	value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
253 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
254 
255 	/* Enable multiblock DMA transfers */
256 	if (drv_data->master_info->enable_dma) {
257 		__lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
258 
259 		if (config->reg_general >= 0) {
260 			value = __lpss_ssp_read_priv(drv_data,
261 						     config->reg_general);
262 			value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
263 			__lpss_ssp_write_priv(drv_data,
264 					      config->reg_general, value);
265 		}
266 	}
267 }
268 
269 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
270 {
271 	const struct lpss_config *config;
272 	u32 value;
273 
274 	config = lpss_get_config(drv_data);
275 
276 	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
277 	if (enable)
278 		value &= ~SPI_CS_CONTROL_CS_HIGH;
279 	else
280 		value |= SPI_CS_CONTROL_CS_HIGH;
281 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
282 }
283 
284 static void cs_assert(struct driver_data *drv_data)
285 {
286 	struct chip_data *chip = drv_data->cur_chip;
287 
288 	if (drv_data->ssp_type == CE4100_SSP) {
289 		pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
290 		return;
291 	}
292 
293 	if (chip->cs_control) {
294 		chip->cs_control(PXA2XX_CS_ASSERT);
295 		return;
296 	}
297 
298 	if (gpio_is_valid(chip->gpio_cs)) {
299 		gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
300 		return;
301 	}
302 
303 	if (is_lpss_ssp(drv_data))
304 		lpss_ssp_cs_control(drv_data, true);
305 }
306 
307 static void cs_deassert(struct driver_data *drv_data)
308 {
309 	struct chip_data *chip = drv_data->cur_chip;
310 
311 	if (drv_data->ssp_type == CE4100_SSP)
312 		return;
313 
314 	if (chip->cs_control) {
315 		chip->cs_control(PXA2XX_CS_DEASSERT);
316 		return;
317 	}
318 
319 	if (gpio_is_valid(chip->gpio_cs)) {
320 		gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
321 		return;
322 	}
323 
324 	if (is_lpss_ssp(drv_data))
325 		lpss_ssp_cs_control(drv_data, false);
326 }
327 
328 int pxa2xx_spi_flush(struct driver_data *drv_data)
329 {
330 	unsigned long limit = loops_per_jiffy << 1;
331 
332 	do {
333 		while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
334 			pxa2xx_spi_read(drv_data, SSDR);
335 	} while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
336 	write_SSSR_CS(drv_data, SSSR_ROR);
337 
338 	return limit;
339 }
340 
341 static int null_writer(struct driver_data *drv_data)
342 {
343 	u8 n_bytes = drv_data->n_bytes;
344 
345 	if (pxa2xx_spi_txfifo_full(drv_data)
346 		|| (drv_data->tx == drv_data->tx_end))
347 		return 0;
348 
349 	pxa2xx_spi_write(drv_data, SSDR, 0);
350 	drv_data->tx += n_bytes;
351 
352 	return 1;
353 }
354 
355 static int null_reader(struct driver_data *drv_data)
356 {
357 	u8 n_bytes = drv_data->n_bytes;
358 
359 	while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
360 	       && (drv_data->rx < drv_data->rx_end)) {
361 		pxa2xx_spi_read(drv_data, SSDR);
362 		drv_data->rx += n_bytes;
363 	}
364 
365 	return drv_data->rx == drv_data->rx_end;
366 }
367 
368 static int u8_writer(struct driver_data *drv_data)
369 {
370 	if (pxa2xx_spi_txfifo_full(drv_data)
371 		|| (drv_data->tx == drv_data->tx_end))
372 		return 0;
373 
374 	pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
375 	++drv_data->tx;
376 
377 	return 1;
378 }
379 
380 static int u8_reader(struct driver_data *drv_data)
381 {
382 	while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
383 	       && (drv_data->rx < drv_data->rx_end)) {
384 		*(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
385 		++drv_data->rx;
386 	}
387 
388 	return drv_data->rx == drv_data->rx_end;
389 }
390 
391 static int u16_writer(struct driver_data *drv_data)
392 {
393 	if (pxa2xx_spi_txfifo_full(drv_data)
394 		|| (drv_data->tx == drv_data->tx_end))
395 		return 0;
396 
397 	pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
398 	drv_data->tx += 2;
399 
400 	return 1;
401 }
402 
403 static int u16_reader(struct driver_data *drv_data)
404 {
405 	while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
406 	       && (drv_data->rx < drv_data->rx_end)) {
407 		*(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
408 		drv_data->rx += 2;
409 	}
410 
411 	return drv_data->rx == drv_data->rx_end;
412 }
413 
414 static int u32_writer(struct driver_data *drv_data)
415 {
416 	if (pxa2xx_spi_txfifo_full(drv_data)
417 		|| (drv_data->tx == drv_data->tx_end))
418 		return 0;
419 
420 	pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
421 	drv_data->tx += 4;
422 
423 	return 1;
424 }
425 
426 static int u32_reader(struct driver_data *drv_data)
427 {
428 	while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
429 	       && (drv_data->rx < drv_data->rx_end)) {
430 		*(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
431 		drv_data->rx += 4;
432 	}
433 
434 	return drv_data->rx == drv_data->rx_end;
435 }
436 
437 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
438 {
439 	struct spi_message *msg = drv_data->cur_msg;
440 	struct spi_transfer *trans = drv_data->cur_transfer;
441 
442 	/* Move to next transfer */
443 	if (trans->transfer_list.next != &msg->transfers) {
444 		drv_data->cur_transfer =
445 			list_entry(trans->transfer_list.next,
446 					struct spi_transfer,
447 					transfer_list);
448 		return RUNNING_STATE;
449 	} else
450 		return DONE_STATE;
451 }
452 
453 /* caller already set message->status; dma and pio irqs are blocked */
454 static void giveback(struct driver_data *drv_data)
455 {
456 	struct spi_transfer* last_transfer;
457 	struct spi_message *msg;
458 
459 	msg = drv_data->cur_msg;
460 	drv_data->cur_msg = NULL;
461 	drv_data->cur_transfer = NULL;
462 
463 	last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
464 					transfer_list);
465 
466 	/* Delay if requested before any change in chip select */
467 	if (last_transfer->delay_usecs)
468 		udelay(last_transfer->delay_usecs);
469 
470 	/* Drop chip select UNLESS cs_change is true or we are returning
471 	 * a message with an error, or next message is for another chip
472 	 */
473 	if (!last_transfer->cs_change)
474 		cs_deassert(drv_data);
475 	else {
476 		struct spi_message *next_msg;
477 
478 		/* Holding of cs was hinted, but we need to make sure
479 		 * the next message is for the same chip.  Don't waste
480 		 * time with the following tests unless this was hinted.
481 		 *
482 		 * We cannot postpone this until pump_messages, because
483 		 * after calling msg->complete (below) the driver that
484 		 * sent the current message could be unloaded, which
485 		 * could invalidate the cs_control() callback...
486 		 */
487 
488 		/* get a pointer to the next message, if any */
489 		next_msg = spi_get_next_queued_message(drv_data->master);
490 
491 		/* see if the next and current messages point
492 		 * to the same chip
493 		 */
494 		if (next_msg && next_msg->spi != msg->spi)
495 			next_msg = NULL;
496 		if (!next_msg || msg->state == ERROR_STATE)
497 			cs_deassert(drv_data);
498 	}
499 
500 	drv_data->cur_chip = NULL;
501 	spi_finalize_current_message(drv_data->master);
502 }
503 
504 static void reset_sccr1(struct driver_data *drv_data)
505 {
506 	struct chip_data *chip = drv_data->cur_chip;
507 	u32 sccr1_reg;
508 
509 	sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
510 	sccr1_reg &= ~SSCR1_RFT;
511 	sccr1_reg |= chip->threshold;
512 	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
513 }
514 
515 static void int_error_stop(struct driver_data *drv_data, const char* msg)
516 {
517 	/* Stop and reset SSP */
518 	write_SSSR_CS(drv_data, drv_data->clear_sr);
519 	reset_sccr1(drv_data);
520 	if (!pxa25x_ssp_comp(drv_data))
521 		pxa2xx_spi_write(drv_data, SSTO, 0);
522 	pxa2xx_spi_flush(drv_data);
523 	pxa2xx_spi_write(drv_data, SSCR0,
524 			 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
525 
526 	dev_err(&drv_data->pdev->dev, "%s\n", msg);
527 
528 	drv_data->cur_msg->state = ERROR_STATE;
529 	tasklet_schedule(&drv_data->pump_transfers);
530 }
531 
532 static void int_transfer_complete(struct driver_data *drv_data)
533 {
534 	/* Stop SSP */
535 	write_SSSR_CS(drv_data, drv_data->clear_sr);
536 	reset_sccr1(drv_data);
537 	if (!pxa25x_ssp_comp(drv_data))
538 		pxa2xx_spi_write(drv_data, SSTO, 0);
539 
540 	/* Update total byte transferred return count actual bytes read */
541 	drv_data->cur_msg->actual_length += drv_data->len -
542 				(drv_data->rx_end - drv_data->rx);
543 
544 	/* Transfer delays and chip select release are
545 	 * handled in pump_transfers or giveback
546 	 */
547 
548 	/* Move to next transfer */
549 	drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
550 
551 	/* Schedule transfer tasklet */
552 	tasklet_schedule(&drv_data->pump_transfers);
553 }
554 
555 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
556 {
557 	u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
558 		       drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
559 
560 	u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
561 
562 	if (irq_status & SSSR_ROR) {
563 		int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
564 		return IRQ_HANDLED;
565 	}
566 
567 	if (irq_status & SSSR_TINT) {
568 		pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
569 		if (drv_data->read(drv_data)) {
570 			int_transfer_complete(drv_data);
571 			return IRQ_HANDLED;
572 		}
573 	}
574 
575 	/* Drain rx fifo, Fill tx fifo and prevent overruns */
576 	do {
577 		if (drv_data->read(drv_data)) {
578 			int_transfer_complete(drv_data);
579 			return IRQ_HANDLED;
580 		}
581 	} while (drv_data->write(drv_data));
582 
583 	if (drv_data->read(drv_data)) {
584 		int_transfer_complete(drv_data);
585 		return IRQ_HANDLED;
586 	}
587 
588 	if (drv_data->tx == drv_data->tx_end) {
589 		u32 bytes_left;
590 		u32 sccr1_reg;
591 
592 		sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
593 		sccr1_reg &= ~SSCR1_TIE;
594 
595 		/*
596 		 * PXA25x_SSP has no timeout, set up rx threshould for the
597 		 * remaining RX bytes.
598 		 */
599 		if (pxa25x_ssp_comp(drv_data)) {
600 			u32 rx_thre;
601 
602 			pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
603 
604 			bytes_left = drv_data->rx_end - drv_data->rx;
605 			switch (drv_data->n_bytes) {
606 			case 4:
607 				bytes_left >>= 1;
608 			case 2:
609 				bytes_left >>= 1;
610 			}
611 
612 			rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
613 			if (rx_thre > bytes_left)
614 				rx_thre = bytes_left;
615 
616 			pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
617 		}
618 		pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
619 	}
620 
621 	/* We did something */
622 	return IRQ_HANDLED;
623 }
624 
625 static irqreturn_t ssp_int(int irq, void *dev_id)
626 {
627 	struct driver_data *drv_data = dev_id;
628 	u32 sccr1_reg;
629 	u32 mask = drv_data->mask_sr;
630 	u32 status;
631 
632 	/*
633 	 * The IRQ might be shared with other peripherals so we must first
634 	 * check that are we RPM suspended or not. If we are we assume that
635 	 * the IRQ was not for us (we shouldn't be RPM suspended when the
636 	 * interrupt is enabled).
637 	 */
638 	if (pm_runtime_suspended(&drv_data->pdev->dev))
639 		return IRQ_NONE;
640 
641 	/*
642 	 * If the device is not yet in RPM suspended state and we get an
643 	 * interrupt that is meant for another device, check if status bits
644 	 * are all set to one. That means that the device is already
645 	 * powered off.
646 	 */
647 	status = pxa2xx_spi_read(drv_data, SSSR);
648 	if (status == ~0)
649 		return IRQ_NONE;
650 
651 	sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
652 
653 	/* Ignore possible writes if we don't need to write */
654 	if (!(sccr1_reg & SSCR1_TIE))
655 		mask &= ~SSSR_TFS;
656 
657 	/* Ignore RX timeout interrupt if it is disabled */
658 	if (!(sccr1_reg & SSCR1_TINTE))
659 		mask &= ~SSSR_TINT;
660 
661 	if (!(status & mask))
662 		return IRQ_NONE;
663 
664 	if (!drv_data->cur_msg) {
665 
666 		pxa2xx_spi_write(drv_data, SSCR0,
667 				 pxa2xx_spi_read(drv_data, SSCR0)
668 				 & ~SSCR0_SSE);
669 		pxa2xx_spi_write(drv_data, SSCR1,
670 				 pxa2xx_spi_read(drv_data, SSCR1)
671 				 & ~drv_data->int_cr1);
672 		if (!pxa25x_ssp_comp(drv_data))
673 			pxa2xx_spi_write(drv_data, SSTO, 0);
674 		write_SSSR_CS(drv_data, drv_data->clear_sr);
675 
676 		dev_err(&drv_data->pdev->dev,
677 			"bad message state in interrupt handler\n");
678 
679 		/* Never fail */
680 		return IRQ_HANDLED;
681 	}
682 
683 	return drv_data->transfer_handler(drv_data);
684 }
685 
686 /*
687  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
688  * input frequency by fractions of 2^24. It also has a divider by 5.
689  *
690  * There are formulas to get baud rate value for given input frequency and
691  * divider parameters, such as DDS_CLK_RATE and SCR:
692  *
693  * Fsys = 200MHz
694  *
695  * Fssp = Fsys * DDS_CLK_RATE / 2^24			(1)
696  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))		(2)
697  *
698  * DDS_CLK_RATE either 2^n or 2^n / 5.
699  * SCR is in range 0 .. 255
700  *
701  * Divisor = 5^i * 2^j * 2 * k
702  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
703  *       j = [0, 23]     j = 0 iff i = 1
704  *       k = [1, 256]
705  * Special case: j = 0, i = 1: Divisor = 2 / 5
706  *
707  * Accordingly to the specification the recommended values for DDS_CLK_RATE
708  * are:
709  *	Case 1:		2^n, n = [0, 23]
710  *	Case 2:		2^24 * 2 / 5 (0x666666)
711  *	Case 3:		less than or equal to 2^24 / 5 / 16 (0x33333)
712  *
713  * In all cases the lowest possible value is better.
714  *
715  * The function calculates parameters for all cases and chooses the one closest
716  * to the asked baud rate.
717  */
718 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
719 {
720 	unsigned long xtal = 200000000;
721 	unsigned long fref = xtal / 2;		/* mandatory division by 2,
722 						   see (2) */
723 						/* case 3 */
724 	unsigned long fref1 = fref / 2;		/* case 1 */
725 	unsigned long fref2 = fref * 2 / 5;	/* case 2 */
726 	unsigned long scale;
727 	unsigned long q, q1, q2;
728 	long r, r1, r2;
729 	u32 mul;
730 
731 	/* Case 1 */
732 
733 	/* Set initial value for DDS_CLK_RATE */
734 	mul = (1 << 24) >> 1;
735 
736 	/* Calculate initial quot */
737 	q1 = DIV_ROUND_CLOSEST(fref1, rate);
738 
739 	/* Scale q1 if it's too big */
740 	if (q1 > 256) {
741 		/* Scale q1 to range [1, 512] */
742 		scale = fls_long(q1 - 1);
743 		if (scale > 9) {
744 			q1 >>= scale - 9;
745 			mul >>= scale - 9;
746 		}
747 
748 		/* Round the result if we have a remainder */
749 		q1 += q1 & 1;
750 	}
751 
752 	/* Decrease DDS_CLK_RATE as much as we can without loss in precision */
753 	scale = __ffs(q1);
754 	q1 >>= scale;
755 	mul >>= scale;
756 
757 	/* Get the remainder */
758 	r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
759 
760 	/* Case 2 */
761 
762 	q2 = DIV_ROUND_CLOSEST(fref2, rate);
763 	r2 = abs(fref2 / q2 - rate);
764 
765 	/*
766 	 * Choose the best between two: less remainder we have the better. We
767 	 * can't go case 2 if q2 is greater than 256 since SCR register can
768 	 * hold only values 0 .. 255.
769 	 */
770 	if (r2 >= r1 || q2 > 256) {
771 		/* case 1 is better */
772 		r = r1;
773 		q = q1;
774 	} else {
775 		/* case 2 is better */
776 		r = r2;
777 		q = q2;
778 		mul = (1 << 24) * 2 / 5;
779 	}
780 
781 	/* Check case 3 only If the divisor is big enough */
782 	if (fref / rate >= 80) {
783 		u64 fssp;
784 		u32 m;
785 
786 		/* Calculate initial quot */
787 		q1 = DIV_ROUND_CLOSEST(fref, rate);
788 		m = (1 << 24) / q1;
789 
790 		/* Get the remainder */
791 		fssp = (u64)fref * m;
792 		do_div(fssp, 1 << 24);
793 		r1 = abs(fssp - rate);
794 
795 		/* Choose this one if it suits better */
796 		if (r1 < r) {
797 			/* case 3 is better */
798 			q = 1;
799 			mul = m;
800 		}
801 	}
802 
803 	*dds = mul;
804 	return q - 1;
805 }
806 
807 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
808 {
809 	unsigned long ssp_clk = drv_data->max_clk_rate;
810 	const struct ssp_device *ssp = drv_data->ssp;
811 
812 	rate = min_t(int, ssp_clk, rate);
813 
814 	if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
815 		return (ssp_clk / (2 * rate) - 1) & 0xff;
816 	else
817 		return (ssp_clk / rate - 1) & 0xfff;
818 }
819 
820 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
821 					   struct chip_data *chip, int rate)
822 {
823 	unsigned int clk_div;
824 
825 	switch (drv_data->ssp_type) {
826 	case QUARK_X1000_SSP:
827 		clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
828 		break;
829 	default:
830 		clk_div = ssp_get_clk_div(drv_data, rate);
831 		break;
832 	}
833 	return clk_div << 8;
834 }
835 
836 static void pump_transfers(unsigned long data)
837 {
838 	struct driver_data *drv_data = (struct driver_data *)data;
839 	struct spi_message *message = NULL;
840 	struct spi_transfer *transfer = NULL;
841 	struct spi_transfer *previous = NULL;
842 	struct chip_data *chip = NULL;
843 	u32 clk_div = 0;
844 	u8 bits = 0;
845 	u32 speed = 0;
846 	u32 cr0;
847 	u32 cr1;
848 	u32 dma_thresh = drv_data->cur_chip->dma_threshold;
849 	u32 dma_burst = drv_data->cur_chip->dma_burst_size;
850 	u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
851 
852 	/* Get current state information */
853 	message = drv_data->cur_msg;
854 	transfer = drv_data->cur_transfer;
855 	chip = drv_data->cur_chip;
856 
857 	/* Handle for abort */
858 	if (message->state == ERROR_STATE) {
859 		message->status = -EIO;
860 		giveback(drv_data);
861 		return;
862 	}
863 
864 	/* Handle end of message */
865 	if (message->state == DONE_STATE) {
866 		message->status = 0;
867 		giveback(drv_data);
868 		return;
869 	}
870 
871 	/* Delay if requested at end of transfer before CS change */
872 	if (message->state == RUNNING_STATE) {
873 		previous = list_entry(transfer->transfer_list.prev,
874 					struct spi_transfer,
875 					transfer_list);
876 		if (previous->delay_usecs)
877 			udelay(previous->delay_usecs);
878 
879 		/* Drop chip select only if cs_change is requested */
880 		if (previous->cs_change)
881 			cs_deassert(drv_data);
882 	}
883 
884 	/* Check if we can DMA this transfer */
885 	if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
886 
887 		/* reject already-mapped transfers; PIO won't always work */
888 		if (message->is_dma_mapped
889 				|| transfer->rx_dma || transfer->tx_dma) {
890 			dev_err(&drv_data->pdev->dev,
891 				"pump_transfers: mapped transfer length of "
892 				"%u is greater than %d\n",
893 				transfer->len, MAX_DMA_LEN);
894 			message->status = -EINVAL;
895 			giveback(drv_data);
896 			return;
897 		}
898 
899 		/* warn ... we force this to PIO mode */
900 		dev_warn_ratelimited(&message->spi->dev,
901 				     "pump_transfers: DMA disabled for transfer length %ld "
902 				     "greater than %d\n",
903 				     (long)drv_data->len, MAX_DMA_LEN);
904 	}
905 
906 	/* Setup the transfer state based on the type of transfer */
907 	if (pxa2xx_spi_flush(drv_data) == 0) {
908 		dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
909 		message->status = -EIO;
910 		giveback(drv_data);
911 		return;
912 	}
913 	drv_data->n_bytes = chip->n_bytes;
914 	drv_data->tx = (void *)transfer->tx_buf;
915 	drv_data->tx_end = drv_data->tx + transfer->len;
916 	drv_data->rx = transfer->rx_buf;
917 	drv_data->rx_end = drv_data->rx + transfer->len;
918 	drv_data->rx_dma = transfer->rx_dma;
919 	drv_data->tx_dma = transfer->tx_dma;
920 	drv_data->len = transfer->len;
921 	drv_data->write = drv_data->tx ? chip->write : null_writer;
922 	drv_data->read = drv_data->rx ? chip->read : null_reader;
923 
924 	/* Change speed and bit per word on a per transfer */
925 	cr0 = chip->cr0;
926 	if (transfer->speed_hz || transfer->bits_per_word) {
927 
928 		bits = chip->bits_per_word;
929 		speed = chip->speed_hz;
930 
931 		if (transfer->speed_hz)
932 			speed = transfer->speed_hz;
933 
934 		if (transfer->bits_per_word)
935 			bits = transfer->bits_per_word;
936 
937 		clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed);
938 
939 		if (bits <= 8) {
940 			drv_data->n_bytes = 1;
941 			drv_data->read = drv_data->read != null_reader ?
942 						u8_reader : null_reader;
943 			drv_data->write = drv_data->write != null_writer ?
944 						u8_writer : null_writer;
945 		} else if (bits <= 16) {
946 			drv_data->n_bytes = 2;
947 			drv_data->read = drv_data->read != null_reader ?
948 						u16_reader : null_reader;
949 			drv_data->write = drv_data->write != null_writer ?
950 						u16_writer : null_writer;
951 		} else if (bits <= 32) {
952 			drv_data->n_bytes = 4;
953 			drv_data->read = drv_data->read != null_reader ?
954 						u32_reader : null_reader;
955 			drv_data->write = drv_data->write != null_writer ?
956 						u32_writer : null_writer;
957 		}
958 		/* if bits/word is changed in dma mode, then must check the
959 		 * thresholds and burst also */
960 		if (chip->enable_dma) {
961 			if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
962 							message->spi,
963 							bits, &dma_burst,
964 							&dma_thresh))
965 				dev_warn_ratelimited(&message->spi->dev,
966 						     "pump_transfers: DMA burst size reduced to match bits_per_word\n");
967 		}
968 
969 		cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
970 	}
971 
972 	message->state = RUNNING_STATE;
973 
974 	drv_data->dma_mapped = 0;
975 	if (pxa2xx_spi_dma_is_possible(drv_data->len))
976 		drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
977 	if (drv_data->dma_mapped) {
978 
979 		/* Ensure we have the correct interrupt handler */
980 		drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
981 
982 		pxa2xx_spi_dma_prepare(drv_data, dma_burst);
983 
984 		/* Clear status and start DMA engine */
985 		cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
986 		pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
987 
988 		pxa2xx_spi_dma_start(drv_data);
989 	} else {
990 		/* Ensure we have the correct interrupt handler	*/
991 		drv_data->transfer_handler = interrupt_transfer;
992 
993 		/* Clear status  */
994 		cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
995 		write_SSSR_CS(drv_data, drv_data->clear_sr);
996 	}
997 
998 	if (is_lpss_ssp(drv_data)) {
999 		if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1000 		    != chip->lpss_rx_threshold)
1001 			pxa2xx_spi_write(drv_data, SSIRF,
1002 					 chip->lpss_rx_threshold);
1003 		if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1004 		    != chip->lpss_tx_threshold)
1005 			pxa2xx_spi_write(drv_data, SSITF,
1006 					 chip->lpss_tx_threshold);
1007 	}
1008 
1009 	if (is_quark_x1000_ssp(drv_data) &&
1010 	    (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1011 		pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1012 
1013 	/* see if we need to reload the config registers */
1014 	if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1015 	    || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1016 	    != (cr1 & change_mask)) {
1017 		/* stop the SSP, and update the other bits */
1018 		pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1019 		if (!pxa25x_ssp_comp(drv_data))
1020 			pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1021 		/* first set CR1 without interrupt and service enables */
1022 		pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1023 		/* restart the SSP */
1024 		pxa2xx_spi_write(drv_data, SSCR0, cr0);
1025 
1026 	} else {
1027 		if (!pxa25x_ssp_comp(drv_data))
1028 			pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1029 	}
1030 
1031 	cs_assert(drv_data);
1032 
1033 	/* after chip select, release the data by enabling service
1034 	 * requests and interrupts, without changing any mode bits */
1035 	pxa2xx_spi_write(drv_data, SSCR1, cr1);
1036 }
1037 
1038 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1039 					   struct spi_message *msg)
1040 {
1041 	struct driver_data *drv_data = spi_master_get_devdata(master);
1042 
1043 	drv_data->cur_msg = msg;
1044 	/* Initial message state*/
1045 	drv_data->cur_msg->state = START_STATE;
1046 	drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1047 						struct spi_transfer,
1048 						transfer_list);
1049 
1050 	/* prepare to setup the SSP, in pump_transfers, using the per
1051 	 * chip configuration */
1052 	drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1053 
1054 	/* Mark as busy and launch transfers */
1055 	tasklet_schedule(&drv_data->pump_transfers);
1056 	return 0;
1057 }
1058 
1059 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1060 {
1061 	struct driver_data *drv_data = spi_master_get_devdata(master);
1062 
1063 	/* Disable the SSP now */
1064 	pxa2xx_spi_write(drv_data, SSCR0,
1065 			 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1066 
1067 	return 0;
1068 }
1069 
1070 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1071 		    struct pxa2xx_spi_chip *chip_info)
1072 {
1073 	int err = 0;
1074 
1075 	if (chip == NULL || chip_info == NULL)
1076 		return 0;
1077 
1078 	/* NOTE: setup() can be called multiple times, possibly with
1079 	 * different chip_info, release previously requested GPIO
1080 	 */
1081 	if (gpio_is_valid(chip->gpio_cs))
1082 		gpio_free(chip->gpio_cs);
1083 
1084 	/* If (*cs_control) is provided, ignore GPIO chip select */
1085 	if (chip_info->cs_control) {
1086 		chip->cs_control = chip_info->cs_control;
1087 		return 0;
1088 	}
1089 
1090 	if (gpio_is_valid(chip_info->gpio_cs)) {
1091 		err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1092 		if (err) {
1093 			dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1094 				chip_info->gpio_cs);
1095 			return err;
1096 		}
1097 
1098 		chip->gpio_cs = chip_info->gpio_cs;
1099 		chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1100 
1101 		err = gpio_direction_output(chip->gpio_cs,
1102 					!chip->gpio_cs_inverted);
1103 	}
1104 
1105 	return err;
1106 }
1107 
1108 static int setup(struct spi_device *spi)
1109 {
1110 	struct pxa2xx_spi_chip *chip_info = NULL;
1111 	struct chip_data *chip;
1112 	const struct lpss_config *config;
1113 	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1114 	unsigned int clk_div;
1115 	uint tx_thres, tx_hi_thres, rx_thres;
1116 
1117 	switch (drv_data->ssp_type) {
1118 	case QUARK_X1000_SSP:
1119 		tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1120 		tx_hi_thres = 0;
1121 		rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1122 		break;
1123 	case LPSS_LPT_SSP:
1124 	case LPSS_BYT_SSP:
1125 	case LPSS_SPT_SSP:
1126 		config = lpss_get_config(drv_data);
1127 		tx_thres = config->tx_threshold_lo;
1128 		tx_hi_thres = config->tx_threshold_hi;
1129 		rx_thres = config->rx_threshold;
1130 		break;
1131 	default:
1132 		tx_thres = TX_THRESH_DFLT;
1133 		tx_hi_thres = 0;
1134 		rx_thres = RX_THRESH_DFLT;
1135 		break;
1136 	}
1137 
1138 	/* Only alloc on first setup */
1139 	chip = spi_get_ctldata(spi);
1140 	if (!chip) {
1141 		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1142 		if (!chip)
1143 			return -ENOMEM;
1144 
1145 		if (drv_data->ssp_type == CE4100_SSP) {
1146 			if (spi->chip_select > 4) {
1147 				dev_err(&spi->dev,
1148 					"failed setup: cs number must not be > 4.\n");
1149 				kfree(chip);
1150 				return -EINVAL;
1151 			}
1152 
1153 			chip->frm = spi->chip_select;
1154 		} else
1155 			chip->gpio_cs = -1;
1156 		chip->enable_dma = 0;
1157 		chip->timeout = TIMOUT_DFLT;
1158 	}
1159 
1160 	/* protocol drivers may change the chip settings, so...
1161 	 * if chip_info exists, use it */
1162 	chip_info = spi->controller_data;
1163 
1164 	/* chip_info isn't always needed */
1165 	chip->cr1 = 0;
1166 	if (chip_info) {
1167 		if (chip_info->timeout)
1168 			chip->timeout = chip_info->timeout;
1169 		if (chip_info->tx_threshold)
1170 			tx_thres = chip_info->tx_threshold;
1171 		if (chip_info->tx_hi_threshold)
1172 			tx_hi_thres = chip_info->tx_hi_threshold;
1173 		if (chip_info->rx_threshold)
1174 			rx_thres = chip_info->rx_threshold;
1175 		chip->enable_dma = drv_data->master_info->enable_dma;
1176 		chip->dma_threshold = 0;
1177 		if (chip_info->enable_loopback)
1178 			chip->cr1 = SSCR1_LBM;
1179 	} else if (ACPI_HANDLE(&spi->dev)) {
1180 		/*
1181 		 * Slave devices enumerated from ACPI namespace don't
1182 		 * usually have chip_info but we still might want to use
1183 		 * DMA with them.
1184 		 */
1185 		chip->enable_dma = drv_data->master_info->enable_dma;
1186 	}
1187 
1188 	chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1189 	chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1190 				| SSITF_TxHiThresh(tx_hi_thres);
1191 
1192 	/* set dma burst and threshold outside of chip_info path so that if
1193 	 * chip_info goes away after setting chip->enable_dma, the
1194 	 * burst and threshold can still respond to changes in bits_per_word */
1195 	if (chip->enable_dma) {
1196 		/* set up legal burst and threshold for dma */
1197 		if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1198 						spi->bits_per_word,
1199 						&chip->dma_burst_size,
1200 						&chip->dma_threshold)) {
1201 			dev_warn(&spi->dev,
1202 				 "in setup: DMA burst size reduced to match bits_per_word\n");
1203 		}
1204 	}
1205 
1206 	clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz);
1207 	chip->speed_hz = spi->max_speed_hz;
1208 
1209 	chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div,
1210 					   spi->bits_per_word);
1211 	switch (drv_data->ssp_type) {
1212 	case QUARK_X1000_SSP:
1213 		chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1214 				   & QUARK_X1000_SSCR1_RFT)
1215 				   | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1216 				   & QUARK_X1000_SSCR1_TFT);
1217 		break;
1218 	default:
1219 		chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1220 			(SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1221 		break;
1222 	}
1223 
1224 	chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1225 	chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1226 			| (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1227 
1228 	if (spi->mode & SPI_LOOP)
1229 		chip->cr1 |= SSCR1_LBM;
1230 
1231 	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1232 	if (!pxa25x_ssp_comp(drv_data))
1233 		dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1234 			drv_data->max_clk_rate
1235 				/ (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1236 			chip->enable_dma ? "DMA" : "PIO");
1237 	else
1238 		dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1239 			drv_data->max_clk_rate / 2
1240 				/ (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1241 			chip->enable_dma ? "DMA" : "PIO");
1242 
1243 	if (spi->bits_per_word <= 8) {
1244 		chip->n_bytes = 1;
1245 		chip->read = u8_reader;
1246 		chip->write = u8_writer;
1247 	} else if (spi->bits_per_word <= 16) {
1248 		chip->n_bytes = 2;
1249 		chip->read = u16_reader;
1250 		chip->write = u16_writer;
1251 	} else if (spi->bits_per_word <= 32) {
1252 		if (!is_quark_x1000_ssp(drv_data))
1253 			chip->cr0 |= SSCR0_EDSS;
1254 		chip->n_bytes = 4;
1255 		chip->read = u32_reader;
1256 		chip->write = u32_writer;
1257 	}
1258 	chip->bits_per_word = spi->bits_per_word;
1259 
1260 	spi_set_ctldata(spi, chip);
1261 
1262 	if (drv_data->ssp_type == CE4100_SSP)
1263 		return 0;
1264 
1265 	return setup_cs(spi, chip, chip_info);
1266 }
1267 
1268 static void cleanup(struct spi_device *spi)
1269 {
1270 	struct chip_data *chip = spi_get_ctldata(spi);
1271 	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1272 
1273 	if (!chip)
1274 		return;
1275 
1276 	if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1277 		gpio_free(chip->gpio_cs);
1278 
1279 	kfree(chip);
1280 }
1281 
1282 #ifdef CONFIG_ACPI
1283 
1284 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1285 	{ "INT33C0", LPSS_LPT_SSP },
1286 	{ "INT33C1", LPSS_LPT_SSP },
1287 	{ "INT3430", LPSS_LPT_SSP },
1288 	{ "INT3431", LPSS_LPT_SSP },
1289 	{ "80860F0E", LPSS_BYT_SSP },
1290 	{ "8086228E", LPSS_BYT_SSP },
1291 	{ },
1292 };
1293 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1294 
1295 /*
1296  * PCI IDs of compound devices that integrate both host controller and private
1297  * integrated DMA engine. Please note these are not used in module
1298  * autoloading and probing in this module but matching the LPSS SSP type.
1299  */
1300 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1301 	/* SPT-LP */
1302 	{ PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1303 	{ PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1304 	/* SPT-H */
1305 	{ PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1306 	{ PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1307 	{ },
1308 };
1309 
1310 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1311 {
1312 	struct device *dev = param;
1313 
1314 	if (dev != chan->device->dev->parent)
1315 		return false;
1316 
1317 	return true;
1318 }
1319 
1320 static struct pxa2xx_spi_master *
1321 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1322 {
1323 	struct pxa2xx_spi_master *pdata;
1324 	struct acpi_device *adev;
1325 	struct ssp_device *ssp;
1326 	struct resource *res;
1327 	const struct acpi_device_id *adev_id = NULL;
1328 	const struct pci_device_id *pcidev_id = NULL;
1329 	int devid, type;
1330 
1331 	if (!ACPI_HANDLE(&pdev->dev) ||
1332 	    acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1333 		return NULL;
1334 
1335 	if (dev_is_pci(pdev->dev.parent))
1336 		pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1337 					 to_pci_dev(pdev->dev.parent));
1338 	else
1339 		adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1340 					    &pdev->dev);
1341 
1342 	if (adev_id)
1343 		type = (int)adev_id->driver_data;
1344 	else if (pcidev_id)
1345 		type = (int)pcidev_id->driver_data;
1346 	else
1347 		return NULL;
1348 
1349 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1350 	if (!pdata)
1351 		return NULL;
1352 
1353 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1354 	if (!res)
1355 		return NULL;
1356 
1357 	ssp = &pdata->ssp;
1358 
1359 	ssp->phys_base = res->start;
1360 	ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1361 	if (IS_ERR(ssp->mmio_base))
1362 		return NULL;
1363 
1364 	if (pcidev_id) {
1365 		pdata->tx_param = pdev->dev.parent;
1366 		pdata->rx_param = pdev->dev.parent;
1367 		pdata->dma_filter = pxa2xx_spi_idma_filter;
1368 	}
1369 
1370 	ssp->clk = devm_clk_get(&pdev->dev, NULL);
1371 	ssp->irq = platform_get_irq(pdev, 0);
1372 	ssp->type = type;
1373 	ssp->pdev = pdev;
1374 
1375 	ssp->port_id = -1;
1376 	if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1377 		ssp->port_id = devid;
1378 
1379 	pdata->num_chipselect = 1;
1380 	pdata->enable_dma = true;
1381 
1382 	return pdata;
1383 }
1384 
1385 #else
1386 static inline struct pxa2xx_spi_master *
1387 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1388 {
1389 	return NULL;
1390 }
1391 #endif
1392 
1393 static int pxa2xx_spi_probe(struct platform_device *pdev)
1394 {
1395 	struct device *dev = &pdev->dev;
1396 	struct pxa2xx_spi_master *platform_info;
1397 	struct spi_master *master;
1398 	struct driver_data *drv_data;
1399 	struct ssp_device *ssp;
1400 	int status;
1401 	u32 tmp;
1402 
1403 	platform_info = dev_get_platdata(dev);
1404 	if (!platform_info) {
1405 		platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1406 		if (!platform_info) {
1407 			dev_err(&pdev->dev, "missing platform data\n");
1408 			return -ENODEV;
1409 		}
1410 	}
1411 
1412 	ssp = pxa_ssp_request(pdev->id, pdev->name);
1413 	if (!ssp)
1414 		ssp = &platform_info->ssp;
1415 
1416 	if (!ssp->mmio_base) {
1417 		dev_err(&pdev->dev, "failed to get ssp\n");
1418 		return -ENODEV;
1419 	}
1420 
1421 	master = spi_alloc_master(dev, sizeof(struct driver_data));
1422 	if (!master) {
1423 		dev_err(&pdev->dev, "cannot alloc spi_master\n");
1424 		pxa_ssp_free(ssp);
1425 		return -ENOMEM;
1426 	}
1427 	drv_data = spi_master_get_devdata(master);
1428 	drv_data->master = master;
1429 	drv_data->master_info = platform_info;
1430 	drv_data->pdev = pdev;
1431 	drv_data->ssp = ssp;
1432 
1433 	master->dev.parent = &pdev->dev;
1434 	master->dev.of_node = pdev->dev.of_node;
1435 	/* the spi->mode bits understood by this driver: */
1436 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1437 
1438 	master->bus_num = ssp->port_id;
1439 	master->num_chipselect = platform_info->num_chipselect;
1440 	master->dma_alignment = DMA_ALIGNMENT;
1441 	master->cleanup = cleanup;
1442 	master->setup = setup;
1443 	master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1444 	master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1445 	master->auto_runtime_pm = true;
1446 
1447 	drv_data->ssp_type = ssp->type;
1448 
1449 	drv_data->ioaddr = ssp->mmio_base;
1450 	drv_data->ssdr_physical = ssp->phys_base + SSDR;
1451 	if (pxa25x_ssp_comp(drv_data)) {
1452 		switch (drv_data->ssp_type) {
1453 		case QUARK_X1000_SSP:
1454 			master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1455 			break;
1456 		default:
1457 			master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1458 			break;
1459 		}
1460 
1461 		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1462 		drv_data->dma_cr1 = 0;
1463 		drv_data->clear_sr = SSSR_ROR;
1464 		drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1465 	} else {
1466 		master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1467 		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1468 		drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1469 		drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1470 		drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1471 	}
1472 
1473 	status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1474 			drv_data);
1475 	if (status < 0) {
1476 		dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1477 		goto out_error_master_alloc;
1478 	}
1479 
1480 	/* Setup DMA if requested */
1481 	if (platform_info->enable_dma) {
1482 		status = pxa2xx_spi_dma_setup(drv_data);
1483 		if (status) {
1484 			dev_dbg(dev, "no DMA channels available, using PIO\n");
1485 			platform_info->enable_dma = false;
1486 		}
1487 	}
1488 
1489 	/* Enable SOC clock */
1490 	clk_prepare_enable(ssp->clk);
1491 
1492 	drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1493 
1494 	/* Load default SSP configuration */
1495 	pxa2xx_spi_write(drv_data, SSCR0, 0);
1496 	switch (drv_data->ssp_type) {
1497 	case QUARK_X1000_SSP:
1498 		tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1499 		      | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1500 		pxa2xx_spi_write(drv_data, SSCR1, tmp);
1501 
1502 		/* using the Motorola SPI protocol and use 8 bit frame */
1503 		pxa2xx_spi_write(drv_data, SSCR0,
1504 				 QUARK_X1000_SSCR0_Motorola
1505 				 | QUARK_X1000_SSCR0_DataSize(8));
1506 		break;
1507 	default:
1508 		tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1509 		      SSCR1_TxTresh(TX_THRESH_DFLT);
1510 		pxa2xx_spi_write(drv_data, SSCR1, tmp);
1511 		tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1512 		pxa2xx_spi_write(drv_data, SSCR0, tmp);
1513 		break;
1514 	}
1515 
1516 	if (!pxa25x_ssp_comp(drv_data))
1517 		pxa2xx_spi_write(drv_data, SSTO, 0);
1518 
1519 	if (!is_quark_x1000_ssp(drv_data))
1520 		pxa2xx_spi_write(drv_data, SSPSP, 0);
1521 
1522 	if (is_lpss_ssp(drv_data))
1523 		lpss_ssp_setup(drv_data);
1524 
1525 	tasklet_init(&drv_data->pump_transfers, pump_transfers,
1526 		     (unsigned long)drv_data);
1527 
1528 	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1529 	pm_runtime_use_autosuspend(&pdev->dev);
1530 	pm_runtime_set_active(&pdev->dev);
1531 	pm_runtime_enable(&pdev->dev);
1532 
1533 	/* Register with the SPI framework */
1534 	platform_set_drvdata(pdev, drv_data);
1535 	status = devm_spi_register_master(&pdev->dev, master);
1536 	if (status != 0) {
1537 		dev_err(&pdev->dev, "problem registering spi master\n");
1538 		goto out_error_clock_enabled;
1539 	}
1540 
1541 	return status;
1542 
1543 out_error_clock_enabled:
1544 	clk_disable_unprepare(ssp->clk);
1545 	pxa2xx_spi_dma_release(drv_data);
1546 	free_irq(ssp->irq, drv_data);
1547 
1548 out_error_master_alloc:
1549 	spi_master_put(master);
1550 	pxa_ssp_free(ssp);
1551 	return status;
1552 }
1553 
1554 static int pxa2xx_spi_remove(struct platform_device *pdev)
1555 {
1556 	struct driver_data *drv_data = platform_get_drvdata(pdev);
1557 	struct ssp_device *ssp;
1558 
1559 	if (!drv_data)
1560 		return 0;
1561 	ssp = drv_data->ssp;
1562 
1563 	pm_runtime_get_sync(&pdev->dev);
1564 
1565 	/* Disable the SSP at the peripheral and SOC level */
1566 	pxa2xx_spi_write(drv_data, SSCR0, 0);
1567 	clk_disable_unprepare(ssp->clk);
1568 
1569 	/* Release DMA */
1570 	if (drv_data->master_info->enable_dma)
1571 		pxa2xx_spi_dma_release(drv_data);
1572 
1573 	pm_runtime_put_noidle(&pdev->dev);
1574 	pm_runtime_disable(&pdev->dev);
1575 
1576 	/* Release IRQ */
1577 	free_irq(ssp->irq, drv_data);
1578 
1579 	/* Release SSP */
1580 	pxa_ssp_free(ssp);
1581 
1582 	return 0;
1583 }
1584 
1585 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1586 {
1587 	int status = 0;
1588 
1589 	if ((status = pxa2xx_spi_remove(pdev)) != 0)
1590 		dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1591 }
1592 
1593 #ifdef CONFIG_PM_SLEEP
1594 static int pxa2xx_spi_suspend(struct device *dev)
1595 {
1596 	struct driver_data *drv_data = dev_get_drvdata(dev);
1597 	struct ssp_device *ssp = drv_data->ssp;
1598 	int status = 0;
1599 
1600 	status = spi_master_suspend(drv_data->master);
1601 	if (status != 0)
1602 		return status;
1603 	pxa2xx_spi_write(drv_data, SSCR0, 0);
1604 
1605 	if (!pm_runtime_suspended(dev))
1606 		clk_disable_unprepare(ssp->clk);
1607 
1608 	return 0;
1609 }
1610 
1611 static int pxa2xx_spi_resume(struct device *dev)
1612 {
1613 	struct driver_data *drv_data = dev_get_drvdata(dev);
1614 	struct ssp_device *ssp = drv_data->ssp;
1615 	int status = 0;
1616 
1617 	pxa2xx_spi_dma_resume(drv_data);
1618 
1619 	/* Enable the SSP clock */
1620 	if (!pm_runtime_suspended(dev))
1621 		clk_prepare_enable(ssp->clk);
1622 
1623 	/* Restore LPSS private register bits */
1624 	if (is_lpss_ssp(drv_data))
1625 		lpss_ssp_setup(drv_data);
1626 
1627 	/* Start the queue running */
1628 	status = spi_master_resume(drv_data->master);
1629 	if (status != 0) {
1630 		dev_err(dev, "problem starting queue (%d)\n", status);
1631 		return status;
1632 	}
1633 
1634 	return 0;
1635 }
1636 #endif
1637 
1638 #ifdef CONFIG_PM
1639 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1640 {
1641 	struct driver_data *drv_data = dev_get_drvdata(dev);
1642 
1643 	clk_disable_unprepare(drv_data->ssp->clk);
1644 	return 0;
1645 }
1646 
1647 static int pxa2xx_spi_runtime_resume(struct device *dev)
1648 {
1649 	struct driver_data *drv_data = dev_get_drvdata(dev);
1650 
1651 	clk_prepare_enable(drv_data->ssp->clk);
1652 	return 0;
1653 }
1654 #endif
1655 
1656 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1657 	SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1658 	SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1659 			   pxa2xx_spi_runtime_resume, NULL)
1660 };
1661 
1662 static struct platform_driver driver = {
1663 	.driver = {
1664 		.name	= "pxa2xx-spi",
1665 		.pm	= &pxa2xx_spi_pm_ops,
1666 		.acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1667 	},
1668 	.probe = pxa2xx_spi_probe,
1669 	.remove = pxa2xx_spi_remove,
1670 	.shutdown = pxa2xx_spi_shutdown,
1671 };
1672 
1673 static int __init pxa2xx_spi_init(void)
1674 {
1675 	return platform_driver_register(&driver);
1676 }
1677 subsys_initcall(pxa2xx_spi_init);
1678 
1679 static void __exit pxa2xx_spi_exit(void)
1680 {
1681 	platform_driver_unregister(&driver);
1682 }
1683 module_exit(pxa2xx_spi_exit);
1684