1 /* 2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3 * Copyright (C) 2013, Intel Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/device.h> 23 #include <linux/ioport.h> 24 #include <linux/errno.h> 25 #include <linux/err.h> 26 #include <linux/interrupt.h> 27 #include <linux/platform_device.h> 28 #include <linux/spi/pxa2xx_spi.h> 29 #include <linux/spi/spi.h> 30 #include <linux/delay.h> 31 #include <linux/gpio.h> 32 #include <linux/slab.h> 33 #include <linux/clk.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/acpi.h> 36 37 #include <asm/io.h> 38 #include <asm/irq.h> 39 #include <asm/delay.h> 40 41 #include "spi-pxa2xx.h" 42 43 MODULE_AUTHOR("Stephen Street"); 44 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 45 MODULE_LICENSE("GPL"); 46 MODULE_ALIAS("platform:pxa2xx-spi"); 47 48 #define MAX_BUSES 3 49 50 #define TIMOUT_DFLT 1000 51 52 /* 53 * for testing SSCR1 changes that require SSP restart, basically 54 * everything except the service and interrupt enables, the pxa270 developer 55 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 56 * list, but the PXA255 dev man says all bits without really meaning the 57 * service and interrupt enables 58 */ 59 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 60 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 61 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 62 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 63 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 65 66 #define LPSS_RX_THRESH_DFLT 64 67 #define LPSS_TX_LOTHRESH_DFLT 160 68 #define LPSS_TX_HITHRESH_DFLT 224 69 70 /* Offset from drv_data->lpss_base */ 71 #define GENERAL_REG 0x08 72 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 73 #define SSP_REG 0x0c 74 #define SPI_CS_CONTROL 0x18 75 #define SPI_CS_CONTROL_SW_MODE BIT(0) 76 #define SPI_CS_CONTROL_CS_HIGH BIT(1) 77 78 static bool is_lpss_ssp(const struct driver_data *drv_data) 79 { 80 return drv_data->ssp_type == LPSS_SSP; 81 } 82 83 /* 84 * Read and write LPSS SSP private registers. Caller must first check that 85 * is_lpss_ssp() returns true before these can be called. 86 */ 87 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 88 { 89 WARN_ON(!drv_data->lpss_base); 90 return readl(drv_data->lpss_base + offset); 91 } 92 93 static void __lpss_ssp_write_priv(struct driver_data *drv_data, 94 unsigned offset, u32 value) 95 { 96 WARN_ON(!drv_data->lpss_base); 97 writel(value, drv_data->lpss_base + offset); 98 } 99 100 /* 101 * lpss_ssp_setup - perform LPSS SSP specific setup 102 * @drv_data: pointer to the driver private data 103 * 104 * Perform LPSS SSP specific setup. This function must be called first if 105 * one is going to use LPSS SSP private registers. 106 */ 107 static void lpss_ssp_setup(struct driver_data *drv_data) 108 { 109 unsigned offset = 0x400; 110 u32 value, orig; 111 112 if (!is_lpss_ssp(drv_data)) 113 return; 114 115 /* 116 * Perform auto-detection of the LPSS SSP private registers. They 117 * can be either at 1k or 2k offset from the base address. 118 */ 119 orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 120 121 value = orig | SPI_CS_CONTROL_SW_MODE; 122 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 123 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 124 if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { 125 offset = 0x800; 126 goto detection_done; 127 } 128 129 value &= ~SPI_CS_CONTROL_SW_MODE; 130 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); 131 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); 132 if (value != orig) { 133 offset = 0x800; 134 goto detection_done; 135 } 136 137 detection_done: 138 /* Now set the LPSS base */ 139 drv_data->lpss_base = drv_data->ioaddr + offset; 140 141 /* Enable software chip select control */ 142 value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; 143 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 144 145 /* Enable multiblock DMA transfers */ 146 if (drv_data->master_info->enable_dma) { 147 __lpss_ssp_write_priv(drv_data, SSP_REG, 1); 148 149 value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); 150 value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; 151 __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); 152 } 153 } 154 155 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) 156 { 157 u32 value; 158 159 if (!is_lpss_ssp(drv_data)) 160 return; 161 162 value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); 163 if (enable) 164 value &= ~SPI_CS_CONTROL_CS_HIGH; 165 else 166 value |= SPI_CS_CONTROL_CS_HIGH; 167 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); 168 } 169 170 static void cs_assert(struct driver_data *drv_data) 171 { 172 struct chip_data *chip = drv_data->cur_chip; 173 174 if (drv_data->ssp_type == CE4100_SSP) { 175 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); 176 return; 177 } 178 179 if (chip->cs_control) { 180 chip->cs_control(PXA2XX_CS_ASSERT); 181 return; 182 } 183 184 if (gpio_is_valid(chip->gpio_cs)) { 185 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 186 return; 187 } 188 189 lpss_ssp_cs_control(drv_data, true); 190 } 191 192 static void cs_deassert(struct driver_data *drv_data) 193 { 194 struct chip_data *chip = drv_data->cur_chip; 195 196 if (drv_data->ssp_type == CE4100_SSP) 197 return; 198 199 if (chip->cs_control) { 200 chip->cs_control(PXA2XX_CS_DEASSERT); 201 return; 202 } 203 204 if (gpio_is_valid(chip->gpio_cs)) { 205 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 206 return; 207 } 208 209 lpss_ssp_cs_control(drv_data, false); 210 } 211 212 int pxa2xx_spi_flush(struct driver_data *drv_data) 213 { 214 unsigned long limit = loops_per_jiffy << 1; 215 216 void __iomem *reg = drv_data->ioaddr; 217 218 do { 219 while (read_SSSR(reg) & SSSR_RNE) { 220 read_SSDR(reg); 221 } 222 } while ((read_SSSR(reg) & SSSR_BSY) && --limit); 223 write_SSSR_CS(drv_data, SSSR_ROR); 224 225 return limit; 226 } 227 228 static int null_writer(struct driver_data *drv_data) 229 { 230 void __iomem *reg = drv_data->ioaddr; 231 u8 n_bytes = drv_data->n_bytes; 232 233 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 234 || (drv_data->tx == drv_data->tx_end)) 235 return 0; 236 237 write_SSDR(0, reg); 238 drv_data->tx += n_bytes; 239 240 return 1; 241 } 242 243 static int null_reader(struct driver_data *drv_data) 244 { 245 void __iomem *reg = drv_data->ioaddr; 246 u8 n_bytes = drv_data->n_bytes; 247 248 while ((read_SSSR(reg) & SSSR_RNE) 249 && (drv_data->rx < drv_data->rx_end)) { 250 read_SSDR(reg); 251 drv_data->rx += n_bytes; 252 } 253 254 return drv_data->rx == drv_data->rx_end; 255 } 256 257 static int u8_writer(struct driver_data *drv_data) 258 { 259 void __iomem *reg = drv_data->ioaddr; 260 261 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 262 || (drv_data->tx == drv_data->tx_end)) 263 return 0; 264 265 write_SSDR(*(u8 *)(drv_data->tx), reg); 266 ++drv_data->tx; 267 268 return 1; 269 } 270 271 static int u8_reader(struct driver_data *drv_data) 272 { 273 void __iomem *reg = drv_data->ioaddr; 274 275 while ((read_SSSR(reg) & SSSR_RNE) 276 && (drv_data->rx < drv_data->rx_end)) { 277 *(u8 *)(drv_data->rx) = read_SSDR(reg); 278 ++drv_data->rx; 279 } 280 281 return drv_data->rx == drv_data->rx_end; 282 } 283 284 static int u16_writer(struct driver_data *drv_data) 285 { 286 void __iomem *reg = drv_data->ioaddr; 287 288 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 289 || (drv_data->tx == drv_data->tx_end)) 290 return 0; 291 292 write_SSDR(*(u16 *)(drv_data->tx), reg); 293 drv_data->tx += 2; 294 295 return 1; 296 } 297 298 static int u16_reader(struct driver_data *drv_data) 299 { 300 void __iomem *reg = drv_data->ioaddr; 301 302 while ((read_SSSR(reg) & SSSR_RNE) 303 && (drv_data->rx < drv_data->rx_end)) { 304 *(u16 *)(drv_data->rx) = read_SSDR(reg); 305 drv_data->rx += 2; 306 } 307 308 return drv_data->rx == drv_data->rx_end; 309 } 310 311 static int u32_writer(struct driver_data *drv_data) 312 { 313 void __iomem *reg = drv_data->ioaddr; 314 315 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) 316 || (drv_data->tx == drv_data->tx_end)) 317 return 0; 318 319 write_SSDR(*(u32 *)(drv_data->tx), reg); 320 drv_data->tx += 4; 321 322 return 1; 323 } 324 325 static int u32_reader(struct driver_data *drv_data) 326 { 327 void __iomem *reg = drv_data->ioaddr; 328 329 while ((read_SSSR(reg) & SSSR_RNE) 330 && (drv_data->rx < drv_data->rx_end)) { 331 *(u32 *)(drv_data->rx) = read_SSDR(reg); 332 drv_data->rx += 4; 333 } 334 335 return drv_data->rx == drv_data->rx_end; 336 } 337 338 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) 339 { 340 struct spi_message *msg = drv_data->cur_msg; 341 struct spi_transfer *trans = drv_data->cur_transfer; 342 343 /* Move to next transfer */ 344 if (trans->transfer_list.next != &msg->transfers) { 345 drv_data->cur_transfer = 346 list_entry(trans->transfer_list.next, 347 struct spi_transfer, 348 transfer_list); 349 return RUNNING_STATE; 350 } else 351 return DONE_STATE; 352 } 353 354 /* caller already set message->status; dma and pio irqs are blocked */ 355 static void giveback(struct driver_data *drv_data) 356 { 357 struct spi_transfer* last_transfer; 358 struct spi_message *msg; 359 360 msg = drv_data->cur_msg; 361 drv_data->cur_msg = NULL; 362 drv_data->cur_transfer = NULL; 363 364 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, 365 transfer_list); 366 367 /* Delay if requested before any change in chip select */ 368 if (last_transfer->delay_usecs) 369 udelay(last_transfer->delay_usecs); 370 371 /* Drop chip select UNLESS cs_change is true or we are returning 372 * a message with an error, or next message is for another chip 373 */ 374 if (!last_transfer->cs_change) 375 cs_deassert(drv_data); 376 else { 377 struct spi_message *next_msg; 378 379 /* Holding of cs was hinted, but we need to make sure 380 * the next message is for the same chip. Don't waste 381 * time with the following tests unless this was hinted. 382 * 383 * We cannot postpone this until pump_messages, because 384 * after calling msg->complete (below) the driver that 385 * sent the current message could be unloaded, which 386 * could invalidate the cs_control() callback... 387 */ 388 389 /* get a pointer to the next message, if any */ 390 next_msg = spi_get_next_queued_message(drv_data->master); 391 392 /* see if the next and current messages point 393 * to the same chip 394 */ 395 if (next_msg && next_msg->spi != msg->spi) 396 next_msg = NULL; 397 if (!next_msg || msg->state == ERROR_STATE) 398 cs_deassert(drv_data); 399 } 400 401 spi_finalize_current_message(drv_data->master); 402 drv_data->cur_chip = NULL; 403 } 404 405 static void reset_sccr1(struct driver_data *drv_data) 406 { 407 void __iomem *reg = drv_data->ioaddr; 408 struct chip_data *chip = drv_data->cur_chip; 409 u32 sccr1_reg; 410 411 sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; 412 sccr1_reg &= ~SSCR1_RFT; 413 sccr1_reg |= chip->threshold; 414 write_SSCR1(sccr1_reg, reg); 415 } 416 417 static void int_error_stop(struct driver_data *drv_data, const char* msg) 418 { 419 void __iomem *reg = drv_data->ioaddr; 420 421 /* Stop and reset SSP */ 422 write_SSSR_CS(drv_data, drv_data->clear_sr); 423 reset_sccr1(drv_data); 424 if (!pxa25x_ssp_comp(drv_data)) 425 write_SSTO(0, reg); 426 pxa2xx_spi_flush(drv_data); 427 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 428 429 dev_err(&drv_data->pdev->dev, "%s\n", msg); 430 431 drv_data->cur_msg->state = ERROR_STATE; 432 tasklet_schedule(&drv_data->pump_transfers); 433 } 434 435 static void int_transfer_complete(struct driver_data *drv_data) 436 { 437 void __iomem *reg = drv_data->ioaddr; 438 439 /* Stop SSP */ 440 write_SSSR_CS(drv_data, drv_data->clear_sr); 441 reset_sccr1(drv_data); 442 if (!pxa25x_ssp_comp(drv_data)) 443 write_SSTO(0, reg); 444 445 /* Update total byte transferred return count actual bytes read */ 446 drv_data->cur_msg->actual_length += drv_data->len - 447 (drv_data->rx_end - drv_data->rx); 448 449 /* Transfer delays and chip select release are 450 * handled in pump_transfers or giveback 451 */ 452 453 /* Move to next transfer */ 454 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); 455 456 /* Schedule transfer tasklet */ 457 tasklet_schedule(&drv_data->pump_transfers); 458 } 459 460 static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 461 { 462 void __iomem *reg = drv_data->ioaddr; 463 464 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? 465 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 466 467 u32 irq_status = read_SSSR(reg) & irq_mask; 468 469 if (irq_status & SSSR_ROR) { 470 int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 471 return IRQ_HANDLED; 472 } 473 474 if (irq_status & SSSR_TINT) { 475 write_SSSR(SSSR_TINT, reg); 476 if (drv_data->read(drv_data)) { 477 int_transfer_complete(drv_data); 478 return IRQ_HANDLED; 479 } 480 } 481 482 /* Drain rx fifo, Fill tx fifo and prevent overruns */ 483 do { 484 if (drv_data->read(drv_data)) { 485 int_transfer_complete(drv_data); 486 return IRQ_HANDLED; 487 } 488 } while (drv_data->write(drv_data)); 489 490 if (drv_data->read(drv_data)) { 491 int_transfer_complete(drv_data); 492 return IRQ_HANDLED; 493 } 494 495 if (drv_data->tx == drv_data->tx_end) { 496 u32 bytes_left; 497 u32 sccr1_reg; 498 499 sccr1_reg = read_SSCR1(reg); 500 sccr1_reg &= ~SSCR1_TIE; 501 502 /* 503 * PXA25x_SSP has no timeout, set up rx threshould for the 504 * remaining RX bytes. 505 */ 506 if (pxa25x_ssp_comp(drv_data)) { 507 508 sccr1_reg &= ~SSCR1_RFT; 509 510 bytes_left = drv_data->rx_end - drv_data->rx; 511 switch (drv_data->n_bytes) { 512 case 4: 513 bytes_left >>= 1; 514 case 2: 515 bytes_left >>= 1; 516 } 517 518 if (bytes_left > RX_THRESH_DFLT) 519 bytes_left = RX_THRESH_DFLT; 520 521 sccr1_reg |= SSCR1_RxTresh(bytes_left); 522 } 523 write_SSCR1(sccr1_reg, reg); 524 } 525 526 /* We did something */ 527 return IRQ_HANDLED; 528 } 529 530 static irqreturn_t ssp_int(int irq, void *dev_id) 531 { 532 struct driver_data *drv_data = dev_id; 533 void __iomem *reg = drv_data->ioaddr; 534 u32 sccr1_reg; 535 u32 mask = drv_data->mask_sr; 536 u32 status; 537 538 /* 539 * The IRQ might be shared with other peripherals so we must first 540 * check that are we RPM suspended or not. If we are we assume that 541 * the IRQ was not for us (we shouldn't be RPM suspended when the 542 * interrupt is enabled). 543 */ 544 if (pm_runtime_suspended(&drv_data->pdev->dev)) 545 return IRQ_NONE; 546 547 /* 548 * If the device is not yet in RPM suspended state and we get an 549 * interrupt that is meant for another device, check if status bits 550 * are all set to one. That means that the device is already 551 * powered off. 552 */ 553 status = read_SSSR(reg); 554 if (status == ~0) 555 return IRQ_NONE; 556 557 sccr1_reg = read_SSCR1(reg); 558 559 /* Ignore possible writes if we don't need to write */ 560 if (!(sccr1_reg & SSCR1_TIE)) 561 mask &= ~SSSR_TFS; 562 563 if (!(status & mask)) 564 return IRQ_NONE; 565 566 if (!drv_data->cur_msg) { 567 568 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 569 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); 570 if (!pxa25x_ssp_comp(drv_data)) 571 write_SSTO(0, reg); 572 write_SSSR_CS(drv_data, drv_data->clear_sr); 573 574 dev_err(&drv_data->pdev->dev, 575 "bad message state in interrupt handler\n"); 576 577 /* Never fail */ 578 return IRQ_HANDLED; 579 } 580 581 return drv_data->transfer_handler(drv_data); 582 } 583 584 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 585 { 586 unsigned long ssp_clk = drv_data->max_clk_rate; 587 const struct ssp_device *ssp = drv_data->ssp; 588 589 rate = min_t(int, ssp_clk, rate); 590 591 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 592 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; 593 else 594 return ((ssp_clk / rate - 1) & 0xfff) << 8; 595 } 596 597 static void pump_transfers(unsigned long data) 598 { 599 struct driver_data *drv_data = (struct driver_data *)data; 600 struct spi_message *message = NULL; 601 struct spi_transfer *transfer = NULL; 602 struct spi_transfer *previous = NULL; 603 struct chip_data *chip = NULL; 604 void __iomem *reg = drv_data->ioaddr; 605 u32 clk_div = 0; 606 u8 bits = 0; 607 u32 speed = 0; 608 u32 cr0; 609 u32 cr1; 610 u32 dma_thresh = drv_data->cur_chip->dma_threshold; 611 u32 dma_burst = drv_data->cur_chip->dma_burst_size; 612 613 /* Get current state information */ 614 message = drv_data->cur_msg; 615 transfer = drv_data->cur_transfer; 616 chip = drv_data->cur_chip; 617 618 /* Handle for abort */ 619 if (message->state == ERROR_STATE) { 620 message->status = -EIO; 621 giveback(drv_data); 622 return; 623 } 624 625 /* Handle end of message */ 626 if (message->state == DONE_STATE) { 627 message->status = 0; 628 giveback(drv_data); 629 return; 630 } 631 632 /* Delay if requested at end of transfer before CS change */ 633 if (message->state == RUNNING_STATE) { 634 previous = list_entry(transfer->transfer_list.prev, 635 struct spi_transfer, 636 transfer_list); 637 if (previous->delay_usecs) 638 udelay(previous->delay_usecs); 639 640 /* Drop chip select only if cs_change is requested */ 641 if (previous->cs_change) 642 cs_deassert(drv_data); 643 } 644 645 /* Check if we can DMA this transfer */ 646 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { 647 648 /* reject already-mapped transfers; PIO won't always work */ 649 if (message->is_dma_mapped 650 || transfer->rx_dma || transfer->tx_dma) { 651 dev_err(&drv_data->pdev->dev, 652 "pump_transfers: mapped transfer length of " 653 "%u is greater than %d\n", 654 transfer->len, MAX_DMA_LEN); 655 message->status = -EINVAL; 656 giveback(drv_data); 657 return; 658 } 659 660 /* warn ... we force this to PIO mode */ 661 dev_warn_ratelimited(&message->spi->dev, 662 "pump_transfers: DMA disabled for transfer length %ld " 663 "greater than %d\n", 664 (long)drv_data->len, MAX_DMA_LEN); 665 } 666 667 /* Setup the transfer state based on the type of transfer */ 668 if (pxa2xx_spi_flush(drv_data) == 0) { 669 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); 670 message->status = -EIO; 671 giveback(drv_data); 672 return; 673 } 674 drv_data->n_bytes = chip->n_bytes; 675 drv_data->tx = (void *)transfer->tx_buf; 676 drv_data->tx_end = drv_data->tx + transfer->len; 677 drv_data->rx = transfer->rx_buf; 678 drv_data->rx_end = drv_data->rx + transfer->len; 679 drv_data->rx_dma = transfer->rx_dma; 680 drv_data->tx_dma = transfer->tx_dma; 681 drv_data->len = transfer->len; 682 drv_data->write = drv_data->tx ? chip->write : null_writer; 683 drv_data->read = drv_data->rx ? chip->read : null_reader; 684 685 /* Change speed and bit per word on a per transfer */ 686 cr0 = chip->cr0; 687 if (transfer->speed_hz || transfer->bits_per_word) { 688 689 bits = chip->bits_per_word; 690 speed = chip->speed_hz; 691 692 if (transfer->speed_hz) 693 speed = transfer->speed_hz; 694 695 if (transfer->bits_per_word) 696 bits = transfer->bits_per_word; 697 698 clk_div = ssp_get_clk_div(drv_data, speed); 699 700 if (bits <= 8) { 701 drv_data->n_bytes = 1; 702 drv_data->read = drv_data->read != null_reader ? 703 u8_reader : null_reader; 704 drv_data->write = drv_data->write != null_writer ? 705 u8_writer : null_writer; 706 } else if (bits <= 16) { 707 drv_data->n_bytes = 2; 708 drv_data->read = drv_data->read != null_reader ? 709 u16_reader : null_reader; 710 drv_data->write = drv_data->write != null_writer ? 711 u16_writer : null_writer; 712 } else if (bits <= 32) { 713 drv_data->n_bytes = 4; 714 drv_data->read = drv_data->read != null_reader ? 715 u32_reader : null_reader; 716 drv_data->write = drv_data->write != null_writer ? 717 u32_writer : null_writer; 718 } 719 /* if bits/word is changed in dma mode, then must check the 720 * thresholds and burst also */ 721 if (chip->enable_dma) { 722 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 723 message->spi, 724 bits, &dma_burst, 725 &dma_thresh)) 726 dev_warn_ratelimited(&message->spi->dev, 727 "pump_transfers: DMA burst size reduced to match bits_per_word\n"); 728 } 729 730 cr0 = clk_div 731 | SSCR0_Motorola 732 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 733 | SSCR0_SSE 734 | (bits > 16 ? SSCR0_EDSS : 0); 735 } 736 737 message->state = RUNNING_STATE; 738 739 drv_data->dma_mapped = 0; 740 if (pxa2xx_spi_dma_is_possible(drv_data->len)) 741 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); 742 if (drv_data->dma_mapped) { 743 744 /* Ensure we have the correct interrupt handler */ 745 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 746 747 pxa2xx_spi_dma_prepare(drv_data, dma_burst); 748 749 /* Clear status and start DMA engine */ 750 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 751 write_SSSR(drv_data->clear_sr, reg); 752 753 pxa2xx_spi_dma_start(drv_data); 754 } else { 755 /* Ensure we have the correct interrupt handler */ 756 drv_data->transfer_handler = interrupt_transfer; 757 758 /* Clear status */ 759 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 760 write_SSSR_CS(drv_data, drv_data->clear_sr); 761 } 762 763 if (is_lpss_ssp(drv_data)) { 764 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) 765 write_SSIRF(chip->lpss_rx_threshold, reg); 766 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) 767 write_SSITF(chip->lpss_tx_threshold, reg); 768 } 769 770 /* see if we need to reload the config registers */ 771 if ((read_SSCR0(reg) != cr0) 772 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != 773 (cr1 & SSCR1_CHANGE_MASK)) { 774 775 /* stop the SSP, and update the other bits */ 776 write_SSCR0(cr0 & ~SSCR0_SSE, reg); 777 if (!pxa25x_ssp_comp(drv_data)) 778 write_SSTO(chip->timeout, reg); 779 /* first set CR1 without interrupt and service enables */ 780 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); 781 /* restart the SSP */ 782 write_SSCR0(cr0, reg); 783 784 } else { 785 if (!pxa25x_ssp_comp(drv_data)) 786 write_SSTO(chip->timeout, reg); 787 } 788 789 cs_assert(drv_data); 790 791 /* after chip select, release the data by enabling service 792 * requests and interrupts, without changing any mode bits */ 793 write_SSCR1(cr1, reg); 794 } 795 796 static int pxa2xx_spi_transfer_one_message(struct spi_master *master, 797 struct spi_message *msg) 798 { 799 struct driver_data *drv_data = spi_master_get_devdata(master); 800 801 drv_data->cur_msg = msg; 802 /* Initial message state*/ 803 drv_data->cur_msg->state = START_STATE; 804 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 805 struct spi_transfer, 806 transfer_list); 807 808 /* prepare to setup the SSP, in pump_transfers, using the per 809 * chip configuration */ 810 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 811 812 /* Mark as busy and launch transfers */ 813 tasklet_schedule(&drv_data->pump_transfers); 814 return 0; 815 } 816 817 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) 818 { 819 struct driver_data *drv_data = spi_master_get_devdata(master); 820 821 /* Disable the SSP now */ 822 write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, 823 drv_data->ioaddr); 824 825 return 0; 826 } 827 828 static int setup_cs(struct spi_device *spi, struct chip_data *chip, 829 struct pxa2xx_spi_chip *chip_info) 830 { 831 int err = 0; 832 833 if (chip == NULL || chip_info == NULL) 834 return 0; 835 836 /* NOTE: setup() can be called multiple times, possibly with 837 * different chip_info, release previously requested GPIO 838 */ 839 if (gpio_is_valid(chip->gpio_cs)) 840 gpio_free(chip->gpio_cs); 841 842 /* If (*cs_control) is provided, ignore GPIO chip select */ 843 if (chip_info->cs_control) { 844 chip->cs_control = chip_info->cs_control; 845 return 0; 846 } 847 848 if (gpio_is_valid(chip_info->gpio_cs)) { 849 err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 850 if (err) { 851 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 852 chip_info->gpio_cs); 853 return err; 854 } 855 856 chip->gpio_cs = chip_info->gpio_cs; 857 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 858 859 err = gpio_direction_output(chip->gpio_cs, 860 !chip->gpio_cs_inverted); 861 } 862 863 return err; 864 } 865 866 static int setup(struct spi_device *spi) 867 { 868 struct pxa2xx_spi_chip *chip_info = NULL; 869 struct chip_data *chip; 870 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 871 unsigned int clk_div; 872 uint tx_thres, tx_hi_thres, rx_thres; 873 874 if (is_lpss_ssp(drv_data)) { 875 tx_thres = LPSS_TX_LOTHRESH_DFLT; 876 tx_hi_thres = LPSS_TX_HITHRESH_DFLT; 877 rx_thres = LPSS_RX_THRESH_DFLT; 878 } else { 879 tx_thres = TX_THRESH_DFLT; 880 tx_hi_thres = 0; 881 rx_thres = RX_THRESH_DFLT; 882 } 883 884 /* Only alloc on first setup */ 885 chip = spi_get_ctldata(spi); 886 if (!chip) { 887 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 888 if (!chip) 889 return -ENOMEM; 890 891 if (drv_data->ssp_type == CE4100_SSP) { 892 if (spi->chip_select > 4) { 893 dev_err(&spi->dev, 894 "failed setup: cs number must not be > 4.\n"); 895 kfree(chip); 896 return -EINVAL; 897 } 898 899 chip->frm = spi->chip_select; 900 } else 901 chip->gpio_cs = -1; 902 chip->enable_dma = 0; 903 chip->timeout = TIMOUT_DFLT; 904 } 905 906 /* protocol drivers may change the chip settings, so... 907 * if chip_info exists, use it */ 908 chip_info = spi->controller_data; 909 910 /* chip_info isn't always needed */ 911 chip->cr1 = 0; 912 if (chip_info) { 913 if (chip_info->timeout) 914 chip->timeout = chip_info->timeout; 915 if (chip_info->tx_threshold) 916 tx_thres = chip_info->tx_threshold; 917 if (chip_info->tx_hi_threshold) 918 tx_hi_thres = chip_info->tx_hi_threshold; 919 if (chip_info->rx_threshold) 920 rx_thres = chip_info->rx_threshold; 921 chip->enable_dma = drv_data->master_info->enable_dma; 922 chip->dma_threshold = 0; 923 if (chip_info->enable_loopback) 924 chip->cr1 = SSCR1_LBM; 925 } else if (ACPI_HANDLE(&spi->dev)) { 926 /* 927 * Slave devices enumerated from ACPI namespace don't 928 * usually have chip_info but we still might want to use 929 * DMA with them. 930 */ 931 chip->enable_dma = drv_data->master_info->enable_dma; 932 } 933 934 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 935 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 936 937 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 938 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 939 | SSITF_TxHiThresh(tx_hi_thres); 940 941 /* set dma burst and threshold outside of chip_info path so that if 942 * chip_info goes away after setting chip->enable_dma, the 943 * burst and threshold can still respond to changes in bits_per_word */ 944 if (chip->enable_dma) { 945 /* set up legal burst and threshold for dma */ 946 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 947 spi->bits_per_word, 948 &chip->dma_burst_size, 949 &chip->dma_threshold)) { 950 dev_warn(&spi->dev, 951 "in setup: DMA burst size reduced to match bits_per_word\n"); 952 } 953 } 954 955 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); 956 chip->speed_hz = spi->max_speed_hz; 957 958 chip->cr0 = clk_div 959 | SSCR0_Motorola 960 | SSCR0_DataSize(spi->bits_per_word > 16 ? 961 spi->bits_per_word - 16 : spi->bits_per_word) 962 | SSCR0_SSE 963 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); 964 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 965 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 966 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 967 968 if (spi->mode & SPI_LOOP) 969 chip->cr1 |= SSCR1_LBM; 970 971 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 972 if (!pxa25x_ssp_comp(drv_data)) 973 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 974 drv_data->max_clk_rate 975 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), 976 chip->enable_dma ? "DMA" : "PIO"); 977 else 978 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 979 drv_data->max_clk_rate / 2 980 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), 981 chip->enable_dma ? "DMA" : "PIO"); 982 983 if (spi->bits_per_word <= 8) { 984 chip->n_bytes = 1; 985 chip->read = u8_reader; 986 chip->write = u8_writer; 987 } else if (spi->bits_per_word <= 16) { 988 chip->n_bytes = 2; 989 chip->read = u16_reader; 990 chip->write = u16_writer; 991 } else if (spi->bits_per_word <= 32) { 992 chip->cr0 |= SSCR0_EDSS; 993 chip->n_bytes = 4; 994 chip->read = u32_reader; 995 chip->write = u32_writer; 996 } 997 chip->bits_per_word = spi->bits_per_word; 998 999 spi_set_ctldata(spi, chip); 1000 1001 if (drv_data->ssp_type == CE4100_SSP) 1002 return 0; 1003 1004 return setup_cs(spi, chip, chip_info); 1005 } 1006 1007 static void cleanup(struct spi_device *spi) 1008 { 1009 struct chip_data *chip = spi_get_ctldata(spi); 1010 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1011 1012 if (!chip) 1013 return; 1014 1015 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) 1016 gpio_free(chip->gpio_cs); 1017 1018 kfree(chip); 1019 } 1020 1021 #ifdef CONFIG_ACPI 1022 static struct pxa2xx_spi_master * 1023 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1024 { 1025 struct pxa2xx_spi_master *pdata; 1026 struct acpi_device *adev; 1027 struct ssp_device *ssp; 1028 struct resource *res; 1029 int devid; 1030 1031 if (!ACPI_HANDLE(&pdev->dev) || 1032 acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1033 return NULL; 1034 1035 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1036 if (!pdata) 1037 return NULL; 1038 1039 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1040 if (!res) 1041 return NULL; 1042 1043 ssp = &pdata->ssp; 1044 1045 ssp->phys_base = res->start; 1046 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1047 if (IS_ERR(ssp->mmio_base)) 1048 return NULL; 1049 1050 ssp->clk = devm_clk_get(&pdev->dev, NULL); 1051 ssp->irq = platform_get_irq(pdev, 0); 1052 ssp->type = LPSS_SSP; 1053 ssp->pdev = pdev; 1054 1055 ssp->port_id = -1; 1056 if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) 1057 ssp->port_id = devid; 1058 1059 pdata->num_chipselect = 1; 1060 pdata->enable_dma = true; 1061 pdata->tx_chan_id = -1; 1062 pdata->rx_chan_id = -1; 1063 1064 return pdata; 1065 } 1066 1067 static struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1068 { "INT33C0", 0 }, 1069 { "INT33C1", 0 }, 1070 { "INT3430", 0 }, 1071 { "INT3431", 0 }, 1072 { "80860F0E", 0 }, 1073 { }, 1074 }; 1075 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1076 #else 1077 static inline struct pxa2xx_spi_master * 1078 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) 1079 { 1080 return NULL; 1081 } 1082 #endif 1083 1084 static int pxa2xx_spi_probe(struct platform_device *pdev) 1085 { 1086 struct device *dev = &pdev->dev; 1087 struct pxa2xx_spi_master *platform_info; 1088 struct spi_master *master; 1089 struct driver_data *drv_data; 1090 struct ssp_device *ssp; 1091 int status; 1092 1093 platform_info = dev_get_platdata(dev); 1094 if (!platform_info) { 1095 platform_info = pxa2xx_spi_acpi_get_pdata(pdev); 1096 if (!platform_info) { 1097 dev_err(&pdev->dev, "missing platform data\n"); 1098 return -ENODEV; 1099 } 1100 } 1101 1102 ssp = pxa_ssp_request(pdev->id, pdev->name); 1103 if (!ssp) 1104 ssp = &platform_info->ssp; 1105 1106 if (!ssp->mmio_base) { 1107 dev_err(&pdev->dev, "failed to get ssp\n"); 1108 return -ENODEV; 1109 } 1110 1111 /* Allocate master with space for drv_data and null dma buffer */ 1112 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); 1113 if (!master) { 1114 dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1115 pxa_ssp_free(ssp); 1116 return -ENOMEM; 1117 } 1118 drv_data = spi_master_get_devdata(master); 1119 drv_data->master = master; 1120 drv_data->master_info = platform_info; 1121 drv_data->pdev = pdev; 1122 drv_data->ssp = ssp; 1123 1124 master->dev.parent = &pdev->dev; 1125 master->dev.of_node = pdev->dev.of_node; 1126 /* the spi->mode bits understood by this driver: */ 1127 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1128 1129 master->bus_num = ssp->port_id; 1130 master->num_chipselect = platform_info->num_chipselect; 1131 master->dma_alignment = DMA_ALIGNMENT; 1132 master->cleanup = cleanup; 1133 master->setup = setup; 1134 master->transfer_one_message = pxa2xx_spi_transfer_one_message; 1135 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1136 master->auto_runtime_pm = true; 1137 1138 drv_data->ssp_type = ssp->type; 1139 drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); 1140 1141 drv_data->ioaddr = ssp->mmio_base; 1142 drv_data->ssdr_physical = ssp->phys_base + SSDR; 1143 if (pxa25x_ssp_comp(drv_data)) { 1144 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1145 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1146 drv_data->dma_cr1 = 0; 1147 drv_data->clear_sr = SSSR_ROR; 1148 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1149 } else { 1150 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1151 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1152 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1153 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1154 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1155 } 1156 1157 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1158 drv_data); 1159 if (status < 0) { 1160 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1161 goto out_error_master_alloc; 1162 } 1163 1164 /* Setup DMA if requested */ 1165 drv_data->tx_channel = -1; 1166 drv_data->rx_channel = -1; 1167 if (platform_info->enable_dma) { 1168 status = pxa2xx_spi_dma_setup(drv_data); 1169 if (status) { 1170 dev_dbg(dev, "no DMA channels available, using PIO\n"); 1171 platform_info->enable_dma = false; 1172 } 1173 } 1174 1175 /* Enable SOC clock */ 1176 clk_prepare_enable(ssp->clk); 1177 1178 drv_data->max_clk_rate = clk_get_rate(ssp->clk); 1179 1180 /* Load default SSP configuration */ 1181 write_SSCR0(0, drv_data->ioaddr); 1182 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 1183 SSCR1_TxTresh(TX_THRESH_DFLT), 1184 drv_data->ioaddr); 1185 write_SSCR0(SSCR0_SCR(2) 1186 | SSCR0_Motorola 1187 | SSCR0_DataSize(8), 1188 drv_data->ioaddr); 1189 if (!pxa25x_ssp_comp(drv_data)) 1190 write_SSTO(0, drv_data->ioaddr); 1191 write_SSPSP(0, drv_data->ioaddr); 1192 1193 lpss_ssp_setup(drv_data); 1194 1195 tasklet_init(&drv_data->pump_transfers, pump_transfers, 1196 (unsigned long)drv_data); 1197 1198 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1199 pm_runtime_use_autosuspend(&pdev->dev); 1200 pm_runtime_set_active(&pdev->dev); 1201 pm_runtime_enable(&pdev->dev); 1202 1203 /* Register with the SPI framework */ 1204 platform_set_drvdata(pdev, drv_data); 1205 status = devm_spi_register_master(&pdev->dev, master); 1206 if (status != 0) { 1207 dev_err(&pdev->dev, "problem registering spi master\n"); 1208 goto out_error_clock_enabled; 1209 } 1210 1211 return status; 1212 1213 out_error_clock_enabled: 1214 clk_disable_unprepare(ssp->clk); 1215 pxa2xx_spi_dma_release(drv_data); 1216 free_irq(ssp->irq, drv_data); 1217 1218 out_error_master_alloc: 1219 spi_master_put(master); 1220 pxa_ssp_free(ssp); 1221 return status; 1222 } 1223 1224 static int pxa2xx_spi_remove(struct platform_device *pdev) 1225 { 1226 struct driver_data *drv_data = platform_get_drvdata(pdev); 1227 struct ssp_device *ssp; 1228 1229 if (!drv_data) 1230 return 0; 1231 ssp = drv_data->ssp; 1232 1233 pm_runtime_get_sync(&pdev->dev); 1234 1235 /* Disable the SSP at the peripheral and SOC level */ 1236 write_SSCR0(0, drv_data->ioaddr); 1237 clk_disable_unprepare(ssp->clk); 1238 1239 /* Release DMA */ 1240 if (drv_data->master_info->enable_dma) 1241 pxa2xx_spi_dma_release(drv_data); 1242 1243 pm_runtime_put_noidle(&pdev->dev); 1244 pm_runtime_disable(&pdev->dev); 1245 1246 /* Release IRQ */ 1247 free_irq(ssp->irq, drv_data); 1248 1249 /* Release SSP */ 1250 pxa_ssp_free(ssp); 1251 1252 return 0; 1253 } 1254 1255 static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1256 { 1257 int status = 0; 1258 1259 if ((status = pxa2xx_spi_remove(pdev)) != 0) 1260 dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1261 } 1262 1263 #ifdef CONFIG_PM_SLEEP 1264 static int pxa2xx_spi_suspend(struct device *dev) 1265 { 1266 struct driver_data *drv_data = dev_get_drvdata(dev); 1267 struct ssp_device *ssp = drv_data->ssp; 1268 int status = 0; 1269 1270 status = spi_master_suspend(drv_data->master); 1271 if (status != 0) 1272 return status; 1273 write_SSCR0(0, drv_data->ioaddr); 1274 clk_disable_unprepare(ssp->clk); 1275 1276 return 0; 1277 } 1278 1279 static int pxa2xx_spi_resume(struct device *dev) 1280 { 1281 struct driver_data *drv_data = dev_get_drvdata(dev); 1282 struct ssp_device *ssp = drv_data->ssp; 1283 int status = 0; 1284 1285 pxa2xx_spi_dma_resume(drv_data); 1286 1287 /* Enable the SSP clock */ 1288 clk_prepare_enable(ssp->clk); 1289 1290 /* Restore LPSS private register bits */ 1291 lpss_ssp_setup(drv_data); 1292 1293 /* Start the queue running */ 1294 status = spi_master_resume(drv_data->master); 1295 if (status != 0) { 1296 dev_err(dev, "problem starting queue (%d)\n", status); 1297 return status; 1298 } 1299 1300 return 0; 1301 } 1302 #endif 1303 1304 #ifdef CONFIG_PM_RUNTIME 1305 static int pxa2xx_spi_runtime_suspend(struct device *dev) 1306 { 1307 struct driver_data *drv_data = dev_get_drvdata(dev); 1308 1309 clk_disable_unprepare(drv_data->ssp->clk); 1310 return 0; 1311 } 1312 1313 static int pxa2xx_spi_runtime_resume(struct device *dev) 1314 { 1315 struct driver_data *drv_data = dev_get_drvdata(dev); 1316 1317 clk_prepare_enable(drv_data->ssp->clk); 1318 return 0; 1319 } 1320 #endif 1321 1322 static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1323 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1324 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 1325 pxa2xx_spi_runtime_resume, NULL) 1326 }; 1327 1328 static struct platform_driver driver = { 1329 .driver = { 1330 .name = "pxa2xx-spi", 1331 .owner = THIS_MODULE, 1332 .pm = &pxa2xx_spi_pm_ops, 1333 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1334 }, 1335 .probe = pxa2xx_spi_probe, 1336 .remove = pxa2xx_spi_remove, 1337 .shutdown = pxa2xx_spi_shutdown, 1338 }; 1339 1340 static int __init pxa2xx_spi_init(void) 1341 { 1342 return platform_driver_register(&driver); 1343 } 1344 subsys_initcall(pxa2xx_spi_init); 1345 1346 static void __exit pxa2xx_spi_exit(void) 1347 { 1348 platform_driver_unregister(&driver); 1349 } 1350 module_exit(pxa2xx_spi_exit); 1351