1 /* 2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3 * Copyright (C) 2013, Intel Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/ioport.h> 21 #include <linux/errno.h> 22 #include <linux/err.h> 23 #include <linux/interrupt.h> 24 #include <linux/kernel.h> 25 #include <linux/pci.h> 26 #include <linux/platform_device.h> 27 #include <linux/spi/pxa2xx_spi.h> 28 #include <linux/spi/spi.h> 29 #include <linux/delay.h> 30 #include <linux/gpio.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/clk.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/acpi.h> 36 #include <linux/of_device.h> 37 38 #include "spi-pxa2xx.h" 39 40 MODULE_AUTHOR("Stephen Street"); 41 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 42 MODULE_LICENSE("GPL"); 43 MODULE_ALIAS("platform:pxa2xx-spi"); 44 45 #define TIMOUT_DFLT 1000 46 47 /* 48 * for testing SSCR1 changes that require SSP restart, basically 49 * everything except the service and interrupt enables, the pxa270 developer 50 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 51 * list, but the PXA255 dev man says all bits without really meaning the 52 * service and interrupt enables 53 */ 54 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 55 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 56 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 57 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 58 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 59 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 60 61 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 62 | QUARK_X1000_SSCR1_EFWR \ 63 | QUARK_X1000_SSCR1_RFT \ 64 | QUARK_X1000_SSCR1_TFT \ 65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 66 67 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 68 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 69 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 70 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 71 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ 72 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 73 74 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 75 #define LPSS_CS_CONTROL_SW_MODE BIT(0) 76 #define LPSS_CS_CONTROL_CS_HIGH BIT(1) 77 #define LPSS_CAPS_CS_EN_SHIFT 9 78 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) 79 80 struct lpss_config { 81 /* LPSS offset from drv_data->ioaddr */ 82 unsigned offset; 83 /* Register offsets from drv_data->lpss_base or -1 */ 84 int reg_general; 85 int reg_ssp; 86 int reg_cs_ctrl; 87 int reg_capabilities; 88 /* FIFO thresholds */ 89 u32 rx_threshold; 90 u32 tx_threshold_lo; 91 u32 tx_threshold_hi; 92 /* Chip select control */ 93 unsigned cs_sel_shift; 94 unsigned cs_sel_mask; 95 unsigned cs_num; 96 }; 97 98 /* Keep these sorted with enum pxa_ssp_type */ 99 static const struct lpss_config lpss_platforms[] = { 100 { /* LPSS_LPT_SSP */ 101 .offset = 0x800, 102 .reg_general = 0x08, 103 .reg_ssp = 0x0c, 104 .reg_cs_ctrl = 0x18, 105 .reg_capabilities = -1, 106 .rx_threshold = 64, 107 .tx_threshold_lo = 160, 108 .tx_threshold_hi = 224, 109 }, 110 { /* LPSS_BYT_SSP */ 111 .offset = 0x400, 112 .reg_general = 0x08, 113 .reg_ssp = 0x0c, 114 .reg_cs_ctrl = 0x18, 115 .reg_capabilities = -1, 116 .rx_threshold = 64, 117 .tx_threshold_lo = 160, 118 .tx_threshold_hi = 224, 119 }, 120 { /* LPSS_BSW_SSP */ 121 .offset = 0x400, 122 .reg_general = 0x08, 123 .reg_ssp = 0x0c, 124 .reg_cs_ctrl = 0x18, 125 .reg_capabilities = -1, 126 .rx_threshold = 64, 127 .tx_threshold_lo = 160, 128 .tx_threshold_hi = 224, 129 .cs_sel_shift = 2, 130 .cs_sel_mask = 1 << 2, 131 .cs_num = 2, 132 }, 133 { /* LPSS_SPT_SSP */ 134 .offset = 0x200, 135 .reg_general = -1, 136 .reg_ssp = 0x20, 137 .reg_cs_ctrl = 0x24, 138 .reg_capabilities = -1, 139 .rx_threshold = 1, 140 .tx_threshold_lo = 32, 141 .tx_threshold_hi = 56, 142 }, 143 { /* LPSS_BXT_SSP */ 144 .offset = 0x200, 145 .reg_general = -1, 146 .reg_ssp = 0x20, 147 .reg_cs_ctrl = 0x24, 148 .reg_capabilities = 0xfc, 149 .rx_threshold = 1, 150 .tx_threshold_lo = 16, 151 .tx_threshold_hi = 48, 152 .cs_sel_shift = 8, 153 .cs_sel_mask = 3 << 8, 154 }, 155 { /* LPSS_CNL_SSP */ 156 .offset = 0x200, 157 .reg_general = -1, 158 .reg_ssp = 0x20, 159 .reg_cs_ctrl = 0x24, 160 .reg_capabilities = 0xfc, 161 .rx_threshold = 1, 162 .tx_threshold_lo = 32, 163 .tx_threshold_hi = 56, 164 .cs_sel_shift = 8, 165 .cs_sel_mask = 3 << 8, 166 }, 167 }; 168 169 static inline const struct lpss_config 170 *lpss_get_config(const struct driver_data *drv_data) 171 { 172 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; 173 } 174 175 static bool is_lpss_ssp(const struct driver_data *drv_data) 176 { 177 switch (drv_data->ssp_type) { 178 case LPSS_LPT_SSP: 179 case LPSS_BYT_SSP: 180 case LPSS_BSW_SSP: 181 case LPSS_SPT_SSP: 182 case LPSS_BXT_SSP: 183 case LPSS_CNL_SSP: 184 return true; 185 default: 186 return false; 187 } 188 } 189 190 static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 191 { 192 return drv_data->ssp_type == QUARK_X1000_SSP; 193 } 194 195 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 196 { 197 switch (drv_data->ssp_type) { 198 case QUARK_X1000_SSP: 199 return QUARK_X1000_SSCR1_CHANGE_MASK; 200 case CE4100_SSP: 201 return CE4100_SSCR1_CHANGE_MASK; 202 default: 203 return SSCR1_CHANGE_MASK; 204 } 205 } 206 207 static u32 208 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 209 { 210 switch (drv_data->ssp_type) { 211 case QUARK_X1000_SSP: 212 return RX_THRESH_QUARK_X1000_DFLT; 213 case CE4100_SSP: 214 return RX_THRESH_CE4100_DFLT; 215 default: 216 return RX_THRESH_DFLT; 217 } 218 } 219 220 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 221 { 222 u32 mask; 223 224 switch (drv_data->ssp_type) { 225 case QUARK_X1000_SSP: 226 mask = QUARK_X1000_SSSR_TFL_MASK; 227 break; 228 case CE4100_SSP: 229 mask = CE4100_SSSR_TFL_MASK; 230 break; 231 default: 232 mask = SSSR_TFL_MASK; 233 break; 234 } 235 236 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; 237 } 238 239 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 240 u32 *sccr1_reg) 241 { 242 u32 mask; 243 244 switch (drv_data->ssp_type) { 245 case QUARK_X1000_SSP: 246 mask = QUARK_X1000_SSCR1_RFT; 247 break; 248 case CE4100_SSP: 249 mask = CE4100_SSCR1_RFT; 250 break; 251 default: 252 mask = SSCR1_RFT; 253 break; 254 } 255 *sccr1_reg &= ~mask; 256 } 257 258 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 259 u32 *sccr1_reg, u32 threshold) 260 { 261 switch (drv_data->ssp_type) { 262 case QUARK_X1000_SSP: 263 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 264 break; 265 case CE4100_SSP: 266 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); 267 break; 268 default: 269 *sccr1_reg |= SSCR1_RxTresh(threshold); 270 break; 271 } 272 } 273 274 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 275 u32 clk_div, u8 bits) 276 { 277 switch (drv_data->ssp_type) { 278 case QUARK_X1000_SSP: 279 return clk_div 280 | QUARK_X1000_SSCR0_Motorola 281 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) 282 | SSCR0_SSE; 283 default: 284 return clk_div 285 | SSCR0_Motorola 286 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 287 | SSCR0_SSE 288 | (bits > 16 ? SSCR0_EDSS : 0); 289 } 290 } 291 292 /* 293 * Read and write LPSS SSP private registers. Caller must first check that 294 * is_lpss_ssp() returns true before these can be called. 295 */ 296 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 297 { 298 WARN_ON(!drv_data->lpss_base); 299 return readl(drv_data->lpss_base + offset); 300 } 301 302 static void __lpss_ssp_write_priv(struct driver_data *drv_data, 303 unsigned offset, u32 value) 304 { 305 WARN_ON(!drv_data->lpss_base); 306 writel(value, drv_data->lpss_base + offset); 307 } 308 309 /* 310 * lpss_ssp_setup - perform LPSS SSP specific setup 311 * @drv_data: pointer to the driver private data 312 * 313 * Perform LPSS SSP specific setup. This function must be called first if 314 * one is going to use LPSS SSP private registers. 315 */ 316 static void lpss_ssp_setup(struct driver_data *drv_data) 317 { 318 const struct lpss_config *config; 319 u32 value; 320 321 config = lpss_get_config(drv_data); 322 drv_data->lpss_base = drv_data->ioaddr + config->offset; 323 324 /* Enable software chip select control */ 325 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 326 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); 327 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; 328 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 329 330 /* Enable multiblock DMA transfers */ 331 if (drv_data->controller_info->enable_dma) { 332 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); 333 334 if (config->reg_general >= 0) { 335 value = __lpss_ssp_read_priv(drv_data, 336 config->reg_general); 337 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; 338 __lpss_ssp_write_priv(drv_data, 339 config->reg_general, value); 340 } 341 } 342 } 343 344 static void lpss_ssp_select_cs(struct spi_device *spi, 345 const struct lpss_config *config) 346 { 347 struct driver_data *drv_data = 348 spi_controller_get_devdata(spi->controller); 349 u32 value, cs; 350 351 if (!config->cs_sel_mask) 352 return; 353 354 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 355 356 cs = spi->chip_select; 357 cs <<= config->cs_sel_shift; 358 if (cs != (value & config->cs_sel_mask)) { 359 /* 360 * When switching another chip select output active the 361 * output must be selected first and wait 2 ssp_clk cycles 362 * before changing state to active. Otherwise a short 363 * glitch will occur on the previous chip select since 364 * output select is latched but state control is not. 365 */ 366 value &= ~config->cs_sel_mask; 367 value |= cs; 368 __lpss_ssp_write_priv(drv_data, 369 config->reg_cs_ctrl, value); 370 ndelay(1000000000 / 371 (drv_data->controller->max_speed_hz / 2)); 372 } 373 } 374 375 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) 376 { 377 struct driver_data *drv_data = 378 spi_controller_get_devdata(spi->controller); 379 const struct lpss_config *config; 380 u32 value; 381 382 config = lpss_get_config(drv_data); 383 384 if (enable) 385 lpss_ssp_select_cs(spi, config); 386 387 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 388 if (enable) 389 value &= ~LPSS_CS_CONTROL_CS_HIGH; 390 else 391 value |= LPSS_CS_CONTROL_CS_HIGH; 392 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 393 } 394 395 static void cs_assert(struct spi_device *spi) 396 { 397 struct chip_data *chip = spi_get_ctldata(spi); 398 struct driver_data *drv_data = 399 spi_controller_get_devdata(spi->controller); 400 401 if (drv_data->ssp_type == CE4100_SSP) { 402 pxa2xx_spi_write(drv_data, SSSR, chip->frm); 403 return; 404 } 405 406 if (chip->cs_control) { 407 chip->cs_control(PXA2XX_CS_ASSERT); 408 return; 409 } 410 411 if (chip->gpiod_cs) { 412 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted); 413 return; 414 } 415 416 if (is_lpss_ssp(drv_data)) 417 lpss_ssp_cs_control(spi, true); 418 } 419 420 static void cs_deassert(struct spi_device *spi) 421 { 422 struct chip_data *chip = spi_get_ctldata(spi); 423 struct driver_data *drv_data = 424 spi_controller_get_devdata(spi->controller); 425 unsigned long timeout; 426 427 if (drv_data->ssp_type == CE4100_SSP) 428 return; 429 430 /* Wait until SSP becomes idle before deasserting the CS */ 431 timeout = jiffies + msecs_to_jiffies(10); 432 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && 433 !time_after(jiffies, timeout)) 434 cpu_relax(); 435 436 if (chip->cs_control) { 437 chip->cs_control(PXA2XX_CS_DEASSERT); 438 return; 439 } 440 441 if (chip->gpiod_cs) { 442 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted); 443 return; 444 } 445 446 if (is_lpss_ssp(drv_data)) 447 lpss_ssp_cs_control(spi, false); 448 } 449 450 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) 451 { 452 if (level) 453 cs_deassert(spi); 454 else 455 cs_assert(spi); 456 } 457 458 int pxa2xx_spi_flush(struct driver_data *drv_data) 459 { 460 unsigned long limit = loops_per_jiffy << 1; 461 462 do { 463 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 464 pxa2xx_spi_read(drv_data, SSDR); 465 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 466 write_SSSR_CS(drv_data, SSSR_ROR); 467 468 return limit; 469 } 470 471 static int null_writer(struct driver_data *drv_data) 472 { 473 u8 n_bytes = drv_data->n_bytes; 474 475 if (pxa2xx_spi_txfifo_full(drv_data) 476 || (drv_data->tx == drv_data->tx_end)) 477 return 0; 478 479 pxa2xx_spi_write(drv_data, SSDR, 0); 480 drv_data->tx += n_bytes; 481 482 return 1; 483 } 484 485 static int null_reader(struct driver_data *drv_data) 486 { 487 u8 n_bytes = drv_data->n_bytes; 488 489 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 490 && (drv_data->rx < drv_data->rx_end)) { 491 pxa2xx_spi_read(drv_data, SSDR); 492 drv_data->rx += n_bytes; 493 } 494 495 return drv_data->rx == drv_data->rx_end; 496 } 497 498 static int u8_writer(struct driver_data *drv_data) 499 { 500 if (pxa2xx_spi_txfifo_full(drv_data) 501 || (drv_data->tx == drv_data->tx_end)) 502 return 0; 503 504 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 505 ++drv_data->tx; 506 507 return 1; 508 } 509 510 static int u8_reader(struct driver_data *drv_data) 511 { 512 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 513 && (drv_data->rx < drv_data->rx_end)) { 514 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 515 ++drv_data->rx; 516 } 517 518 return drv_data->rx == drv_data->rx_end; 519 } 520 521 static int u16_writer(struct driver_data *drv_data) 522 { 523 if (pxa2xx_spi_txfifo_full(drv_data) 524 || (drv_data->tx == drv_data->tx_end)) 525 return 0; 526 527 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 528 drv_data->tx += 2; 529 530 return 1; 531 } 532 533 static int u16_reader(struct driver_data *drv_data) 534 { 535 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 536 && (drv_data->rx < drv_data->rx_end)) { 537 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 538 drv_data->rx += 2; 539 } 540 541 return drv_data->rx == drv_data->rx_end; 542 } 543 544 static int u32_writer(struct driver_data *drv_data) 545 { 546 if (pxa2xx_spi_txfifo_full(drv_data) 547 || (drv_data->tx == drv_data->tx_end)) 548 return 0; 549 550 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 551 drv_data->tx += 4; 552 553 return 1; 554 } 555 556 static int u32_reader(struct driver_data *drv_data) 557 { 558 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 559 && (drv_data->rx < drv_data->rx_end)) { 560 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 561 drv_data->rx += 4; 562 } 563 564 return drv_data->rx == drv_data->rx_end; 565 } 566 567 static void reset_sccr1(struct driver_data *drv_data) 568 { 569 struct chip_data *chip = 570 spi_get_ctldata(drv_data->controller->cur_msg->spi); 571 u32 sccr1_reg; 572 573 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; 574 switch (drv_data->ssp_type) { 575 case QUARK_X1000_SSP: 576 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT; 577 break; 578 case CE4100_SSP: 579 sccr1_reg &= ~CE4100_SSCR1_RFT; 580 break; 581 default: 582 sccr1_reg &= ~SSCR1_RFT; 583 break; 584 } 585 sccr1_reg |= chip->threshold; 586 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 587 } 588 589 static void int_error_stop(struct driver_data *drv_data, const char* msg) 590 { 591 /* Stop and reset SSP */ 592 write_SSSR_CS(drv_data, drv_data->clear_sr); 593 reset_sccr1(drv_data); 594 if (!pxa25x_ssp_comp(drv_data)) 595 pxa2xx_spi_write(drv_data, SSTO, 0); 596 pxa2xx_spi_flush(drv_data); 597 pxa2xx_spi_write(drv_data, SSCR0, 598 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 599 600 dev_err(&drv_data->pdev->dev, "%s\n", msg); 601 602 drv_data->controller->cur_msg->status = -EIO; 603 spi_finalize_current_transfer(drv_data->controller); 604 } 605 606 static void int_transfer_complete(struct driver_data *drv_data) 607 { 608 /* Clear and disable interrupts */ 609 write_SSSR_CS(drv_data, drv_data->clear_sr); 610 reset_sccr1(drv_data); 611 if (!pxa25x_ssp_comp(drv_data)) 612 pxa2xx_spi_write(drv_data, SSTO, 0); 613 614 spi_finalize_current_transfer(drv_data->controller); 615 } 616 617 static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 618 { 619 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? 620 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 621 622 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; 623 624 if (irq_status & SSSR_ROR) { 625 int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 626 return IRQ_HANDLED; 627 } 628 629 if (irq_status & SSSR_TUR) { 630 int_error_stop(drv_data, "interrupt_transfer: fifo underrun"); 631 return IRQ_HANDLED; 632 } 633 634 if (irq_status & SSSR_TINT) { 635 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 636 if (drv_data->read(drv_data)) { 637 int_transfer_complete(drv_data); 638 return IRQ_HANDLED; 639 } 640 } 641 642 /* Drain rx fifo, Fill tx fifo and prevent overruns */ 643 do { 644 if (drv_data->read(drv_data)) { 645 int_transfer_complete(drv_data); 646 return IRQ_HANDLED; 647 } 648 } while (drv_data->write(drv_data)); 649 650 if (drv_data->read(drv_data)) { 651 int_transfer_complete(drv_data); 652 return IRQ_HANDLED; 653 } 654 655 if (drv_data->tx == drv_data->tx_end) { 656 u32 bytes_left; 657 u32 sccr1_reg; 658 659 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 660 sccr1_reg &= ~SSCR1_TIE; 661 662 /* 663 * PXA25x_SSP has no timeout, set up rx threshould for the 664 * remaining RX bytes. 665 */ 666 if (pxa25x_ssp_comp(drv_data)) { 667 u32 rx_thre; 668 669 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 670 671 bytes_left = drv_data->rx_end - drv_data->rx; 672 switch (drv_data->n_bytes) { 673 case 4: 674 bytes_left >>= 2; 675 break; 676 case 2: 677 bytes_left >>= 1; 678 break; 679 } 680 681 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 682 if (rx_thre > bytes_left) 683 rx_thre = bytes_left; 684 685 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 686 } 687 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 688 } 689 690 /* We did something */ 691 return IRQ_HANDLED; 692 } 693 694 static void handle_bad_msg(struct driver_data *drv_data) 695 { 696 pxa2xx_spi_write(drv_data, SSCR0, 697 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 698 pxa2xx_spi_write(drv_data, SSCR1, 699 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1); 700 if (!pxa25x_ssp_comp(drv_data)) 701 pxa2xx_spi_write(drv_data, SSTO, 0); 702 write_SSSR_CS(drv_data, drv_data->clear_sr); 703 704 dev_err(&drv_data->pdev->dev, 705 "bad message state in interrupt handler\n"); 706 } 707 708 static irqreturn_t ssp_int(int irq, void *dev_id) 709 { 710 struct driver_data *drv_data = dev_id; 711 u32 sccr1_reg; 712 u32 mask = drv_data->mask_sr; 713 u32 status; 714 715 /* 716 * The IRQ might be shared with other peripherals so we must first 717 * check that are we RPM suspended or not. If we are we assume that 718 * the IRQ was not for us (we shouldn't be RPM suspended when the 719 * interrupt is enabled). 720 */ 721 if (pm_runtime_suspended(&drv_data->pdev->dev)) 722 return IRQ_NONE; 723 724 /* 725 * If the device is not yet in RPM suspended state and we get an 726 * interrupt that is meant for another device, check if status bits 727 * are all set to one. That means that the device is already 728 * powered off. 729 */ 730 status = pxa2xx_spi_read(drv_data, SSSR); 731 if (status == ~0) 732 return IRQ_NONE; 733 734 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 735 736 /* Ignore possible writes if we don't need to write */ 737 if (!(sccr1_reg & SSCR1_TIE)) 738 mask &= ~SSSR_TFS; 739 740 /* Ignore RX timeout interrupt if it is disabled */ 741 if (!(sccr1_reg & SSCR1_TINTE)) 742 mask &= ~SSSR_TINT; 743 744 if (!(status & mask)) 745 return IRQ_NONE; 746 747 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); 748 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 749 750 if (!drv_data->controller->cur_msg) { 751 handle_bad_msg(drv_data); 752 /* Never fail */ 753 return IRQ_HANDLED; 754 } 755 756 return drv_data->transfer_handler(drv_data); 757 } 758 759 /* 760 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply 761 * input frequency by fractions of 2^24. It also has a divider by 5. 762 * 763 * There are formulas to get baud rate value for given input frequency and 764 * divider parameters, such as DDS_CLK_RATE and SCR: 765 * 766 * Fsys = 200MHz 767 * 768 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) 769 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) 770 * 771 * DDS_CLK_RATE either 2^n or 2^n / 5. 772 * SCR is in range 0 .. 255 773 * 774 * Divisor = 5^i * 2^j * 2 * k 775 * i = [0, 1] i = 1 iff j = 0 or j > 3 776 * j = [0, 23] j = 0 iff i = 1 777 * k = [1, 256] 778 * Special case: j = 0, i = 1: Divisor = 2 / 5 779 * 780 * Accordingly to the specification the recommended values for DDS_CLK_RATE 781 * are: 782 * Case 1: 2^n, n = [0, 23] 783 * Case 2: 2^24 * 2 / 5 (0x666666) 784 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) 785 * 786 * In all cases the lowest possible value is better. 787 * 788 * The function calculates parameters for all cases and chooses the one closest 789 * to the asked baud rate. 790 */ 791 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 792 { 793 unsigned long xtal = 200000000; 794 unsigned long fref = xtal / 2; /* mandatory division by 2, 795 see (2) */ 796 /* case 3 */ 797 unsigned long fref1 = fref / 2; /* case 1 */ 798 unsigned long fref2 = fref * 2 / 5; /* case 2 */ 799 unsigned long scale; 800 unsigned long q, q1, q2; 801 long r, r1, r2; 802 u32 mul; 803 804 /* Case 1 */ 805 806 /* Set initial value for DDS_CLK_RATE */ 807 mul = (1 << 24) >> 1; 808 809 /* Calculate initial quot */ 810 q1 = DIV_ROUND_UP(fref1, rate); 811 812 /* Scale q1 if it's too big */ 813 if (q1 > 256) { 814 /* Scale q1 to range [1, 512] */ 815 scale = fls_long(q1 - 1); 816 if (scale > 9) { 817 q1 >>= scale - 9; 818 mul >>= scale - 9; 819 } 820 821 /* Round the result if we have a remainder */ 822 q1 += q1 & 1; 823 } 824 825 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ 826 scale = __ffs(q1); 827 q1 >>= scale; 828 mul >>= scale; 829 830 /* Get the remainder */ 831 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); 832 833 /* Case 2 */ 834 835 q2 = DIV_ROUND_UP(fref2, rate); 836 r2 = abs(fref2 / q2 - rate); 837 838 /* 839 * Choose the best between two: less remainder we have the better. We 840 * can't go case 2 if q2 is greater than 256 since SCR register can 841 * hold only values 0 .. 255. 842 */ 843 if (r2 >= r1 || q2 > 256) { 844 /* case 1 is better */ 845 r = r1; 846 q = q1; 847 } else { 848 /* case 2 is better */ 849 r = r2; 850 q = q2; 851 mul = (1 << 24) * 2 / 5; 852 } 853 854 /* Check case 3 only if the divisor is big enough */ 855 if (fref / rate >= 80) { 856 u64 fssp; 857 u32 m; 858 859 /* Calculate initial quot */ 860 q1 = DIV_ROUND_UP(fref, rate); 861 m = (1 << 24) / q1; 862 863 /* Get the remainder */ 864 fssp = (u64)fref * m; 865 do_div(fssp, 1 << 24); 866 r1 = abs(fssp - rate); 867 868 /* Choose this one if it suits better */ 869 if (r1 < r) { 870 /* case 3 is better */ 871 q = 1; 872 mul = m; 873 } 874 } 875 876 *dds = mul; 877 return q - 1; 878 } 879 880 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 881 { 882 unsigned long ssp_clk = drv_data->controller->max_speed_hz; 883 const struct ssp_device *ssp = drv_data->ssp; 884 885 rate = min_t(int, ssp_clk, rate); 886 887 /* 888 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding 889 * that the SSP transmission rate can be greater than the device rate 890 */ 891 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 892 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; 893 else 894 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; 895 } 896 897 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 898 int rate) 899 { 900 struct chip_data *chip = 901 spi_get_ctldata(drv_data->controller->cur_msg->spi); 902 unsigned int clk_div; 903 904 switch (drv_data->ssp_type) { 905 case QUARK_X1000_SSP: 906 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); 907 break; 908 default: 909 clk_div = ssp_get_clk_div(drv_data, rate); 910 break; 911 } 912 return clk_div << 8; 913 } 914 915 static bool pxa2xx_spi_can_dma(struct spi_controller *controller, 916 struct spi_device *spi, 917 struct spi_transfer *xfer) 918 { 919 struct chip_data *chip = spi_get_ctldata(spi); 920 921 return chip->enable_dma && 922 xfer->len <= MAX_DMA_LEN && 923 xfer->len >= chip->dma_burst_size; 924 } 925 926 static int pxa2xx_spi_transfer_one(struct spi_controller *controller, 927 struct spi_device *spi, 928 struct spi_transfer *transfer) 929 { 930 struct driver_data *drv_data = spi_controller_get_devdata(controller); 931 struct spi_message *message = controller->cur_msg; 932 struct chip_data *chip = spi_get_ctldata(spi); 933 u32 dma_thresh = chip->dma_threshold; 934 u32 dma_burst = chip->dma_burst_size; 935 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 936 u32 clk_div; 937 u8 bits; 938 u32 speed; 939 u32 cr0; 940 u32 cr1; 941 int err; 942 int dma_mapped; 943 944 /* Check if we can DMA this transfer */ 945 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { 946 947 /* reject already-mapped transfers; PIO won't always work */ 948 if (message->is_dma_mapped 949 || transfer->rx_dma || transfer->tx_dma) { 950 dev_err(&spi->dev, 951 "Mapped transfer length of %u is greater than %d\n", 952 transfer->len, MAX_DMA_LEN); 953 return -EINVAL; 954 } 955 956 /* warn ... we force this to PIO mode */ 957 dev_warn_ratelimited(&spi->dev, 958 "DMA disabled for transfer length %ld greater than %d\n", 959 (long)transfer->len, MAX_DMA_LEN); 960 } 961 962 /* Setup the transfer state based on the type of transfer */ 963 if (pxa2xx_spi_flush(drv_data) == 0) { 964 dev_err(&spi->dev, "Flush failed\n"); 965 return -EIO; 966 } 967 drv_data->n_bytes = chip->n_bytes; 968 drv_data->tx = (void *)transfer->tx_buf; 969 drv_data->tx_end = drv_data->tx + transfer->len; 970 drv_data->rx = transfer->rx_buf; 971 drv_data->rx_end = drv_data->rx + transfer->len; 972 drv_data->write = drv_data->tx ? chip->write : null_writer; 973 drv_data->read = drv_data->rx ? chip->read : null_reader; 974 975 /* Change speed and bit per word on a per transfer */ 976 bits = transfer->bits_per_word; 977 speed = transfer->speed_hz; 978 979 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); 980 981 if (bits <= 8) { 982 drv_data->n_bytes = 1; 983 drv_data->read = drv_data->read != null_reader ? 984 u8_reader : null_reader; 985 drv_data->write = drv_data->write != null_writer ? 986 u8_writer : null_writer; 987 } else if (bits <= 16) { 988 drv_data->n_bytes = 2; 989 drv_data->read = drv_data->read != null_reader ? 990 u16_reader : null_reader; 991 drv_data->write = drv_data->write != null_writer ? 992 u16_writer : null_writer; 993 } else if (bits <= 32) { 994 drv_data->n_bytes = 4; 995 drv_data->read = drv_data->read != null_reader ? 996 u32_reader : null_reader; 997 drv_data->write = drv_data->write != null_writer ? 998 u32_writer : null_writer; 999 } 1000 /* 1001 * if bits/word is changed in dma mode, then must check the 1002 * thresholds and burst also 1003 */ 1004 if (chip->enable_dma) { 1005 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 1006 spi, 1007 bits, &dma_burst, 1008 &dma_thresh)) 1009 dev_warn_ratelimited(&spi->dev, 1010 "DMA burst size reduced to match bits_per_word\n"); 1011 } 1012 1013 dma_mapped = controller->can_dma && 1014 controller->can_dma(controller, spi, transfer) && 1015 controller->cur_msg_mapped; 1016 if (dma_mapped) { 1017 1018 /* Ensure we have the correct interrupt handler */ 1019 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 1020 1021 err = pxa2xx_spi_dma_prepare(drv_data, transfer); 1022 if (err) 1023 return err; 1024 1025 /* Clear status and start DMA engine */ 1026 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 1027 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 1028 1029 pxa2xx_spi_dma_start(drv_data); 1030 } else { 1031 /* Ensure we have the correct interrupt handler */ 1032 drv_data->transfer_handler = interrupt_transfer; 1033 1034 /* Clear status */ 1035 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 1036 write_SSSR_CS(drv_data, drv_data->clear_sr); 1037 } 1038 1039 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1040 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 1041 if (!pxa25x_ssp_comp(drv_data)) 1042 dev_dbg(&spi->dev, "%u Hz actual, %s\n", 1043 controller->max_speed_hz 1044 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), 1045 dma_mapped ? "DMA" : "PIO"); 1046 else 1047 dev_dbg(&spi->dev, "%u Hz actual, %s\n", 1048 controller->max_speed_hz / 2 1049 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1050 dma_mapped ? "DMA" : "PIO"); 1051 1052 if (is_lpss_ssp(drv_data)) { 1053 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) 1054 != chip->lpss_rx_threshold) 1055 pxa2xx_spi_write(drv_data, SSIRF, 1056 chip->lpss_rx_threshold); 1057 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) 1058 != chip->lpss_tx_threshold) 1059 pxa2xx_spi_write(drv_data, SSITF, 1060 chip->lpss_tx_threshold); 1061 } 1062 1063 if (is_quark_x1000_ssp(drv_data) && 1064 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) 1065 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); 1066 1067 /* see if we need to reload the config registers */ 1068 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) 1069 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) 1070 != (cr1 & change_mask)) { 1071 /* stop the SSP, and update the other bits */ 1072 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); 1073 if (!pxa25x_ssp_comp(drv_data)) 1074 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1075 /* first set CR1 without interrupt and service enables */ 1076 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); 1077 /* restart the SSP */ 1078 pxa2xx_spi_write(drv_data, SSCR0, cr0); 1079 1080 } else { 1081 if (!pxa25x_ssp_comp(drv_data)) 1082 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1083 } 1084 1085 if (drv_data->ssp_type == MMP2_SSP) { 1086 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR) 1087 & SSSR_TFL_MASK) >> 8; 1088 1089 if (tx_level) { 1090 /* On MMP2, flipping SSE doesn't to empty TXFIFO. */ 1091 dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n", 1092 tx_level); 1093 if (tx_level > transfer->len) 1094 tx_level = transfer->len; 1095 drv_data->tx += tx_level; 1096 } 1097 } 1098 1099 if (spi_controller_is_slave(controller)) { 1100 while (drv_data->write(drv_data)) 1101 ; 1102 if (drv_data->gpiod_ready) { 1103 gpiod_set_value(drv_data->gpiod_ready, 1); 1104 udelay(1); 1105 gpiod_set_value(drv_data->gpiod_ready, 0); 1106 } 1107 } 1108 1109 /* 1110 * Release the data by enabling service requests and interrupts, 1111 * without changing any mode bits 1112 */ 1113 pxa2xx_spi_write(drv_data, SSCR1, cr1); 1114 1115 return 1; 1116 } 1117 1118 static int pxa2xx_spi_slave_abort(struct spi_controller *controller) 1119 { 1120 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1121 1122 /* Stop and reset SSP */ 1123 write_SSSR_CS(drv_data, drv_data->clear_sr); 1124 reset_sccr1(drv_data); 1125 if (!pxa25x_ssp_comp(drv_data)) 1126 pxa2xx_spi_write(drv_data, SSTO, 0); 1127 pxa2xx_spi_flush(drv_data); 1128 pxa2xx_spi_write(drv_data, SSCR0, 1129 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1130 1131 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n"); 1132 1133 drv_data->controller->cur_msg->status = -EINTR; 1134 spi_finalize_current_transfer(drv_data->controller); 1135 1136 return 0; 1137 } 1138 1139 static void pxa2xx_spi_handle_err(struct spi_controller *controller, 1140 struct spi_message *msg) 1141 { 1142 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1143 1144 /* Disable the SSP */ 1145 pxa2xx_spi_write(drv_data, SSCR0, 1146 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1147 /* Clear and disable interrupts and service requests */ 1148 write_SSSR_CS(drv_data, drv_data->clear_sr); 1149 pxa2xx_spi_write(drv_data, SSCR1, 1150 pxa2xx_spi_read(drv_data, SSCR1) 1151 & ~(drv_data->int_cr1 | drv_data->dma_cr1)); 1152 if (!pxa25x_ssp_comp(drv_data)) 1153 pxa2xx_spi_write(drv_data, SSTO, 0); 1154 1155 /* 1156 * Stop the DMA if running. Note DMA callback handler may have unset 1157 * the dma_running already, which is fine as stopping is not needed 1158 * then but we shouldn't rely this flag for anything else than 1159 * stopping. For instance to differentiate between PIO and DMA 1160 * transfers. 1161 */ 1162 if (atomic_read(&drv_data->dma_running)) 1163 pxa2xx_spi_dma_stop(drv_data); 1164 } 1165 1166 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller) 1167 { 1168 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1169 1170 /* Disable the SSP now */ 1171 pxa2xx_spi_write(drv_data, SSCR0, 1172 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1173 1174 return 0; 1175 } 1176 1177 static int setup_cs(struct spi_device *spi, struct chip_data *chip, 1178 struct pxa2xx_spi_chip *chip_info) 1179 { 1180 struct driver_data *drv_data = 1181 spi_controller_get_devdata(spi->controller); 1182 struct gpio_desc *gpiod; 1183 int err = 0; 1184 1185 if (chip == NULL) 1186 return 0; 1187 1188 if (drv_data->cs_gpiods) { 1189 gpiod = drv_data->cs_gpiods[spi->chip_select]; 1190 if (gpiod) { 1191 chip->gpiod_cs = gpiod; 1192 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1193 gpiod_set_value(gpiod, chip->gpio_cs_inverted); 1194 } 1195 1196 return 0; 1197 } 1198 1199 if (chip_info == NULL) 1200 return 0; 1201 1202 /* NOTE: setup() can be called multiple times, possibly with 1203 * different chip_info, release previously requested GPIO 1204 */ 1205 if (chip->gpiod_cs) { 1206 gpiod_put(chip->gpiod_cs); 1207 chip->gpiod_cs = NULL; 1208 } 1209 1210 /* If (*cs_control) is provided, ignore GPIO chip select */ 1211 if (chip_info->cs_control) { 1212 chip->cs_control = chip_info->cs_control; 1213 return 0; 1214 } 1215 1216 if (gpio_is_valid(chip_info->gpio_cs)) { 1217 err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1218 if (err) { 1219 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 1220 chip_info->gpio_cs); 1221 return err; 1222 } 1223 1224 gpiod = gpio_to_desc(chip_info->gpio_cs); 1225 chip->gpiod_cs = gpiod; 1226 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1227 1228 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted); 1229 } 1230 1231 return err; 1232 } 1233 1234 static int setup(struct spi_device *spi) 1235 { 1236 struct pxa2xx_spi_chip *chip_info; 1237 struct chip_data *chip; 1238 const struct lpss_config *config; 1239 struct driver_data *drv_data = 1240 spi_controller_get_devdata(spi->controller); 1241 uint tx_thres, tx_hi_thres, rx_thres; 1242 1243 switch (drv_data->ssp_type) { 1244 case QUARK_X1000_SSP: 1245 tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1246 tx_hi_thres = 0; 1247 rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1248 break; 1249 case CE4100_SSP: 1250 tx_thres = TX_THRESH_CE4100_DFLT; 1251 tx_hi_thres = 0; 1252 rx_thres = RX_THRESH_CE4100_DFLT; 1253 break; 1254 case LPSS_LPT_SSP: 1255 case LPSS_BYT_SSP: 1256 case LPSS_BSW_SSP: 1257 case LPSS_SPT_SSP: 1258 case LPSS_BXT_SSP: 1259 case LPSS_CNL_SSP: 1260 config = lpss_get_config(drv_data); 1261 tx_thres = config->tx_threshold_lo; 1262 tx_hi_thres = config->tx_threshold_hi; 1263 rx_thres = config->rx_threshold; 1264 break; 1265 default: 1266 tx_hi_thres = 0; 1267 if (spi_controller_is_slave(drv_data->controller)) { 1268 tx_thres = 1; 1269 rx_thres = 2; 1270 } else { 1271 tx_thres = TX_THRESH_DFLT; 1272 rx_thres = RX_THRESH_DFLT; 1273 } 1274 break; 1275 } 1276 1277 /* Only alloc on first setup */ 1278 chip = spi_get_ctldata(spi); 1279 if (!chip) { 1280 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1281 if (!chip) 1282 return -ENOMEM; 1283 1284 if (drv_data->ssp_type == CE4100_SSP) { 1285 if (spi->chip_select > 4) { 1286 dev_err(&spi->dev, 1287 "failed setup: cs number must not be > 4.\n"); 1288 kfree(chip); 1289 return -EINVAL; 1290 } 1291 1292 chip->frm = spi->chip_select; 1293 } 1294 chip->enable_dma = drv_data->controller_info->enable_dma; 1295 chip->timeout = TIMOUT_DFLT; 1296 } 1297 1298 /* protocol drivers may change the chip settings, so... 1299 * if chip_info exists, use it */ 1300 chip_info = spi->controller_data; 1301 1302 /* chip_info isn't always needed */ 1303 chip->cr1 = 0; 1304 if (chip_info) { 1305 if (chip_info->timeout) 1306 chip->timeout = chip_info->timeout; 1307 if (chip_info->tx_threshold) 1308 tx_thres = chip_info->tx_threshold; 1309 if (chip_info->tx_hi_threshold) 1310 tx_hi_thres = chip_info->tx_hi_threshold; 1311 if (chip_info->rx_threshold) 1312 rx_thres = chip_info->rx_threshold; 1313 chip->dma_threshold = 0; 1314 if (chip_info->enable_loopback) 1315 chip->cr1 = SSCR1_LBM; 1316 } 1317 if (spi_controller_is_slave(drv_data->controller)) { 1318 chip->cr1 |= SSCR1_SCFR; 1319 chip->cr1 |= SSCR1_SCLKDIR; 1320 chip->cr1 |= SSCR1_SFRMDIR; 1321 chip->cr1 |= SSCR1_SPH; 1322 } 1323 1324 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1325 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 1326 | SSITF_TxHiThresh(tx_hi_thres); 1327 1328 /* set dma burst and threshold outside of chip_info path so that if 1329 * chip_info goes away after setting chip->enable_dma, the 1330 * burst and threshold can still respond to changes in bits_per_word */ 1331 if (chip->enable_dma) { 1332 /* set up legal burst and threshold for dma */ 1333 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1334 spi->bits_per_word, 1335 &chip->dma_burst_size, 1336 &chip->dma_threshold)) { 1337 dev_warn(&spi->dev, 1338 "in setup: DMA burst size reduced to match bits_per_word\n"); 1339 } 1340 dev_dbg(&spi->dev, 1341 "in setup: DMA burst size set to %u\n", 1342 chip->dma_burst_size); 1343 } 1344 1345 switch (drv_data->ssp_type) { 1346 case QUARK_X1000_SSP: 1347 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1348 & QUARK_X1000_SSCR1_RFT) 1349 | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1350 & QUARK_X1000_SSCR1_TFT); 1351 break; 1352 case CE4100_SSP: 1353 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | 1354 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); 1355 break; 1356 default: 1357 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1358 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1359 break; 1360 } 1361 1362 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1363 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1364 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1365 1366 if (spi->mode & SPI_LOOP) 1367 chip->cr1 |= SSCR1_LBM; 1368 1369 if (spi->bits_per_word <= 8) { 1370 chip->n_bytes = 1; 1371 chip->read = u8_reader; 1372 chip->write = u8_writer; 1373 } else if (spi->bits_per_word <= 16) { 1374 chip->n_bytes = 2; 1375 chip->read = u16_reader; 1376 chip->write = u16_writer; 1377 } else if (spi->bits_per_word <= 32) { 1378 chip->n_bytes = 4; 1379 chip->read = u32_reader; 1380 chip->write = u32_writer; 1381 } 1382 1383 spi_set_ctldata(spi, chip); 1384 1385 if (drv_data->ssp_type == CE4100_SSP) 1386 return 0; 1387 1388 return setup_cs(spi, chip, chip_info); 1389 } 1390 1391 static void cleanup(struct spi_device *spi) 1392 { 1393 struct chip_data *chip = spi_get_ctldata(spi); 1394 struct driver_data *drv_data = 1395 spi_controller_get_devdata(spi->controller); 1396 1397 if (!chip) 1398 return; 1399 1400 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && 1401 chip->gpiod_cs) 1402 gpiod_put(chip->gpiod_cs); 1403 1404 kfree(chip); 1405 } 1406 1407 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1408 { "INT33C0", LPSS_LPT_SSP }, 1409 { "INT33C1", LPSS_LPT_SSP }, 1410 { "INT3430", LPSS_LPT_SSP }, 1411 { "INT3431", LPSS_LPT_SSP }, 1412 { "80860F0E", LPSS_BYT_SSP }, 1413 { "8086228E", LPSS_BSW_SSP }, 1414 { }, 1415 }; 1416 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1417 1418 /* 1419 * PCI IDs of compound devices that integrate both host controller and private 1420 * integrated DMA engine. Please note these are not used in module 1421 * autoloading and probing in this module but matching the LPSS SSP type. 1422 */ 1423 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { 1424 /* SPT-LP */ 1425 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, 1426 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, 1427 /* SPT-H */ 1428 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, 1429 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, 1430 /* KBL-H */ 1431 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, 1432 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, 1433 /* BXT A-Step */ 1434 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, 1435 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, 1436 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, 1437 /* BXT B-Step */ 1438 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, 1439 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, 1440 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, 1441 /* GLK */ 1442 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, 1443 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, 1444 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, 1445 /* ICL-LP */ 1446 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP }, 1447 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP }, 1448 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP }, 1449 /* APL */ 1450 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, 1451 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, 1452 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, 1453 /* CNL-LP */ 1454 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, 1455 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, 1456 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP }, 1457 /* CNL-H */ 1458 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP }, 1459 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP }, 1460 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP }, 1461 /* CML-LP */ 1462 { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP }, 1463 { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP }, 1464 { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP }, 1465 { }, 1466 }; 1467 1468 static const struct of_device_id pxa2xx_spi_of_match[] = { 1469 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP }, 1470 {}, 1471 }; 1472 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match); 1473 1474 #ifdef CONFIG_ACPI 1475 1476 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1477 { 1478 unsigned int devid; 1479 int port_id = -1; 1480 1481 if (adev && adev->pnp.unique_id && 1482 !kstrtouint(adev->pnp.unique_id, 0, &devid)) 1483 port_id = devid; 1484 return port_id; 1485 } 1486 1487 #else /* !CONFIG_ACPI */ 1488 1489 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1490 { 1491 return -1; 1492 } 1493 1494 #endif /* CONFIG_ACPI */ 1495 1496 1497 #ifdef CONFIG_PCI 1498 1499 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) 1500 { 1501 return param == chan->device->dev; 1502 } 1503 1504 #endif /* CONFIG_PCI */ 1505 1506 static struct pxa2xx_spi_controller * 1507 pxa2xx_spi_init_pdata(struct platform_device *pdev) 1508 { 1509 struct pxa2xx_spi_controller *pdata; 1510 struct acpi_device *adev; 1511 struct ssp_device *ssp; 1512 struct resource *res; 1513 const struct acpi_device_id *adev_id = NULL; 1514 const struct pci_device_id *pcidev_id = NULL; 1515 const struct of_device_id *of_id = NULL; 1516 enum pxa_ssp_type type; 1517 1518 adev = ACPI_COMPANION(&pdev->dev); 1519 1520 if (pdev->dev.of_node) 1521 of_id = of_match_device(pdev->dev.driver->of_match_table, 1522 &pdev->dev); 1523 else if (dev_is_pci(pdev->dev.parent)) 1524 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, 1525 to_pci_dev(pdev->dev.parent)); 1526 else if (adev) 1527 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 1528 &pdev->dev); 1529 else 1530 return NULL; 1531 1532 if (adev_id) 1533 type = (enum pxa_ssp_type)adev_id->driver_data; 1534 else if (pcidev_id) 1535 type = (enum pxa_ssp_type)pcidev_id->driver_data; 1536 else if (of_id) 1537 type = (enum pxa_ssp_type)of_id->data; 1538 else 1539 return NULL; 1540 1541 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1542 if (!pdata) 1543 return NULL; 1544 1545 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1546 if (!res) 1547 return NULL; 1548 1549 ssp = &pdata->ssp; 1550 1551 ssp->phys_base = res->start; 1552 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1553 if (IS_ERR(ssp->mmio_base)) 1554 return NULL; 1555 1556 #ifdef CONFIG_PCI 1557 if (pcidev_id) { 1558 pdata->tx_param = pdev->dev.parent; 1559 pdata->rx_param = pdev->dev.parent; 1560 pdata->dma_filter = pxa2xx_spi_idma_filter; 1561 } 1562 #endif 1563 1564 ssp->clk = devm_clk_get(&pdev->dev, NULL); 1565 ssp->irq = platform_get_irq(pdev, 0); 1566 ssp->type = type; 1567 ssp->pdev = pdev; 1568 ssp->port_id = pxa2xx_spi_get_port_id(adev); 1569 1570 pdata->is_slave = of_property_read_bool(pdev->dev.of_node, "spi-slave"); 1571 pdata->num_chipselect = 1; 1572 pdata->enable_dma = true; 1573 pdata->dma_burst_size = 1; 1574 1575 return pdata; 1576 } 1577 1578 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller, 1579 unsigned int cs) 1580 { 1581 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1582 1583 if (has_acpi_companion(&drv_data->pdev->dev)) { 1584 switch (drv_data->ssp_type) { 1585 /* 1586 * For Atoms the ACPI DeviceSelection used by the Windows 1587 * driver starts from 1 instead of 0 so translate it here 1588 * to match what Linux expects. 1589 */ 1590 case LPSS_BYT_SSP: 1591 case LPSS_BSW_SSP: 1592 return cs - 1; 1593 1594 default: 1595 break; 1596 } 1597 } 1598 1599 return cs; 1600 } 1601 1602 static int pxa2xx_spi_probe(struct platform_device *pdev) 1603 { 1604 struct device *dev = &pdev->dev; 1605 struct pxa2xx_spi_controller *platform_info; 1606 struct spi_controller *controller; 1607 struct driver_data *drv_data; 1608 struct ssp_device *ssp; 1609 const struct lpss_config *config; 1610 int status, count; 1611 u32 tmp; 1612 1613 platform_info = dev_get_platdata(dev); 1614 if (!platform_info) { 1615 platform_info = pxa2xx_spi_init_pdata(pdev); 1616 if (!platform_info) { 1617 dev_err(&pdev->dev, "missing platform data\n"); 1618 return -ENODEV; 1619 } 1620 } 1621 1622 ssp = pxa_ssp_request(pdev->id, pdev->name); 1623 if (!ssp) 1624 ssp = &platform_info->ssp; 1625 1626 if (!ssp->mmio_base) { 1627 dev_err(&pdev->dev, "failed to get ssp\n"); 1628 return -ENODEV; 1629 } 1630 1631 if (platform_info->is_slave) 1632 controller = spi_alloc_slave(dev, sizeof(struct driver_data)); 1633 else 1634 controller = spi_alloc_master(dev, sizeof(struct driver_data)); 1635 1636 if (!controller) { 1637 dev_err(&pdev->dev, "cannot alloc spi_controller\n"); 1638 pxa_ssp_free(ssp); 1639 return -ENOMEM; 1640 } 1641 drv_data = spi_controller_get_devdata(controller); 1642 drv_data->controller = controller; 1643 drv_data->controller_info = platform_info; 1644 drv_data->pdev = pdev; 1645 drv_data->ssp = ssp; 1646 1647 controller->dev.of_node = pdev->dev.of_node; 1648 /* the spi->mode bits understood by this driver: */ 1649 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1650 1651 controller->bus_num = ssp->port_id; 1652 controller->dma_alignment = DMA_ALIGNMENT; 1653 controller->cleanup = cleanup; 1654 controller->setup = setup; 1655 controller->set_cs = pxa2xx_spi_set_cs; 1656 controller->transfer_one = pxa2xx_spi_transfer_one; 1657 controller->slave_abort = pxa2xx_spi_slave_abort; 1658 controller->handle_err = pxa2xx_spi_handle_err; 1659 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1660 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; 1661 controller->auto_runtime_pm = true; 1662 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; 1663 1664 drv_data->ssp_type = ssp->type; 1665 1666 drv_data->ioaddr = ssp->mmio_base; 1667 drv_data->ssdr_physical = ssp->phys_base + SSDR; 1668 if (pxa25x_ssp_comp(drv_data)) { 1669 switch (drv_data->ssp_type) { 1670 case QUARK_X1000_SSP: 1671 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1672 break; 1673 default: 1674 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1675 break; 1676 } 1677 1678 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1679 drv_data->dma_cr1 = 0; 1680 drv_data->clear_sr = SSSR_ROR; 1681 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1682 } else { 1683 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1684 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1685 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1686 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1687 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS 1688 | SSSR_ROR | SSSR_TUR; 1689 } 1690 1691 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1692 drv_data); 1693 if (status < 0) { 1694 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1695 goto out_error_controller_alloc; 1696 } 1697 1698 /* Setup DMA if requested */ 1699 if (platform_info->enable_dma) { 1700 status = pxa2xx_spi_dma_setup(drv_data); 1701 if (status) { 1702 dev_warn(dev, "no DMA channels available, using PIO\n"); 1703 platform_info->enable_dma = false; 1704 } else { 1705 controller->can_dma = pxa2xx_spi_can_dma; 1706 controller->max_dma_len = MAX_DMA_LEN; 1707 } 1708 } 1709 1710 /* Enable SOC clock */ 1711 status = clk_prepare_enable(ssp->clk); 1712 if (status) 1713 goto out_error_dma_irq_alloc; 1714 1715 controller->max_speed_hz = clk_get_rate(ssp->clk); 1716 1717 /* Load default SSP configuration */ 1718 pxa2xx_spi_write(drv_data, SSCR0, 0); 1719 switch (drv_data->ssp_type) { 1720 case QUARK_X1000_SSP: 1721 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | 1722 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1723 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1724 1725 /* using the Motorola SPI protocol and use 8 bit frame */ 1726 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); 1727 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1728 break; 1729 case CE4100_SSP: 1730 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | 1731 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); 1732 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1733 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1734 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1735 break; 1736 default: 1737 1738 if (spi_controller_is_slave(controller)) { 1739 tmp = SSCR1_SCFR | 1740 SSCR1_SCLKDIR | 1741 SSCR1_SFRMDIR | 1742 SSCR1_RxTresh(2) | 1743 SSCR1_TxTresh(1) | 1744 SSCR1_SPH; 1745 } else { 1746 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1747 SSCR1_TxTresh(TX_THRESH_DFLT); 1748 } 1749 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1750 tmp = SSCR0_Motorola | SSCR0_DataSize(8); 1751 if (!spi_controller_is_slave(controller)) 1752 tmp |= SSCR0_SCR(2); 1753 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1754 break; 1755 } 1756 1757 if (!pxa25x_ssp_comp(drv_data)) 1758 pxa2xx_spi_write(drv_data, SSTO, 0); 1759 1760 if (!is_quark_x1000_ssp(drv_data)) 1761 pxa2xx_spi_write(drv_data, SSPSP, 0); 1762 1763 if (is_lpss_ssp(drv_data)) { 1764 lpss_ssp_setup(drv_data); 1765 config = lpss_get_config(drv_data); 1766 if (config->reg_capabilities >= 0) { 1767 tmp = __lpss_ssp_read_priv(drv_data, 1768 config->reg_capabilities); 1769 tmp &= LPSS_CAPS_CS_EN_MASK; 1770 tmp >>= LPSS_CAPS_CS_EN_SHIFT; 1771 platform_info->num_chipselect = ffz(tmp); 1772 } else if (config->cs_num) { 1773 platform_info->num_chipselect = config->cs_num; 1774 } 1775 } 1776 controller->num_chipselect = platform_info->num_chipselect; 1777 1778 count = gpiod_count(&pdev->dev, "cs"); 1779 if (count > 0) { 1780 int i; 1781 1782 controller->num_chipselect = max_t(int, count, 1783 controller->num_chipselect); 1784 1785 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev, 1786 controller->num_chipselect, sizeof(struct gpio_desc *), 1787 GFP_KERNEL); 1788 if (!drv_data->cs_gpiods) { 1789 status = -ENOMEM; 1790 goto out_error_clock_enabled; 1791 } 1792 1793 for (i = 0; i < controller->num_chipselect; i++) { 1794 struct gpio_desc *gpiod; 1795 1796 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS); 1797 if (IS_ERR(gpiod)) { 1798 /* Means use native chip select */ 1799 if (PTR_ERR(gpiod) == -ENOENT) 1800 continue; 1801 1802 status = PTR_ERR(gpiod); 1803 goto out_error_clock_enabled; 1804 } else { 1805 drv_data->cs_gpiods[i] = gpiod; 1806 } 1807 } 1808 } 1809 1810 if (platform_info->is_slave) { 1811 drv_data->gpiod_ready = devm_gpiod_get_optional(dev, 1812 "ready", GPIOD_OUT_LOW); 1813 if (IS_ERR(drv_data->gpiod_ready)) { 1814 status = PTR_ERR(drv_data->gpiod_ready); 1815 goto out_error_clock_enabled; 1816 } 1817 } 1818 1819 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1820 pm_runtime_use_autosuspend(&pdev->dev); 1821 pm_runtime_set_active(&pdev->dev); 1822 pm_runtime_enable(&pdev->dev); 1823 1824 /* Register with the SPI framework */ 1825 platform_set_drvdata(pdev, drv_data); 1826 status = devm_spi_register_controller(&pdev->dev, controller); 1827 if (status != 0) { 1828 dev_err(&pdev->dev, "problem registering spi controller\n"); 1829 goto out_error_clock_enabled; 1830 } 1831 1832 return status; 1833 1834 out_error_clock_enabled: 1835 pm_runtime_put_noidle(&pdev->dev); 1836 pm_runtime_disable(&pdev->dev); 1837 clk_disable_unprepare(ssp->clk); 1838 1839 out_error_dma_irq_alloc: 1840 pxa2xx_spi_dma_release(drv_data); 1841 free_irq(ssp->irq, drv_data); 1842 1843 out_error_controller_alloc: 1844 spi_controller_put(controller); 1845 pxa_ssp_free(ssp); 1846 return status; 1847 } 1848 1849 static int pxa2xx_spi_remove(struct platform_device *pdev) 1850 { 1851 struct driver_data *drv_data = platform_get_drvdata(pdev); 1852 struct ssp_device *ssp; 1853 1854 if (!drv_data) 1855 return 0; 1856 ssp = drv_data->ssp; 1857 1858 pm_runtime_get_sync(&pdev->dev); 1859 1860 /* Disable the SSP at the peripheral and SOC level */ 1861 pxa2xx_spi_write(drv_data, SSCR0, 0); 1862 clk_disable_unprepare(ssp->clk); 1863 1864 /* Release DMA */ 1865 if (drv_data->controller_info->enable_dma) 1866 pxa2xx_spi_dma_release(drv_data); 1867 1868 pm_runtime_put_noidle(&pdev->dev); 1869 pm_runtime_disable(&pdev->dev); 1870 1871 /* Release IRQ */ 1872 free_irq(ssp->irq, drv_data); 1873 1874 /* Release SSP */ 1875 pxa_ssp_free(ssp); 1876 1877 return 0; 1878 } 1879 1880 #ifdef CONFIG_PM_SLEEP 1881 static int pxa2xx_spi_suspend(struct device *dev) 1882 { 1883 struct driver_data *drv_data = dev_get_drvdata(dev); 1884 struct ssp_device *ssp = drv_data->ssp; 1885 int status; 1886 1887 status = spi_controller_suspend(drv_data->controller); 1888 if (status != 0) 1889 return status; 1890 pxa2xx_spi_write(drv_data, SSCR0, 0); 1891 1892 if (!pm_runtime_suspended(dev)) 1893 clk_disable_unprepare(ssp->clk); 1894 1895 return 0; 1896 } 1897 1898 static int pxa2xx_spi_resume(struct device *dev) 1899 { 1900 struct driver_data *drv_data = dev_get_drvdata(dev); 1901 struct ssp_device *ssp = drv_data->ssp; 1902 int status; 1903 1904 /* Enable the SSP clock */ 1905 if (!pm_runtime_suspended(dev)) { 1906 status = clk_prepare_enable(ssp->clk); 1907 if (status) 1908 return status; 1909 } 1910 1911 /* Start the queue running */ 1912 return spi_controller_resume(drv_data->controller); 1913 } 1914 #endif 1915 1916 #ifdef CONFIG_PM 1917 static int pxa2xx_spi_runtime_suspend(struct device *dev) 1918 { 1919 struct driver_data *drv_data = dev_get_drvdata(dev); 1920 1921 clk_disable_unprepare(drv_data->ssp->clk); 1922 return 0; 1923 } 1924 1925 static int pxa2xx_spi_runtime_resume(struct device *dev) 1926 { 1927 struct driver_data *drv_data = dev_get_drvdata(dev); 1928 int status; 1929 1930 status = clk_prepare_enable(drv_data->ssp->clk); 1931 return status; 1932 } 1933 #endif 1934 1935 static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1936 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1937 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 1938 pxa2xx_spi_runtime_resume, NULL) 1939 }; 1940 1941 static struct platform_driver driver = { 1942 .driver = { 1943 .name = "pxa2xx-spi", 1944 .pm = &pxa2xx_spi_pm_ops, 1945 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1946 .of_match_table = of_match_ptr(pxa2xx_spi_of_match), 1947 }, 1948 .probe = pxa2xx_spi_probe, 1949 .remove = pxa2xx_spi_remove, 1950 }; 1951 1952 static int __init pxa2xx_spi_init(void) 1953 { 1954 return platform_driver_register(&driver); 1955 } 1956 subsys_initcall(pxa2xx_spi_init); 1957 1958 static void __exit pxa2xx_spi_exit(void) 1959 { 1960 platform_driver_unregister(&driver); 1961 } 1962 module_exit(pxa2xx_spi_exit); 1963 1964 MODULE_SOFTDEP("pre: dw_dmac"); 1965