1 /* 2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3 * Copyright (C) 2013, Intel Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/ioport.h> 21 #include <linux/errno.h> 22 #include <linux/err.h> 23 #include <linux/interrupt.h> 24 #include <linux/kernel.h> 25 #include <linux/pci.h> 26 #include <linux/platform_device.h> 27 #include <linux/spi/pxa2xx_spi.h> 28 #include <linux/spi/spi.h> 29 #include <linux/delay.h> 30 #include <linux/gpio.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/clk.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/acpi.h> 36 #include <linux/of_device.h> 37 38 #include "spi-pxa2xx.h" 39 40 MODULE_AUTHOR("Stephen Street"); 41 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 42 MODULE_LICENSE("GPL"); 43 MODULE_ALIAS("platform:pxa2xx-spi"); 44 45 #define TIMOUT_DFLT 1000 46 47 /* 48 * for testing SSCR1 changes that require SSP restart, basically 49 * everything except the service and interrupt enables, the pxa270 developer 50 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 51 * list, but the PXA255 dev man says all bits without really meaning the 52 * service and interrupt enables 53 */ 54 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 55 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 56 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 57 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 58 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 59 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 60 61 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 62 | QUARK_X1000_SSCR1_EFWR \ 63 | QUARK_X1000_SSCR1_RFT \ 64 | QUARK_X1000_SSCR1_TFT \ 65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 66 67 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 68 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 69 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 70 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 71 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ 72 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 73 74 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 75 #define LPSS_CS_CONTROL_SW_MODE BIT(0) 76 #define LPSS_CS_CONTROL_CS_HIGH BIT(1) 77 #define LPSS_CAPS_CS_EN_SHIFT 9 78 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) 79 80 struct lpss_config { 81 /* LPSS offset from drv_data->ioaddr */ 82 unsigned offset; 83 /* Register offsets from drv_data->lpss_base or -1 */ 84 int reg_general; 85 int reg_ssp; 86 int reg_cs_ctrl; 87 int reg_capabilities; 88 /* FIFO thresholds */ 89 u32 rx_threshold; 90 u32 tx_threshold_lo; 91 u32 tx_threshold_hi; 92 /* Chip select control */ 93 unsigned cs_sel_shift; 94 unsigned cs_sel_mask; 95 unsigned cs_num; 96 }; 97 98 /* Keep these sorted with enum pxa_ssp_type */ 99 static const struct lpss_config lpss_platforms[] = { 100 { /* LPSS_LPT_SSP */ 101 .offset = 0x800, 102 .reg_general = 0x08, 103 .reg_ssp = 0x0c, 104 .reg_cs_ctrl = 0x18, 105 .reg_capabilities = -1, 106 .rx_threshold = 64, 107 .tx_threshold_lo = 160, 108 .tx_threshold_hi = 224, 109 }, 110 { /* LPSS_BYT_SSP */ 111 .offset = 0x400, 112 .reg_general = 0x08, 113 .reg_ssp = 0x0c, 114 .reg_cs_ctrl = 0x18, 115 .reg_capabilities = -1, 116 .rx_threshold = 64, 117 .tx_threshold_lo = 160, 118 .tx_threshold_hi = 224, 119 }, 120 { /* LPSS_BSW_SSP */ 121 .offset = 0x400, 122 .reg_general = 0x08, 123 .reg_ssp = 0x0c, 124 .reg_cs_ctrl = 0x18, 125 .reg_capabilities = -1, 126 .rx_threshold = 64, 127 .tx_threshold_lo = 160, 128 .tx_threshold_hi = 224, 129 .cs_sel_shift = 2, 130 .cs_sel_mask = 1 << 2, 131 .cs_num = 2, 132 }, 133 { /* LPSS_SPT_SSP */ 134 .offset = 0x200, 135 .reg_general = -1, 136 .reg_ssp = 0x20, 137 .reg_cs_ctrl = 0x24, 138 .reg_capabilities = -1, 139 .rx_threshold = 1, 140 .tx_threshold_lo = 32, 141 .tx_threshold_hi = 56, 142 }, 143 { /* LPSS_BXT_SSP */ 144 .offset = 0x200, 145 .reg_general = -1, 146 .reg_ssp = 0x20, 147 .reg_cs_ctrl = 0x24, 148 .reg_capabilities = 0xfc, 149 .rx_threshold = 1, 150 .tx_threshold_lo = 16, 151 .tx_threshold_hi = 48, 152 .cs_sel_shift = 8, 153 .cs_sel_mask = 3 << 8, 154 }, 155 { /* LPSS_CNL_SSP */ 156 .offset = 0x200, 157 .reg_general = -1, 158 .reg_ssp = 0x20, 159 .reg_cs_ctrl = 0x24, 160 .reg_capabilities = 0xfc, 161 .rx_threshold = 1, 162 .tx_threshold_lo = 32, 163 .tx_threshold_hi = 56, 164 .cs_sel_shift = 8, 165 .cs_sel_mask = 3 << 8, 166 }, 167 }; 168 169 static inline const struct lpss_config 170 *lpss_get_config(const struct driver_data *drv_data) 171 { 172 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; 173 } 174 175 static bool is_lpss_ssp(const struct driver_data *drv_data) 176 { 177 switch (drv_data->ssp_type) { 178 case LPSS_LPT_SSP: 179 case LPSS_BYT_SSP: 180 case LPSS_BSW_SSP: 181 case LPSS_SPT_SSP: 182 case LPSS_BXT_SSP: 183 case LPSS_CNL_SSP: 184 return true; 185 default: 186 return false; 187 } 188 } 189 190 static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 191 { 192 return drv_data->ssp_type == QUARK_X1000_SSP; 193 } 194 195 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 196 { 197 switch (drv_data->ssp_type) { 198 case QUARK_X1000_SSP: 199 return QUARK_X1000_SSCR1_CHANGE_MASK; 200 case CE4100_SSP: 201 return CE4100_SSCR1_CHANGE_MASK; 202 default: 203 return SSCR1_CHANGE_MASK; 204 } 205 } 206 207 static u32 208 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 209 { 210 switch (drv_data->ssp_type) { 211 case QUARK_X1000_SSP: 212 return RX_THRESH_QUARK_X1000_DFLT; 213 case CE4100_SSP: 214 return RX_THRESH_CE4100_DFLT; 215 default: 216 return RX_THRESH_DFLT; 217 } 218 } 219 220 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 221 { 222 u32 mask; 223 224 switch (drv_data->ssp_type) { 225 case QUARK_X1000_SSP: 226 mask = QUARK_X1000_SSSR_TFL_MASK; 227 break; 228 case CE4100_SSP: 229 mask = CE4100_SSSR_TFL_MASK; 230 break; 231 default: 232 mask = SSSR_TFL_MASK; 233 break; 234 } 235 236 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; 237 } 238 239 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 240 u32 *sccr1_reg) 241 { 242 u32 mask; 243 244 switch (drv_data->ssp_type) { 245 case QUARK_X1000_SSP: 246 mask = QUARK_X1000_SSCR1_RFT; 247 break; 248 case CE4100_SSP: 249 mask = CE4100_SSCR1_RFT; 250 break; 251 default: 252 mask = SSCR1_RFT; 253 break; 254 } 255 *sccr1_reg &= ~mask; 256 } 257 258 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 259 u32 *sccr1_reg, u32 threshold) 260 { 261 switch (drv_data->ssp_type) { 262 case QUARK_X1000_SSP: 263 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 264 break; 265 case CE4100_SSP: 266 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); 267 break; 268 default: 269 *sccr1_reg |= SSCR1_RxTresh(threshold); 270 break; 271 } 272 } 273 274 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 275 u32 clk_div, u8 bits) 276 { 277 switch (drv_data->ssp_type) { 278 case QUARK_X1000_SSP: 279 return clk_div 280 | QUARK_X1000_SSCR0_Motorola 281 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) 282 | SSCR0_SSE; 283 default: 284 return clk_div 285 | SSCR0_Motorola 286 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 287 | SSCR0_SSE 288 | (bits > 16 ? SSCR0_EDSS : 0); 289 } 290 } 291 292 /* 293 * Read and write LPSS SSP private registers. Caller must first check that 294 * is_lpss_ssp() returns true before these can be called. 295 */ 296 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 297 { 298 WARN_ON(!drv_data->lpss_base); 299 return readl(drv_data->lpss_base + offset); 300 } 301 302 static void __lpss_ssp_write_priv(struct driver_data *drv_data, 303 unsigned offset, u32 value) 304 { 305 WARN_ON(!drv_data->lpss_base); 306 writel(value, drv_data->lpss_base + offset); 307 } 308 309 /* 310 * lpss_ssp_setup - perform LPSS SSP specific setup 311 * @drv_data: pointer to the driver private data 312 * 313 * Perform LPSS SSP specific setup. This function must be called first if 314 * one is going to use LPSS SSP private registers. 315 */ 316 static void lpss_ssp_setup(struct driver_data *drv_data) 317 { 318 const struct lpss_config *config; 319 u32 value; 320 321 config = lpss_get_config(drv_data); 322 drv_data->lpss_base = drv_data->ioaddr + config->offset; 323 324 /* Enable software chip select control */ 325 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 326 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); 327 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; 328 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 329 330 /* Enable multiblock DMA transfers */ 331 if (drv_data->master_info->enable_dma) { 332 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); 333 334 if (config->reg_general >= 0) { 335 value = __lpss_ssp_read_priv(drv_data, 336 config->reg_general); 337 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; 338 __lpss_ssp_write_priv(drv_data, 339 config->reg_general, value); 340 } 341 } 342 } 343 344 static void lpss_ssp_select_cs(struct spi_device *spi, 345 const struct lpss_config *config) 346 { 347 struct driver_data *drv_data = 348 spi_controller_get_devdata(spi->controller); 349 u32 value, cs; 350 351 if (!config->cs_sel_mask) 352 return; 353 354 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 355 356 cs = spi->chip_select; 357 cs <<= config->cs_sel_shift; 358 if (cs != (value & config->cs_sel_mask)) { 359 /* 360 * When switching another chip select output active the 361 * output must be selected first and wait 2 ssp_clk cycles 362 * before changing state to active. Otherwise a short 363 * glitch will occur on the previous chip select since 364 * output select is latched but state control is not. 365 */ 366 value &= ~config->cs_sel_mask; 367 value |= cs; 368 __lpss_ssp_write_priv(drv_data, 369 config->reg_cs_ctrl, value); 370 ndelay(1000000000 / 371 (drv_data->master->max_speed_hz / 2)); 372 } 373 } 374 375 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) 376 { 377 struct driver_data *drv_data = 378 spi_controller_get_devdata(spi->controller); 379 const struct lpss_config *config; 380 u32 value; 381 382 config = lpss_get_config(drv_data); 383 384 if (enable) 385 lpss_ssp_select_cs(spi, config); 386 387 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 388 if (enable) 389 value &= ~LPSS_CS_CONTROL_CS_HIGH; 390 else 391 value |= LPSS_CS_CONTROL_CS_HIGH; 392 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 393 } 394 395 static void cs_assert(struct spi_device *spi) 396 { 397 struct chip_data *chip = spi_get_ctldata(spi); 398 struct driver_data *drv_data = 399 spi_controller_get_devdata(spi->controller); 400 401 if (drv_data->ssp_type == CE4100_SSP) { 402 pxa2xx_spi_write(drv_data, SSSR, chip->frm); 403 return; 404 } 405 406 if (chip->cs_control) { 407 chip->cs_control(PXA2XX_CS_ASSERT); 408 return; 409 } 410 411 if (chip->gpiod_cs) { 412 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted); 413 return; 414 } 415 416 if (is_lpss_ssp(drv_data)) 417 lpss_ssp_cs_control(spi, true); 418 } 419 420 static void cs_deassert(struct spi_device *spi) 421 { 422 struct chip_data *chip = spi_get_ctldata(spi); 423 struct driver_data *drv_data = 424 spi_controller_get_devdata(spi->controller); 425 unsigned long timeout; 426 427 if (drv_data->ssp_type == CE4100_SSP) 428 return; 429 430 /* Wait until SSP becomes idle before deasserting the CS */ 431 timeout = jiffies + msecs_to_jiffies(10); 432 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && 433 !time_after(jiffies, timeout)) 434 cpu_relax(); 435 436 if (chip->cs_control) { 437 chip->cs_control(PXA2XX_CS_DEASSERT); 438 return; 439 } 440 441 if (chip->gpiod_cs) { 442 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted); 443 return; 444 } 445 446 if (is_lpss_ssp(drv_data)) 447 lpss_ssp_cs_control(spi, false); 448 } 449 450 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) 451 { 452 if (level) 453 cs_deassert(spi); 454 else 455 cs_assert(spi); 456 } 457 458 int pxa2xx_spi_flush(struct driver_data *drv_data) 459 { 460 unsigned long limit = loops_per_jiffy << 1; 461 462 do { 463 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 464 pxa2xx_spi_read(drv_data, SSDR); 465 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 466 write_SSSR_CS(drv_data, SSSR_ROR); 467 468 return limit; 469 } 470 471 static int null_writer(struct driver_data *drv_data) 472 { 473 u8 n_bytes = drv_data->n_bytes; 474 475 if (pxa2xx_spi_txfifo_full(drv_data) 476 || (drv_data->tx == drv_data->tx_end)) 477 return 0; 478 479 pxa2xx_spi_write(drv_data, SSDR, 0); 480 drv_data->tx += n_bytes; 481 482 return 1; 483 } 484 485 static int null_reader(struct driver_data *drv_data) 486 { 487 u8 n_bytes = drv_data->n_bytes; 488 489 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 490 && (drv_data->rx < drv_data->rx_end)) { 491 pxa2xx_spi_read(drv_data, SSDR); 492 drv_data->rx += n_bytes; 493 } 494 495 return drv_data->rx == drv_data->rx_end; 496 } 497 498 static int u8_writer(struct driver_data *drv_data) 499 { 500 if (pxa2xx_spi_txfifo_full(drv_data) 501 || (drv_data->tx == drv_data->tx_end)) 502 return 0; 503 504 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 505 ++drv_data->tx; 506 507 return 1; 508 } 509 510 static int u8_reader(struct driver_data *drv_data) 511 { 512 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 513 && (drv_data->rx < drv_data->rx_end)) { 514 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 515 ++drv_data->rx; 516 } 517 518 return drv_data->rx == drv_data->rx_end; 519 } 520 521 static int u16_writer(struct driver_data *drv_data) 522 { 523 if (pxa2xx_spi_txfifo_full(drv_data) 524 || (drv_data->tx == drv_data->tx_end)) 525 return 0; 526 527 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 528 drv_data->tx += 2; 529 530 return 1; 531 } 532 533 static int u16_reader(struct driver_data *drv_data) 534 { 535 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 536 && (drv_data->rx < drv_data->rx_end)) { 537 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 538 drv_data->rx += 2; 539 } 540 541 return drv_data->rx == drv_data->rx_end; 542 } 543 544 static int u32_writer(struct driver_data *drv_data) 545 { 546 if (pxa2xx_spi_txfifo_full(drv_data) 547 || (drv_data->tx == drv_data->tx_end)) 548 return 0; 549 550 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 551 drv_data->tx += 4; 552 553 return 1; 554 } 555 556 static int u32_reader(struct driver_data *drv_data) 557 { 558 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 559 && (drv_data->rx < drv_data->rx_end)) { 560 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 561 drv_data->rx += 4; 562 } 563 564 return drv_data->rx == drv_data->rx_end; 565 } 566 567 static void reset_sccr1(struct driver_data *drv_data) 568 { 569 struct chip_data *chip = 570 spi_get_ctldata(drv_data->master->cur_msg->spi); 571 u32 sccr1_reg; 572 573 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; 574 switch (drv_data->ssp_type) { 575 case QUARK_X1000_SSP: 576 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT; 577 break; 578 case CE4100_SSP: 579 sccr1_reg &= ~CE4100_SSCR1_RFT; 580 break; 581 default: 582 sccr1_reg &= ~SSCR1_RFT; 583 break; 584 } 585 sccr1_reg |= chip->threshold; 586 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 587 } 588 589 static void int_error_stop(struct driver_data *drv_data, const char* msg) 590 { 591 /* Stop and reset SSP */ 592 write_SSSR_CS(drv_data, drv_data->clear_sr); 593 reset_sccr1(drv_data); 594 if (!pxa25x_ssp_comp(drv_data)) 595 pxa2xx_spi_write(drv_data, SSTO, 0); 596 pxa2xx_spi_flush(drv_data); 597 pxa2xx_spi_write(drv_data, SSCR0, 598 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 599 600 dev_err(&drv_data->pdev->dev, "%s\n", msg); 601 602 drv_data->master->cur_msg->status = -EIO; 603 spi_finalize_current_transfer(drv_data->master); 604 } 605 606 static void int_transfer_complete(struct driver_data *drv_data) 607 { 608 /* Clear and disable interrupts */ 609 write_SSSR_CS(drv_data, drv_data->clear_sr); 610 reset_sccr1(drv_data); 611 if (!pxa25x_ssp_comp(drv_data)) 612 pxa2xx_spi_write(drv_data, SSTO, 0); 613 614 spi_finalize_current_transfer(drv_data->master); 615 } 616 617 static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 618 { 619 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? 620 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 621 622 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; 623 624 if (irq_status & SSSR_ROR) { 625 int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 626 return IRQ_HANDLED; 627 } 628 629 if (irq_status & SSSR_TUR) { 630 int_error_stop(drv_data, "interrupt_transfer: fifo underrun"); 631 return IRQ_HANDLED; 632 } 633 634 if (irq_status & SSSR_TINT) { 635 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 636 if (drv_data->read(drv_data)) { 637 int_transfer_complete(drv_data); 638 return IRQ_HANDLED; 639 } 640 } 641 642 /* Drain rx fifo, Fill tx fifo and prevent overruns */ 643 do { 644 if (drv_data->read(drv_data)) { 645 int_transfer_complete(drv_data); 646 return IRQ_HANDLED; 647 } 648 } while (drv_data->write(drv_data)); 649 650 if (drv_data->read(drv_data)) { 651 int_transfer_complete(drv_data); 652 return IRQ_HANDLED; 653 } 654 655 if (drv_data->tx == drv_data->tx_end) { 656 u32 bytes_left; 657 u32 sccr1_reg; 658 659 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 660 sccr1_reg &= ~SSCR1_TIE; 661 662 /* 663 * PXA25x_SSP has no timeout, set up rx threshould for the 664 * remaining RX bytes. 665 */ 666 if (pxa25x_ssp_comp(drv_data)) { 667 u32 rx_thre; 668 669 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 670 671 bytes_left = drv_data->rx_end - drv_data->rx; 672 switch (drv_data->n_bytes) { 673 case 4: 674 bytes_left >>= 2; 675 break; 676 case 2: 677 bytes_left >>= 1; 678 break; 679 } 680 681 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 682 if (rx_thre > bytes_left) 683 rx_thre = bytes_left; 684 685 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 686 } 687 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 688 } 689 690 /* We did something */ 691 return IRQ_HANDLED; 692 } 693 694 static void handle_bad_msg(struct driver_data *drv_data) 695 { 696 pxa2xx_spi_write(drv_data, SSCR0, 697 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 698 pxa2xx_spi_write(drv_data, SSCR1, 699 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1); 700 if (!pxa25x_ssp_comp(drv_data)) 701 pxa2xx_spi_write(drv_data, SSTO, 0); 702 write_SSSR_CS(drv_data, drv_data->clear_sr); 703 704 dev_err(&drv_data->pdev->dev, 705 "bad message state in interrupt handler\n"); 706 } 707 708 static irqreturn_t ssp_int(int irq, void *dev_id) 709 { 710 struct driver_data *drv_data = dev_id; 711 u32 sccr1_reg; 712 u32 mask = drv_data->mask_sr; 713 u32 status; 714 715 /* 716 * The IRQ might be shared with other peripherals so we must first 717 * check that are we RPM suspended or not. If we are we assume that 718 * the IRQ was not for us (we shouldn't be RPM suspended when the 719 * interrupt is enabled). 720 */ 721 if (pm_runtime_suspended(&drv_data->pdev->dev)) 722 return IRQ_NONE; 723 724 /* 725 * If the device is not yet in RPM suspended state and we get an 726 * interrupt that is meant for another device, check if status bits 727 * are all set to one. That means that the device is already 728 * powered off. 729 */ 730 status = pxa2xx_spi_read(drv_data, SSSR); 731 if (status == ~0) 732 return IRQ_NONE; 733 734 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 735 736 /* Ignore possible writes if we don't need to write */ 737 if (!(sccr1_reg & SSCR1_TIE)) 738 mask &= ~SSSR_TFS; 739 740 /* Ignore RX timeout interrupt if it is disabled */ 741 if (!(sccr1_reg & SSCR1_TINTE)) 742 mask &= ~SSSR_TINT; 743 744 if (!(status & mask)) 745 return IRQ_NONE; 746 747 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); 748 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 749 750 if (!drv_data->master->cur_msg) { 751 handle_bad_msg(drv_data); 752 /* Never fail */ 753 return IRQ_HANDLED; 754 } 755 756 return drv_data->transfer_handler(drv_data); 757 } 758 759 /* 760 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply 761 * input frequency by fractions of 2^24. It also has a divider by 5. 762 * 763 * There are formulas to get baud rate value for given input frequency and 764 * divider parameters, such as DDS_CLK_RATE and SCR: 765 * 766 * Fsys = 200MHz 767 * 768 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) 769 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) 770 * 771 * DDS_CLK_RATE either 2^n or 2^n / 5. 772 * SCR is in range 0 .. 255 773 * 774 * Divisor = 5^i * 2^j * 2 * k 775 * i = [0, 1] i = 1 iff j = 0 or j > 3 776 * j = [0, 23] j = 0 iff i = 1 777 * k = [1, 256] 778 * Special case: j = 0, i = 1: Divisor = 2 / 5 779 * 780 * Accordingly to the specification the recommended values for DDS_CLK_RATE 781 * are: 782 * Case 1: 2^n, n = [0, 23] 783 * Case 2: 2^24 * 2 / 5 (0x666666) 784 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) 785 * 786 * In all cases the lowest possible value is better. 787 * 788 * The function calculates parameters for all cases and chooses the one closest 789 * to the asked baud rate. 790 */ 791 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 792 { 793 unsigned long xtal = 200000000; 794 unsigned long fref = xtal / 2; /* mandatory division by 2, 795 see (2) */ 796 /* case 3 */ 797 unsigned long fref1 = fref / 2; /* case 1 */ 798 unsigned long fref2 = fref * 2 / 5; /* case 2 */ 799 unsigned long scale; 800 unsigned long q, q1, q2; 801 long r, r1, r2; 802 u32 mul; 803 804 /* Case 1 */ 805 806 /* Set initial value for DDS_CLK_RATE */ 807 mul = (1 << 24) >> 1; 808 809 /* Calculate initial quot */ 810 q1 = DIV_ROUND_UP(fref1, rate); 811 812 /* Scale q1 if it's too big */ 813 if (q1 > 256) { 814 /* Scale q1 to range [1, 512] */ 815 scale = fls_long(q1 - 1); 816 if (scale > 9) { 817 q1 >>= scale - 9; 818 mul >>= scale - 9; 819 } 820 821 /* Round the result if we have a remainder */ 822 q1 += q1 & 1; 823 } 824 825 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ 826 scale = __ffs(q1); 827 q1 >>= scale; 828 mul >>= scale; 829 830 /* Get the remainder */ 831 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); 832 833 /* Case 2 */ 834 835 q2 = DIV_ROUND_UP(fref2, rate); 836 r2 = abs(fref2 / q2 - rate); 837 838 /* 839 * Choose the best between two: less remainder we have the better. We 840 * can't go case 2 if q2 is greater than 256 since SCR register can 841 * hold only values 0 .. 255. 842 */ 843 if (r2 >= r1 || q2 > 256) { 844 /* case 1 is better */ 845 r = r1; 846 q = q1; 847 } else { 848 /* case 2 is better */ 849 r = r2; 850 q = q2; 851 mul = (1 << 24) * 2 / 5; 852 } 853 854 /* Check case 3 only if the divisor is big enough */ 855 if (fref / rate >= 80) { 856 u64 fssp; 857 u32 m; 858 859 /* Calculate initial quot */ 860 q1 = DIV_ROUND_UP(fref, rate); 861 m = (1 << 24) / q1; 862 863 /* Get the remainder */ 864 fssp = (u64)fref * m; 865 do_div(fssp, 1 << 24); 866 r1 = abs(fssp - rate); 867 868 /* Choose this one if it suits better */ 869 if (r1 < r) { 870 /* case 3 is better */ 871 q = 1; 872 mul = m; 873 } 874 } 875 876 *dds = mul; 877 return q - 1; 878 } 879 880 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 881 { 882 unsigned long ssp_clk = drv_data->master->max_speed_hz; 883 const struct ssp_device *ssp = drv_data->ssp; 884 885 rate = min_t(int, ssp_clk, rate); 886 887 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 888 return (ssp_clk / (2 * rate) - 1) & 0xff; 889 else 890 return (ssp_clk / rate - 1) & 0xfff; 891 } 892 893 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 894 int rate) 895 { 896 struct chip_data *chip = 897 spi_get_ctldata(drv_data->master->cur_msg->spi); 898 unsigned int clk_div; 899 900 switch (drv_data->ssp_type) { 901 case QUARK_X1000_SSP: 902 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); 903 break; 904 default: 905 clk_div = ssp_get_clk_div(drv_data, rate); 906 break; 907 } 908 return clk_div << 8; 909 } 910 911 static bool pxa2xx_spi_can_dma(struct spi_controller *master, 912 struct spi_device *spi, 913 struct spi_transfer *xfer) 914 { 915 struct chip_data *chip = spi_get_ctldata(spi); 916 917 return chip->enable_dma && 918 xfer->len <= MAX_DMA_LEN && 919 xfer->len >= chip->dma_burst_size; 920 } 921 922 static int pxa2xx_spi_transfer_one(struct spi_controller *master, 923 struct spi_device *spi, 924 struct spi_transfer *transfer) 925 { 926 struct driver_data *drv_data = spi_controller_get_devdata(master); 927 struct spi_message *message = master->cur_msg; 928 struct chip_data *chip = spi_get_ctldata(message->spi); 929 u32 dma_thresh = chip->dma_threshold; 930 u32 dma_burst = chip->dma_burst_size; 931 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 932 u32 clk_div; 933 u8 bits; 934 u32 speed; 935 u32 cr0; 936 u32 cr1; 937 int err; 938 int dma_mapped; 939 940 /* Check if we can DMA this transfer */ 941 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { 942 943 /* reject already-mapped transfers; PIO won't always work */ 944 if (message->is_dma_mapped 945 || transfer->rx_dma || transfer->tx_dma) { 946 dev_err(&drv_data->pdev->dev, 947 "Mapped transfer length of %u is greater than %d\n", 948 transfer->len, MAX_DMA_LEN); 949 return -EINVAL; 950 } 951 952 /* warn ... we force this to PIO mode */ 953 dev_warn_ratelimited(&message->spi->dev, 954 "DMA disabled for transfer length %ld greater than %d\n", 955 (long)transfer->len, MAX_DMA_LEN); 956 } 957 958 /* Setup the transfer state based on the type of transfer */ 959 if (pxa2xx_spi_flush(drv_data) == 0) { 960 dev_err(&drv_data->pdev->dev, "Flush failed\n"); 961 return -EIO; 962 } 963 drv_data->n_bytes = chip->n_bytes; 964 drv_data->tx = (void *)transfer->tx_buf; 965 drv_data->tx_end = drv_data->tx + transfer->len; 966 drv_data->rx = transfer->rx_buf; 967 drv_data->rx_end = drv_data->rx + transfer->len; 968 drv_data->write = drv_data->tx ? chip->write : null_writer; 969 drv_data->read = drv_data->rx ? chip->read : null_reader; 970 971 /* Change speed and bit per word on a per transfer */ 972 bits = transfer->bits_per_word; 973 speed = transfer->speed_hz; 974 975 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); 976 977 if (bits <= 8) { 978 drv_data->n_bytes = 1; 979 drv_data->read = drv_data->read != null_reader ? 980 u8_reader : null_reader; 981 drv_data->write = drv_data->write != null_writer ? 982 u8_writer : null_writer; 983 } else if (bits <= 16) { 984 drv_data->n_bytes = 2; 985 drv_data->read = drv_data->read != null_reader ? 986 u16_reader : null_reader; 987 drv_data->write = drv_data->write != null_writer ? 988 u16_writer : null_writer; 989 } else if (bits <= 32) { 990 drv_data->n_bytes = 4; 991 drv_data->read = drv_data->read != null_reader ? 992 u32_reader : null_reader; 993 drv_data->write = drv_data->write != null_writer ? 994 u32_writer : null_writer; 995 } 996 /* 997 * if bits/word is changed in dma mode, then must check the 998 * thresholds and burst also 999 */ 1000 if (chip->enable_dma) { 1001 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 1002 message->spi, 1003 bits, &dma_burst, 1004 &dma_thresh)) 1005 dev_warn_ratelimited(&message->spi->dev, 1006 "DMA burst size reduced to match bits_per_word\n"); 1007 } 1008 1009 dma_mapped = master->can_dma && 1010 master->can_dma(master, message->spi, transfer) && 1011 master->cur_msg_mapped; 1012 if (dma_mapped) { 1013 1014 /* Ensure we have the correct interrupt handler */ 1015 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 1016 1017 err = pxa2xx_spi_dma_prepare(drv_data, transfer); 1018 if (err) 1019 return err; 1020 1021 /* Clear status and start DMA engine */ 1022 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 1023 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 1024 1025 pxa2xx_spi_dma_start(drv_data); 1026 } else { 1027 /* Ensure we have the correct interrupt handler */ 1028 drv_data->transfer_handler = interrupt_transfer; 1029 1030 /* Clear status */ 1031 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 1032 write_SSSR_CS(drv_data, drv_data->clear_sr); 1033 } 1034 1035 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1036 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 1037 if (!pxa25x_ssp_comp(drv_data)) 1038 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", 1039 master->max_speed_hz 1040 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), 1041 dma_mapped ? "DMA" : "PIO"); 1042 else 1043 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", 1044 master->max_speed_hz / 2 1045 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1046 dma_mapped ? "DMA" : "PIO"); 1047 1048 if (is_lpss_ssp(drv_data)) { 1049 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) 1050 != chip->lpss_rx_threshold) 1051 pxa2xx_spi_write(drv_data, SSIRF, 1052 chip->lpss_rx_threshold); 1053 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) 1054 != chip->lpss_tx_threshold) 1055 pxa2xx_spi_write(drv_data, SSITF, 1056 chip->lpss_tx_threshold); 1057 } 1058 1059 if (is_quark_x1000_ssp(drv_data) && 1060 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) 1061 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); 1062 1063 /* see if we need to reload the config registers */ 1064 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) 1065 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) 1066 != (cr1 & change_mask)) { 1067 /* stop the SSP, and update the other bits */ 1068 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); 1069 if (!pxa25x_ssp_comp(drv_data)) 1070 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1071 /* first set CR1 without interrupt and service enables */ 1072 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); 1073 /* restart the SSP */ 1074 pxa2xx_spi_write(drv_data, SSCR0, cr0); 1075 1076 } else { 1077 if (!pxa25x_ssp_comp(drv_data)) 1078 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1079 } 1080 1081 if (drv_data->ssp_type == MMP2_SSP) { 1082 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR) 1083 & SSSR_TFL_MASK) >> 8; 1084 1085 if (tx_level) { 1086 /* On MMP2, flipping SSE doesn't to empty TXFIFO. */ 1087 dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n", 1088 tx_level); 1089 if (tx_level > transfer->len) 1090 tx_level = transfer->len; 1091 drv_data->tx += tx_level; 1092 } 1093 } 1094 1095 if (spi_controller_is_slave(master)) { 1096 while (drv_data->write(drv_data)) 1097 ; 1098 if (drv_data->gpiod_ready) { 1099 gpiod_set_value(drv_data->gpiod_ready, 1); 1100 udelay(1); 1101 gpiod_set_value(drv_data->gpiod_ready, 0); 1102 } 1103 } 1104 1105 /* 1106 * Release the data by enabling service requests and interrupts, 1107 * without changing any mode bits 1108 */ 1109 pxa2xx_spi_write(drv_data, SSCR1, cr1); 1110 1111 return 1; 1112 } 1113 1114 static int pxa2xx_spi_slave_abort(struct spi_master *master) 1115 { 1116 struct driver_data *drv_data = spi_controller_get_devdata(master); 1117 1118 /* Stop and reset SSP */ 1119 write_SSSR_CS(drv_data, drv_data->clear_sr); 1120 reset_sccr1(drv_data); 1121 if (!pxa25x_ssp_comp(drv_data)) 1122 pxa2xx_spi_write(drv_data, SSTO, 0); 1123 pxa2xx_spi_flush(drv_data); 1124 pxa2xx_spi_write(drv_data, SSCR0, 1125 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1126 1127 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n"); 1128 1129 drv_data->master->cur_msg->status = -EINTR; 1130 spi_finalize_current_transfer(drv_data->master); 1131 1132 return 0; 1133 } 1134 1135 static void pxa2xx_spi_handle_err(struct spi_controller *master, 1136 struct spi_message *msg) 1137 { 1138 struct driver_data *drv_data = spi_controller_get_devdata(master); 1139 1140 /* Disable the SSP */ 1141 pxa2xx_spi_write(drv_data, SSCR0, 1142 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1143 /* Clear and disable interrupts and service requests */ 1144 write_SSSR_CS(drv_data, drv_data->clear_sr); 1145 pxa2xx_spi_write(drv_data, SSCR1, 1146 pxa2xx_spi_read(drv_data, SSCR1) 1147 & ~(drv_data->int_cr1 | drv_data->dma_cr1)); 1148 if (!pxa25x_ssp_comp(drv_data)) 1149 pxa2xx_spi_write(drv_data, SSTO, 0); 1150 1151 /* 1152 * Stop the DMA if running. Note DMA callback handler may have unset 1153 * the dma_running already, which is fine as stopping is not needed 1154 * then but we shouldn't rely this flag for anything else than 1155 * stopping. For instance to differentiate between PIO and DMA 1156 * transfers. 1157 */ 1158 if (atomic_read(&drv_data->dma_running)) 1159 pxa2xx_spi_dma_stop(drv_data); 1160 } 1161 1162 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *master) 1163 { 1164 struct driver_data *drv_data = spi_controller_get_devdata(master); 1165 1166 /* Disable the SSP now */ 1167 pxa2xx_spi_write(drv_data, SSCR0, 1168 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1169 1170 return 0; 1171 } 1172 1173 static int setup_cs(struct spi_device *spi, struct chip_data *chip, 1174 struct pxa2xx_spi_chip *chip_info) 1175 { 1176 struct driver_data *drv_data = 1177 spi_controller_get_devdata(spi->controller); 1178 struct gpio_desc *gpiod; 1179 int err = 0; 1180 1181 if (chip == NULL) 1182 return 0; 1183 1184 if (drv_data->cs_gpiods) { 1185 gpiod = drv_data->cs_gpiods[spi->chip_select]; 1186 if (gpiod) { 1187 chip->gpiod_cs = gpiod; 1188 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1189 gpiod_set_value(gpiod, chip->gpio_cs_inverted); 1190 } 1191 1192 return 0; 1193 } 1194 1195 if (chip_info == NULL) 1196 return 0; 1197 1198 /* NOTE: setup() can be called multiple times, possibly with 1199 * different chip_info, release previously requested GPIO 1200 */ 1201 if (chip->gpiod_cs) { 1202 gpiod_put(chip->gpiod_cs); 1203 chip->gpiod_cs = NULL; 1204 } 1205 1206 /* If (*cs_control) is provided, ignore GPIO chip select */ 1207 if (chip_info->cs_control) { 1208 chip->cs_control = chip_info->cs_control; 1209 return 0; 1210 } 1211 1212 if (gpio_is_valid(chip_info->gpio_cs)) { 1213 err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1214 if (err) { 1215 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 1216 chip_info->gpio_cs); 1217 return err; 1218 } 1219 1220 gpiod = gpio_to_desc(chip_info->gpio_cs); 1221 chip->gpiod_cs = gpiod; 1222 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1223 1224 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted); 1225 } 1226 1227 return err; 1228 } 1229 1230 static int setup(struct spi_device *spi) 1231 { 1232 struct pxa2xx_spi_chip *chip_info; 1233 struct chip_data *chip; 1234 const struct lpss_config *config; 1235 struct driver_data *drv_data = 1236 spi_controller_get_devdata(spi->controller); 1237 uint tx_thres, tx_hi_thres, rx_thres; 1238 1239 switch (drv_data->ssp_type) { 1240 case QUARK_X1000_SSP: 1241 tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1242 tx_hi_thres = 0; 1243 rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1244 break; 1245 case CE4100_SSP: 1246 tx_thres = TX_THRESH_CE4100_DFLT; 1247 tx_hi_thres = 0; 1248 rx_thres = RX_THRESH_CE4100_DFLT; 1249 break; 1250 case LPSS_LPT_SSP: 1251 case LPSS_BYT_SSP: 1252 case LPSS_BSW_SSP: 1253 case LPSS_SPT_SSP: 1254 case LPSS_BXT_SSP: 1255 case LPSS_CNL_SSP: 1256 config = lpss_get_config(drv_data); 1257 tx_thres = config->tx_threshold_lo; 1258 tx_hi_thres = config->tx_threshold_hi; 1259 rx_thres = config->rx_threshold; 1260 break; 1261 default: 1262 tx_hi_thres = 0; 1263 if (spi_controller_is_slave(drv_data->master)) { 1264 tx_thres = 1; 1265 rx_thres = 2; 1266 } else { 1267 tx_thres = TX_THRESH_DFLT; 1268 rx_thres = RX_THRESH_DFLT; 1269 } 1270 break; 1271 } 1272 1273 /* Only alloc on first setup */ 1274 chip = spi_get_ctldata(spi); 1275 if (!chip) { 1276 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1277 if (!chip) 1278 return -ENOMEM; 1279 1280 if (drv_data->ssp_type == CE4100_SSP) { 1281 if (spi->chip_select > 4) { 1282 dev_err(&spi->dev, 1283 "failed setup: cs number must not be > 4.\n"); 1284 kfree(chip); 1285 return -EINVAL; 1286 } 1287 1288 chip->frm = spi->chip_select; 1289 } 1290 chip->enable_dma = drv_data->master_info->enable_dma; 1291 chip->timeout = TIMOUT_DFLT; 1292 } 1293 1294 /* protocol drivers may change the chip settings, so... 1295 * if chip_info exists, use it */ 1296 chip_info = spi->controller_data; 1297 1298 /* chip_info isn't always needed */ 1299 chip->cr1 = 0; 1300 if (chip_info) { 1301 if (chip_info->timeout) 1302 chip->timeout = chip_info->timeout; 1303 if (chip_info->tx_threshold) 1304 tx_thres = chip_info->tx_threshold; 1305 if (chip_info->tx_hi_threshold) 1306 tx_hi_thres = chip_info->tx_hi_threshold; 1307 if (chip_info->rx_threshold) 1308 rx_thres = chip_info->rx_threshold; 1309 chip->dma_threshold = 0; 1310 if (chip_info->enable_loopback) 1311 chip->cr1 = SSCR1_LBM; 1312 } 1313 if (spi_controller_is_slave(drv_data->master)) { 1314 chip->cr1 |= SSCR1_SCFR; 1315 chip->cr1 |= SSCR1_SCLKDIR; 1316 chip->cr1 |= SSCR1_SFRMDIR; 1317 chip->cr1 |= SSCR1_SPH; 1318 } 1319 1320 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1321 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 1322 | SSITF_TxHiThresh(tx_hi_thres); 1323 1324 /* set dma burst and threshold outside of chip_info path so that if 1325 * chip_info goes away after setting chip->enable_dma, the 1326 * burst and threshold can still respond to changes in bits_per_word */ 1327 if (chip->enable_dma) { 1328 /* set up legal burst and threshold for dma */ 1329 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1330 spi->bits_per_word, 1331 &chip->dma_burst_size, 1332 &chip->dma_threshold)) { 1333 dev_warn(&spi->dev, 1334 "in setup: DMA burst size reduced to match bits_per_word\n"); 1335 } 1336 } 1337 1338 switch (drv_data->ssp_type) { 1339 case QUARK_X1000_SSP: 1340 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1341 & QUARK_X1000_SSCR1_RFT) 1342 | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1343 & QUARK_X1000_SSCR1_TFT); 1344 break; 1345 case CE4100_SSP: 1346 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | 1347 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); 1348 break; 1349 default: 1350 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1351 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1352 break; 1353 } 1354 1355 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1356 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1357 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1358 1359 if (spi->mode & SPI_LOOP) 1360 chip->cr1 |= SSCR1_LBM; 1361 1362 if (spi->bits_per_word <= 8) { 1363 chip->n_bytes = 1; 1364 chip->read = u8_reader; 1365 chip->write = u8_writer; 1366 } else if (spi->bits_per_word <= 16) { 1367 chip->n_bytes = 2; 1368 chip->read = u16_reader; 1369 chip->write = u16_writer; 1370 } else if (spi->bits_per_word <= 32) { 1371 chip->n_bytes = 4; 1372 chip->read = u32_reader; 1373 chip->write = u32_writer; 1374 } 1375 1376 spi_set_ctldata(spi, chip); 1377 1378 if (drv_data->ssp_type == CE4100_SSP) 1379 return 0; 1380 1381 return setup_cs(spi, chip, chip_info); 1382 } 1383 1384 static void cleanup(struct spi_device *spi) 1385 { 1386 struct chip_data *chip = spi_get_ctldata(spi); 1387 struct driver_data *drv_data = 1388 spi_controller_get_devdata(spi->controller); 1389 1390 if (!chip) 1391 return; 1392 1393 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && 1394 chip->gpiod_cs) 1395 gpiod_put(chip->gpiod_cs); 1396 1397 kfree(chip); 1398 } 1399 1400 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1401 { "INT33C0", LPSS_LPT_SSP }, 1402 { "INT33C1", LPSS_LPT_SSP }, 1403 { "INT3430", LPSS_LPT_SSP }, 1404 { "INT3431", LPSS_LPT_SSP }, 1405 { "80860F0E", LPSS_BYT_SSP }, 1406 { "8086228E", LPSS_BSW_SSP }, 1407 { }, 1408 }; 1409 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1410 1411 /* 1412 * PCI IDs of compound devices that integrate both host controller and private 1413 * integrated DMA engine. Please note these are not used in module 1414 * autoloading and probing in this module but matching the LPSS SSP type. 1415 */ 1416 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { 1417 /* SPT-LP */ 1418 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, 1419 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, 1420 /* SPT-H */ 1421 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, 1422 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, 1423 /* KBL-H */ 1424 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, 1425 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, 1426 /* BXT A-Step */ 1427 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, 1428 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, 1429 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, 1430 /* BXT B-Step */ 1431 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, 1432 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, 1433 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, 1434 /* GLK */ 1435 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, 1436 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, 1437 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, 1438 /* ICL-LP */ 1439 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP }, 1440 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP }, 1441 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP }, 1442 /* APL */ 1443 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, 1444 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, 1445 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, 1446 /* CNL-LP */ 1447 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, 1448 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, 1449 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP }, 1450 /* CNL-H */ 1451 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP }, 1452 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP }, 1453 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP }, 1454 { }, 1455 }; 1456 1457 static const struct of_device_id pxa2xx_spi_of_match[] = { 1458 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP }, 1459 {}, 1460 }; 1461 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match); 1462 1463 #ifdef CONFIG_ACPI 1464 1465 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1466 { 1467 unsigned int devid; 1468 int port_id = -1; 1469 1470 if (adev && adev->pnp.unique_id && 1471 !kstrtouint(adev->pnp.unique_id, 0, &devid)) 1472 port_id = devid; 1473 return port_id; 1474 } 1475 1476 #else /* !CONFIG_ACPI */ 1477 1478 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1479 { 1480 return -1; 1481 } 1482 1483 #endif /* CONFIG_ACPI */ 1484 1485 1486 #ifdef CONFIG_PCI 1487 1488 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) 1489 { 1490 struct device *dev = param; 1491 1492 if (dev != chan->device->dev->parent) 1493 return false; 1494 1495 return true; 1496 } 1497 1498 #endif /* CONFIG_PCI */ 1499 1500 static struct pxa2xx_spi_master * 1501 pxa2xx_spi_init_pdata(struct platform_device *pdev) 1502 { 1503 struct pxa2xx_spi_master *pdata; 1504 struct acpi_device *adev; 1505 struct ssp_device *ssp; 1506 struct resource *res; 1507 const struct acpi_device_id *adev_id = NULL; 1508 const struct pci_device_id *pcidev_id = NULL; 1509 const struct of_device_id *of_id = NULL; 1510 enum pxa_ssp_type type; 1511 1512 adev = ACPI_COMPANION(&pdev->dev); 1513 1514 if (pdev->dev.of_node) 1515 of_id = of_match_device(pdev->dev.driver->of_match_table, 1516 &pdev->dev); 1517 else if (dev_is_pci(pdev->dev.parent)) 1518 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, 1519 to_pci_dev(pdev->dev.parent)); 1520 else if (adev) 1521 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 1522 &pdev->dev); 1523 else 1524 return NULL; 1525 1526 if (adev_id) 1527 type = (enum pxa_ssp_type)adev_id->driver_data; 1528 else if (pcidev_id) 1529 type = (enum pxa_ssp_type)pcidev_id->driver_data; 1530 else if (of_id) 1531 type = (enum pxa_ssp_type)of_id->data; 1532 else 1533 return NULL; 1534 1535 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1536 if (!pdata) 1537 return NULL; 1538 1539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1540 if (!res) 1541 return NULL; 1542 1543 ssp = &pdata->ssp; 1544 1545 ssp->phys_base = res->start; 1546 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1547 if (IS_ERR(ssp->mmio_base)) 1548 return NULL; 1549 1550 #ifdef CONFIG_PCI 1551 if (pcidev_id) { 1552 pdata->tx_param = pdev->dev.parent; 1553 pdata->rx_param = pdev->dev.parent; 1554 pdata->dma_filter = pxa2xx_spi_idma_filter; 1555 } 1556 #endif 1557 1558 ssp->clk = devm_clk_get(&pdev->dev, NULL); 1559 ssp->irq = platform_get_irq(pdev, 0); 1560 ssp->type = type; 1561 ssp->pdev = pdev; 1562 ssp->port_id = pxa2xx_spi_get_port_id(adev); 1563 1564 pdata->is_slave = of_property_read_bool(pdev->dev.of_node, "spi-slave"); 1565 pdata->num_chipselect = 1; 1566 pdata->enable_dma = true; 1567 1568 return pdata; 1569 } 1570 1571 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *master, 1572 unsigned int cs) 1573 { 1574 struct driver_data *drv_data = spi_controller_get_devdata(master); 1575 1576 if (has_acpi_companion(&drv_data->pdev->dev)) { 1577 switch (drv_data->ssp_type) { 1578 /* 1579 * For Atoms the ACPI DeviceSelection used by the Windows 1580 * driver starts from 1 instead of 0 so translate it here 1581 * to match what Linux expects. 1582 */ 1583 case LPSS_BYT_SSP: 1584 case LPSS_BSW_SSP: 1585 return cs - 1; 1586 1587 default: 1588 break; 1589 } 1590 } 1591 1592 return cs; 1593 } 1594 1595 static int pxa2xx_spi_probe(struct platform_device *pdev) 1596 { 1597 struct device *dev = &pdev->dev; 1598 struct pxa2xx_spi_master *platform_info; 1599 struct spi_controller *master; 1600 struct driver_data *drv_data; 1601 struct ssp_device *ssp; 1602 const struct lpss_config *config; 1603 int status, count; 1604 u32 tmp; 1605 1606 platform_info = dev_get_platdata(dev); 1607 if (!platform_info) { 1608 platform_info = pxa2xx_spi_init_pdata(pdev); 1609 if (!platform_info) { 1610 dev_err(&pdev->dev, "missing platform data\n"); 1611 return -ENODEV; 1612 } 1613 } 1614 1615 ssp = pxa_ssp_request(pdev->id, pdev->name); 1616 if (!ssp) 1617 ssp = &platform_info->ssp; 1618 1619 if (!ssp->mmio_base) { 1620 dev_err(&pdev->dev, "failed to get ssp\n"); 1621 return -ENODEV; 1622 } 1623 1624 if (platform_info->is_slave) 1625 master = spi_alloc_slave(dev, sizeof(struct driver_data)); 1626 else 1627 master = spi_alloc_master(dev, sizeof(struct driver_data)); 1628 1629 if (!master) { 1630 dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1631 pxa_ssp_free(ssp); 1632 return -ENOMEM; 1633 } 1634 drv_data = spi_controller_get_devdata(master); 1635 drv_data->master = master; 1636 drv_data->master_info = platform_info; 1637 drv_data->pdev = pdev; 1638 drv_data->ssp = ssp; 1639 1640 master->dev.of_node = pdev->dev.of_node; 1641 /* the spi->mode bits understood by this driver: */ 1642 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1643 1644 master->bus_num = ssp->port_id; 1645 master->dma_alignment = DMA_ALIGNMENT; 1646 master->cleanup = cleanup; 1647 master->setup = setup; 1648 master->set_cs = pxa2xx_spi_set_cs; 1649 master->transfer_one = pxa2xx_spi_transfer_one; 1650 master->slave_abort = pxa2xx_spi_slave_abort; 1651 master->handle_err = pxa2xx_spi_handle_err; 1652 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1653 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs; 1654 master->auto_runtime_pm = true; 1655 master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; 1656 1657 drv_data->ssp_type = ssp->type; 1658 1659 drv_data->ioaddr = ssp->mmio_base; 1660 drv_data->ssdr_physical = ssp->phys_base + SSDR; 1661 if (pxa25x_ssp_comp(drv_data)) { 1662 switch (drv_data->ssp_type) { 1663 case QUARK_X1000_SSP: 1664 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1665 break; 1666 default: 1667 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1668 break; 1669 } 1670 1671 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1672 drv_data->dma_cr1 = 0; 1673 drv_data->clear_sr = SSSR_ROR; 1674 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1675 } else { 1676 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1677 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1678 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1679 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1680 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS 1681 | SSSR_ROR | SSSR_TUR; 1682 } 1683 1684 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1685 drv_data); 1686 if (status < 0) { 1687 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1688 goto out_error_master_alloc; 1689 } 1690 1691 /* Setup DMA if requested */ 1692 if (platform_info->enable_dma) { 1693 status = pxa2xx_spi_dma_setup(drv_data); 1694 if (status) { 1695 dev_dbg(dev, "no DMA channels available, using PIO\n"); 1696 platform_info->enable_dma = false; 1697 } else { 1698 master->can_dma = pxa2xx_spi_can_dma; 1699 } 1700 } 1701 1702 /* Enable SOC clock */ 1703 status = clk_prepare_enable(ssp->clk); 1704 if (status) 1705 goto out_error_dma_irq_alloc; 1706 1707 master->max_speed_hz = clk_get_rate(ssp->clk); 1708 1709 /* Load default SSP configuration */ 1710 pxa2xx_spi_write(drv_data, SSCR0, 0); 1711 switch (drv_data->ssp_type) { 1712 case QUARK_X1000_SSP: 1713 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | 1714 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1715 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1716 1717 /* using the Motorola SPI protocol and use 8 bit frame */ 1718 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); 1719 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1720 break; 1721 case CE4100_SSP: 1722 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | 1723 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); 1724 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1725 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1726 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1727 break; 1728 default: 1729 1730 if (spi_controller_is_slave(master)) { 1731 tmp = SSCR1_SCFR | 1732 SSCR1_SCLKDIR | 1733 SSCR1_SFRMDIR | 1734 SSCR1_RxTresh(2) | 1735 SSCR1_TxTresh(1) | 1736 SSCR1_SPH; 1737 } else { 1738 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1739 SSCR1_TxTresh(TX_THRESH_DFLT); 1740 } 1741 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1742 tmp = SSCR0_Motorola | SSCR0_DataSize(8); 1743 if (!spi_controller_is_slave(master)) 1744 tmp |= SSCR0_SCR(2); 1745 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1746 break; 1747 } 1748 1749 if (!pxa25x_ssp_comp(drv_data)) 1750 pxa2xx_spi_write(drv_data, SSTO, 0); 1751 1752 if (!is_quark_x1000_ssp(drv_data)) 1753 pxa2xx_spi_write(drv_data, SSPSP, 0); 1754 1755 if (is_lpss_ssp(drv_data)) { 1756 lpss_ssp_setup(drv_data); 1757 config = lpss_get_config(drv_data); 1758 if (config->reg_capabilities >= 0) { 1759 tmp = __lpss_ssp_read_priv(drv_data, 1760 config->reg_capabilities); 1761 tmp &= LPSS_CAPS_CS_EN_MASK; 1762 tmp >>= LPSS_CAPS_CS_EN_SHIFT; 1763 platform_info->num_chipselect = ffz(tmp); 1764 } else if (config->cs_num) { 1765 platform_info->num_chipselect = config->cs_num; 1766 } 1767 } 1768 master->num_chipselect = platform_info->num_chipselect; 1769 1770 count = gpiod_count(&pdev->dev, "cs"); 1771 if (count > 0) { 1772 int i; 1773 1774 master->num_chipselect = max_t(int, count, 1775 master->num_chipselect); 1776 1777 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev, 1778 master->num_chipselect, sizeof(struct gpio_desc *), 1779 GFP_KERNEL); 1780 if (!drv_data->cs_gpiods) { 1781 status = -ENOMEM; 1782 goto out_error_clock_enabled; 1783 } 1784 1785 for (i = 0; i < master->num_chipselect; i++) { 1786 struct gpio_desc *gpiod; 1787 1788 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS); 1789 if (IS_ERR(gpiod)) { 1790 /* Means use native chip select */ 1791 if (PTR_ERR(gpiod) == -ENOENT) 1792 continue; 1793 1794 status = PTR_ERR(gpiod); 1795 goto out_error_clock_enabled; 1796 } else { 1797 drv_data->cs_gpiods[i] = gpiod; 1798 } 1799 } 1800 } 1801 1802 if (platform_info->is_slave) { 1803 drv_data->gpiod_ready = devm_gpiod_get_optional(dev, 1804 "ready", GPIOD_OUT_LOW); 1805 if (IS_ERR(drv_data->gpiod_ready)) { 1806 status = PTR_ERR(drv_data->gpiod_ready); 1807 goto out_error_clock_enabled; 1808 } 1809 } 1810 1811 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1812 pm_runtime_use_autosuspend(&pdev->dev); 1813 pm_runtime_set_active(&pdev->dev); 1814 pm_runtime_enable(&pdev->dev); 1815 1816 /* Register with the SPI framework */ 1817 platform_set_drvdata(pdev, drv_data); 1818 status = devm_spi_register_controller(&pdev->dev, master); 1819 if (status != 0) { 1820 dev_err(&pdev->dev, "problem registering spi master\n"); 1821 goto out_error_clock_enabled; 1822 } 1823 1824 return status; 1825 1826 out_error_clock_enabled: 1827 pm_runtime_put_noidle(&pdev->dev); 1828 pm_runtime_disable(&pdev->dev); 1829 clk_disable_unprepare(ssp->clk); 1830 1831 out_error_dma_irq_alloc: 1832 pxa2xx_spi_dma_release(drv_data); 1833 free_irq(ssp->irq, drv_data); 1834 1835 out_error_master_alloc: 1836 spi_controller_put(master); 1837 pxa_ssp_free(ssp); 1838 return status; 1839 } 1840 1841 static int pxa2xx_spi_remove(struct platform_device *pdev) 1842 { 1843 struct driver_data *drv_data = platform_get_drvdata(pdev); 1844 struct ssp_device *ssp; 1845 1846 if (!drv_data) 1847 return 0; 1848 ssp = drv_data->ssp; 1849 1850 pm_runtime_get_sync(&pdev->dev); 1851 1852 /* Disable the SSP at the peripheral and SOC level */ 1853 pxa2xx_spi_write(drv_data, SSCR0, 0); 1854 clk_disable_unprepare(ssp->clk); 1855 1856 /* Release DMA */ 1857 if (drv_data->master_info->enable_dma) 1858 pxa2xx_spi_dma_release(drv_data); 1859 1860 pm_runtime_put_noidle(&pdev->dev); 1861 pm_runtime_disable(&pdev->dev); 1862 1863 /* Release IRQ */ 1864 free_irq(ssp->irq, drv_data); 1865 1866 /* Release SSP */ 1867 pxa_ssp_free(ssp); 1868 1869 return 0; 1870 } 1871 1872 #ifdef CONFIG_PM_SLEEP 1873 static int pxa2xx_spi_suspend(struct device *dev) 1874 { 1875 struct driver_data *drv_data = dev_get_drvdata(dev); 1876 struct ssp_device *ssp = drv_data->ssp; 1877 int status; 1878 1879 status = spi_controller_suspend(drv_data->master); 1880 if (status != 0) 1881 return status; 1882 pxa2xx_spi_write(drv_data, SSCR0, 0); 1883 1884 if (!pm_runtime_suspended(dev)) 1885 clk_disable_unprepare(ssp->clk); 1886 1887 return 0; 1888 } 1889 1890 static int pxa2xx_spi_resume(struct device *dev) 1891 { 1892 struct driver_data *drv_data = dev_get_drvdata(dev); 1893 struct ssp_device *ssp = drv_data->ssp; 1894 int status; 1895 1896 /* Enable the SSP clock */ 1897 if (!pm_runtime_suspended(dev)) { 1898 status = clk_prepare_enable(ssp->clk); 1899 if (status) 1900 return status; 1901 } 1902 1903 /* Start the queue running */ 1904 return spi_controller_resume(drv_data->master); 1905 } 1906 #endif 1907 1908 #ifdef CONFIG_PM 1909 static int pxa2xx_spi_runtime_suspend(struct device *dev) 1910 { 1911 struct driver_data *drv_data = dev_get_drvdata(dev); 1912 1913 clk_disable_unprepare(drv_data->ssp->clk); 1914 return 0; 1915 } 1916 1917 static int pxa2xx_spi_runtime_resume(struct device *dev) 1918 { 1919 struct driver_data *drv_data = dev_get_drvdata(dev); 1920 int status; 1921 1922 status = clk_prepare_enable(drv_data->ssp->clk); 1923 return status; 1924 } 1925 #endif 1926 1927 static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1928 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1929 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 1930 pxa2xx_spi_runtime_resume, NULL) 1931 }; 1932 1933 static struct platform_driver driver = { 1934 .driver = { 1935 .name = "pxa2xx-spi", 1936 .pm = &pxa2xx_spi_pm_ops, 1937 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1938 .of_match_table = of_match_ptr(pxa2xx_spi_of_match), 1939 }, 1940 .probe = pxa2xx_spi_probe, 1941 .remove = pxa2xx_spi_remove, 1942 }; 1943 1944 static int __init pxa2xx_spi_init(void) 1945 { 1946 return platform_driver_register(&driver); 1947 } 1948 subsys_initcall(pxa2xx_spi_init); 1949 1950 static void __exit pxa2xx_spi_exit(void) 1951 { 1952 platform_driver_unregister(&driver); 1953 } 1954 module_exit(pxa2xx_spi_exit); 1955