1 /* 2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3 * Copyright (C) 2013, Intel Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/ioport.h> 21 #include <linux/errno.h> 22 #include <linux/err.h> 23 #include <linux/interrupt.h> 24 #include <linux/kernel.h> 25 #include <linux/pci.h> 26 #include <linux/platform_device.h> 27 #include <linux/spi/pxa2xx_spi.h> 28 #include <linux/spi/spi.h> 29 #include <linux/delay.h> 30 #include <linux/gpio.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/clk.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/acpi.h> 36 #include <linux/of_device.h> 37 38 #include "spi-pxa2xx.h" 39 40 MODULE_AUTHOR("Stephen Street"); 41 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 42 MODULE_LICENSE("GPL"); 43 MODULE_ALIAS("platform:pxa2xx-spi"); 44 45 #define TIMOUT_DFLT 1000 46 47 /* 48 * for testing SSCR1 changes that require SSP restart, basically 49 * everything except the service and interrupt enables, the pxa270 developer 50 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 51 * list, but the PXA255 dev man says all bits without really meaning the 52 * service and interrupt enables 53 */ 54 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 55 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 56 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 57 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 58 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 59 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 60 61 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 62 | QUARK_X1000_SSCR1_EFWR \ 63 | QUARK_X1000_SSCR1_RFT \ 64 | QUARK_X1000_SSCR1_TFT \ 65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 66 67 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 68 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 69 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 70 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 71 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ 72 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 73 74 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 75 #define LPSS_CS_CONTROL_SW_MODE BIT(0) 76 #define LPSS_CS_CONTROL_CS_HIGH BIT(1) 77 #define LPSS_CAPS_CS_EN_SHIFT 9 78 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) 79 80 struct lpss_config { 81 /* LPSS offset from drv_data->ioaddr */ 82 unsigned offset; 83 /* Register offsets from drv_data->lpss_base or -1 */ 84 int reg_general; 85 int reg_ssp; 86 int reg_cs_ctrl; 87 int reg_capabilities; 88 /* FIFO thresholds */ 89 u32 rx_threshold; 90 u32 tx_threshold_lo; 91 u32 tx_threshold_hi; 92 /* Chip select control */ 93 unsigned cs_sel_shift; 94 unsigned cs_sel_mask; 95 unsigned cs_num; 96 }; 97 98 /* Keep these sorted with enum pxa_ssp_type */ 99 static const struct lpss_config lpss_platforms[] = { 100 { /* LPSS_LPT_SSP */ 101 .offset = 0x800, 102 .reg_general = 0x08, 103 .reg_ssp = 0x0c, 104 .reg_cs_ctrl = 0x18, 105 .reg_capabilities = -1, 106 .rx_threshold = 64, 107 .tx_threshold_lo = 160, 108 .tx_threshold_hi = 224, 109 }, 110 { /* LPSS_BYT_SSP */ 111 .offset = 0x400, 112 .reg_general = 0x08, 113 .reg_ssp = 0x0c, 114 .reg_cs_ctrl = 0x18, 115 .reg_capabilities = -1, 116 .rx_threshold = 64, 117 .tx_threshold_lo = 160, 118 .tx_threshold_hi = 224, 119 }, 120 { /* LPSS_BSW_SSP */ 121 .offset = 0x400, 122 .reg_general = 0x08, 123 .reg_ssp = 0x0c, 124 .reg_cs_ctrl = 0x18, 125 .reg_capabilities = -1, 126 .rx_threshold = 64, 127 .tx_threshold_lo = 160, 128 .tx_threshold_hi = 224, 129 .cs_sel_shift = 2, 130 .cs_sel_mask = 1 << 2, 131 .cs_num = 2, 132 }, 133 { /* LPSS_SPT_SSP */ 134 .offset = 0x200, 135 .reg_general = -1, 136 .reg_ssp = 0x20, 137 .reg_cs_ctrl = 0x24, 138 .reg_capabilities = -1, 139 .rx_threshold = 1, 140 .tx_threshold_lo = 32, 141 .tx_threshold_hi = 56, 142 }, 143 { /* LPSS_BXT_SSP */ 144 .offset = 0x200, 145 .reg_general = -1, 146 .reg_ssp = 0x20, 147 .reg_cs_ctrl = 0x24, 148 .reg_capabilities = 0xfc, 149 .rx_threshold = 1, 150 .tx_threshold_lo = 16, 151 .tx_threshold_hi = 48, 152 .cs_sel_shift = 8, 153 .cs_sel_mask = 3 << 8, 154 }, 155 { /* LPSS_CNL_SSP */ 156 .offset = 0x200, 157 .reg_general = -1, 158 .reg_ssp = 0x20, 159 .reg_cs_ctrl = 0x24, 160 .reg_capabilities = 0xfc, 161 .rx_threshold = 1, 162 .tx_threshold_lo = 32, 163 .tx_threshold_hi = 56, 164 .cs_sel_shift = 8, 165 .cs_sel_mask = 3 << 8, 166 }, 167 }; 168 169 static inline const struct lpss_config 170 *lpss_get_config(const struct driver_data *drv_data) 171 { 172 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; 173 } 174 175 static bool is_lpss_ssp(const struct driver_data *drv_data) 176 { 177 switch (drv_data->ssp_type) { 178 case LPSS_LPT_SSP: 179 case LPSS_BYT_SSP: 180 case LPSS_BSW_SSP: 181 case LPSS_SPT_SSP: 182 case LPSS_BXT_SSP: 183 case LPSS_CNL_SSP: 184 return true; 185 default: 186 return false; 187 } 188 } 189 190 static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 191 { 192 return drv_data->ssp_type == QUARK_X1000_SSP; 193 } 194 195 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 196 { 197 switch (drv_data->ssp_type) { 198 case QUARK_X1000_SSP: 199 return QUARK_X1000_SSCR1_CHANGE_MASK; 200 case CE4100_SSP: 201 return CE4100_SSCR1_CHANGE_MASK; 202 default: 203 return SSCR1_CHANGE_MASK; 204 } 205 } 206 207 static u32 208 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 209 { 210 switch (drv_data->ssp_type) { 211 case QUARK_X1000_SSP: 212 return RX_THRESH_QUARK_X1000_DFLT; 213 case CE4100_SSP: 214 return RX_THRESH_CE4100_DFLT; 215 default: 216 return RX_THRESH_DFLT; 217 } 218 } 219 220 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 221 { 222 u32 mask; 223 224 switch (drv_data->ssp_type) { 225 case QUARK_X1000_SSP: 226 mask = QUARK_X1000_SSSR_TFL_MASK; 227 break; 228 case CE4100_SSP: 229 mask = CE4100_SSSR_TFL_MASK; 230 break; 231 default: 232 mask = SSSR_TFL_MASK; 233 break; 234 } 235 236 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; 237 } 238 239 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 240 u32 *sccr1_reg) 241 { 242 u32 mask; 243 244 switch (drv_data->ssp_type) { 245 case QUARK_X1000_SSP: 246 mask = QUARK_X1000_SSCR1_RFT; 247 break; 248 case CE4100_SSP: 249 mask = CE4100_SSCR1_RFT; 250 break; 251 default: 252 mask = SSCR1_RFT; 253 break; 254 } 255 *sccr1_reg &= ~mask; 256 } 257 258 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 259 u32 *sccr1_reg, u32 threshold) 260 { 261 switch (drv_data->ssp_type) { 262 case QUARK_X1000_SSP: 263 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 264 break; 265 case CE4100_SSP: 266 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); 267 break; 268 default: 269 *sccr1_reg |= SSCR1_RxTresh(threshold); 270 break; 271 } 272 } 273 274 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 275 u32 clk_div, u8 bits) 276 { 277 switch (drv_data->ssp_type) { 278 case QUARK_X1000_SSP: 279 return clk_div 280 | QUARK_X1000_SSCR0_Motorola 281 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) 282 | SSCR0_SSE; 283 default: 284 return clk_div 285 | SSCR0_Motorola 286 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 287 | SSCR0_SSE 288 | (bits > 16 ? SSCR0_EDSS : 0); 289 } 290 } 291 292 /* 293 * Read and write LPSS SSP private registers. Caller must first check that 294 * is_lpss_ssp() returns true before these can be called. 295 */ 296 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 297 { 298 WARN_ON(!drv_data->lpss_base); 299 return readl(drv_data->lpss_base + offset); 300 } 301 302 static void __lpss_ssp_write_priv(struct driver_data *drv_data, 303 unsigned offset, u32 value) 304 { 305 WARN_ON(!drv_data->lpss_base); 306 writel(value, drv_data->lpss_base + offset); 307 } 308 309 /* 310 * lpss_ssp_setup - perform LPSS SSP specific setup 311 * @drv_data: pointer to the driver private data 312 * 313 * Perform LPSS SSP specific setup. This function must be called first if 314 * one is going to use LPSS SSP private registers. 315 */ 316 static void lpss_ssp_setup(struct driver_data *drv_data) 317 { 318 const struct lpss_config *config; 319 u32 value; 320 321 config = lpss_get_config(drv_data); 322 drv_data->lpss_base = drv_data->ioaddr + config->offset; 323 324 /* Enable software chip select control */ 325 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 326 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); 327 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; 328 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 329 330 /* Enable multiblock DMA transfers */ 331 if (drv_data->master_info->enable_dma) { 332 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); 333 334 if (config->reg_general >= 0) { 335 value = __lpss_ssp_read_priv(drv_data, 336 config->reg_general); 337 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; 338 __lpss_ssp_write_priv(drv_data, 339 config->reg_general, value); 340 } 341 } 342 } 343 344 static void lpss_ssp_select_cs(struct spi_device *spi, 345 const struct lpss_config *config) 346 { 347 struct driver_data *drv_data = 348 spi_controller_get_devdata(spi->controller); 349 u32 value, cs; 350 351 if (!config->cs_sel_mask) 352 return; 353 354 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 355 356 cs = spi->chip_select; 357 cs <<= config->cs_sel_shift; 358 if (cs != (value & config->cs_sel_mask)) { 359 /* 360 * When switching another chip select output active the 361 * output must be selected first and wait 2 ssp_clk cycles 362 * before changing state to active. Otherwise a short 363 * glitch will occur on the previous chip select since 364 * output select is latched but state control is not. 365 */ 366 value &= ~config->cs_sel_mask; 367 value |= cs; 368 __lpss_ssp_write_priv(drv_data, 369 config->reg_cs_ctrl, value); 370 ndelay(1000000000 / 371 (drv_data->master->max_speed_hz / 2)); 372 } 373 } 374 375 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) 376 { 377 struct driver_data *drv_data = 378 spi_controller_get_devdata(spi->controller); 379 const struct lpss_config *config; 380 u32 value; 381 382 config = lpss_get_config(drv_data); 383 384 if (enable) 385 lpss_ssp_select_cs(spi, config); 386 387 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 388 if (enable) 389 value &= ~LPSS_CS_CONTROL_CS_HIGH; 390 else 391 value |= LPSS_CS_CONTROL_CS_HIGH; 392 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 393 } 394 395 static void cs_assert(struct spi_device *spi) 396 { 397 struct chip_data *chip = spi_get_ctldata(spi); 398 struct driver_data *drv_data = 399 spi_controller_get_devdata(spi->controller); 400 401 if (drv_data->ssp_type == CE4100_SSP) { 402 pxa2xx_spi_write(drv_data, SSSR, chip->frm); 403 return; 404 } 405 406 if (chip->cs_control) { 407 chip->cs_control(PXA2XX_CS_ASSERT); 408 return; 409 } 410 411 if (chip->gpiod_cs) { 412 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted); 413 return; 414 } 415 416 if (is_lpss_ssp(drv_data)) 417 lpss_ssp_cs_control(spi, true); 418 } 419 420 static void cs_deassert(struct spi_device *spi) 421 { 422 struct chip_data *chip = spi_get_ctldata(spi); 423 struct driver_data *drv_data = 424 spi_controller_get_devdata(spi->controller); 425 unsigned long timeout; 426 427 if (drv_data->ssp_type == CE4100_SSP) 428 return; 429 430 /* Wait until SSP becomes idle before deasserting the CS */ 431 timeout = jiffies + msecs_to_jiffies(10); 432 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && 433 !time_after(jiffies, timeout)) 434 cpu_relax(); 435 436 if (chip->cs_control) { 437 chip->cs_control(PXA2XX_CS_DEASSERT); 438 return; 439 } 440 441 if (chip->gpiod_cs) { 442 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted); 443 return; 444 } 445 446 if (is_lpss_ssp(drv_data)) 447 lpss_ssp_cs_control(spi, false); 448 } 449 450 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) 451 { 452 if (level) 453 cs_deassert(spi); 454 else 455 cs_assert(spi); 456 } 457 458 int pxa2xx_spi_flush(struct driver_data *drv_data) 459 { 460 unsigned long limit = loops_per_jiffy << 1; 461 462 do { 463 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 464 pxa2xx_spi_read(drv_data, SSDR); 465 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 466 write_SSSR_CS(drv_data, SSSR_ROR); 467 468 return limit; 469 } 470 471 static int null_writer(struct driver_data *drv_data) 472 { 473 u8 n_bytes = drv_data->n_bytes; 474 475 if (pxa2xx_spi_txfifo_full(drv_data) 476 || (drv_data->tx == drv_data->tx_end)) 477 return 0; 478 479 pxa2xx_spi_write(drv_data, SSDR, 0); 480 drv_data->tx += n_bytes; 481 482 return 1; 483 } 484 485 static int null_reader(struct driver_data *drv_data) 486 { 487 u8 n_bytes = drv_data->n_bytes; 488 489 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 490 && (drv_data->rx < drv_data->rx_end)) { 491 pxa2xx_spi_read(drv_data, SSDR); 492 drv_data->rx += n_bytes; 493 } 494 495 return drv_data->rx == drv_data->rx_end; 496 } 497 498 static int u8_writer(struct driver_data *drv_data) 499 { 500 if (pxa2xx_spi_txfifo_full(drv_data) 501 || (drv_data->tx == drv_data->tx_end)) 502 return 0; 503 504 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 505 ++drv_data->tx; 506 507 return 1; 508 } 509 510 static int u8_reader(struct driver_data *drv_data) 511 { 512 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 513 && (drv_data->rx < drv_data->rx_end)) { 514 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 515 ++drv_data->rx; 516 } 517 518 return drv_data->rx == drv_data->rx_end; 519 } 520 521 static int u16_writer(struct driver_data *drv_data) 522 { 523 if (pxa2xx_spi_txfifo_full(drv_data) 524 || (drv_data->tx == drv_data->tx_end)) 525 return 0; 526 527 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 528 drv_data->tx += 2; 529 530 return 1; 531 } 532 533 static int u16_reader(struct driver_data *drv_data) 534 { 535 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 536 && (drv_data->rx < drv_data->rx_end)) { 537 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 538 drv_data->rx += 2; 539 } 540 541 return drv_data->rx == drv_data->rx_end; 542 } 543 544 static int u32_writer(struct driver_data *drv_data) 545 { 546 if (pxa2xx_spi_txfifo_full(drv_data) 547 || (drv_data->tx == drv_data->tx_end)) 548 return 0; 549 550 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 551 drv_data->tx += 4; 552 553 return 1; 554 } 555 556 static int u32_reader(struct driver_data *drv_data) 557 { 558 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 559 && (drv_data->rx < drv_data->rx_end)) { 560 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 561 drv_data->rx += 4; 562 } 563 564 return drv_data->rx == drv_data->rx_end; 565 } 566 567 static void reset_sccr1(struct driver_data *drv_data) 568 { 569 struct chip_data *chip = 570 spi_get_ctldata(drv_data->master->cur_msg->spi); 571 u32 sccr1_reg; 572 573 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; 574 switch (drv_data->ssp_type) { 575 case QUARK_X1000_SSP: 576 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT; 577 break; 578 case CE4100_SSP: 579 sccr1_reg &= ~CE4100_SSCR1_RFT; 580 break; 581 default: 582 sccr1_reg &= ~SSCR1_RFT; 583 break; 584 } 585 sccr1_reg |= chip->threshold; 586 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 587 } 588 589 static void int_error_stop(struct driver_data *drv_data, const char* msg) 590 { 591 /* Stop and reset SSP */ 592 write_SSSR_CS(drv_data, drv_data->clear_sr); 593 reset_sccr1(drv_data); 594 if (!pxa25x_ssp_comp(drv_data)) 595 pxa2xx_spi_write(drv_data, SSTO, 0); 596 pxa2xx_spi_flush(drv_data); 597 pxa2xx_spi_write(drv_data, SSCR0, 598 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 599 600 dev_err(&drv_data->pdev->dev, "%s\n", msg); 601 602 drv_data->master->cur_msg->status = -EIO; 603 spi_finalize_current_transfer(drv_data->master); 604 } 605 606 static void int_transfer_complete(struct driver_data *drv_data) 607 { 608 /* Clear and disable interrupts */ 609 write_SSSR_CS(drv_data, drv_data->clear_sr); 610 reset_sccr1(drv_data); 611 if (!pxa25x_ssp_comp(drv_data)) 612 pxa2xx_spi_write(drv_data, SSTO, 0); 613 614 spi_finalize_current_transfer(drv_data->master); 615 } 616 617 static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 618 { 619 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? 620 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 621 622 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; 623 624 if (irq_status & SSSR_ROR) { 625 int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 626 return IRQ_HANDLED; 627 } 628 629 if (irq_status & SSSR_TINT) { 630 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 631 if (drv_data->read(drv_data)) { 632 int_transfer_complete(drv_data); 633 return IRQ_HANDLED; 634 } 635 } 636 637 /* Drain rx fifo, Fill tx fifo and prevent overruns */ 638 do { 639 if (drv_data->read(drv_data)) { 640 int_transfer_complete(drv_data); 641 return IRQ_HANDLED; 642 } 643 } while (drv_data->write(drv_data)); 644 645 if (drv_data->read(drv_data)) { 646 int_transfer_complete(drv_data); 647 return IRQ_HANDLED; 648 } 649 650 if (drv_data->tx == drv_data->tx_end) { 651 u32 bytes_left; 652 u32 sccr1_reg; 653 654 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 655 sccr1_reg &= ~SSCR1_TIE; 656 657 /* 658 * PXA25x_SSP has no timeout, set up rx threshould for the 659 * remaining RX bytes. 660 */ 661 if (pxa25x_ssp_comp(drv_data)) { 662 u32 rx_thre; 663 664 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 665 666 bytes_left = drv_data->rx_end - drv_data->rx; 667 switch (drv_data->n_bytes) { 668 case 4: 669 bytes_left >>= 2; 670 break; 671 case 2: 672 bytes_left >>= 1; 673 break; 674 } 675 676 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 677 if (rx_thre > bytes_left) 678 rx_thre = bytes_left; 679 680 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 681 } 682 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 683 } 684 685 /* We did something */ 686 return IRQ_HANDLED; 687 } 688 689 static void handle_bad_msg(struct driver_data *drv_data) 690 { 691 pxa2xx_spi_write(drv_data, SSCR0, 692 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 693 pxa2xx_spi_write(drv_data, SSCR1, 694 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1); 695 if (!pxa25x_ssp_comp(drv_data)) 696 pxa2xx_spi_write(drv_data, SSTO, 0); 697 write_SSSR_CS(drv_data, drv_data->clear_sr); 698 699 dev_err(&drv_data->pdev->dev, 700 "bad message state in interrupt handler\n"); 701 } 702 703 static irqreturn_t ssp_int(int irq, void *dev_id) 704 { 705 struct driver_data *drv_data = dev_id; 706 u32 sccr1_reg; 707 u32 mask = drv_data->mask_sr; 708 u32 status; 709 710 /* 711 * The IRQ might be shared with other peripherals so we must first 712 * check that are we RPM suspended or not. If we are we assume that 713 * the IRQ was not for us (we shouldn't be RPM suspended when the 714 * interrupt is enabled). 715 */ 716 if (pm_runtime_suspended(&drv_data->pdev->dev)) 717 return IRQ_NONE; 718 719 /* 720 * If the device is not yet in RPM suspended state and we get an 721 * interrupt that is meant for another device, check if status bits 722 * are all set to one. That means that the device is already 723 * powered off. 724 */ 725 status = pxa2xx_spi_read(drv_data, SSSR); 726 if (status == ~0) 727 return IRQ_NONE; 728 729 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 730 731 /* Ignore possible writes if we don't need to write */ 732 if (!(sccr1_reg & SSCR1_TIE)) 733 mask &= ~SSSR_TFS; 734 735 /* Ignore RX timeout interrupt if it is disabled */ 736 if (!(sccr1_reg & SSCR1_TINTE)) 737 mask &= ~SSSR_TINT; 738 739 if (!(status & mask)) 740 return IRQ_NONE; 741 742 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); 743 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 744 745 if (!drv_data->master->cur_msg) { 746 handle_bad_msg(drv_data); 747 /* Never fail */ 748 return IRQ_HANDLED; 749 } 750 751 return drv_data->transfer_handler(drv_data); 752 } 753 754 /* 755 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply 756 * input frequency by fractions of 2^24. It also has a divider by 5. 757 * 758 * There are formulas to get baud rate value for given input frequency and 759 * divider parameters, such as DDS_CLK_RATE and SCR: 760 * 761 * Fsys = 200MHz 762 * 763 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) 764 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) 765 * 766 * DDS_CLK_RATE either 2^n or 2^n / 5. 767 * SCR is in range 0 .. 255 768 * 769 * Divisor = 5^i * 2^j * 2 * k 770 * i = [0, 1] i = 1 iff j = 0 or j > 3 771 * j = [0, 23] j = 0 iff i = 1 772 * k = [1, 256] 773 * Special case: j = 0, i = 1: Divisor = 2 / 5 774 * 775 * Accordingly to the specification the recommended values for DDS_CLK_RATE 776 * are: 777 * Case 1: 2^n, n = [0, 23] 778 * Case 2: 2^24 * 2 / 5 (0x666666) 779 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) 780 * 781 * In all cases the lowest possible value is better. 782 * 783 * The function calculates parameters for all cases and chooses the one closest 784 * to the asked baud rate. 785 */ 786 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 787 { 788 unsigned long xtal = 200000000; 789 unsigned long fref = xtal / 2; /* mandatory division by 2, 790 see (2) */ 791 /* case 3 */ 792 unsigned long fref1 = fref / 2; /* case 1 */ 793 unsigned long fref2 = fref * 2 / 5; /* case 2 */ 794 unsigned long scale; 795 unsigned long q, q1, q2; 796 long r, r1, r2; 797 u32 mul; 798 799 /* Case 1 */ 800 801 /* Set initial value for DDS_CLK_RATE */ 802 mul = (1 << 24) >> 1; 803 804 /* Calculate initial quot */ 805 q1 = DIV_ROUND_UP(fref1, rate); 806 807 /* Scale q1 if it's too big */ 808 if (q1 > 256) { 809 /* Scale q1 to range [1, 512] */ 810 scale = fls_long(q1 - 1); 811 if (scale > 9) { 812 q1 >>= scale - 9; 813 mul >>= scale - 9; 814 } 815 816 /* Round the result if we have a remainder */ 817 q1 += q1 & 1; 818 } 819 820 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ 821 scale = __ffs(q1); 822 q1 >>= scale; 823 mul >>= scale; 824 825 /* Get the remainder */ 826 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); 827 828 /* Case 2 */ 829 830 q2 = DIV_ROUND_UP(fref2, rate); 831 r2 = abs(fref2 / q2 - rate); 832 833 /* 834 * Choose the best between two: less remainder we have the better. We 835 * can't go case 2 if q2 is greater than 256 since SCR register can 836 * hold only values 0 .. 255. 837 */ 838 if (r2 >= r1 || q2 > 256) { 839 /* case 1 is better */ 840 r = r1; 841 q = q1; 842 } else { 843 /* case 2 is better */ 844 r = r2; 845 q = q2; 846 mul = (1 << 24) * 2 / 5; 847 } 848 849 /* Check case 3 only if the divisor is big enough */ 850 if (fref / rate >= 80) { 851 u64 fssp; 852 u32 m; 853 854 /* Calculate initial quot */ 855 q1 = DIV_ROUND_UP(fref, rate); 856 m = (1 << 24) / q1; 857 858 /* Get the remainder */ 859 fssp = (u64)fref * m; 860 do_div(fssp, 1 << 24); 861 r1 = abs(fssp - rate); 862 863 /* Choose this one if it suits better */ 864 if (r1 < r) { 865 /* case 3 is better */ 866 q = 1; 867 mul = m; 868 } 869 } 870 871 *dds = mul; 872 return q - 1; 873 } 874 875 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 876 { 877 unsigned long ssp_clk = drv_data->master->max_speed_hz; 878 const struct ssp_device *ssp = drv_data->ssp; 879 880 rate = min_t(int, ssp_clk, rate); 881 882 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 883 return (ssp_clk / (2 * rate) - 1) & 0xff; 884 else 885 return (ssp_clk / rate - 1) & 0xfff; 886 } 887 888 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 889 int rate) 890 { 891 struct chip_data *chip = 892 spi_get_ctldata(drv_data->master->cur_msg->spi); 893 unsigned int clk_div; 894 895 switch (drv_data->ssp_type) { 896 case QUARK_X1000_SSP: 897 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); 898 break; 899 default: 900 clk_div = ssp_get_clk_div(drv_data, rate); 901 break; 902 } 903 return clk_div << 8; 904 } 905 906 static bool pxa2xx_spi_can_dma(struct spi_controller *master, 907 struct spi_device *spi, 908 struct spi_transfer *xfer) 909 { 910 struct chip_data *chip = spi_get_ctldata(spi); 911 912 return chip->enable_dma && 913 xfer->len <= MAX_DMA_LEN && 914 xfer->len >= chip->dma_burst_size; 915 } 916 917 static int pxa2xx_spi_transfer_one(struct spi_controller *master, 918 struct spi_device *spi, 919 struct spi_transfer *transfer) 920 { 921 struct driver_data *drv_data = spi_controller_get_devdata(master); 922 struct spi_message *message = master->cur_msg; 923 struct chip_data *chip = spi_get_ctldata(message->spi); 924 u32 dma_thresh = chip->dma_threshold; 925 u32 dma_burst = chip->dma_burst_size; 926 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 927 u32 clk_div; 928 u8 bits; 929 u32 speed; 930 u32 cr0; 931 u32 cr1; 932 int err; 933 int dma_mapped; 934 935 /* Check if we can DMA this transfer */ 936 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { 937 938 /* reject already-mapped transfers; PIO won't always work */ 939 if (message->is_dma_mapped 940 || transfer->rx_dma || transfer->tx_dma) { 941 dev_err(&drv_data->pdev->dev, 942 "Mapped transfer length of %u is greater than %d\n", 943 transfer->len, MAX_DMA_LEN); 944 return -EINVAL; 945 } 946 947 /* warn ... we force this to PIO mode */ 948 dev_warn_ratelimited(&message->spi->dev, 949 "DMA disabled for transfer length %ld greater than %d\n", 950 (long)transfer->len, MAX_DMA_LEN); 951 } 952 953 /* Setup the transfer state based on the type of transfer */ 954 if (pxa2xx_spi_flush(drv_data) == 0) { 955 dev_err(&drv_data->pdev->dev, "Flush failed\n"); 956 return -EIO; 957 } 958 drv_data->n_bytes = chip->n_bytes; 959 drv_data->tx = (void *)transfer->tx_buf; 960 drv_data->tx_end = drv_data->tx + transfer->len; 961 drv_data->rx = transfer->rx_buf; 962 drv_data->rx_end = drv_data->rx + transfer->len; 963 drv_data->write = drv_data->tx ? chip->write : null_writer; 964 drv_data->read = drv_data->rx ? chip->read : null_reader; 965 966 /* Change speed and bit per word on a per transfer */ 967 bits = transfer->bits_per_word; 968 speed = transfer->speed_hz; 969 970 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); 971 972 if (bits <= 8) { 973 drv_data->n_bytes = 1; 974 drv_data->read = drv_data->read != null_reader ? 975 u8_reader : null_reader; 976 drv_data->write = drv_data->write != null_writer ? 977 u8_writer : null_writer; 978 } else if (bits <= 16) { 979 drv_data->n_bytes = 2; 980 drv_data->read = drv_data->read != null_reader ? 981 u16_reader : null_reader; 982 drv_data->write = drv_data->write != null_writer ? 983 u16_writer : null_writer; 984 } else if (bits <= 32) { 985 drv_data->n_bytes = 4; 986 drv_data->read = drv_data->read != null_reader ? 987 u32_reader : null_reader; 988 drv_data->write = drv_data->write != null_writer ? 989 u32_writer : null_writer; 990 } 991 /* 992 * if bits/word is changed in dma mode, then must check the 993 * thresholds and burst also 994 */ 995 if (chip->enable_dma) { 996 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 997 message->spi, 998 bits, &dma_burst, 999 &dma_thresh)) 1000 dev_warn_ratelimited(&message->spi->dev, 1001 "DMA burst size reduced to match bits_per_word\n"); 1002 } 1003 1004 dma_mapped = master->can_dma && 1005 master->can_dma(master, message->spi, transfer) && 1006 master->cur_msg_mapped; 1007 if (dma_mapped) { 1008 1009 /* Ensure we have the correct interrupt handler */ 1010 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 1011 1012 err = pxa2xx_spi_dma_prepare(drv_data, transfer); 1013 if (err) 1014 return err; 1015 1016 /* Clear status and start DMA engine */ 1017 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 1018 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 1019 1020 pxa2xx_spi_dma_start(drv_data); 1021 } else { 1022 /* Ensure we have the correct interrupt handler */ 1023 drv_data->transfer_handler = interrupt_transfer; 1024 1025 /* Clear status */ 1026 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 1027 write_SSSR_CS(drv_data, drv_data->clear_sr); 1028 } 1029 1030 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1031 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 1032 if (!pxa25x_ssp_comp(drv_data)) 1033 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", 1034 master->max_speed_hz 1035 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), 1036 dma_mapped ? "DMA" : "PIO"); 1037 else 1038 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", 1039 master->max_speed_hz / 2 1040 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1041 dma_mapped ? "DMA" : "PIO"); 1042 1043 if (is_lpss_ssp(drv_data)) { 1044 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) 1045 != chip->lpss_rx_threshold) 1046 pxa2xx_spi_write(drv_data, SSIRF, 1047 chip->lpss_rx_threshold); 1048 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) 1049 != chip->lpss_tx_threshold) 1050 pxa2xx_spi_write(drv_data, SSITF, 1051 chip->lpss_tx_threshold); 1052 } 1053 1054 if (is_quark_x1000_ssp(drv_data) && 1055 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) 1056 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); 1057 1058 /* see if we need to reload the config registers */ 1059 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) 1060 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) 1061 != (cr1 & change_mask)) { 1062 /* stop the SSP, and update the other bits */ 1063 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); 1064 if (!pxa25x_ssp_comp(drv_data)) 1065 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1066 /* first set CR1 without interrupt and service enables */ 1067 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); 1068 /* restart the SSP */ 1069 pxa2xx_spi_write(drv_data, SSCR0, cr0); 1070 1071 } else { 1072 if (!pxa25x_ssp_comp(drv_data)) 1073 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1074 } 1075 1076 /* 1077 * Release the data by enabling service requests and interrupts, 1078 * without changing any mode bits 1079 */ 1080 pxa2xx_spi_write(drv_data, SSCR1, cr1); 1081 1082 return 1; 1083 } 1084 1085 static void pxa2xx_spi_handle_err(struct spi_controller *master, 1086 struct spi_message *msg) 1087 { 1088 struct driver_data *drv_data = spi_controller_get_devdata(master); 1089 1090 /* Disable the SSP */ 1091 pxa2xx_spi_write(drv_data, SSCR0, 1092 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1093 /* Clear and disable interrupts and service requests */ 1094 write_SSSR_CS(drv_data, drv_data->clear_sr); 1095 pxa2xx_spi_write(drv_data, SSCR1, 1096 pxa2xx_spi_read(drv_data, SSCR1) 1097 & ~(drv_data->int_cr1 | drv_data->dma_cr1)); 1098 if (!pxa25x_ssp_comp(drv_data)) 1099 pxa2xx_spi_write(drv_data, SSTO, 0); 1100 1101 /* 1102 * Stop the DMA if running. Note DMA callback handler may have unset 1103 * the dma_running already, which is fine as stopping is not needed 1104 * then but we shouldn't rely this flag for anything else than 1105 * stopping. For instance to differentiate between PIO and DMA 1106 * transfers. 1107 */ 1108 if (atomic_read(&drv_data->dma_running)) 1109 pxa2xx_spi_dma_stop(drv_data); 1110 } 1111 1112 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *master) 1113 { 1114 struct driver_data *drv_data = spi_controller_get_devdata(master); 1115 1116 /* Disable the SSP now */ 1117 pxa2xx_spi_write(drv_data, SSCR0, 1118 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1119 1120 return 0; 1121 } 1122 1123 static int setup_cs(struct spi_device *spi, struct chip_data *chip, 1124 struct pxa2xx_spi_chip *chip_info) 1125 { 1126 struct driver_data *drv_data = 1127 spi_controller_get_devdata(spi->controller); 1128 struct gpio_desc *gpiod; 1129 int err = 0; 1130 1131 if (chip == NULL) 1132 return 0; 1133 1134 if (drv_data->cs_gpiods) { 1135 gpiod = drv_data->cs_gpiods[spi->chip_select]; 1136 if (gpiod) { 1137 chip->gpiod_cs = gpiod; 1138 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1139 gpiod_set_value(gpiod, chip->gpio_cs_inverted); 1140 } 1141 1142 return 0; 1143 } 1144 1145 if (chip_info == NULL) 1146 return 0; 1147 1148 /* NOTE: setup() can be called multiple times, possibly with 1149 * different chip_info, release previously requested GPIO 1150 */ 1151 if (chip->gpiod_cs) { 1152 gpiod_put(chip->gpiod_cs); 1153 chip->gpiod_cs = NULL; 1154 } 1155 1156 /* If (*cs_control) is provided, ignore GPIO chip select */ 1157 if (chip_info->cs_control) { 1158 chip->cs_control = chip_info->cs_control; 1159 return 0; 1160 } 1161 1162 if (gpio_is_valid(chip_info->gpio_cs)) { 1163 err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1164 if (err) { 1165 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 1166 chip_info->gpio_cs); 1167 return err; 1168 } 1169 1170 gpiod = gpio_to_desc(chip_info->gpio_cs); 1171 chip->gpiod_cs = gpiod; 1172 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1173 1174 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted); 1175 } 1176 1177 return err; 1178 } 1179 1180 static int setup(struct spi_device *spi) 1181 { 1182 struct pxa2xx_spi_chip *chip_info; 1183 struct chip_data *chip; 1184 const struct lpss_config *config; 1185 struct driver_data *drv_data = 1186 spi_controller_get_devdata(spi->controller); 1187 uint tx_thres, tx_hi_thres, rx_thres; 1188 1189 switch (drv_data->ssp_type) { 1190 case QUARK_X1000_SSP: 1191 tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1192 tx_hi_thres = 0; 1193 rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1194 break; 1195 case CE4100_SSP: 1196 tx_thres = TX_THRESH_CE4100_DFLT; 1197 tx_hi_thres = 0; 1198 rx_thres = RX_THRESH_CE4100_DFLT; 1199 break; 1200 case LPSS_LPT_SSP: 1201 case LPSS_BYT_SSP: 1202 case LPSS_BSW_SSP: 1203 case LPSS_SPT_SSP: 1204 case LPSS_BXT_SSP: 1205 case LPSS_CNL_SSP: 1206 config = lpss_get_config(drv_data); 1207 tx_thres = config->tx_threshold_lo; 1208 tx_hi_thres = config->tx_threshold_hi; 1209 rx_thres = config->rx_threshold; 1210 break; 1211 default: 1212 tx_thres = TX_THRESH_DFLT; 1213 tx_hi_thres = 0; 1214 rx_thres = RX_THRESH_DFLT; 1215 break; 1216 } 1217 1218 /* Only alloc on first setup */ 1219 chip = spi_get_ctldata(spi); 1220 if (!chip) { 1221 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1222 if (!chip) 1223 return -ENOMEM; 1224 1225 if (drv_data->ssp_type == CE4100_SSP) { 1226 if (spi->chip_select > 4) { 1227 dev_err(&spi->dev, 1228 "failed setup: cs number must not be > 4.\n"); 1229 kfree(chip); 1230 return -EINVAL; 1231 } 1232 1233 chip->frm = spi->chip_select; 1234 } 1235 chip->enable_dma = drv_data->master_info->enable_dma; 1236 chip->timeout = TIMOUT_DFLT; 1237 } 1238 1239 /* protocol drivers may change the chip settings, so... 1240 * if chip_info exists, use it */ 1241 chip_info = spi->controller_data; 1242 1243 /* chip_info isn't always needed */ 1244 chip->cr1 = 0; 1245 if (chip_info) { 1246 if (chip_info->timeout) 1247 chip->timeout = chip_info->timeout; 1248 if (chip_info->tx_threshold) 1249 tx_thres = chip_info->tx_threshold; 1250 if (chip_info->tx_hi_threshold) 1251 tx_hi_thres = chip_info->tx_hi_threshold; 1252 if (chip_info->rx_threshold) 1253 rx_thres = chip_info->rx_threshold; 1254 chip->dma_threshold = 0; 1255 if (chip_info->enable_loopback) 1256 chip->cr1 = SSCR1_LBM; 1257 } 1258 1259 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1260 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 1261 | SSITF_TxHiThresh(tx_hi_thres); 1262 1263 /* set dma burst and threshold outside of chip_info path so that if 1264 * chip_info goes away after setting chip->enable_dma, the 1265 * burst and threshold can still respond to changes in bits_per_word */ 1266 if (chip->enable_dma) { 1267 /* set up legal burst and threshold for dma */ 1268 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1269 spi->bits_per_word, 1270 &chip->dma_burst_size, 1271 &chip->dma_threshold)) { 1272 dev_warn(&spi->dev, 1273 "in setup: DMA burst size reduced to match bits_per_word\n"); 1274 } 1275 } 1276 1277 switch (drv_data->ssp_type) { 1278 case QUARK_X1000_SSP: 1279 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1280 & QUARK_X1000_SSCR1_RFT) 1281 | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1282 & QUARK_X1000_SSCR1_TFT); 1283 break; 1284 case CE4100_SSP: 1285 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | 1286 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); 1287 break; 1288 default: 1289 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1290 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1291 break; 1292 } 1293 1294 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1295 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1296 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1297 1298 if (spi->mode & SPI_LOOP) 1299 chip->cr1 |= SSCR1_LBM; 1300 1301 if (spi->bits_per_word <= 8) { 1302 chip->n_bytes = 1; 1303 chip->read = u8_reader; 1304 chip->write = u8_writer; 1305 } else if (spi->bits_per_word <= 16) { 1306 chip->n_bytes = 2; 1307 chip->read = u16_reader; 1308 chip->write = u16_writer; 1309 } else if (spi->bits_per_word <= 32) { 1310 chip->n_bytes = 4; 1311 chip->read = u32_reader; 1312 chip->write = u32_writer; 1313 } 1314 1315 spi_set_ctldata(spi, chip); 1316 1317 if (drv_data->ssp_type == CE4100_SSP) 1318 return 0; 1319 1320 return setup_cs(spi, chip, chip_info); 1321 } 1322 1323 static void cleanup(struct spi_device *spi) 1324 { 1325 struct chip_data *chip = spi_get_ctldata(spi); 1326 struct driver_data *drv_data = 1327 spi_controller_get_devdata(spi->controller); 1328 1329 if (!chip) 1330 return; 1331 1332 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && 1333 chip->gpiod_cs) 1334 gpiod_put(chip->gpiod_cs); 1335 1336 kfree(chip); 1337 } 1338 1339 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1340 { "INT33C0", LPSS_LPT_SSP }, 1341 { "INT33C1", LPSS_LPT_SSP }, 1342 { "INT3430", LPSS_LPT_SSP }, 1343 { "INT3431", LPSS_LPT_SSP }, 1344 { "80860F0E", LPSS_BYT_SSP }, 1345 { "8086228E", LPSS_BSW_SSP }, 1346 { }, 1347 }; 1348 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1349 1350 /* 1351 * PCI IDs of compound devices that integrate both host controller and private 1352 * integrated DMA engine. Please note these are not used in module 1353 * autoloading and probing in this module but matching the LPSS SSP type. 1354 */ 1355 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { 1356 /* SPT-LP */ 1357 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, 1358 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, 1359 /* SPT-H */ 1360 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, 1361 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, 1362 /* KBL-H */ 1363 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, 1364 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, 1365 /* BXT A-Step */ 1366 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, 1367 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, 1368 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, 1369 /* BXT B-Step */ 1370 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, 1371 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, 1372 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, 1373 /* GLK */ 1374 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, 1375 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, 1376 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, 1377 /* ICL-LP */ 1378 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP }, 1379 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP }, 1380 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP }, 1381 /* APL */ 1382 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, 1383 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, 1384 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, 1385 /* CNL-LP */ 1386 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, 1387 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, 1388 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP }, 1389 /* CNL-H */ 1390 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP }, 1391 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP }, 1392 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP }, 1393 { }, 1394 }; 1395 1396 static const struct of_device_id pxa2xx_spi_of_match[] = { 1397 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP }, 1398 {}, 1399 }; 1400 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match); 1401 1402 #ifdef CONFIG_ACPI 1403 1404 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1405 { 1406 unsigned int devid; 1407 int port_id = -1; 1408 1409 if (adev && adev->pnp.unique_id && 1410 !kstrtouint(adev->pnp.unique_id, 0, &devid)) 1411 port_id = devid; 1412 return port_id; 1413 } 1414 1415 #else /* !CONFIG_ACPI */ 1416 1417 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1418 { 1419 return -1; 1420 } 1421 1422 #endif /* CONFIG_ACPI */ 1423 1424 1425 #ifdef CONFIG_PCI 1426 1427 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) 1428 { 1429 struct device *dev = param; 1430 1431 if (dev != chan->device->dev->parent) 1432 return false; 1433 1434 return true; 1435 } 1436 1437 #endif /* CONFIG_PCI */ 1438 1439 static struct pxa2xx_spi_master * 1440 pxa2xx_spi_init_pdata(struct platform_device *pdev) 1441 { 1442 struct pxa2xx_spi_master *pdata; 1443 struct acpi_device *adev; 1444 struct ssp_device *ssp; 1445 struct resource *res; 1446 const struct acpi_device_id *adev_id = NULL; 1447 const struct pci_device_id *pcidev_id = NULL; 1448 const struct of_device_id *of_id = NULL; 1449 enum pxa_ssp_type type; 1450 1451 adev = ACPI_COMPANION(&pdev->dev); 1452 1453 if (pdev->dev.of_node) 1454 of_id = of_match_device(pdev->dev.driver->of_match_table, 1455 &pdev->dev); 1456 else if (dev_is_pci(pdev->dev.parent)) 1457 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, 1458 to_pci_dev(pdev->dev.parent)); 1459 else if (adev) 1460 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 1461 &pdev->dev); 1462 else 1463 return NULL; 1464 1465 if (adev_id) 1466 type = (enum pxa_ssp_type)adev_id->driver_data; 1467 else if (pcidev_id) 1468 type = (enum pxa_ssp_type)pcidev_id->driver_data; 1469 else if (of_id) 1470 type = (enum pxa_ssp_type)of_id->data; 1471 else 1472 return NULL; 1473 1474 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1475 if (!pdata) 1476 return NULL; 1477 1478 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1479 if (!res) 1480 return NULL; 1481 1482 ssp = &pdata->ssp; 1483 1484 ssp->phys_base = res->start; 1485 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1486 if (IS_ERR(ssp->mmio_base)) 1487 return NULL; 1488 1489 #ifdef CONFIG_PCI 1490 if (pcidev_id) { 1491 pdata->tx_param = pdev->dev.parent; 1492 pdata->rx_param = pdev->dev.parent; 1493 pdata->dma_filter = pxa2xx_spi_idma_filter; 1494 } 1495 #endif 1496 1497 ssp->clk = devm_clk_get(&pdev->dev, NULL); 1498 ssp->irq = platform_get_irq(pdev, 0); 1499 ssp->type = type; 1500 ssp->pdev = pdev; 1501 ssp->port_id = pxa2xx_spi_get_port_id(adev); 1502 1503 pdata->num_chipselect = 1; 1504 pdata->enable_dma = true; 1505 1506 return pdata; 1507 } 1508 1509 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *master, 1510 unsigned int cs) 1511 { 1512 struct driver_data *drv_data = spi_controller_get_devdata(master); 1513 1514 if (has_acpi_companion(&drv_data->pdev->dev)) { 1515 switch (drv_data->ssp_type) { 1516 /* 1517 * For Atoms the ACPI DeviceSelection used by the Windows 1518 * driver starts from 1 instead of 0 so translate it here 1519 * to match what Linux expects. 1520 */ 1521 case LPSS_BYT_SSP: 1522 case LPSS_BSW_SSP: 1523 return cs - 1; 1524 1525 default: 1526 break; 1527 } 1528 } 1529 1530 return cs; 1531 } 1532 1533 static int pxa2xx_spi_probe(struct platform_device *pdev) 1534 { 1535 struct device *dev = &pdev->dev; 1536 struct pxa2xx_spi_master *platform_info; 1537 struct spi_controller *master; 1538 struct driver_data *drv_data; 1539 struct ssp_device *ssp; 1540 const struct lpss_config *config; 1541 int status, count; 1542 u32 tmp; 1543 1544 platform_info = dev_get_platdata(dev); 1545 if (!platform_info) { 1546 platform_info = pxa2xx_spi_init_pdata(pdev); 1547 if (!platform_info) { 1548 dev_err(&pdev->dev, "missing platform data\n"); 1549 return -ENODEV; 1550 } 1551 } 1552 1553 ssp = pxa_ssp_request(pdev->id, pdev->name); 1554 if (!ssp) 1555 ssp = &platform_info->ssp; 1556 1557 if (!ssp->mmio_base) { 1558 dev_err(&pdev->dev, "failed to get ssp\n"); 1559 return -ENODEV; 1560 } 1561 1562 master = spi_alloc_master(dev, sizeof(struct driver_data)); 1563 if (!master) { 1564 dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1565 pxa_ssp_free(ssp); 1566 return -ENOMEM; 1567 } 1568 drv_data = spi_controller_get_devdata(master); 1569 drv_data->master = master; 1570 drv_data->master_info = platform_info; 1571 drv_data->pdev = pdev; 1572 drv_data->ssp = ssp; 1573 1574 master->dev.of_node = pdev->dev.of_node; 1575 /* the spi->mode bits understood by this driver: */ 1576 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1577 1578 master->bus_num = ssp->port_id; 1579 master->dma_alignment = DMA_ALIGNMENT; 1580 master->cleanup = cleanup; 1581 master->setup = setup; 1582 master->set_cs = pxa2xx_spi_set_cs; 1583 master->transfer_one = pxa2xx_spi_transfer_one; 1584 master->handle_err = pxa2xx_spi_handle_err; 1585 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1586 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs; 1587 master->auto_runtime_pm = true; 1588 master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; 1589 1590 drv_data->ssp_type = ssp->type; 1591 1592 drv_data->ioaddr = ssp->mmio_base; 1593 drv_data->ssdr_physical = ssp->phys_base + SSDR; 1594 if (pxa25x_ssp_comp(drv_data)) { 1595 switch (drv_data->ssp_type) { 1596 case QUARK_X1000_SSP: 1597 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1598 break; 1599 default: 1600 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1601 break; 1602 } 1603 1604 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1605 drv_data->dma_cr1 = 0; 1606 drv_data->clear_sr = SSSR_ROR; 1607 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1608 } else { 1609 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1610 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1611 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1612 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1613 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1614 } 1615 1616 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1617 drv_data); 1618 if (status < 0) { 1619 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1620 goto out_error_master_alloc; 1621 } 1622 1623 /* Setup DMA if requested */ 1624 if (platform_info->enable_dma) { 1625 status = pxa2xx_spi_dma_setup(drv_data); 1626 if (status) { 1627 dev_dbg(dev, "no DMA channels available, using PIO\n"); 1628 platform_info->enable_dma = false; 1629 } else { 1630 master->can_dma = pxa2xx_spi_can_dma; 1631 } 1632 } 1633 1634 /* Enable SOC clock */ 1635 status = clk_prepare_enable(ssp->clk); 1636 if (status) 1637 goto out_error_dma_irq_alloc; 1638 1639 master->max_speed_hz = clk_get_rate(ssp->clk); 1640 1641 /* Load default SSP configuration */ 1642 pxa2xx_spi_write(drv_data, SSCR0, 0); 1643 switch (drv_data->ssp_type) { 1644 case QUARK_X1000_SSP: 1645 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | 1646 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1647 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1648 1649 /* using the Motorola SPI protocol and use 8 bit frame */ 1650 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); 1651 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1652 break; 1653 case CE4100_SSP: 1654 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | 1655 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); 1656 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1657 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1658 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1659 break; 1660 default: 1661 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1662 SSCR1_TxTresh(TX_THRESH_DFLT); 1663 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1664 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1665 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1666 break; 1667 } 1668 1669 if (!pxa25x_ssp_comp(drv_data)) 1670 pxa2xx_spi_write(drv_data, SSTO, 0); 1671 1672 if (!is_quark_x1000_ssp(drv_data)) 1673 pxa2xx_spi_write(drv_data, SSPSP, 0); 1674 1675 if (is_lpss_ssp(drv_data)) { 1676 lpss_ssp_setup(drv_data); 1677 config = lpss_get_config(drv_data); 1678 if (config->reg_capabilities >= 0) { 1679 tmp = __lpss_ssp_read_priv(drv_data, 1680 config->reg_capabilities); 1681 tmp &= LPSS_CAPS_CS_EN_MASK; 1682 tmp >>= LPSS_CAPS_CS_EN_SHIFT; 1683 platform_info->num_chipselect = ffz(tmp); 1684 } else if (config->cs_num) { 1685 platform_info->num_chipselect = config->cs_num; 1686 } 1687 } 1688 master->num_chipselect = platform_info->num_chipselect; 1689 1690 count = gpiod_count(&pdev->dev, "cs"); 1691 if (count > 0) { 1692 int i; 1693 1694 master->num_chipselect = max_t(int, count, 1695 master->num_chipselect); 1696 1697 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev, 1698 master->num_chipselect, sizeof(struct gpio_desc *), 1699 GFP_KERNEL); 1700 if (!drv_data->cs_gpiods) { 1701 status = -ENOMEM; 1702 goto out_error_clock_enabled; 1703 } 1704 1705 for (i = 0; i < master->num_chipselect; i++) { 1706 struct gpio_desc *gpiod; 1707 1708 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS); 1709 if (IS_ERR(gpiod)) { 1710 /* Means use native chip select */ 1711 if (PTR_ERR(gpiod) == -ENOENT) 1712 continue; 1713 1714 status = (int)PTR_ERR(gpiod); 1715 goto out_error_clock_enabled; 1716 } else { 1717 drv_data->cs_gpiods[i] = gpiod; 1718 } 1719 } 1720 } 1721 1722 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1723 pm_runtime_use_autosuspend(&pdev->dev); 1724 pm_runtime_set_active(&pdev->dev); 1725 pm_runtime_enable(&pdev->dev); 1726 1727 /* Register with the SPI framework */ 1728 platform_set_drvdata(pdev, drv_data); 1729 status = devm_spi_register_controller(&pdev->dev, master); 1730 if (status != 0) { 1731 dev_err(&pdev->dev, "problem registering spi master\n"); 1732 goto out_error_clock_enabled; 1733 } 1734 1735 return status; 1736 1737 out_error_clock_enabled: 1738 pm_runtime_put_noidle(&pdev->dev); 1739 pm_runtime_disable(&pdev->dev); 1740 clk_disable_unprepare(ssp->clk); 1741 1742 out_error_dma_irq_alloc: 1743 pxa2xx_spi_dma_release(drv_data); 1744 free_irq(ssp->irq, drv_data); 1745 1746 out_error_master_alloc: 1747 spi_controller_put(master); 1748 pxa_ssp_free(ssp); 1749 return status; 1750 } 1751 1752 static int pxa2xx_spi_remove(struct platform_device *pdev) 1753 { 1754 struct driver_data *drv_data = platform_get_drvdata(pdev); 1755 struct ssp_device *ssp; 1756 1757 if (!drv_data) 1758 return 0; 1759 ssp = drv_data->ssp; 1760 1761 pm_runtime_get_sync(&pdev->dev); 1762 1763 /* Disable the SSP at the peripheral and SOC level */ 1764 pxa2xx_spi_write(drv_data, SSCR0, 0); 1765 clk_disable_unprepare(ssp->clk); 1766 1767 /* Release DMA */ 1768 if (drv_data->master_info->enable_dma) 1769 pxa2xx_spi_dma_release(drv_data); 1770 1771 pm_runtime_put_noidle(&pdev->dev); 1772 pm_runtime_disable(&pdev->dev); 1773 1774 /* Release IRQ */ 1775 free_irq(ssp->irq, drv_data); 1776 1777 /* Release SSP */ 1778 pxa_ssp_free(ssp); 1779 1780 return 0; 1781 } 1782 1783 #ifdef CONFIG_PM_SLEEP 1784 static int pxa2xx_spi_suspend(struct device *dev) 1785 { 1786 struct driver_data *drv_data = dev_get_drvdata(dev); 1787 struct ssp_device *ssp = drv_data->ssp; 1788 int status; 1789 1790 status = spi_controller_suspend(drv_data->master); 1791 if (status != 0) 1792 return status; 1793 pxa2xx_spi_write(drv_data, SSCR0, 0); 1794 1795 if (!pm_runtime_suspended(dev)) 1796 clk_disable_unprepare(ssp->clk); 1797 1798 return 0; 1799 } 1800 1801 static int pxa2xx_spi_resume(struct device *dev) 1802 { 1803 struct driver_data *drv_data = dev_get_drvdata(dev); 1804 struct ssp_device *ssp = drv_data->ssp; 1805 int status; 1806 1807 /* Enable the SSP clock */ 1808 if (!pm_runtime_suspended(dev)) { 1809 status = clk_prepare_enable(ssp->clk); 1810 if (status) 1811 return status; 1812 } 1813 1814 /* Restore LPSS private register bits */ 1815 if (is_lpss_ssp(drv_data)) 1816 lpss_ssp_setup(drv_data); 1817 1818 /* Start the queue running */ 1819 return spi_controller_resume(drv_data->master); 1820 } 1821 #endif 1822 1823 #ifdef CONFIG_PM 1824 static int pxa2xx_spi_runtime_suspend(struct device *dev) 1825 { 1826 struct driver_data *drv_data = dev_get_drvdata(dev); 1827 1828 clk_disable_unprepare(drv_data->ssp->clk); 1829 return 0; 1830 } 1831 1832 static int pxa2xx_spi_runtime_resume(struct device *dev) 1833 { 1834 struct driver_data *drv_data = dev_get_drvdata(dev); 1835 int status; 1836 1837 status = clk_prepare_enable(drv_data->ssp->clk); 1838 return status; 1839 } 1840 #endif 1841 1842 static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1843 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1844 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 1845 pxa2xx_spi_runtime_resume, NULL) 1846 }; 1847 1848 static struct platform_driver driver = { 1849 .driver = { 1850 .name = "pxa2xx-spi", 1851 .pm = &pxa2xx_spi_pm_ops, 1852 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1853 .of_match_table = of_match_ptr(pxa2xx_spi_of_match), 1854 }, 1855 .probe = pxa2xx_spi_probe, 1856 .remove = pxa2xx_spi_remove, 1857 }; 1858 1859 static int __init pxa2xx_spi_init(void) 1860 { 1861 return platform_driver_register(&driver); 1862 } 1863 subsys_initcall(pxa2xx_spi_init); 1864 1865 static void __exit pxa2xx_spi_exit(void) 1866 { 1867 platform_driver_unregister(&driver); 1868 } 1869 module_exit(pxa2xx_spi_exit); 1870