1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SPI_PPC4XX SPI controller driver. 4 * 5 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de> 6 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 7 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com> 8 * 9 * Based in part on drivers/spi/spi_s3c24xx.c 10 * 11 * Copyright (c) 2006 Ben Dooks 12 * Copyright (c) 2006 Simtec Electronics 13 * Ben Dooks <ben@simtec.co.uk> 14 */ 15 16 /* 17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will 18 * generate an interrupt to the CPU. This can cause high CPU utilization. 19 * This driver allows platforms to reduce the interrupt load on the CPU 20 * during SPI transfers by setting max_speed_hz via the device tree. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/sched.h> 25 #include <linux/slab.h> 26 #include <linux/errno.h> 27 #include <linux/wait.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/interrupt.h> 31 #include <linux/delay.h> 32 33 #include <linux/spi/spi.h> 34 #include <linux/spi/spi_bitbang.h> 35 36 #include <linux/io.h> 37 #include <asm/dcr.h> 38 #include <asm/dcr-regs.h> 39 40 /* bits in mode register - bit 0 is MSb */ 41 42 /* 43 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock" 44 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock" 45 * Note: This is the inverse of CPHA. 46 */ 47 #define SPI_PPC4XX_MODE_SCP (0x80 >> 3) 48 49 /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */ 50 #define SPI_PPC4XX_MODE_SPE (0x80 >> 4) 51 52 /* 53 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode 54 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode 55 * Note: This is identical to SPI_LSB_FIRST. 56 */ 57 #define SPI_PPC4XX_MODE_RD (0x80 >> 5) 58 59 /* 60 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low" 61 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high" 62 * Note: This is identical to CPOL. 63 */ 64 #define SPI_PPC4XX_MODE_CI (0x80 >> 6) 65 66 /* 67 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable" 68 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable" 69 */ 70 #define SPI_PPC4XX_MODE_IL (0x80 >> 7) 71 72 /* bits in control register */ 73 /* starts a transfer when set */ 74 #define SPI_PPC4XX_CR_STR (0x80 >> 7) 75 76 /* bits in status register */ 77 /* port is busy with a transfer */ 78 #define SPI_PPC4XX_SR_BSY (0x80 >> 6) 79 /* RxD ready */ 80 #define SPI_PPC4XX_SR_RBR (0x80 >> 7) 81 82 /* clock settings (SCP and CI) for various SPI modes */ 83 #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0) 84 #define SPI_CLK_MODE1 (0 | 0) 85 #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI) 86 #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI) 87 88 #define DRIVER_NAME "spi_ppc4xx_of" 89 90 struct spi_ppc4xx_regs { 91 u8 mode; 92 u8 rxd; 93 u8 txd; 94 u8 cr; 95 u8 sr; 96 u8 dummy; 97 /* 98 * Clock divisor modulus register 99 * This uses the following formula: 100 * SCPClkOut = OPBCLK/(4(CDM + 1)) 101 * or 102 * CDM = (OPBCLK/4*SCPClkOut) - 1 103 * bit 0 is the MSb! 104 */ 105 u8 cdm; 106 }; 107 108 /* SPI Controller driver's private data. */ 109 struct ppc4xx_spi { 110 /* bitbang has to be first */ 111 struct spi_bitbang bitbang; 112 struct completion done; 113 114 u64 mapbase; 115 u64 mapsize; 116 int irqnum; 117 /* need this to set the SPI clock */ 118 unsigned int opb_freq; 119 120 /* for transfers */ 121 int len; 122 int count; 123 /* data buffers */ 124 const unsigned char *tx; 125 unsigned char *rx; 126 127 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */ 128 struct spi_controller *host; 129 struct device *dev; 130 }; 131 132 /* need this so we can set the clock in the chipselect routine */ 133 struct spi_ppc4xx_cs { 134 u8 mode; 135 }; 136 137 static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t) 138 { 139 struct ppc4xx_spi *hw; 140 u8 data; 141 142 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 143 t->tx_buf, t->rx_buf, t->len); 144 145 hw = spi_controller_get_devdata(spi->controller); 146 147 hw->tx = t->tx_buf; 148 hw->rx = t->rx_buf; 149 hw->len = t->len; 150 hw->count = 0; 151 152 /* send the first byte */ 153 data = hw->tx ? hw->tx[0] : 0; 154 out_8(&hw->regs->txd, data); 155 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); 156 wait_for_completion(&hw->done); 157 158 return hw->count; 159 } 160 161 static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t) 162 { 163 struct ppc4xx_spi *hw = spi_controller_get_devdata(spi->controller); 164 struct spi_ppc4xx_cs *cs = spi->controller_state; 165 int scr; 166 u8 cdm = 0; 167 u32 speed; 168 169 /* Start with the generic configuration for this device. */ 170 speed = spi->max_speed_hz; 171 172 /* 173 * Modify the configuration if the transfer overrides it. Do not allow 174 * the transfer to overwrite the generic configuration with zeros. 175 */ 176 if (t) { 177 if (t->speed_hz) 178 speed = min(t->speed_hz, spi->max_speed_hz); 179 } 180 181 if (!speed || (speed > spi->max_speed_hz)) { 182 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed); 183 return -EINVAL; 184 } 185 186 /* Write new configuration */ 187 out_8(&hw->regs->mode, cs->mode); 188 189 /* Set the clock */ 190 /* opb_freq was already divided by 4 */ 191 scr = (hw->opb_freq / speed) - 1; 192 if (scr > 0) 193 cdm = min(scr, 0xff); 194 195 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed); 196 197 if (in_8(&hw->regs->cdm) != cdm) 198 out_8(&hw->regs->cdm, cdm); 199 200 mutex_lock(&hw->bitbang.lock); 201 if (!hw->bitbang.busy) { 202 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); 203 /* Need to ndelay here? */ 204 } 205 mutex_unlock(&hw->bitbang.lock); 206 207 return 0; 208 } 209 210 static int spi_ppc4xx_setup(struct spi_device *spi) 211 { 212 struct spi_ppc4xx_cs *cs = spi->controller_state; 213 214 if (!spi->max_speed_hz) { 215 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n"); 216 return -EINVAL; 217 } 218 219 if (cs == NULL) { 220 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 221 if (!cs) 222 return -ENOMEM; 223 spi->controller_state = cs; 224 } 225 226 /* 227 * We set all bits of the SPI0_MODE register, so, 228 * no need to read-modify-write 229 */ 230 cs->mode = SPI_PPC4XX_MODE_SPE; 231 232 switch (spi->mode & SPI_MODE_X_MASK) { 233 case SPI_MODE_0: 234 cs->mode |= SPI_CLK_MODE0; 235 break; 236 case SPI_MODE_1: 237 cs->mode |= SPI_CLK_MODE1; 238 break; 239 case SPI_MODE_2: 240 cs->mode |= SPI_CLK_MODE2; 241 break; 242 case SPI_MODE_3: 243 cs->mode |= SPI_CLK_MODE3; 244 break; 245 } 246 247 if (spi->mode & SPI_LSB_FIRST) 248 cs->mode |= SPI_PPC4XX_MODE_RD; 249 250 return 0; 251 } 252 253 static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id) 254 { 255 struct ppc4xx_spi *hw; 256 u8 status; 257 u8 data; 258 unsigned int count; 259 260 hw = (struct ppc4xx_spi *)dev_id; 261 262 status = in_8(&hw->regs->sr); 263 if (!status) 264 return IRQ_NONE; 265 266 /* 267 * BSY de-asserts one cycle after the transfer is complete. The 268 * interrupt is asserted after the transfer is complete. The exact 269 * relationship is not documented, hence this code. 270 */ 271 272 if (unlikely(status & SPI_PPC4XX_SR_BSY)) { 273 u8 lstatus; 274 int cnt = 0; 275 276 dev_dbg(hw->dev, "got interrupt but spi still busy?\n"); 277 do { 278 ndelay(10); 279 lstatus = in_8(&hw->regs->sr); 280 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY); 281 282 if (cnt >= 100) { 283 dev_err(hw->dev, "busywait: too many loops!\n"); 284 complete(&hw->done); 285 return IRQ_HANDLED; 286 } else { 287 /* status is always 1 (RBR) here */ 288 status = in_8(&hw->regs->sr); 289 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status); 290 } 291 } 292 293 count = hw->count; 294 hw->count++; 295 296 /* RBR triggered this interrupt. Therefore, data must be ready. */ 297 data = in_8(&hw->regs->rxd); 298 if (hw->rx) 299 hw->rx[count] = data; 300 301 count++; 302 303 if (count < hw->len) { 304 data = hw->tx ? hw->tx[count] : 0; 305 out_8(&hw->regs->txd, data); 306 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); 307 } else { 308 complete(&hw->done); 309 } 310 311 return IRQ_HANDLED; 312 } 313 314 static void spi_ppc4xx_cleanup(struct spi_device *spi) 315 { 316 kfree(spi->controller_state); 317 } 318 319 static void spi_ppc4xx_enable(struct ppc4xx_spi *hw) 320 { 321 /* 322 * On all 4xx PPC's the SPI bus is shared/multiplexed with 323 * the 2nd I2C bus. We need to enable the SPI bus before 324 * using it. 325 */ 326 327 /* need to clear bit 14 to enable SPC */ 328 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0); 329 } 330 331 /* 332 * platform_device layer stuff... 333 */ 334 static int spi_ppc4xx_of_probe(struct platform_device *op) 335 { 336 struct ppc4xx_spi *hw; 337 struct spi_controller *host; 338 struct spi_bitbang *bbp; 339 struct resource resource; 340 struct device_node *np = op->dev.of_node; 341 struct device *dev = &op->dev; 342 struct device_node *opbnp; 343 int ret; 344 const unsigned int *clk; 345 346 host = spi_alloc_host(dev, sizeof(*hw)); 347 if (host == NULL) 348 return -ENOMEM; 349 host->dev.of_node = np; 350 platform_set_drvdata(op, host); 351 hw = spi_controller_get_devdata(host); 352 hw->host = host; 353 hw->dev = dev; 354 355 init_completion(&hw->done); 356 357 /* Setup the state for the bitbang driver */ 358 bbp = &hw->bitbang; 359 bbp->master = hw->host; 360 bbp->setup_transfer = spi_ppc4xx_setupxfer; 361 bbp->txrx_bufs = spi_ppc4xx_txrx; 362 bbp->use_dma = 0; 363 bbp->master->setup = spi_ppc4xx_setup; 364 bbp->master->cleanup = spi_ppc4xx_cleanup; 365 bbp->master->bits_per_word_mask = SPI_BPW_MASK(8); 366 bbp->master->use_gpio_descriptors = true; 367 /* 368 * The SPI core will count the number of GPIO descriptors to figure 369 * out the number of chip selects available on the platform. 370 */ 371 bbp->master->num_chipselect = 0; 372 373 /* the spi->mode bits understood by this driver: */ 374 bbp->master->mode_bits = 375 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST; 376 377 /* Get the clock for the OPB */ 378 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb"); 379 if (opbnp == NULL) { 380 dev_err(dev, "OPB: cannot find node\n"); 381 ret = -ENODEV; 382 goto free_host; 383 } 384 /* Get the clock (Hz) for the OPB */ 385 clk = of_get_property(opbnp, "clock-frequency", NULL); 386 if (clk == NULL) { 387 dev_err(dev, "OPB: no clock-frequency property set\n"); 388 of_node_put(opbnp); 389 ret = -ENODEV; 390 goto free_host; 391 } 392 hw->opb_freq = *clk; 393 hw->opb_freq >>= 2; 394 of_node_put(opbnp); 395 396 ret = of_address_to_resource(np, 0, &resource); 397 if (ret) { 398 dev_err(dev, "error while parsing device node resource\n"); 399 goto free_host; 400 } 401 hw->mapbase = resource.start; 402 hw->mapsize = resource_size(&resource); 403 404 /* Sanity check */ 405 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) { 406 dev_err(dev, "too small to map registers\n"); 407 ret = -EINVAL; 408 goto free_host; 409 } 410 411 /* Request IRQ */ 412 ret = platform_get_irq(op, 0); 413 if (ret < 0) 414 goto free_host; 415 hw->irqnum = ret; 416 417 ret = request_irq(hw->irqnum, spi_ppc4xx_int, 418 0, "spi_ppc4xx_of", (void *)hw); 419 if (ret) { 420 dev_err(dev, "unable to allocate interrupt\n"); 421 goto free_host; 422 } 423 424 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) { 425 dev_err(dev, "resource unavailable\n"); 426 ret = -EBUSY; 427 goto request_mem_error; 428 } 429 430 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs)); 431 432 if (!hw->regs) { 433 dev_err(dev, "unable to memory map registers\n"); 434 ret = -ENXIO; 435 goto map_io_error; 436 } 437 438 spi_ppc4xx_enable(hw); 439 440 /* Finally register our spi controller */ 441 dev->dma_mask = 0; 442 ret = spi_bitbang_start(bbp); 443 if (ret) { 444 dev_err(dev, "failed to register SPI host\n"); 445 goto unmap_regs; 446 } 447 448 dev_info(dev, "driver initialized\n"); 449 450 return 0; 451 452 unmap_regs: 453 iounmap(hw->regs); 454 map_io_error: 455 release_mem_region(hw->mapbase, hw->mapsize); 456 request_mem_error: 457 free_irq(hw->irqnum, hw); 458 free_host: 459 spi_controller_put(host); 460 461 dev_err(dev, "initialization failed\n"); 462 return ret; 463 } 464 465 static void spi_ppc4xx_of_remove(struct platform_device *op) 466 { 467 struct spi_controller *host = platform_get_drvdata(op); 468 struct ppc4xx_spi *hw = spi_controller_get_devdata(host); 469 470 spi_bitbang_stop(&hw->bitbang); 471 release_mem_region(hw->mapbase, hw->mapsize); 472 free_irq(hw->irqnum, hw); 473 iounmap(hw->regs); 474 spi_controller_put(host); 475 } 476 477 static const struct of_device_id spi_ppc4xx_of_match[] = { 478 { .compatible = "ibm,ppc4xx-spi", }, 479 {}, 480 }; 481 482 MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match); 483 484 static struct platform_driver spi_ppc4xx_of_driver = { 485 .probe = spi_ppc4xx_of_probe, 486 .remove_new = spi_ppc4xx_of_remove, 487 .driver = { 488 .name = DRIVER_NAME, 489 .of_match_table = spi_ppc4xx_of_match, 490 }, 491 }; 492 module_platform_driver(spi_ppc4xx_of_driver); 493 494 MODULE_AUTHOR("Gary Jennejohn & Stefan Roese"); 495 MODULE_DESCRIPTION("Simple PPC4xx SPI Driver"); 496 MODULE_LICENSE("GPL"); 497