1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2009 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/delay.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/amba/bus.h> 36 #include <linux/amba/pl022.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 #include <linux/dmaengine.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/scatterlist.h> 42 #include <linux/pm_runtime.h> 43 44 /* 45 * This macro is used to define some register default values. 46 * reg is masked with mask, the OR:ed with an (again masked) 47 * val shifted sb steps to the left. 48 */ 49 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 50 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 51 52 /* 53 * This macro is also used to define some default values. 54 * It will just shift val by sb steps to the left and mask 55 * the result with mask. 56 */ 57 #define GEN_MASK_BITS(val, mask, sb) \ 58 (((val)<<(sb)) & (mask)) 59 60 #define DRIVE_TX 0 61 #define DO_NOT_DRIVE_TX 1 62 63 #define DO_NOT_QUEUE_DMA 0 64 #define QUEUE_DMA 1 65 66 #define RX_TRANSFER 1 67 #define TX_TRANSFER 2 68 69 /* 70 * Macros to access SSP Registers with their offsets 71 */ 72 #define SSP_CR0(r) (r + 0x000) 73 #define SSP_CR1(r) (r + 0x004) 74 #define SSP_DR(r) (r + 0x008) 75 #define SSP_SR(r) (r + 0x00C) 76 #define SSP_CPSR(r) (r + 0x010) 77 #define SSP_IMSC(r) (r + 0x014) 78 #define SSP_RIS(r) (r + 0x018) 79 #define SSP_MIS(r) (r + 0x01C) 80 #define SSP_ICR(r) (r + 0x020) 81 #define SSP_DMACR(r) (r + 0x024) 82 #define SSP_ITCR(r) (r + 0x080) 83 #define SSP_ITIP(r) (r + 0x084) 84 #define SSP_ITOP(r) (r + 0x088) 85 #define SSP_TDR(r) (r + 0x08C) 86 87 #define SSP_PID0(r) (r + 0xFE0) 88 #define SSP_PID1(r) (r + 0xFE4) 89 #define SSP_PID2(r) (r + 0xFE8) 90 #define SSP_PID3(r) (r + 0xFEC) 91 92 #define SSP_CID0(r) (r + 0xFF0) 93 #define SSP_CID1(r) (r + 0xFF4) 94 #define SSP_CID2(r) (r + 0xFF8) 95 #define SSP_CID3(r) (r + 0xFFC) 96 97 /* 98 * SSP Control Register 0 - SSP_CR0 99 */ 100 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 101 #define SSP_CR0_MASK_FRF (0x3UL << 4) 102 #define SSP_CR0_MASK_SPO (0x1UL << 6) 103 #define SSP_CR0_MASK_SPH (0x1UL << 7) 104 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 105 106 /* 107 * The ST version of this block moves som bits 108 * in SSP_CR0 and extends it to 32 bits 109 */ 110 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 111 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 112 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 113 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 114 115 /* 116 * SSP Control Register 0 - SSP_CR1 117 */ 118 #define SSP_CR1_MASK_LBM (0x1UL << 0) 119 #define SSP_CR1_MASK_SSE (0x1UL << 1) 120 #define SSP_CR1_MASK_MS (0x1UL << 2) 121 #define SSP_CR1_MASK_SOD (0x1UL << 3) 122 123 /* 124 * The ST version of this block adds some bits 125 * in SSP_CR1 126 */ 127 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 128 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 129 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 130 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 131 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 132 /* This one is only in the PL023 variant */ 133 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 134 135 /* 136 * SSP Status Register - SSP_SR 137 */ 138 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 139 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 140 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 141 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 142 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 143 144 /* 145 * SSP Clock Prescale Register - SSP_CPSR 146 */ 147 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 148 149 /* 150 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 151 */ 152 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 153 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 154 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 155 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 156 157 /* 158 * SSP Raw Interrupt Status Register - SSP_RIS 159 */ 160 /* Receive Overrun Raw Interrupt status */ 161 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 162 /* Receive Timeout Raw Interrupt status */ 163 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 164 /* Receive FIFO Raw Interrupt status */ 165 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 166 /* Transmit FIFO Raw Interrupt status */ 167 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 168 169 /* 170 * SSP Masked Interrupt Status Register - SSP_MIS 171 */ 172 /* Receive Overrun Masked Interrupt status */ 173 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 174 /* Receive Timeout Masked Interrupt status */ 175 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 176 /* Receive FIFO Masked Interrupt status */ 177 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 178 /* Transmit FIFO Masked Interrupt status */ 179 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 180 181 /* 182 * SSP Interrupt Clear Register - SSP_ICR 183 */ 184 /* Receive Overrun Raw Clear Interrupt bit */ 185 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 186 /* Receive Timeout Clear Interrupt bit */ 187 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 188 189 /* 190 * SSP DMA Control Register - SSP_DMACR 191 */ 192 /* Receive DMA Enable bit */ 193 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 194 /* Transmit DMA Enable bit */ 195 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 196 197 /* 198 * SSP Integration Test control Register - SSP_ITCR 199 */ 200 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 201 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 202 203 /* 204 * SSP Integration Test Input Register - SSP_ITIP 205 */ 206 #define ITIP_MASK_SSPRXD (0x1UL << 0) 207 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 208 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 209 #define ITIP_MASK_RXDMAC (0x1UL << 3) 210 #define ITIP_MASK_TXDMAC (0x1UL << 4) 211 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 212 213 /* 214 * SSP Integration Test output Register - SSP_ITOP 215 */ 216 #define ITOP_MASK_SSPTXD (0x1UL << 0) 217 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 218 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 219 #define ITOP_MASK_SSPOEn (0x1UL << 3) 220 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 221 #define ITOP_MASK_RORINTR (0x1UL << 5) 222 #define ITOP_MASK_RTINTR (0x1UL << 6) 223 #define ITOP_MASK_RXINTR (0x1UL << 7) 224 #define ITOP_MASK_TXINTR (0x1UL << 8) 225 #define ITOP_MASK_INTR (0x1UL << 9) 226 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 227 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 228 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 229 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 230 231 /* 232 * SSP Test Data Register - SSP_TDR 233 */ 234 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 235 236 /* 237 * Message State 238 * we use the spi_message.state (void *) pointer to 239 * hold a single state value, that's why all this 240 * (void *) casting is done here. 241 */ 242 #define STATE_START ((void *) 0) 243 #define STATE_RUNNING ((void *) 1) 244 #define STATE_DONE ((void *) 2) 245 #define STATE_ERROR ((void *) -1) 246 247 /* 248 * SSP State - Whether Enabled or Disabled 249 */ 250 #define SSP_DISABLED (0) 251 #define SSP_ENABLED (1) 252 253 /* 254 * SSP DMA State - Whether DMA Enabled or Disabled 255 */ 256 #define SSP_DMA_DISABLED (0) 257 #define SSP_DMA_ENABLED (1) 258 259 /* 260 * SSP Clock Defaults 261 */ 262 #define SSP_DEFAULT_CLKRATE 0x2 263 #define SSP_DEFAULT_PRESCALE 0x40 264 265 /* 266 * SSP Clock Parameter ranges 267 */ 268 #define CPSDVR_MIN 0x02 269 #define CPSDVR_MAX 0xFE 270 #define SCR_MIN 0x00 271 #define SCR_MAX 0xFF 272 273 /* 274 * SSP Interrupt related Macros 275 */ 276 #define DEFAULT_SSP_REG_IMSC 0x0UL 277 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 278 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 279 280 #define CLEAR_ALL_INTERRUPTS 0x3 281 282 #define SPI_POLLING_TIMEOUT 1000 283 284 /* 285 * The type of reading going on on this chip 286 */ 287 enum ssp_reading { 288 READING_NULL, 289 READING_U8, 290 READING_U16, 291 READING_U32 292 }; 293 294 /** 295 * The type of writing going on on this chip 296 */ 297 enum ssp_writing { 298 WRITING_NULL, 299 WRITING_U8, 300 WRITING_U16, 301 WRITING_U32 302 }; 303 304 /** 305 * struct vendor_data - vendor-specific config parameters 306 * for PL022 derivates 307 * @fifodepth: depth of FIFOs (both) 308 * @max_bpw: maximum number of bits per word 309 * @unidir: supports unidirection transfers 310 * @extended_cr: 32 bit wide control register 0 with extra 311 * features and extra features in CR1 as found in the ST variants 312 * @pl023: supports a subset of the ST extensions called "PL023" 313 */ 314 struct vendor_data { 315 int fifodepth; 316 int max_bpw; 317 bool unidir; 318 bool extended_cr; 319 bool pl023; 320 bool loopback; 321 }; 322 323 /** 324 * struct pl022 - This is the private SSP driver data structure 325 * @adev: AMBA device model hookup 326 * @vendor: vendor data for the IP block 327 * @phybase: the physical memory where the SSP device resides 328 * @virtbase: the virtual memory where the SSP is mapped 329 * @clk: outgoing clock "SPICLK" for the SPI bus 330 * @master: SPI framework hookup 331 * @master_info: controller-specific data from machine setup 332 * @kworker: thread struct for message pump 333 * @kworker_task: pointer to task for message pump kworker thread 334 * @pump_messages: work struct for scheduling work to the message pump 335 * @queue_lock: spinlock to syncronise access to message queue 336 * @queue: message queue 337 * @busy: message pump is busy 338 * @running: message pump is running 339 * @pump_transfers: Tasklet used in Interrupt Transfer mode 340 * @cur_msg: Pointer to current spi_message being processed 341 * @cur_transfer: Pointer to current spi_transfer 342 * @cur_chip: pointer to current clients chip(assigned from controller_state) 343 * @next_msg_cs_active: the next message in the queue has been examined 344 * and it was found that it uses the same chip select as the previous 345 * message, so we left it active after the previous transfer, and it's 346 * active already. 347 * @tx: current position in TX buffer to be read 348 * @tx_end: end position in TX buffer to be read 349 * @rx: current position in RX buffer to be written 350 * @rx_end: end position in RX buffer to be written 351 * @read: the type of read currently going on 352 * @write: the type of write currently going on 353 * @exp_fifo_level: expected FIFO level 354 * @dma_rx_channel: optional channel for RX DMA 355 * @dma_tx_channel: optional channel for TX DMA 356 * @sgt_rx: scattertable for the RX transfer 357 * @sgt_tx: scattertable for the TX transfer 358 * @dummypage: a dummy page used for driving data on the bus with DMA 359 */ 360 struct pl022 { 361 struct amba_device *adev; 362 struct vendor_data *vendor; 363 resource_size_t phybase; 364 void __iomem *virtbase; 365 struct clk *clk; 366 struct spi_master *master; 367 struct pl022_ssp_controller *master_info; 368 /* Message per-transfer pump */ 369 struct tasklet_struct pump_transfers; 370 struct spi_message *cur_msg; 371 struct spi_transfer *cur_transfer; 372 struct chip_data *cur_chip; 373 bool next_msg_cs_active; 374 void *tx; 375 void *tx_end; 376 void *rx; 377 void *rx_end; 378 enum ssp_reading read; 379 enum ssp_writing write; 380 u32 exp_fifo_level; 381 enum ssp_rx_level_trig rx_lev_trig; 382 enum ssp_tx_level_trig tx_lev_trig; 383 /* DMA settings */ 384 #ifdef CONFIG_DMA_ENGINE 385 struct dma_chan *dma_rx_channel; 386 struct dma_chan *dma_tx_channel; 387 struct sg_table sgt_rx; 388 struct sg_table sgt_tx; 389 char *dummypage; 390 bool dma_running; 391 #endif 392 }; 393 394 /** 395 * struct chip_data - To maintain runtime state of SSP for each client chip 396 * @cr0: Value of control register CR0 of SSP - on later ST variants this 397 * register is 32 bits wide rather than just 16 398 * @cr1: Value of control register CR1 of SSP 399 * @dmacr: Value of DMA control Register of SSP 400 * @cpsr: Value of Clock prescale register 401 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 402 * @enable_dma: Whether to enable DMA or not 403 * @read: function ptr to be used to read when doing xfer for this chip 404 * @write: function ptr to be used to write when doing xfer for this chip 405 * @cs_control: chip select callback provided by chip 406 * @xfer_type: polling/interrupt/DMA 407 * 408 * Runtime state of the SSP controller, maintained per chip, 409 * This would be set according to the current message that would be served 410 */ 411 struct chip_data { 412 u32 cr0; 413 u16 cr1; 414 u16 dmacr; 415 u16 cpsr; 416 u8 n_bytes; 417 bool enable_dma; 418 enum ssp_reading read; 419 enum ssp_writing write; 420 void (*cs_control) (u32 command); 421 int xfer_type; 422 }; 423 424 /** 425 * null_cs_control - Dummy chip select function 426 * @command: select/delect the chip 427 * 428 * If no chip select function is provided by client this is used as dummy 429 * chip select 430 */ 431 static void null_cs_control(u32 command) 432 { 433 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 434 } 435 436 /** 437 * giveback - current spi_message is over, schedule next message and call 438 * callback of this message. Assumes that caller already 439 * set message->status; dma and pio irqs are blocked 440 * @pl022: SSP driver private data structure 441 */ 442 static void giveback(struct pl022 *pl022) 443 { 444 struct spi_transfer *last_transfer; 445 pl022->next_msg_cs_active = false; 446 447 last_transfer = list_entry(pl022->cur_msg->transfers.prev, 448 struct spi_transfer, 449 transfer_list); 450 451 /* Delay if requested before any change in chip select */ 452 if (last_transfer->delay_usecs) 453 /* 454 * FIXME: This runs in interrupt context. 455 * Is this really smart? 456 */ 457 udelay(last_transfer->delay_usecs); 458 459 if (!last_transfer->cs_change) { 460 struct spi_message *next_msg; 461 462 /* 463 * cs_change was not set. We can keep the chip select 464 * enabled if there is message in the queue and it is 465 * for the same spi device. 466 * 467 * We cannot postpone this until pump_messages, because 468 * after calling msg->complete (below) the driver that 469 * sent the current message could be unloaded, which 470 * could invalidate the cs_control() callback... 471 */ 472 /* get a pointer to the next message, if any */ 473 next_msg = spi_get_next_queued_message(pl022->master); 474 475 /* 476 * see if the next and current messages point 477 * to the same spi device. 478 */ 479 if (next_msg && next_msg->spi != pl022->cur_msg->spi) 480 next_msg = NULL; 481 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 482 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 483 else 484 pl022->next_msg_cs_active = true; 485 486 } 487 488 pl022->cur_msg = NULL; 489 pl022->cur_transfer = NULL; 490 pl022->cur_chip = NULL; 491 spi_finalize_current_message(pl022->master); 492 } 493 494 /** 495 * flush - flush the FIFO to reach a clean state 496 * @pl022: SSP driver private data structure 497 */ 498 static int flush(struct pl022 *pl022) 499 { 500 unsigned long limit = loops_per_jiffy << 1; 501 502 dev_dbg(&pl022->adev->dev, "flush\n"); 503 do { 504 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 505 readw(SSP_DR(pl022->virtbase)); 506 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 507 508 pl022->exp_fifo_level = 0; 509 510 return limit; 511 } 512 513 /** 514 * restore_state - Load configuration of current chip 515 * @pl022: SSP driver private data structure 516 */ 517 static void restore_state(struct pl022 *pl022) 518 { 519 struct chip_data *chip = pl022->cur_chip; 520 521 if (pl022->vendor->extended_cr) 522 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 523 else 524 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 525 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 526 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 527 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 528 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 529 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 530 } 531 532 /* 533 * Default SSP Register Values 534 */ 535 #define DEFAULT_SSP_REG_CR0 ( \ 536 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 537 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 538 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 539 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 540 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 541 ) 542 543 /* ST versions have slightly different bit layout */ 544 #define DEFAULT_SSP_REG_CR0_ST ( \ 545 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 546 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 547 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 548 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 549 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 550 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 551 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 552 ) 553 554 /* The PL023 version is slightly different again */ 555 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 556 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 557 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 558 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 559 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 560 ) 561 562 #define DEFAULT_SSP_REG_CR1 ( \ 563 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 564 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 565 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 566 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 567 ) 568 569 /* ST versions extend this register to use all 16 bits */ 570 #define DEFAULT_SSP_REG_CR1_ST ( \ 571 DEFAULT_SSP_REG_CR1 | \ 572 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 573 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 574 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 575 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 576 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 577 ) 578 579 /* 580 * The PL023 variant has further differences: no loopback mode, no microwire 581 * support, and a new clock feedback delay setting. 582 */ 583 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 584 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 585 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 586 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 587 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 588 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 589 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 590 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 591 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 592 ) 593 594 #define DEFAULT_SSP_REG_CPSR ( \ 595 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 596 ) 597 598 #define DEFAULT_SSP_REG_DMACR (\ 599 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 600 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 601 ) 602 603 /** 604 * load_ssp_default_config - Load default configuration for SSP 605 * @pl022: SSP driver private data structure 606 */ 607 static void load_ssp_default_config(struct pl022 *pl022) 608 { 609 if (pl022->vendor->pl023) { 610 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 611 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 612 } else if (pl022->vendor->extended_cr) { 613 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 614 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 615 } else { 616 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 617 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 618 } 619 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 620 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 621 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 622 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 623 } 624 625 /** 626 * This will write to TX and read from RX according to the parameters 627 * set in pl022. 628 */ 629 static void readwriter(struct pl022 *pl022) 630 { 631 632 /* 633 * The FIFO depth is different between primecell variants. 634 * I believe filling in too much in the FIFO might cause 635 * errons in 8bit wide transfers on ARM variants (just 8 words 636 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 637 * 638 * To prevent this issue, the TX FIFO is only filled to the 639 * unused RX FIFO fill length, regardless of what the TX 640 * FIFO status flag indicates. 641 */ 642 dev_dbg(&pl022->adev->dev, 643 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 644 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 645 646 /* Read as much as you can */ 647 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 648 && (pl022->rx < pl022->rx_end)) { 649 switch (pl022->read) { 650 case READING_NULL: 651 readw(SSP_DR(pl022->virtbase)); 652 break; 653 case READING_U8: 654 *(u8 *) (pl022->rx) = 655 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 656 break; 657 case READING_U16: 658 *(u16 *) (pl022->rx) = 659 (u16) readw(SSP_DR(pl022->virtbase)); 660 break; 661 case READING_U32: 662 *(u32 *) (pl022->rx) = 663 readl(SSP_DR(pl022->virtbase)); 664 break; 665 } 666 pl022->rx += (pl022->cur_chip->n_bytes); 667 pl022->exp_fifo_level--; 668 } 669 /* 670 * Write as much as possible up to the RX FIFO size 671 */ 672 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 673 && (pl022->tx < pl022->tx_end)) { 674 switch (pl022->write) { 675 case WRITING_NULL: 676 writew(0x0, SSP_DR(pl022->virtbase)); 677 break; 678 case WRITING_U8: 679 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 680 break; 681 case WRITING_U16: 682 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 683 break; 684 case WRITING_U32: 685 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 686 break; 687 } 688 pl022->tx += (pl022->cur_chip->n_bytes); 689 pl022->exp_fifo_level++; 690 /* 691 * This inner reader takes care of things appearing in the RX 692 * FIFO as we're transmitting. This will happen a lot since the 693 * clock starts running when you put things into the TX FIFO, 694 * and then things are continuously clocked into the RX FIFO. 695 */ 696 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 697 && (pl022->rx < pl022->rx_end)) { 698 switch (pl022->read) { 699 case READING_NULL: 700 readw(SSP_DR(pl022->virtbase)); 701 break; 702 case READING_U8: 703 *(u8 *) (pl022->rx) = 704 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 705 break; 706 case READING_U16: 707 *(u16 *) (pl022->rx) = 708 (u16) readw(SSP_DR(pl022->virtbase)); 709 break; 710 case READING_U32: 711 *(u32 *) (pl022->rx) = 712 readl(SSP_DR(pl022->virtbase)); 713 break; 714 } 715 pl022->rx += (pl022->cur_chip->n_bytes); 716 pl022->exp_fifo_level--; 717 } 718 } 719 /* 720 * When we exit here the TX FIFO should be full and the RX FIFO 721 * should be empty 722 */ 723 } 724 725 /** 726 * next_transfer - Move to the Next transfer in the current spi message 727 * @pl022: SSP driver private data structure 728 * 729 * This function moves though the linked list of spi transfers in the 730 * current spi message and returns with the state of current spi 731 * message i.e whether its last transfer is done(STATE_DONE) or 732 * Next transfer is ready(STATE_RUNNING) 733 */ 734 static void *next_transfer(struct pl022 *pl022) 735 { 736 struct spi_message *msg = pl022->cur_msg; 737 struct spi_transfer *trans = pl022->cur_transfer; 738 739 /* Move to next transfer */ 740 if (trans->transfer_list.next != &msg->transfers) { 741 pl022->cur_transfer = 742 list_entry(trans->transfer_list.next, 743 struct spi_transfer, transfer_list); 744 return STATE_RUNNING; 745 } 746 return STATE_DONE; 747 } 748 749 /* 750 * This DMA functionality is only compiled in if we have 751 * access to the generic DMA devices/DMA engine. 752 */ 753 #ifdef CONFIG_DMA_ENGINE 754 static void unmap_free_dma_scatter(struct pl022 *pl022) 755 { 756 /* Unmap and free the SG tables */ 757 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 758 pl022->sgt_tx.nents, DMA_TO_DEVICE); 759 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 760 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 761 sg_free_table(&pl022->sgt_rx); 762 sg_free_table(&pl022->sgt_tx); 763 } 764 765 static void dma_callback(void *data) 766 { 767 struct pl022 *pl022 = data; 768 struct spi_message *msg = pl022->cur_msg; 769 770 BUG_ON(!pl022->sgt_rx.sgl); 771 772 #ifdef VERBOSE_DEBUG 773 /* 774 * Optionally dump out buffers to inspect contents, this is 775 * good if you want to convince yourself that the loopback 776 * read/write contents are the same, when adopting to a new 777 * DMA engine. 778 */ 779 { 780 struct scatterlist *sg; 781 unsigned int i; 782 783 dma_sync_sg_for_cpu(&pl022->adev->dev, 784 pl022->sgt_rx.sgl, 785 pl022->sgt_rx.nents, 786 DMA_FROM_DEVICE); 787 788 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 789 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 790 print_hex_dump(KERN_ERR, "SPI RX: ", 791 DUMP_PREFIX_OFFSET, 792 16, 793 1, 794 sg_virt(sg), 795 sg_dma_len(sg), 796 1); 797 } 798 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 799 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 800 print_hex_dump(KERN_ERR, "SPI TX: ", 801 DUMP_PREFIX_OFFSET, 802 16, 803 1, 804 sg_virt(sg), 805 sg_dma_len(sg), 806 1); 807 } 808 } 809 #endif 810 811 unmap_free_dma_scatter(pl022); 812 813 /* Update total bytes transferred */ 814 msg->actual_length += pl022->cur_transfer->len; 815 if (pl022->cur_transfer->cs_change) 816 pl022->cur_chip-> 817 cs_control(SSP_CHIP_DESELECT); 818 819 /* Move to next transfer */ 820 msg->state = next_transfer(pl022); 821 tasklet_schedule(&pl022->pump_transfers); 822 } 823 824 static void setup_dma_scatter(struct pl022 *pl022, 825 void *buffer, 826 unsigned int length, 827 struct sg_table *sgtab) 828 { 829 struct scatterlist *sg; 830 int bytesleft = length; 831 void *bufp = buffer; 832 int mapbytes; 833 int i; 834 835 if (buffer) { 836 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 837 /* 838 * If there are less bytes left than what fits 839 * in the current page (plus page alignment offset) 840 * we just feed in this, else we stuff in as much 841 * as we can. 842 */ 843 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 844 mapbytes = bytesleft; 845 else 846 mapbytes = PAGE_SIZE - offset_in_page(bufp); 847 sg_set_page(sg, virt_to_page(bufp), 848 mapbytes, offset_in_page(bufp)); 849 bufp += mapbytes; 850 bytesleft -= mapbytes; 851 dev_dbg(&pl022->adev->dev, 852 "set RX/TX target page @ %p, %d bytes, %d left\n", 853 bufp, mapbytes, bytesleft); 854 } 855 } else { 856 /* Map the dummy buffer on every page */ 857 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 858 if (bytesleft < PAGE_SIZE) 859 mapbytes = bytesleft; 860 else 861 mapbytes = PAGE_SIZE; 862 sg_set_page(sg, virt_to_page(pl022->dummypage), 863 mapbytes, 0); 864 bytesleft -= mapbytes; 865 dev_dbg(&pl022->adev->dev, 866 "set RX/TX to dummy page %d bytes, %d left\n", 867 mapbytes, bytesleft); 868 869 } 870 } 871 BUG_ON(bytesleft); 872 } 873 874 /** 875 * configure_dma - configures the channels for the next transfer 876 * @pl022: SSP driver's private data structure 877 */ 878 static int configure_dma(struct pl022 *pl022) 879 { 880 struct dma_slave_config rx_conf = { 881 .src_addr = SSP_DR(pl022->phybase), 882 .direction = DMA_DEV_TO_MEM, 883 }; 884 struct dma_slave_config tx_conf = { 885 .dst_addr = SSP_DR(pl022->phybase), 886 .direction = DMA_MEM_TO_DEV, 887 }; 888 unsigned int pages; 889 int ret; 890 int rx_sglen, tx_sglen; 891 struct dma_chan *rxchan = pl022->dma_rx_channel; 892 struct dma_chan *txchan = pl022->dma_tx_channel; 893 struct dma_async_tx_descriptor *rxdesc; 894 struct dma_async_tx_descriptor *txdesc; 895 896 /* Check that the channels are available */ 897 if (!rxchan || !txchan) 898 return -ENODEV; 899 900 /* 901 * If supplied, the DMA burstsize should equal the FIFO trigger level. 902 * Notice that the DMA engine uses one-to-one mapping. Since we can 903 * not trigger on 2 elements this needs explicit mapping rather than 904 * calculation. 905 */ 906 switch (pl022->rx_lev_trig) { 907 case SSP_RX_1_OR_MORE_ELEM: 908 rx_conf.src_maxburst = 1; 909 break; 910 case SSP_RX_4_OR_MORE_ELEM: 911 rx_conf.src_maxburst = 4; 912 break; 913 case SSP_RX_8_OR_MORE_ELEM: 914 rx_conf.src_maxburst = 8; 915 break; 916 case SSP_RX_16_OR_MORE_ELEM: 917 rx_conf.src_maxburst = 16; 918 break; 919 case SSP_RX_32_OR_MORE_ELEM: 920 rx_conf.src_maxburst = 32; 921 break; 922 default: 923 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 924 break; 925 } 926 927 switch (pl022->tx_lev_trig) { 928 case SSP_TX_1_OR_MORE_EMPTY_LOC: 929 tx_conf.dst_maxburst = 1; 930 break; 931 case SSP_TX_4_OR_MORE_EMPTY_LOC: 932 tx_conf.dst_maxburst = 4; 933 break; 934 case SSP_TX_8_OR_MORE_EMPTY_LOC: 935 tx_conf.dst_maxburst = 8; 936 break; 937 case SSP_TX_16_OR_MORE_EMPTY_LOC: 938 tx_conf.dst_maxburst = 16; 939 break; 940 case SSP_TX_32_OR_MORE_EMPTY_LOC: 941 tx_conf.dst_maxburst = 32; 942 break; 943 default: 944 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 945 break; 946 } 947 948 switch (pl022->read) { 949 case READING_NULL: 950 /* Use the same as for writing */ 951 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 952 break; 953 case READING_U8: 954 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 955 break; 956 case READING_U16: 957 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 958 break; 959 case READING_U32: 960 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 961 break; 962 } 963 964 switch (pl022->write) { 965 case WRITING_NULL: 966 /* Use the same as for reading */ 967 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 968 break; 969 case WRITING_U8: 970 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 971 break; 972 case WRITING_U16: 973 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 974 break; 975 case WRITING_U32: 976 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 977 break; 978 } 979 980 /* SPI pecularity: we need to read and write the same width */ 981 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 982 rx_conf.src_addr_width = tx_conf.dst_addr_width; 983 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 984 tx_conf.dst_addr_width = rx_conf.src_addr_width; 985 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 986 987 dmaengine_slave_config(rxchan, &rx_conf); 988 dmaengine_slave_config(txchan, &tx_conf); 989 990 /* Create sglists for the transfers */ 991 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 992 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 993 994 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 995 if (ret) 996 goto err_alloc_rx_sg; 997 998 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 999 if (ret) 1000 goto err_alloc_tx_sg; 1001 1002 /* Fill in the scatterlists for the RX+TX buffers */ 1003 setup_dma_scatter(pl022, pl022->rx, 1004 pl022->cur_transfer->len, &pl022->sgt_rx); 1005 setup_dma_scatter(pl022, pl022->tx, 1006 pl022->cur_transfer->len, &pl022->sgt_tx); 1007 1008 /* Map DMA buffers */ 1009 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1010 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1011 if (!rx_sglen) 1012 goto err_rx_sgmap; 1013 1014 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1015 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1016 if (!tx_sglen) 1017 goto err_tx_sgmap; 1018 1019 /* Send both scatterlists */ 1020 rxdesc = rxchan->device->device_prep_slave_sg(rxchan, 1021 pl022->sgt_rx.sgl, 1022 rx_sglen, 1023 DMA_DEV_TO_MEM, 1024 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1025 if (!rxdesc) 1026 goto err_rxdesc; 1027 1028 txdesc = txchan->device->device_prep_slave_sg(txchan, 1029 pl022->sgt_tx.sgl, 1030 tx_sglen, 1031 DMA_MEM_TO_DEV, 1032 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1033 if (!txdesc) 1034 goto err_txdesc; 1035 1036 /* Put the callback on the RX transfer only, that should finish last */ 1037 rxdesc->callback = dma_callback; 1038 rxdesc->callback_param = pl022; 1039 1040 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1041 dmaengine_submit(rxdesc); 1042 dmaengine_submit(txdesc); 1043 dma_async_issue_pending(rxchan); 1044 dma_async_issue_pending(txchan); 1045 pl022->dma_running = true; 1046 1047 return 0; 1048 1049 err_txdesc: 1050 dmaengine_terminate_all(txchan); 1051 err_rxdesc: 1052 dmaengine_terminate_all(rxchan); 1053 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1054 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1055 err_tx_sgmap: 1056 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1057 pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1058 err_rx_sgmap: 1059 sg_free_table(&pl022->sgt_tx); 1060 err_alloc_tx_sg: 1061 sg_free_table(&pl022->sgt_rx); 1062 err_alloc_rx_sg: 1063 return -ENOMEM; 1064 } 1065 1066 static int __init pl022_dma_probe(struct pl022 *pl022) 1067 { 1068 dma_cap_mask_t mask; 1069 1070 /* Try to acquire a generic DMA engine slave channel */ 1071 dma_cap_zero(mask); 1072 dma_cap_set(DMA_SLAVE, mask); 1073 /* 1074 * We need both RX and TX channels to do DMA, else do none 1075 * of them. 1076 */ 1077 pl022->dma_rx_channel = dma_request_channel(mask, 1078 pl022->master_info->dma_filter, 1079 pl022->master_info->dma_rx_param); 1080 if (!pl022->dma_rx_channel) { 1081 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1082 goto err_no_rxchan; 1083 } 1084 1085 pl022->dma_tx_channel = dma_request_channel(mask, 1086 pl022->master_info->dma_filter, 1087 pl022->master_info->dma_tx_param); 1088 if (!pl022->dma_tx_channel) { 1089 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1090 goto err_no_txchan; 1091 } 1092 1093 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1094 if (!pl022->dummypage) { 1095 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1096 goto err_no_dummypage; 1097 } 1098 1099 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1100 dma_chan_name(pl022->dma_rx_channel), 1101 dma_chan_name(pl022->dma_tx_channel)); 1102 1103 return 0; 1104 1105 err_no_dummypage: 1106 dma_release_channel(pl022->dma_tx_channel); 1107 err_no_txchan: 1108 dma_release_channel(pl022->dma_rx_channel); 1109 pl022->dma_rx_channel = NULL; 1110 err_no_rxchan: 1111 dev_err(&pl022->adev->dev, 1112 "Failed to work in dma mode, work without dma!\n"); 1113 return -ENODEV; 1114 } 1115 1116 static void terminate_dma(struct pl022 *pl022) 1117 { 1118 struct dma_chan *rxchan = pl022->dma_rx_channel; 1119 struct dma_chan *txchan = pl022->dma_tx_channel; 1120 1121 dmaengine_terminate_all(rxchan); 1122 dmaengine_terminate_all(txchan); 1123 unmap_free_dma_scatter(pl022); 1124 pl022->dma_running = false; 1125 } 1126 1127 static void pl022_dma_remove(struct pl022 *pl022) 1128 { 1129 if (pl022->dma_running) 1130 terminate_dma(pl022); 1131 if (pl022->dma_tx_channel) 1132 dma_release_channel(pl022->dma_tx_channel); 1133 if (pl022->dma_rx_channel) 1134 dma_release_channel(pl022->dma_rx_channel); 1135 kfree(pl022->dummypage); 1136 } 1137 1138 #else 1139 static inline int configure_dma(struct pl022 *pl022) 1140 { 1141 return -ENODEV; 1142 } 1143 1144 static inline int pl022_dma_probe(struct pl022 *pl022) 1145 { 1146 return 0; 1147 } 1148 1149 static inline void pl022_dma_remove(struct pl022 *pl022) 1150 { 1151 } 1152 #endif 1153 1154 /** 1155 * pl022_interrupt_handler - Interrupt handler for SSP controller 1156 * 1157 * This function handles interrupts generated for an interrupt based transfer. 1158 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1159 * current message's state as STATE_ERROR and schedule the tasklet 1160 * pump_transfers which will do the postprocessing of the current message by 1161 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1162 * more data, and writes data in TX FIFO till it is not full. If we complete 1163 * the transfer we move to the next transfer and schedule the tasklet. 1164 */ 1165 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1166 { 1167 struct pl022 *pl022 = dev_id; 1168 struct spi_message *msg = pl022->cur_msg; 1169 u16 irq_status = 0; 1170 u16 flag = 0; 1171 1172 if (unlikely(!msg)) { 1173 dev_err(&pl022->adev->dev, 1174 "bad message state in interrupt handler"); 1175 /* Never fail */ 1176 return IRQ_HANDLED; 1177 } 1178 1179 /* Read the Interrupt Status Register */ 1180 irq_status = readw(SSP_MIS(pl022->virtbase)); 1181 1182 if (unlikely(!irq_status)) 1183 return IRQ_NONE; 1184 1185 /* 1186 * This handles the FIFO interrupts, the timeout 1187 * interrupts are flatly ignored, they cannot be 1188 * trusted. 1189 */ 1190 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1191 /* 1192 * Overrun interrupt - bail out since our Data has been 1193 * corrupted 1194 */ 1195 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1196 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1197 dev_err(&pl022->adev->dev, 1198 "RXFIFO is full\n"); 1199 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1200 dev_err(&pl022->adev->dev, 1201 "TXFIFO is full\n"); 1202 1203 /* 1204 * Disable and clear interrupts, disable SSP, 1205 * mark message with bad status so it can be 1206 * retried. 1207 */ 1208 writew(DISABLE_ALL_INTERRUPTS, 1209 SSP_IMSC(pl022->virtbase)); 1210 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1211 writew((readw(SSP_CR1(pl022->virtbase)) & 1212 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1213 msg->state = STATE_ERROR; 1214 1215 /* Schedule message queue handler */ 1216 tasklet_schedule(&pl022->pump_transfers); 1217 return IRQ_HANDLED; 1218 } 1219 1220 readwriter(pl022); 1221 1222 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1223 flag = 1; 1224 /* Disable Transmit interrupt, enable receive interrupt */ 1225 writew((readw(SSP_IMSC(pl022->virtbase)) & 1226 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1227 SSP_IMSC(pl022->virtbase)); 1228 } 1229 1230 /* 1231 * Since all transactions must write as much as shall be read, 1232 * we can conclude the entire transaction once RX is complete. 1233 * At this point, all TX will always be finished. 1234 */ 1235 if (pl022->rx >= pl022->rx_end) { 1236 writew(DISABLE_ALL_INTERRUPTS, 1237 SSP_IMSC(pl022->virtbase)); 1238 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1239 if (unlikely(pl022->rx > pl022->rx_end)) { 1240 dev_warn(&pl022->adev->dev, "read %u surplus " 1241 "bytes (did you request an odd " 1242 "number of bytes on a 16bit bus?)\n", 1243 (u32) (pl022->rx - pl022->rx_end)); 1244 } 1245 /* Update total bytes transferred */ 1246 msg->actual_length += pl022->cur_transfer->len; 1247 if (pl022->cur_transfer->cs_change) 1248 pl022->cur_chip-> 1249 cs_control(SSP_CHIP_DESELECT); 1250 /* Move to next transfer */ 1251 msg->state = next_transfer(pl022); 1252 tasklet_schedule(&pl022->pump_transfers); 1253 return IRQ_HANDLED; 1254 } 1255 1256 return IRQ_HANDLED; 1257 } 1258 1259 /** 1260 * This sets up the pointers to memory for the next message to 1261 * send out on the SPI bus. 1262 */ 1263 static int set_up_next_transfer(struct pl022 *pl022, 1264 struct spi_transfer *transfer) 1265 { 1266 int residue; 1267 1268 /* Sanity check the message for this bus width */ 1269 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1270 if (unlikely(residue != 0)) { 1271 dev_err(&pl022->adev->dev, 1272 "message of %u bytes to transmit but the current " 1273 "chip bus has a data width of %u bytes!\n", 1274 pl022->cur_transfer->len, 1275 pl022->cur_chip->n_bytes); 1276 dev_err(&pl022->adev->dev, "skipping this message\n"); 1277 return -EIO; 1278 } 1279 pl022->tx = (void *)transfer->tx_buf; 1280 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1281 pl022->rx = (void *)transfer->rx_buf; 1282 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1283 pl022->write = 1284 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1285 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1286 return 0; 1287 } 1288 1289 /** 1290 * pump_transfers - Tasklet function which schedules next transfer 1291 * when running in interrupt or DMA transfer mode. 1292 * @data: SSP driver private data structure 1293 * 1294 */ 1295 static void pump_transfers(unsigned long data) 1296 { 1297 struct pl022 *pl022 = (struct pl022 *) data; 1298 struct spi_message *message = NULL; 1299 struct spi_transfer *transfer = NULL; 1300 struct spi_transfer *previous = NULL; 1301 1302 /* Get current state information */ 1303 message = pl022->cur_msg; 1304 transfer = pl022->cur_transfer; 1305 1306 /* Handle for abort */ 1307 if (message->state == STATE_ERROR) { 1308 message->status = -EIO; 1309 giveback(pl022); 1310 return; 1311 } 1312 1313 /* Handle end of message */ 1314 if (message->state == STATE_DONE) { 1315 message->status = 0; 1316 giveback(pl022); 1317 return; 1318 } 1319 1320 /* Delay if requested at end of transfer before CS change */ 1321 if (message->state == STATE_RUNNING) { 1322 previous = list_entry(transfer->transfer_list.prev, 1323 struct spi_transfer, 1324 transfer_list); 1325 if (previous->delay_usecs) 1326 /* 1327 * FIXME: This runs in interrupt context. 1328 * Is this really smart? 1329 */ 1330 udelay(previous->delay_usecs); 1331 1332 /* Reselect chip select only if cs_change was requested */ 1333 if (previous->cs_change) 1334 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1335 } else { 1336 /* STATE_START */ 1337 message->state = STATE_RUNNING; 1338 } 1339 1340 if (set_up_next_transfer(pl022, transfer)) { 1341 message->state = STATE_ERROR; 1342 message->status = -EIO; 1343 giveback(pl022); 1344 return; 1345 } 1346 /* Flush the FIFOs and let's go! */ 1347 flush(pl022); 1348 1349 if (pl022->cur_chip->enable_dma) { 1350 if (configure_dma(pl022)) { 1351 dev_dbg(&pl022->adev->dev, 1352 "configuration of DMA failed, fall back to interrupt mode\n"); 1353 goto err_config_dma; 1354 } 1355 return; 1356 } 1357 1358 err_config_dma: 1359 /* enable all interrupts except RX */ 1360 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1361 } 1362 1363 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1364 { 1365 /* 1366 * Default is to enable all interrupts except RX - 1367 * this will be enabled once TX is complete 1368 */ 1369 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1370 1371 /* Enable target chip, if not already active */ 1372 if (!pl022->next_msg_cs_active) 1373 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1374 1375 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1376 /* Error path */ 1377 pl022->cur_msg->state = STATE_ERROR; 1378 pl022->cur_msg->status = -EIO; 1379 giveback(pl022); 1380 return; 1381 } 1382 /* If we're using DMA, set up DMA here */ 1383 if (pl022->cur_chip->enable_dma) { 1384 /* Configure DMA transfer */ 1385 if (configure_dma(pl022)) { 1386 dev_dbg(&pl022->adev->dev, 1387 "configuration of DMA failed, fall back to interrupt mode\n"); 1388 goto err_config_dma; 1389 } 1390 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1391 irqflags = DISABLE_ALL_INTERRUPTS; 1392 } 1393 err_config_dma: 1394 /* Enable SSP, turn on interrupts */ 1395 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1396 SSP_CR1(pl022->virtbase)); 1397 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1398 } 1399 1400 static void do_polling_transfer(struct pl022 *pl022) 1401 { 1402 struct spi_message *message = NULL; 1403 struct spi_transfer *transfer = NULL; 1404 struct spi_transfer *previous = NULL; 1405 struct chip_data *chip; 1406 unsigned long time, timeout; 1407 1408 chip = pl022->cur_chip; 1409 message = pl022->cur_msg; 1410 1411 while (message->state != STATE_DONE) { 1412 /* Handle for abort */ 1413 if (message->state == STATE_ERROR) 1414 break; 1415 transfer = pl022->cur_transfer; 1416 1417 /* Delay if requested at end of transfer */ 1418 if (message->state == STATE_RUNNING) { 1419 previous = 1420 list_entry(transfer->transfer_list.prev, 1421 struct spi_transfer, transfer_list); 1422 if (previous->delay_usecs) 1423 udelay(previous->delay_usecs); 1424 if (previous->cs_change) 1425 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1426 } else { 1427 /* STATE_START */ 1428 message->state = STATE_RUNNING; 1429 if (!pl022->next_msg_cs_active) 1430 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1431 } 1432 1433 /* Configuration Changing Per Transfer */ 1434 if (set_up_next_transfer(pl022, transfer)) { 1435 /* Error path */ 1436 message->state = STATE_ERROR; 1437 break; 1438 } 1439 /* Flush FIFOs and enable SSP */ 1440 flush(pl022); 1441 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1442 SSP_CR1(pl022->virtbase)); 1443 1444 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1445 1446 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1447 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1448 time = jiffies; 1449 readwriter(pl022); 1450 if (time_after(time, timeout)) { 1451 dev_warn(&pl022->adev->dev, 1452 "%s: timeout!\n", __func__); 1453 message->state = STATE_ERROR; 1454 goto out; 1455 } 1456 cpu_relax(); 1457 } 1458 1459 /* Update total byte transferred */ 1460 message->actual_length += pl022->cur_transfer->len; 1461 if (pl022->cur_transfer->cs_change) 1462 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 1463 /* Move to next transfer */ 1464 message->state = next_transfer(pl022); 1465 } 1466 out: 1467 /* Handle end of message */ 1468 if (message->state == STATE_DONE) 1469 message->status = 0; 1470 else 1471 message->status = -EIO; 1472 1473 giveback(pl022); 1474 return; 1475 } 1476 1477 static int pl022_transfer_one_message(struct spi_master *master, 1478 struct spi_message *msg) 1479 { 1480 struct pl022 *pl022 = spi_master_get_devdata(master); 1481 1482 /* Initial message state */ 1483 pl022->cur_msg = msg; 1484 msg->state = STATE_START; 1485 1486 pl022->cur_transfer = list_entry(msg->transfers.next, 1487 struct spi_transfer, transfer_list); 1488 1489 /* Setup the SPI using the per chip configuration */ 1490 pl022->cur_chip = spi_get_ctldata(msg->spi); 1491 1492 restore_state(pl022); 1493 flush(pl022); 1494 1495 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1496 do_polling_transfer(pl022); 1497 else 1498 do_interrupt_dma_transfer(pl022); 1499 1500 return 0; 1501 } 1502 1503 static int pl022_prepare_transfer_hardware(struct spi_master *master) 1504 { 1505 struct pl022 *pl022 = spi_master_get_devdata(master); 1506 1507 /* 1508 * Just make sure we have all we need to run the transfer by syncing 1509 * with the runtime PM framework. 1510 */ 1511 pm_runtime_get_sync(&pl022->adev->dev); 1512 return 0; 1513 } 1514 1515 static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1516 { 1517 struct pl022 *pl022 = spi_master_get_devdata(master); 1518 1519 /* nothing more to do - disable spi/ssp and power off */ 1520 writew((readw(SSP_CR1(pl022->virtbase)) & 1521 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1522 1523 if (pl022->master_info->autosuspend_delay > 0) { 1524 pm_runtime_mark_last_busy(&pl022->adev->dev); 1525 pm_runtime_put_autosuspend(&pl022->adev->dev); 1526 } else { 1527 pm_runtime_put(&pl022->adev->dev); 1528 } 1529 1530 return 0; 1531 } 1532 1533 static int verify_controller_parameters(struct pl022 *pl022, 1534 struct pl022_config_chip const *chip_info) 1535 { 1536 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1537 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1538 dev_err(&pl022->adev->dev, 1539 "interface is configured incorrectly\n"); 1540 return -EINVAL; 1541 } 1542 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1543 (!pl022->vendor->unidir)) { 1544 dev_err(&pl022->adev->dev, 1545 "unidirectional mode not supported in this " 1546 "hardware version\n"); 1547 return -EINVAL; 1548 } 1549 if ((chip_info->hierarchy != SSP_MASTER) 1550 && (chip_info->hierarchy != SSP_SLAVE)) { 1551 dev_err(&pl022->adev->dev, 1552 "hierarchy is configured incorrectly\n"); 1553 return -EINVAL; 1554 } 1555 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1556 && (chip_info->com_mode != DMA_TRANSFER) 1557 && (chip_info->com_mode != POLLING_TRANSFER)) { 1558 dev_err(&pl022->adev->dev, 1559 "Communication mode is configured incorrectly\n"); 1560 return -EINVAL; 1561 } 1562 switch (chip_info->rx_lev_trig) { 1563 case SSP_RX_1_OR_MORE_ELEM: 1564 case SSP_RX_4_OR_MORE_ELEM: 1565 case SSP_RX_8_OR_MORE_ELEM: 1566 /* These are always OK, all variants can handle this */ 1567 break; 1568 case SSP_RX_16_OR_MORE_ELEM: 1569 if (pl022->vendor->fifodepth < 16) { 1570 dev_err(&pl022->adev->dev, 1571 "RX FIFO Trigger Level is configured incorrectly\n"); 1572 return -EINVAL; 1573 } 1574 break; 1575 case SSP_RX_32_OR_MORE_ELEM: 1576 if (pl022->vendor->fifodepth < 32) { 1577 dev_err(&pl022->adev->dev, 1578 "RX FIFO Trigger Level is configured incorrectly\n"); 1579 return -EINVAL; 1580 } 1581 break; 1582 default: 1583 dev_err(&pl022->adev->dev, 1584 "RX FIFO Trigger Level is configured incorrectly\n"); 1585 return -EINVAL; 1586 break; 1587 } 1588 switch (chip_info->tx_lev_trig) { 1589 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1590 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1591 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1592 /* These are always OK, all variants can handle this */ 1593 break; 1594 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1595 if (pl022->vendor->fifodepth < 16) { 1596 dev_err(&pl022->adev->dev, 1597 "TX FIFO Trigger Level is configured incorrectly\n"); 1598 return -EINVAL; 1599 } 1600 break; 1601 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1602 if (pl022->vendor->fifodepth < 32) { 1603 dev_err(&pl022->adev->dev, 1604 "TX FIFO Trigger Level is configured incorrectly\n"); 1605 return -EINVAL; 1606 } 1607 break; 1608 default: 1609 dev_err(&pl022->adev->dev, 1610 "TX FIFO Trigger Level is configured incorrectly\n"); 1611 return -EINVAL; 1612 break; 1613 } 1614 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1615 if ((chip_info->ctrl_len < SSP_BITS_4) 1616 || (chip_info->ctrl_len > SSP_BITS_32)) { 1617 dev_err(&pl022->adev->dev, 1618 "CTRL LEN is configured incorrectly\n"); 1619 return -EINVAL; 1620 } 1621 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1622 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1623 dev_err(&pl022->adev->dev, 1624 "Wait State is configured incorrectly\n"); 1625 return -EINVAL; 1626 } 1627 /* Half duplex is only available in the ST Micro version */ 1628 if (pl022->vendor->extended_cr) { 1629 if ((chip_info->duplex != 1630 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1631 && (chip_info->duplex != 1632 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1633 dev_err(&pl022->adev->dev, 1634 "Microwire duplex mode is configured incorrectly\n"); 1635 return -EINVAL; 1636 } 1637 } else { 1638 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1639 dev_err(&pl022->adev->dev, 1640 "Microwire half duplex mode requested," 1641 " but this is only available in the" 1642 " ST version of PL022\n"); 1643 return -EINVAL; 1644 } 1645 } 1646 return 0; 1647 } 1648 1649 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1650 { 1651 return rate / (cpsdvsr * (1 + scr)); 1652 } 1653 1654 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1655 ssp_clock_params * clk_freq) 1656 { 1657 /* Lets calculate the frequency parameters */ 1658 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1659 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1660 best_scr = 0, tmp, found = 0; 1661 1662 rate = clk_get_rate(pl022->clk); 1663 /* cpsdvscr = 2 & scr 0 */ 1664 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1665 /* cpsdvsr = 254 & scr = 255 */ 1666 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1667 1668 if (!((freq <= max_tclk) && (freq >= min_tclk))) { 1669 dev_err(&pl022->adev->dev, 1670 "controller data is incorrect: out of range frequency"); 1671 return -EINVAL; 1672 } 1673 1674 /* 1675 * best_freq will give closest possible available rate (<= requested 1676 * freq) for all values of scr & cpsdvsr. 1677 */ 1678 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1679 while (scr <= SCR_MAX) { 1680 tmp = spi_rate(rate, cpsdvsr, scr); 1681 1682 if (tmp > freq) 1683 scr++; 1684 /* 1685 * If found exact value, update and break. 1686 * If found more closer value, update and continue. 1687 */ 1688 else if ((tmp == freq) || (tmp > best_freq)) { 1689 best_freq = tmp; 1690 best_cpsdvsr = cpsdvsr; 1691 best_scr = scr; 1692 1693 if (tmp == freq) 1694 break; 1695 } 1696 scr++; 1697 } 1698 cpsdvsr += 2; 1699 scr = SCR_MIN; 1700 } 1701 1702 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1703 clk_freq->scr = (u8) (best_scr & 0xFF); 1704 dev_dbg(&pl022->adev->dev, 1705 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1706 freq, best_freq); 1707 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1708 clk_freq->cpsdvsr, clk_freq->scr); 1709 1710 return 0; 1711 } 1712 1713 /* 1714 * A piece of default chip info unless the platform 1715 * supplies it. 1716 */ 1717 static const struct pl022_config_chip pl022_default_chip_info = { 1718 .com_mode = POLLING_TRANSFER, 1719 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1720 .hierarchy = SSP_SLAVE, 1721 .slave_tx_disable = DO_NOT_DRIVE_TX, 1722 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1723 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1724 .ctrl_len = SSP_BITS_8, 1725 .wait_state = SSP_MWIRE_WAIT_ZERO, 1726 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1727 .cs_control = null_cs_control, 1728 }; 1729 1730 /** 1731 * pl022_setup - setup function registered to SPI master framework 1732 * @spi: spi device which is requesting setup 1733 * 1734 * This function is registered to the SPI framework for this SPI master 1735 * controller. If it is the first time when setup is called by this device, 1736 * this function will initialize the runtime state for this chip and save 1737 * the same in the device structure. Else it will update the runtime info 1738 * with the updated chip info. Nothing is really being written to the 1739 * controller hardware here, that is not done until the actual transfer 1740 * commence. 1741 */ 1742 static int pl022_setup(struct spi_device *spi) 1743 { 1744 struct pl022_config_chip const *chip_info; 1745 struct chip_data *chip; 1746 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1747 int status = 0; 1748 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1749 unsigned int bits = spi->bits_per_word; 1750 u32 tmp; 1751 1752 if (!spi->max_speed_hz) 1753 return -EINVAL; 1754 1755 /* Get controller_state if one is supplied */ 1756 chip = spi_get_ctldata(spi); 1757 1758 if (chip == NULL) { 1759 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1760 if (!chip) { 1761 dev_err(&spi->dev, 1762 "cannot allocate controller state\n"); 1763 return -ENOMEM; 1764 } 1765 dev_dbg(&spi->dev, 1766 "allocated memory for controller's runtime state\n"); 1767 } 1768 1769 /* Get controller data if one is supplied */ 1770 chip_info = spi->controller_data; 1771 1772 if (chip_info == NULL) { 1773 chip_info = &pl022_default_chip_info; 1774 /* spi_board_info.controller_data not is supplied */ 1775 dev_dbg(&spi->dev, 1776 "using default controller_data settings\n"); 1777 } else 1778 dev_dbg(&spi->dev, 1779 "using user supplied controller_data settings\n"); 1780 1781 /* 1782 * We can override with custom divisors, else we use the board 1783 * frequency setting 1784 */ 1785 if ((0 == chip_info->clk_freq.cpsdvsr) 1786 && (0 == chip_info->clk_freq.scr)) { 1787 status = calculate_effective_freq(pl022, 1788 spi->max_speed_hz, 1789 &clk_freq); 1790 if (status < 0) 1791 goto err_config_params; 1792 } else { 1793 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1794 if ((clk_freq.cpsdvsr % 2) != 0) 1795 clk_freq.cpsdvsr = 1796 clk_freq.cpsdvsr - 1; 1797 } 1798 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1799 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1800 status = -EINVAL; 1801 dev_err(&spi->dev, 1802 "cpsdvsr is configured incorrectly\n"); 1803 goto err_config_params; 1804 } 1805 1806 status = verify_controller_parameters(pl022, chip_info); 1807 if (status) { 1808 dev_err(&spi->dev, "controller data is incorrect"); 1809 goto err_config_params; 1810 } 1811 1812 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1813 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1814 1815 /* Now set controller state based on controller data */ 1816 chip->xfer_type = chip_info->com_mode; 1817 if (!chip_info->cs_control) { 1818 chip->cs_control = null_cs_control; 1819 dev_warn(&spi->dev, 1820 "chip select function is NULL for this chip\n"); 1821 } else 1822 chip->cs_control = chip_info->cs_control; 1823 1824 if (bits <= 3) { 1825 /* PL022 doesn't support less than 4-bits */ 1826 status = -ENOTSUPP; 1827 goto err_config_params; 1828 } else if (bits <= 8) { 1829 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1830 chip->n_bytes = 1; 1831 chip->read = READING_U8; 1832 chip->write = WRITING_U8; 1833 } else if (bits <= 16) { 1834 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1835 chip->n_bytes = 2; 1836 chip->read = READING_U16; 1837 chip->write = WRITING_U16; 1838 } else { 1839 if (pl022->vendor->max_bpw >= 32) { 1840 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1841 chip->n_bytes = 4; 1842 chip->read = READING_U32; 1843 chip->write = WRITING_U32; 1844 } else { 1845 dev_err(&spi->dev, 1846 "illegal data size for this controller!\n"); 1847 dev_err(&spi->dev, 1848 "a standard pl022 can only handle " 1849 "1 <= n <= 16 bit words\n"); 1850 status = -ENOTSUPP; 1851 goto err_config_params; 1852 } 1853 } 1854 1855 /* Now Initialize all register settings required for this chip */ 1856 chip->cr0 = 0; 1857 chip->cr1 = 0; 1858 chip->dmacr = 0; 1859 chip->cpsr = 0; 1860 if ((chip_info->com_mode == DMA_TRANSFER) 1861 && ((pl022->master_info)->enable_dma)) { 1862 chip->enable_dma = true; 1863 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1864 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1865 SSP_DMACR_MASK_RXDMAE, 0); 1866 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1867 SSP_DMACR_MASK_TXDMAE, 1); 1868 } else { 1869 chip->enable_dma = false; 1870 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1871 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1872 SSP_DMACR_MASK_RXDMAE, 0); 1873 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1874 SSP_DMACR_MASK_TXDMAE, 1); 1875 } 1876 1877 chip->cpsr = clk_freq.cpsdvsr; 1878 1879 /* Special setup for the ST micro extended control registers */ 1880 if (pl022->vendor->extended_cr) { 1881 u32 etx; 1882 1883 if (pl022->vendor->pl023) { 1884 /* These bits are only in the PL023 */ 1885 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1886 SSP_CR1_MASK_FBCLKDEL_ST, 13); 1887 } else { 1888 /* These bits are in the PL022 but not PL023 */ 1889 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1890 SSP_CR0_MASK_HALFDUP_ST, 5); 1891 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1892 SSP_CR0_MASK_CSS_ST, 16); 1893 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1894 SSP_CR0_MASK_FRF_ST, 21); 1895 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 1896 SSP_CR1_MASK_MWAIT_ST, 6); 1897 } 1898 SSP_WRITE_BITS(chip->cr0, bits - 1, 1899 SSP_CR0_MASK_DSS_ST, 0); 1900 1901 if (spi->mode & SPI_LSB_FIRST) { 1902 tmp = SSP_RX_LSB; 1903 etx = SSP_TX_LSB; 1904 } else { 1905 tmp = SSP_RX_MSB; 1906 etx = SSP_TX_MSB; 1907 } 1908 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 1909 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 1910 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 1911 SSP_CR1_MASK_RXIFLSEL_ST, 7); 1912 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 1913 SSP_CR1_MASK_TXIFLSEL_ST, 10); 1914 } else { 1915 SSP_WRITE_BITS(chip->cr0, bits - 1, 1916 SSP_CR0_MASK_DSS, 0); 1917 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1918 SSP_CR0_MASK_FRF, 4); 1919 } 1920 1921 /* Stuff that is common for all versions */ 1922 if (spi->mode & SPI_CPOL) 1923 tmp = SSP_CLK_POL_IDLE_HIGH; 1924 else 1925 tmp = SSP_CLK_POL_IDLE_LOW; 1926 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 1927 1928 if (spi->mode & SPI_CPHA) 1929 tmp = SSP_CLK_SECOND_EDGE; 1930 else 1931 tmp = SSP_CLK_FIRST_EDGE; 1932 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 1933 1934 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 1935 /* Loopback is available on all versions except PL023 */ 1936 if (pl022->vendor->loopback) { 1937 if (spi->mode & SPI_LOOP) 1938 tmp = LOOPBACK_ENABLED; 1939 else 1940 tmp = LOOPBACK_DISABLED; 1941 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 1942 } 1943 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 1944 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 1945 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 1946 3); 1947 1948 /* Save controller_state */ 1949 spi_set_ctldata(spi, chip); 1950 return status; 1951 err_config_params: 1952 spi_set_ctldata(spi, NULL); 1953 kfree(chip); 1954 return status; 1955 } 1956 1957 /** 1958 * pl022_cleanup - cleanup function registered to SPI master framework 1959 * @spi: spi device which is requesting cleanup 1960 * 1961 * This function is registered to the SPI framework for this SPI master 1962 * controller. It will free the runtime state of chip. 1963 */ 1964 static void pl022_cleanup(struct spi_device *spi) 1965 { 1966 struct chip_data *chip = spi_get_ctldata(spi); 1967 1968 spi_set_ctldata(spi, NULL); 1969 kfree(chip); 1970 } 1971 1972 static int __devinit 1973 pl022_probe(struct amba_device *adev, const struct amba_id *id) 1974 { 1975 struct device *dev = &adev->dev; 1976 struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 1977 struct spi_master *master; 1978 struct pl022 *pl022 = NULL; /*Data for this driver */ 1979 int status = 0; 1980 1981 dev_info(&adev->dev, 1982 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 1983 if (platform_info == NULL) { 1984 dev_err(&adev->dev, "probe - no platform data supplied\n"); 1985 status = -ENODEV; 1986 goto err_no_pdata; 1987 } 1988 1989 /* Allocate master with space for data */ 1990 master = spi_alloc_master(dev, sizeof(struct pl022)); 1991 if (master == NULL) { 1992 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 1993 status = -ENOMEM; 1994 goto err_no_master; 1995 } 1996 1997 pl022 = spi_master_get_devdata(master); 1998 pl022->master = master; 1999 pl022->master_info = platform_info; 2000 pl022->adev = adev; 2001 pl022->vendor = id->data; 2002 2003 /* 2004 * Bus Number Which has been Assigned to this SSP controller 2005 * on this board 2006 */ 2007 master->bus_num = platform_info->bus_id; 2008 master->num_chipselect = platform_info->num_chipselect; 2009 master->cleanup = pl022_cleanup; 2010 master->setup = pl022_setup; 2011 master->prepare_transfer_hardware = pl022_prepare_transfer_hardware; 2012 master->transfer_one_message = pl022_transfer_one_message; 2013 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2014 master->rt = platform_info->rt; 2015 2016 /* 2017 * Supports mode 0-3, loopback, and active low CS. Transfers are 2018 * always MS bit first on the original pl022. 2019 */ 2020 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2021 if (pl022->vendor->extended_cr) 2022 master->mode_bits |= SPI_LSB_FIRST; 2023 2024 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2025 2026 status = amba_request_regions(adev, NULL); 2027 if (status) 2028 goto err_no_ioregion; 2029 2030 pl022->phybase = adev->res.start; 2031 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2032 if (pl022->virtbase == NULL) { 2033 status = -ENOMEM; 2034 goto err_no_ioremap; 2035 } 2036 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2037 adev->res.start, pl022->virtbase); 2038 2039 pl022->clk = clk_get(&adev->dev, NULL); 2040 if (IS_ERR(pl022->clk)) { 2041 status = PTR_ERR(pl022->clk); 2042 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2043 goto err_no_clk; 2044 } 2045 2046 status = clk_prepare(pl022->clk); 2047 if (status) { 2048 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 2049 goto err_clk_prep; 2050 } 2051 2052 status = clk_enable(pl022->clk); 2053 if (status) { 2054 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2055 goto err_no_clk_en; 2056 } 2057 2058 /* Initialize transfer pump */ 2059 tasklet_init(&pl022->pump_transfers, pump_transfers, 2060 (unsigned long)pl022); 2061 2062 /* Disable SSP */ 2063 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2064 SSP_CR1(pl022->virtbase)); 2065 load_ssp_default_config(pl022); 2066 2067 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2068 pl022); 2069 if (status < 0) { 2070 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2071 goto err_no_irq; 2072 } 2073 2074 /* Get DMA channels */ 2075 if (platform_info->enable_dma) { 2076 status = pl022_dma_probe(pl022); 2077 if (status != 0) 2078 platform_info->enable_dma = 0; 2079 } 2080 2081 /* Register with the SPI framework */ 2082 amba_set_drvdata(adev, pl022); 2083 status = spi_register_master(master); 2084 if (status != 0) { 2085 dev_err(&adev->dev, 2086 "probe - problem registering spi master\n"); 2087 goto err_spi_register; 2088 } 2089 dev_dbg(dev, "probe succeeded\n"); 2090 2091 /* let runtime pm put suspend */ 2092 if (platform_info->autosuspend_delay > 0) { 2093 dev_info(&adev->dev, 2094 "will use autosuspend for runtime pm, delay %dms\n", 2095 platform_info->autosuspend_delay); 2096 pm_runtime_set_autosuspend_delay(dev, 2097 platform_info->autosuspend_delay); 2098 pm_runtime_use_autosuspend(dev); 2099 pm_runtime_put_autosuspend(dev); 2100 } else { 2101 pm_runtime_put(dev); 2102 } 2103 return 0; 2104 2105 err_spi_register: 2106 if (platform_info->enable_dma) 2107 pl022_dma_remove(pl022); 2108 2109 free_irq(adev->irq[0], pl022); 2110 err_no_irq: 2111 clk_disable(pl022->clk); 2112 err_no_clk_en: 2113 clk_unprepare(pl022->clk); 2114 err_clk_prep: 2115 clk_put(pl022->clk); 2116 err_no_clk: 2117 iounmap(pl022->virtbase); 2118 err_no_ioremap: 2119 amba_release_regions(adev); 2120 err_no_ioregion: 2121 spi_master_put(master); 2122 err_no_master: 2123 err_no_pdata: 2124 return status; 2125 } 2126 2127 static int __devexit 2128 pl022_remove(struct amba_device *adev) 2129 { 2130 struct pl022 *pl022 = amba_get_drvdata(adev); 2131 2132 if (!pl022) 2133 return 0; 2134 2135 /* 2136 * undo pm_runtime_put() in probe. I assume that we're not 2137 * accessing the primecell here. 2138 */ 2139 pm_runtime_get_noresume(&adev->dev); 2140 2141 load_ssp_default_config(pl022); 2142 if (pl022->master_info->enable_dma) 2143 pl022_dma_remove(pl022); 2144 2145 free_irq(adev->irq[0], pl022); 2146 clk_disable(pl022->clk); 2147 clk_unprepare(pl022->clk); 2148 clk_put(pl022->clk); 2149 iounmap(pl022->virtbase); 2150 amba_release_regions(adev); 2151 tasklet_disable(&pl022->pump_transfers); 2152 spi_unregister_master(pl022->master); 2153 spi_master_put(pl022->master); 2154 amba_set_drvdata(adev, NULL); 2155 return 0; 2156 } 2157 2158 #ifdef CONFIG_SUSPEND 2159 static int pl022_suspend(struct device *dev) 2160 { 2161 struct pl022 *pl022 = dev_get_drvdata(dev); 2162 int ret; 2163 2164 ret = spi_master_suspend(pl022->master); 2165 if (ret) { 2166 dev_warn(dev, "cannot suspend master\n"); 2167 return ret; 2168 } 2169 2170 dev_dbg(dev, "suspended\n"); 2171 return 0; 2172 } 2173 2174 static int pl022_resume(struct device *dev) 2175 { 2176 struct pl022 *pl022 = dev_get_drvdata(dev); 2177 int ret; 2178 2179 /* Start the queue running */ 2180 ret = spi_master_resume(pl022->master); 2181 if (ret) 2182 dev_err(dev, "problem starting queue (%d)\n", ret); 2183 else 2184 dev_dbg(dev, "resumed\n"); 2185 2186 return ret; 2187 } 2188 #endif /* CONFIG_PM */ 2189 2190 #ifdef CONFIG_PM_RUNTIME 2191 static int pl022_runtime_suspend(struct device *dev) 2192 { 2193 struct pl022 *pl022 = dev_get_drvdata(dev); 2194 2195 clk_disable(pl022->clk); 2196 amba_vcore_disable(pl022->adev); 2197 2198 return 0; 2199 } 2200 2201 static int pl022_runtime_resume(struct device *dev) 2202 { 2203 struct pl022 *pl022 = dev_get_drvdata(dev); 2204 2205 amba_vcore_enable(pl022->adev); 2206 clk_enable(pl022->clk); 2207 2208 return 0; 2209 } 2210 #endif 2211 2212 static const struct dev_pm_ops pl022_dev_pm_ops = { 2213 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2214 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2215 }; 2216 2217 static struct vendor_data vendor_arm = { 2218 .fifodepth = 8, 2219 .max_bpw = 16, 2220 .unidir = false, 2221 .extended_cr = false, 2222 .pl023 = false, 2223 .loopback = true, 2224 }; 2225 2226 static struct vendor_data vendor_st = { 2227 .fifodepth = 32, 2228 .max_bpw = 32, 2229 .unidir = false, 2230 .extended_cr = true, 2231 .pl023 = false, 2232 .loopback = true, 2233 }; 2234 2235 static struct vendor_data vendor_st_pl023 = { 2236 .fifodepth = 32, 2237 .max_bpw = 32, 2238 .unidir = false, 2239 .extended_cr = true, 2240 .pl023 = true, 2241 .loopback = false, 2242 }; 2243 2244 static struct vendor_data vendor_db5500_pl023 = { 2245 .fifodepth = 32, 2246 .max_bpw = 32, 2247 .unidir = false, 2248 .extended_cr = true, 2249 .pl023 = true, 2250 .loopback = true, 2251 }; 2252 2253 static struct amba_id pl022_ids[] = { 2254 { 2255 /* 2256 * ARM PL022 variant, this has a 16bit wide 2257 * and 8 locations deep TX/RX FIFO 2258 */ 2259 .id = 0x00041022, 2260 .mask = 0x000fffff, 2261 .data = &vendor_arm, 2262 }, 2263 { 2264 /* 2265 * ST Micro derivative, this has 32bit wide 2266 * and 32 locations deep TX/RX FIFO 2267 */ 2268 .id = 0x01080022, 2269 .mask = 0xffffffff, 2270 .data = &vendor_st, 2271 }, 2272 { 2273 /* 2274 * ST-Ericsson derivative "PL023" (this is not 2275 * an official ARM number), this is a PL022 SSP block 2276 * stripped to SPI mode only, it has 32bit wide 2277 * and 32 locations deep TX/RX FIFO but no extended 2278 * CR0/CR1 register 2279 */ 2280 .id = 0x00080023, 2281 .mask = 0xffffffff, 2282 .data = &vendor_st_pl023, 2283 }, 2284 { 2285 .id = 0x10080023, 2286 .mask = 0xffffffff, 2287 .data = &vendor_db5500_pl023, 2288 }, 2289 { 0, 0 }, 2290 }; 2291 2292 MODULE_DEVICE_TABLE(amba, pl022_ids); 2293 2294 static struct amba_driver pl022_driver = { 2295 .drv = { 2296 .name = "ssp-pl022", 2297 .pm = &pl022_dev_pm_ops, 2298 }, 2299 .id_table = pl022_ids, 2300 .probe = pl022_probe, 2301 .remove = __devexit_p(pl022_remove), 2302 }; 2303 2304 static int __init pl022_init(void) 2305 { 2306 return amba_driver_register(&pl022_driver); 2307 } 2308 subsys_initcall(pl022_init); 2309 2310 static void __exit pl022_exit(void) 2311 { 2312 amba_driver_unregister(&pl022_driver); 2313 } 2314 module_exit(pl022_exit); 2315 2316 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2317 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2318 MODULE_LICENSE("GPL"); 2319