1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2012 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/delay.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/amba/bus.h> 36 #include <linux/amba/pl022.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 #include <linux/dmaengine.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/scatterlist.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/gpio.h> 44 #include <linux/of_gpio.h> 45 #include <linux/pinctrl/consumer.h> 46 47 /* 48 * This macro is used to define some register default values. 49 * reg is masked with mask, the OR:ed with an (again masked) 50 * val shifted sb steps to the left. 51 */ 52 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 54 55 /* 56 * This macro is also used to define some default values. 57 * It will just shift val by sb steps to the left and mask 58 * the result with mask. 59 */ 60 #define GEN_MASK_BITS(val, mask, sb) \ 61 (((val)<<(sb)) & (mask)) 62 63 #define DRIVE_TX 0 64 #define DO_NOT_DRIVE_TX 1 65 66 #define DO_NOT_QUEUE_DMA 0 67 #define QUEUE_DMA 1 68 69 #define RX_TRANSFER 1 70 #define TX_TRANSFER 2 71 72 /* 73 * Macros to access SSP Registers with their offsets 74 */ 75 #define SSP_CR0(r) (r + 0x000) 76 #define SSP_CR1(r) (r + 0x004) 77 #define SSP_DR(r) (r + 0x008) 78 #define SSP_SR(r) (r + 0x00C) 79 #define SSP_CPSR(r) (r + 0x010) 80 #define SSP_IMSC(r) (r + 0x014) 81 #define SSP_RIS(r) (r + 0x018) 82 #define SSP_MIS(r) (r + 0x01C) 83 #define SSP_ICR(r) (r + 0x020) 84 #define SSP_DMACR(r) (r + 0x024) 85 #define SSP_ITCR(r) (r + 0x080) 86 #define SSP_ITIP(r) (r + 0x084) 87 #define SSP_ITOP(r) (r + 0x088) 88 #define SSP_TDR(r) (r + 0x08C) 89 90 #define SSP_PID0(r) (r + 0xFE0) 91 #define SSP_PID1(r) (r + 0xFE4) 92 #define SSP_PID2(r) (r + 0xFE8) 93 #define SSP_PID3(r) (r + 0xFEC) 94 95 #define SSP_CID0(r) (r + 0xFF0) 96 #define SSP_CID1(r) (r + 0xFF4) 97 #define SSP_CID2(r) (r + 0xFF8) 98 #define SSP_CID3(r) (r + 0xFFC) 99 100 /* 101 * SSP Control Register 0 - SSP_CR0 102 */ 103 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 104 #define SSP_CR0_MASK_FRF (0x3UL << 4) 105 #define SSP_CR0_MASK_SPO (0x1UL << 6) 106 #define SSP_CR0_MASK_SPH (0x1UL << 7) 107 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 108 109 /* 110 * The ST version of this block moves som bits 111 * in SSP_CR0 and extends it to 32 bits 112 */ 113 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 114 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 115 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 116 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 117 118 /* 119 * SSP Control Register 0 - SSP_CR1 120 */ 121 #define SSP_CR1_MASK_LBM (0x1UL << 0) 122 #define SSP_CR1_MASK_SSE (0x1UL << 1) 123 #define SSP_CR1_MASK_MS (0x1UL << 2) 124 #define SSP_CR1_MASK_SOD (0x1UL << 3) 125 126 /* 127 * The ST version of this block adds some bits 128 * in SSP_CR1 129 */ 130 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 131 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 132 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 133 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 134 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 135 /* This one is only in the PL023 variant */ 136 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 137 138 /* 139 * SSP Status Register - SSP_SR 140 */ 141 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 142 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 143 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 144 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 145 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 146 147 /* 148 * SSP Clock Prescale Register - SSP_CPSR 149 */ 150 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 151 152 /* 153 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 154 */ 155 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 156 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 157 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 158 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 159 160 /* 161 * SSP Raw Interrupt Status Register - SSP_RIS 162 */ 163 /* Receive Overrun Raw Interrupt status */ 164 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 165 /* Receive Timeout Raw Interrupt status */ 166 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 167 /* Receive FIFO Raw Interrupt status */ 168 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 169 /* Transmit FIFO Raw Interrupt status */ 170 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 171 172 /* 173 * SSP Masked Interrupt Status Register - SSP_MIS 174 */ 175 /* Receive Overrun Masked Interrupt status */ 176 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 177 /* Receive Timeout Masked Interrupt status */ 178 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 179 /* Receive FIFO Masked Interrupt status */ 180 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 181 /* Transmit FIFO Masked Interrupt status */ 182 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 183 184 /* 185 * SSP Interrupt Clear Register - SSP_ICR 186 */ 187 /* Receive Overrun Raw Clear Interrupt bit */ 188 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 189 /* Receive Timeout Clear Interrupt bit */ 190 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 191 192 /* 193 * SSP DMA Control Register - SSP_DMACR 194 */ 195 /* Receive DMA Enable bit */ 196 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 197 /* Transmit DMA Enable bit */ 198 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 199 200 /* 201 * SSP Integration Test control Register - SSP_ITCR 202 */ 203 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 204 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 205 206 /* 207 * SSP Integration Test Input Register - SSP_ITIP 208 */ 209 #define ITIP_MASK_SSPRXD (0x1UL << 0) 210 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 211 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 212 #define ITIP_MASK_RXDMAC (0x1UL << 3) 213 #define ITIP_MASK_TXDMAC (0x1UL << 4) 214 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 215 216 /* 217 * SSP Integration Test output Register - SSP_ITOP 218 */ 219 #define ITOP_MASK_SSPTXD (0x1UL << 0) 220 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 221 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 222 #define ITOP_MASK_SSPOEn (0x1UL << 3) 223 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 224 #define ITOP_MASK_RORINTR (0x1UL << 5) 225 #define ITOP_MASK_RTINTR (0x1UL << 6) 226 #define ITOP_MASK_RXINTR (0x1UL << 7) 227 #define ITOP_MASK_TXINTR (0x1UL << 8) 228 #define ITOP_MASK_INTR (0x1UL << 9) 229 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 230 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 231 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 232 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 233 234 /* 235 * SSP Test Data Register - SSP_TDR 236 */ 237 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 238 239 /* 240 * Message State 241 * we use the spi_message.state (void *) pointer to 242 * hold a single state value, that's why all this 243 * (void *) casting is done here. 244 */ 245 #define STATE_START ((void *) 0) 246 #define STATE_RUNNING ((void *) 1) 247 #define STATE_DONE ((void *) 2) 248 #define STATE_ERROR ((void *) -1) 249 250 /* 251 * SSP State - Whether Enabled or Disabled 252 */ 253 #define SSP_DISABLED (0) 254 #define SSP_ENABLED (1) 255 256 /* 257 * SSP DMA State - Whether DMA Enabled or Disabled 258 */ 259 #define SSP_DMA_DISABLED (0) 260 #define SSP_DMA_ENABLED (1) 261 262 /* 263 * SSP Clock Defaults 264 */ 265 #define SSP_DEFAULT_CLKRATE 0x2 266 #define SSP_DEFAULT_PRESCALE 0x40 267 268 /* 269 * SSP Clock Parameter ranges 270 */ 271 #define CPSDVR_MIN 0x02 272 #define CPSDVR_MAX 0xFE 273 #define SCR_MIN 0x00 274 #define SCR_MAX 0xFF 275 276 /* 277 * SSP Interrupt related Macros 278 */ 279 #define DEFAULT_SSP_REG_IMSC 0x0UL 280 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 281 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 282 283 #define CLEAR_ALL_INTERRUPTS 0x3 284 285 #define SPI_POLLING_TIMEOUT 1000 286 287 /* 288 * The type of reading going on on this chip 289 */ 290 enum ssp_reading { 291 READING_NULL, 292 READING_U8, 293 READING_U16, 294 READING_U32 295 }; 296 297 /** 298 * The type of writing going on on this chip 299 */ 300 enum ssp_writing { 301 WRITING_NULL, 302 WRITING_U8, 303 WRITING_U16, 304 WRITING_U32 305 }; 306 307 /** 308 * struct vendor_data - vendor-specific config parameters 309 * for PL022 derivates 310 * @fifodepth: depth of FIFOs (both) 311 * @max_bpw: maximum number of bits per word 312 * @unidir: supports unidirection transfers 313 * @extended_cr: 32 bit wide control register 0 with extra 314 * features and extra features in CR1 as found in the ST variants 315 * @pl023: supports a subset of the ST extensions called "PL023" 316 */ 317 struct vendor_data { 318 int fifodepth; 319 int max_bpw; 320 bool unidir; 321 bool extended_cr; 322 bool pl023; 323 bool loopback; 324 }; 325 326 /** 327 * struct pl022 - This is the private SSP driver data structure 328 * @adev: AMBA device model hookup 329 * @vendor: vendor data for the IP block 330 * @phybase: the physical memory where the SSP device resides 331 * @virtbase: the virtual memory where the SSP is mapped 332 * @clk: outgoing clock "SPICLK" for the SPI bus 333 * @master: SPI framework hookup 334 * @master_info: controller-specific data from machine setup 335 * @kworker: thread struct for message pump 336 * @kworker_task: pointer to task for message pump kworker thread 337 * @pump_messages: work struct for scheduling work to the message pump 338 * @queue_lock: spinlock to syncronise access to message queue 339 * @queue: message queue 340 * @busy: message pump is busy 341 * @running: message pump is running 342 * @pump_transfers: Tasklet used in Interrupt Transfer mode 343 * @cur_msg: Pointer to current spi_message being processed 344 * @cur_transfer: Pointer to current spi_transfer 345 * @cur_chip: pointer to current clients chip(assigned from controller_state) 346 * @next_msg_cs_active: the next message in the queue has been examined 347 * and it was found that it uses the same chip select as the previous 348 * message, so we left it active after the previous transfer, and it's 349 * active already. 350 * @tx: current position in TX buffer to be read 351 * @tx_end: end position in TX buffer to be read 352 * @rx: current position in RX buffer to be written 353 * @rx_end: end position in RX buffer to be written 354 * @read: the type of read currently going on 355 * @write: the type of write currently going on 356 * @exp_fifo_level: expected FIFO level 357 * @dma_rx_channel: optional channel for RX DMA 358 * @dma_tx_channel: optional channel for TX DMA 359 * @sgt_rx: scattertable for the RX transfer 360 * @sgt_tx: scattertable for the TX transfer 361 * @dummypage: a dummy page used for driving data on the bus with DMA 362 * @cur_cs: current chip select (gpio) 363 * @chipselects: list of chipselects (gpios) 364 */ 365 struct pl022 { 366 struct amba_device *adev; 367 struct vendor_data *vendor; 368 resource_size_t phybase; 369 void __iomem *virtbase; 370 struct clk *clk; 371 /* Two optional pin states - default & sleep */ 372 struct pinctrl *pinctrl; 373 struct pinctrl_state *pins_default; 374 struct pinctrl_state *pins_idle; 375 struct pinctrl_state *pins_sleep; 376 struct spi_master *master; 377 struct pl022_ssp_controller *master_info; 378 /* Message per-transfer pump */ 379 struct tasklet_struct pump_transfers; 380 struct spi_message *cur_msg; 381 struct spi_transfer *cur_transfer; 382 struct chip_data *cur_chip; 383 bool next_msg_cs_active; 384 void *tx; 385 void *tx_end; 386 void *rx; 387 void *rx_end; 388 enum ssp_reading read; 389 enum ssp_writing write; 390 u32 exp_fifo_level; 391 enum ssp_rx_level_trig rx_lev_trig; 392 enum ssp_tx_level_trig tx_lev_trig; 393 /* DMA settings */ 394 #ifdef CONFIG_DMA_ENGINE 395 struct dma_chan *dma_rx_channel; 396 struct dma_chan *dma_tx_channel; 397 struct sg_table sgt_rx; 398 struct sg_table sgt_tx; 399 char *dummypage; 400 bool dma_running; 401 #endif 402 int cur_cs; 403 int *chipselects; 404 }; 405 406 /** 407 * struct chip_data - To maintain runtime state of SSP for each client chip 408 * @cr0: Value of control register CR0 of SSP - on later ST variants this 409 * register is 32 bits wide rather than just 16 410 * @cr1: Value of control register CR1 of SSP 411 * @dmacr: Value of DMA control Register of SSP 412 * @cpsr: Value of Clock prescale register 413 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 414 * @enable_dma: Whether to enable DMA or not 415 * @read: function ptr to be used to read when doing xfer for this chip 416 * @write: function ptr to be used to write when doing xfer for this chip 417 * @cs_control: chip select callback provided by chip 418 * @xfer_type: polling/interrupt/DMA 419 * 420 * Runtime state of the SSP controller, maintained per chip, 421 * This would be set according to the current message that would be served 422 */ 423 struct chip_data { 424 u32 cr0; 425 u16 cr1; 426 u16 dmacr; 427 u16 cpsr; 428 u8 n_bytes; 429 bool enable_dma; 430 enum ssp_reading read; 431 enum ssp_writing write; 432 void (*cs_control) (u32 command); 433 int xfer_type; 434 }; 435 436 /** 437 * null_cs_control - Dummy chip select function 438 * @command: select/delect the chip 439 * 440 * If no chip select function is provided by client this is used as dummy 441 * chip select 442 */ 443 static void null_cs_control(u32 command) 444 { 445 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 446 } 447 448 static void pl022_cs_control(struct pl022 *pl022, u32 command) 449 { 450 if (gpio_is_valid(pl022->cur_cs)) 451 gpio_set_value(pl022->cur_cs, command); 452 else 453 pl022->cur_chip->cs_control(command); 454 } 455 456 /** 457 * giveback - current spi_message is over, schedule next message and call 458 * callback of this message. Assumes that caller already 459 * set message->status; dma and pio irqs are blocked 460 * @pl022: SSP driver private data structure 461 */ 462 static void giveback(struct pl022 *pl022) 463 { 464 struct spi_transfer *last_transfer; 465 pl022->next_msg_cs_active = false; 466 467 last_transfer = list_entry(pl022->cur_msg->transfers.prev, 468 struct spi_transfer, 469 transfer_list); 470 471 /* Delay if requested before any change in chip select */ 472 if (last_transfer->delay_usecs) 473 /* 474 * FIXME: This runs in interrupt context. 475 * Is this really smart? 476 */ 477 udelay(last_transfer->delay_usecs); 478 479 if (!last_transfer->cs_change) { 480 struct spi_message *next_msg; 481 482 /* 483 * cs_change was not set. We can keep the chip select 484 * enabled if there is message in the queue and it is 485 * for the same spi device. 486 * 487 * We cannot postpone this until pump_messages, because 488 * after calling msg->complete (below) the driver that 489 * sent the current message could be unloaded, which 490 * could invalidate the cs_control() callback... 491 */ 492 /* get a pointer to the next message, if any */ 493 next_msg = spi_get_next_queued_message(pl022->master); 494 495 /* 496 * see if the next and current messages point 497 * to the same spi device. 498 */ 499 if (next_msg && next_msg->spi != pl022->cur_msg->spi) 500 next_msg = NULL; 501 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 502 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 503 else 504 pl022->next_msg_cs_active = true; 505 506 } 507 508 pl022->cur_msg = NULL; 509 pl022->cur_transfer = NULL; 510 pl022->cur_chip = NULL; 511 spi_finalize_current_message(pl022->master); 512 513 /* disable the SPI/SSP operation */ 514 writew((readw(SSP_CR1(pl022->virtbase)) & 515 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 516 517 } 518 519 /** 520 * flush - flush the FIFO to reach a clean state 521 * @pl022: SSP driver private data structure 522 */ 523 static int flush(struct pl022 *pl022) 524 { 525 unsigned long limit = loops_per_jiffy << 1; 526 527 dev_dbg(&pl022->adev->dev, "flush\n"); 528 do { 529 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 530 readw(SSP_DR(pl022->virtbase)); 531 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 532 533 pl022->exp_fifo_level = 0; 534 535 return limit; 536 } 537 538 /** 539 * restore_state - Load configuration of current chip 540 * @pl022: SSP driver private data structure 541 */ 542 static void restore_state(struct pl022 *pl022) 543 { 544 struct chip_data *chip = pl022->cur_chip; 545 546 if (pl022->vendor->extended_cr) 547 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 548 else 549 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 550 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 551 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 552 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 553 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 554 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 555 } 556 557 /* 558 * Default SSP Register Values 559 */ 560 #define DEFAULT_SSP_REG_CR0 ( \ 561 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 562 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 563 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 564 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 565 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 566 ) 567 568 /* ST versions have slightly different bit layout */ 569 #define DEFAULT_SSP_REG_CR0_ST ( \ 570 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 571 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 572 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 573 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 574 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 575 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 576 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 577 ) 578 579 /* The PL023 version is slightly different again */ 580 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 581 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 582 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 583 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 584 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 585 ) 586 587 #define DEFAULT_SSP_REG_CR1 ( \ 588 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 589 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 590 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 591 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 592 ) 593 594 /* ST versions extend this register to use all 16 bits */ 595 #define DEFAULT_SSP_REG_CR1_ST ( \ 596 DEFAULT_SSP_REG_CR1 | \ 597 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 598 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 599 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 600 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 601 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 602 ) 603 604 /* 605 * The PL023 variant has further differences: no loopback mode, no microwire 606 * support, and a new clock feedback delay setting. 607 */ 608 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 609 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 610 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 611 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 612 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 613 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 614 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 615 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 616 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 617 ) 618 619 #define DEFAULT_SSP_REG_CPSR ( \ 620 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 621 ) 622 623 #define DEFAULT_SSP_REG_DMACR (\ 624 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 625 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 626 ) 627 628 /** 629 * load_ssp_default_config - Load default configuration for SSP 630 * @pl022: SSP driver private data structure 631 */ 632 static void load_ssp_default_config(struct pl022 *pl022) 633 { 634 if (pl022->vendor->pl023) { 635 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 636 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 637 } else if (pl022->vendor->extended_cr) { 638 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 639 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 640 } else { 641 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 642 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 643 } 644 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 645 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 646 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 647 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 648 } 649 650 /** 651 * This will write to TX and read from RX according to the parameters 652 * set in pl022. 653 */ 654 static void readwriter(struct pl022 *pl022) 655 { 656 657 /* 658 * The FIFO depth is different between primecell variants. 659 * I believe filling in too much in the FIFO might cause 660 * errons in 8bit wide transfers on ARM variants (just 8 words 661 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 662 * 663 * To prevent this issue, the TX FIFO is only filled to the 664 * unused RX FIFO fill length, regardless of what the TX 665 * FIFO status flag indicates. 666 */ 667 dev_dbg(&pl022->adev->dev, 668 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 669 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 670 671 /* Read as much as you can */ 672 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 673 && (pl022->rx < pl022->rx_end)) { 674 switch (pl022->read) { 675 case READING_NULL: 676 readw(SSP_DR(pl022->virtbase)); 677 break; 678 case READING_U8: 679 *(u8 *) (pl022->rx) = 680 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 681 break; 682 case READING_U16: 683 *(u16 *) (pl022->rx) = 684 (u16) readw(SSP_DR(pl022->virtbase)); 685 break; 686 case READING_U32: 687 *(u32 *) (pl022->rx) = 688 readl(SSP_DR(pl022->virtbase)); 689 break; 690 } 691 pl022->rx += (pl022->cur_chip->n_bytes); 692 pl022->exp_fifo_level--; 693 } 694 /* 695 * Write as much as possible up to the RX FIFO size 696 */ 697 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 698 && (pl022->tx < pl022->tx_end)) { 699 switch (pl022->write) { 700 case WRITING_NULL: 701 writew(0x0, SSP_DR(pl022->virtbase)); 702 break; 703 case WRITING_U8: 704 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 705 break; 706 case WRITING_U16: 707 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 708 break; 709 case WRITING_U32: 710 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 711 break; 712 } 713 pl022->tx += (pl022->cur_chip->n_bytes); 714 pl022->exp_fifo_level++; 715 /* 716 * This inner reader takes care of things appearing in the RX 717 * FIFO as we're transmitting. This will happen a lot since the 718 * clock starts running when you put things into the TX FIFO, 719 * and then things are continuously clocked into the RX FIFO. 720 */ 721 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 722 && (pl022->rx < pl022->rx_end)) { 723 switch (pl022->read) { 724 case READING_NULL: 725 readw(SSP_DR(pl022->virtbase)); 726 break; 727 case READING_U8: 728 *(u8 *) (pl022->rx) = 729 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 730 break; 731 case READING_U16: 732 *(u16 *) (pl022->rx) = 733 (u16) readw(SSP_DR(pl022->virtbase)); 734 break; 735 case READING_U32: 736 *(u32 *) (pl022->rx) = 737 readl(SSP_DR(pl022->virtbase)); 738 break; 739 } 740 pl022->rx += (pl022->cur_chip->n_bytes); 741 pl022->exp_fifo_level--; 742 } 743 } 744 /* 745 * When we exit here the TX FIFO should be full and the RX FIFO 746 * should be empty 747 */ 748 } 749 750 /** 751 * next_transfer - Move to the Next transfer in the current spi message 752 * @pl022: SSP driver private data structure 753 * 754 * This function moves though the linked list of spi transfers in the 755 * current spi message and returns with the state of current spi 756 * message i.e whether its last transfer is done(STATE_DONE) or 757 * Next transfer is ready(STATE_RUNNING) 758 */ 759 static void *next_transfer(struct pl022 *pl022) 760 { 761 struct spi_message *msg = pl022->cur_msg; 762 struct spi_transfer *trans = pl022->cur_transfer; 763 764 /* Move to next transfer */ 765 if (trans->transfer_list.next != &msg->transfers) { 766 pl022->cur_transfer = 767 list_entry(trans->transfer_list.next, 768 struct spi_transfer, transfer_list); 769 return STATE_RUNNING; 770 } 771 return STATE_DONE; 772 } 773 774 /* 775 * This DMA functionality is only compiled in if we have 776 * access to the generic DMA devices/DMA engine. 777 */ 778 #ifdef CONFIG_DMA_ENGINE 779 static void unmap_free_dma_scatter(struct pl022 *pl022) 780 { 781 /* Unmap and free the SG tables */ 782 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 783 pl022->sgt_tx.nents, DMA_TO_DEVICE); 784 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 785 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 786 sg_free_table(&pl022->sgt_rx); 787 sg_free_table(&pl022->sgt_tx); 788 } 789 790 static void dma_callback(void *data) 791 { 792 struct pl022 *pl022 = data; 793 struct spi_message *msg = pl022->cur_msg; 794 795 BUG_ON(!pl022->sgt_rx.sgl); 796 797 #ifdef VERBOSE_DEBUG 798 /* 799 * Optionally dump out buffers to inspect contents, this is 800 * good if you want to convince yourself that the loopback 801 * read/write contents are the same, when adopting to a new 802 * DMA engine. 803 */ 804 { 805 struct scatterlist *sg; 806 unsigned int i; 807 808 dma_sync_sg_for_cpu(&pl022->adev->dev, 809 pl022->sgt_rx.sgl, 810 pl022->sgt_rx.nents, 811 DMA_FROM_DEVICE); 812 813 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 814 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 815 print_hex_dump(KERN_ERR, "SPI RX: ", 816 DUMP_PREFIX_OFFSET, 817 16, 818 1, 819 sg_virt(sg), 820 sg_dma_len(sg), 821 1); 822 } 823 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 824 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 825 print_hex_dump(KERN_ERR, "SPI TX: ", 826 DUMP_PREFIX_OFFSET, 827 16, 828 1, 829 sg_virt(sg), 830 sg_dma_len(sg), 831 1); 832 } 833 } 834 #endif 835 836 unmap_free_dma_scatter(pl022); 837 838 /* Update total bytes transferred */ 839 msg->actual_length += pl022->cur_transfer->len; 840 if (pl022->cur_transfer->cs_change) 841 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 842 843 /* Move to next transfer */ 844 msg->state = next_transfer(pl022); 845 tasklet_schedule(&pl022->pump_transfers); 846 } 847 848 static void setup_dma_scatter(struct pl022 *pl022, 849 void *buffer, 850 unsigned int length, 851 struct sg_table *sgtab) 852 { 853 struct scatterlist *sg; 854 int bytesleft = length; 855 void *bufp = buffer; 856 int mapbytes; 857 int i; 858 859 if (buffer) { 860 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 861 /* 862 * If there are less bytes left than what fits 863 * in the current page (plus page alignment offset) 864 * we just feed in this, else we stuff in as much 865 * as we can. 866 */ 867 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 868 mapbytes = bytesleft; 869 else 870 mapbytes = PAGE_SIZE - offset_in_page(bufp); 871 sg_set_page(sg, virt_to_page(bufp), 872 mapbytes, offset_in_page(bufp)); 873 bufp += mapbytes; 874 bytesleft -= mapbytes; 875 dev_dbg(&pl022->adev->dev, 876 "set RX/TX target page @ %p, %d bytes, %d left\n", 877 bufp, mapbytes, bytesleft); 878 } 879 } else { 880 /* Map the dummy buffer on every page */ 881 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 882 if (bytesleft < PAGE_SIZE) 883 mapbytes = bytesleft; 884 else 885 mapbytes = PAGE_SIZE; 886 sg_set_page(sg, virt_to_page(pl022->dummypage), 887 mapbytes, 0); 888 bytesleft -= mapbytes; 889 dev_dbg(&pl022->adev->dev, 890 "set RX/TX to dummy page %d bytes, %d left\n", 891 mapbytes, bytesleft); 892 893 } 894 } 895 BUG_ON(bytesleft); 896 } 897 898 /** 899 * configure_dma - configures the channels for the next transfer 900 * @pl022: SSP driver's private data structure 901 */ 902 static int configure_dma(struct pl022 *pl022) 903 { 904 struct dma_slave_config rx_conf = { 905 .src_addr = SSP_DR(pl022->phybase), 906 .direction = DMA_DEV_TO_MEM, 907 .device_fc = false, 908 }; 909 struct dma_slave_config tx_conf = { 910 .dst_addr = SSP_DR(pl022->phybase), 911 .direction = DMA_MEM_TO_DEV, 912 .device_fc = false, 913 }; 914 unsigned int pages; 915 int ret; 916 int rx_sglen, tx_sglen; 917 struct dma_chan *rxchan = pl022->dma_rx_channel; 918 struct dma_chan *txchan = pl022->dma_tx_channel; 919 struct dma_async_tx_descriptor *rxdesc; 920 struct dma_async_tx_descriptor *txdesc; 921 922 /* Check that the channels are available */ 923 if (!rxchan || !txchan) 924 return -ENODEV; 925 926 /* 927 * If supplied, the DMA burstsize should equal the FIFO trigger level. 928 * Notice that the DMA engine uses one-to-one mapping. Since we can 929 * not trigger on 2 elements this needs explicit mapping rather than 930 * calculation. 931 */ 932 switch (pl022->rx_lev_trig) { 933 case SSP_RX_1_OR_MORE_ELEM: 934 rx_conf.src_maxburst = 1; 935 break; 936 case SSP_RX_4_OR_MORE_ELEM: 937 rx_conf.src_maxburst = 4; 938 break; 939 case SSP_RX_8_OR_MORE_ELEM: 940 rx_conf.src_maxburst = 8; 941 break; 942 case SSP_RX_16_OR_MORE_ELEM: 943 rx_conf.src_maxburst = 16; 944 break; 945 case SSP_RX_32_OR_MORE_ELEM: 946 rx_conf.src_maxburst = 32; 947 break; 948 default: 949 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 950 break; 951 } 952 953 switch (pl022->tx_lev_trig) { 954 case SSP_TX_1_OR_MORE_EMPTY_LOC: 955 tx_conf.dst_maxburst = 1; 956 break; 957 case SSP_TX_4_OR_MORE_EMPTY_LOC: 958 tx_conf.dst_maxburst = 4; 959 break; 960 case SSP_TX_8_OR_MORE_EMPTY_LOC: 961 tx_conf.dst_maxburst = 8; 962 break; 963 case SSP_TX_16_OR_MORE_EMPTY_LOC: 964 tx_conf.dst_maxburst = 16; 965 break; 966 case SSP_TX_32_OR_MORE_EMPTY_LOC: 967 tx_conf.dst_maxburst = 32; 968 break; 969 default: 970 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 971 break; 972 } 973 974 switch (pl022->read) { 975 case READING_NULL: 976 /* Use the same as for writing */ 977 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 978 break; 979 case READING_U8: 980 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 981 break; 982 case READING_U16: 983 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 984 break; 985 case READING_U32: 986 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 987 break; 988 } 989 990 switch (pl022->write) { 991 case WRITING_NULL: 992 /* Use the same as for reading */ 993 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 994 break; 995 case WRITING_U8: 996 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 997 break; 998 case WRITING_U16: 999 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1000 break; 1001 case WRITING_U32: 1002 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1003 break; 1004 } 1005 1006 /* SPI pecularity: we need to read and write the same width */ 1007 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1008 rx_conf.src_addr_width = tx_conf.dst_addr_width; 1009 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1010 tx_conf.dst_addr_width = rx_conf.src_addr_width; 1011 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1012 1013 dmaengine_slave_config(rxchan, &rx_conf); 1014 dmaengine_slave_config(txchan, &tx_conf); 1015 1016 /* Create sglists for the transfers */ 1017 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1018 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1019 1020 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1021 if (ret) 1022 goto err_alloc_rx_sg; 1023 1024 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1025 if (ret) 1026 goto err_alloc_tx_sg; 1027 1028 /* Fill in the scatterlists for the RX+TX buffers */ 1029 setup_dma_scatter(pl022, pl022->rx, 1030 pl022->cur_transfer->len, &pl022->sgt_rx); 1031 setup_dma_scatter(pl022, pl022->tx, 1032 pl022->cur_transfer->len, &pl022->sgt_tx); 1033 1034 /* Map DMA buffers */ 1035 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1036 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1037 if (!rx_sglen) 1038 goto err_rx_sgmap; 1039 1040 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1041 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1042 if (!tx_sglen) 1043 goto err_tx_sgmap; 1044 1045 /* Send both scatterlists */ 1046 rxdesc = dmaengine_prep_slave_sg(rxchan, 1047 pl022->sgt_rx.sgl, 1048 rx_sglen, 1049 DMA_DEV_TO_MEM, 1050 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1051 if (!rxdesc) 1052 goto err_rxdesc; 1053 1054 txdesc = dmaengine_prep_slave_sg(txchan, 1055 pl022->sgt_tx.sgl, 1056 tx_sglen, 1057 DMA_MEM_TO_DEV, 1058 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1059 if (!txdesc) 1060 goto err_txdesc; 1061 1062 /* Put the callback on the RX transfer only, that should finish last */ 1063 rxdesc->callback = dma_callback; 1064 rxdesc->callback_param = pl022; 1065 1066 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1067 dmaengine_submit(rxdesc); 1068 dmaengine_submit(txdesc); 1069 dma_async_issue_pending(rxchan); 1070 dma_async_issue_pending(txchan); 1071 pl022->dma_running = true; 1072 1073 return 0; 1074 1075 err_txdesc: 1076 dmaengine_terminate_all(txchan); 1077 err_rxdesc: 1078 dmaengine_terminate_all(rxchan); 1079 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1080 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1081 err_tx_sgmap: 1082 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1083 pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1084 err_rx_sgmap: 1085 sg_free_table(&pl022->sgt_tx); 1086 err_alloc_tx_sg: 1087 sg_free_table(&pl022->sgt_rx); 1088 err_alloc_rx_sg: 1089 return -ENOMEM; 1090 } 1091 1092 static int pl022_dma_probe(struct pl022 *pl022) 1093 { 1094 dma_cap_mask_t mask; 1095 1096 /* Try to acquire a generic DMA engine slave channel */ 1097 dma_cap_zero(mask); 1098 dma_cap_set(DMA_SLAVE, mask); 1099 /* 1100 * We need both RX and TX channels to do DMA, else do none 1101 * of them. 1102 */ 1103 pl022->dma_rx_channel = dma_request_channel(mask, 1104 pl022->master_info->dma_filter, 1105 pl022->master_info->dma_rx_param); 1106 if (!pl022->dma_rx_channel) { 1107 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1108 goto err_no_rxchan; 1109 } 1110 1111 pl022->dma_tx_channel = dma_request_channel(mask, 1112 pl022->master_info->dma_filter, 1113 pl022->master_info->dma_tx_param); 1114 if (!pl022->dma_tx_channel) { 1115 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1116 goto err_no_txchan; 1117 } 1118 1119 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1120 if (!pl022->dummypage) { 1121 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1122 goto err_no_dummypage; 1123 } 1124 1125 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1126 dma_chan_name(pl022->dma_rx_channel), 1127 dma_chan_name(pl022->dma_tx_channel)); 1128 1129 return 0; 1130 1131 err_no_dummypage: 1132 dma_release_channel(pl022->dma_tx_channel); 1133 err_no_txchan: 1134 dma_release_channel(pl022->dma_rx_channel); 1135 pl022->dma_rx_channel = NULL; 1136 err_no_rxchan: 1137 dev_err(&pl022->adev->dev, 1138 "Failed to work in dma mode, work without dma!\n"); 1139 return -ENODEV; 1140 } 1141 1142 static void terminate_dma(struct pl022 *pl022) 1143 { 1144 struct dma_chan *rxchan = pl022->dma_rx_channel; 1145 struct dma_chan *txchan = pl022->dma_tx_channel; 1146 1147 dmaengine_terminate_all(rxchan); 1148 dmaengine_terminate_all(txchan); 1149 unmap_free_dma_scatter(pl022); 1150 pl022->dma_running = false; 1151 } 1152 1153 static void pl022_dma_remove(struct pl022 *pl022) 1154 { 1155 if (pl022->dma_running) 1156 terminate_dma(pl022); 1157 if (pl022->dma_tx_channel) 1158 dma_release_channel(pl022->dma_tx_channel); 1159 if (pl022->dma_rx_channel) 1160 dma_release_channel(pl022->dma_rx_channel); 1161 kfree(pl022->dummypage); 1162 } 1163 1164 #else 1165 static inline int configure_dma(struct pl022 *pl022) 1166 { 1167 return -ENODEV; 1168 } 1169 1170 static inline int pl022_dma_probe(struct pl022 *pl022) 1171 { 1172 return 0; 1173 } 1174 1175 static inline void pl022_dma_remove(struct pl022 *pl022) 1176 { 1177 } 1178 #endif 1179 1180 /** 1181 * pl022_interrupt_handler - Interrupt handler for SSP controller 1182 * 1183 * This function handles interrupts generated for an interrupt based transfer. 1184 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1185 * current message's state as STATE_ERROR and schedule the tasklet 1186 * pump_transfers which will do the postprocessing of the current message by 1187 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1188 * more data, and writes data in TX FIFO till it is not full. If we complete 1189 * the transfer we move to the next transfer and schedule the tasklet. 1190 */ 1191 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1192 { 1193 struct pl022 *pl022 = dev_id; 1194 struct spi_message *msg = pl022->cur_msg; 1195 u16 irq_status = 0; 1196 u16 flag = 0; 1197 1198 if (unlikely(!msg)) { 1199 dev_err(&pl022->adev->dev, 1200 "bad message state in interrupt handler"); 1201 /* Never fail */ 1202 return IRQ_HANDLED; 1203 } 1204 1205 /* Read the Interrupt Status Register */ 1206 irq_status = readw(SSP_MIS(pl022->virtbase)); 1207 1208 if (unlikely(!irq_status)) 1209 return IRQ_NONE; 1210 1211 /* 1212 * This handles the FIFO interrupts, the timeout 1213 * interrupts are flatly ignored, they cannot be 1214 * trusted. 1215 */ 1216 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1217 /* 1218 * Overrun interrupt - bail out since our Data has been 1219 * corrupted 1220 */ 1221 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1222 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1223 dev_err(&pl022->adev->dev, 1224 "RXFIFO is full\n"); 1225 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1226 dev_err(&pl022->adev->dev, 1227 "TXFIFO is full\n"); 1228 1229 /* 1230 * Disable and clear interrupts, disable SSP, 1231 * mark message with bad status so it can be 1232 * retried. 1233 */ 1234 writew(DISABLE_ALL_INTERRUPTS, 1235 SSP_IMSC(pl022->virtbase)); 1236 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1237 writew((readw(SSP_CR1(pl022->virtbase)) & 1238 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1239 msg->state = STATE_ERROR; 1240 1241 /* Schedule message queue handler */ 1242 tasklet_schedule(&pl022->pump_transfers); 1243 return IRQ_HANDLED; 1244 } 1245 1246 readwriter(pl022); 1247 1248 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1249 flag = 1; 1250 /* Disable Transmit interrupt, enable receive interrupt */ 1251 writew((readw(SSP_IMSC(pl022->virtbase)) & 1252 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1253 SSP_IMSC(pl022->virtbase)); 1254 } 1255 1256 /* 1257 * Since all transactions must write as much as shall be read, 1258 * we can conclude the entire transaction once RX is complete. 1259 * At this point, all TX will always be finished. 1260 */ 1261 if (pl022->rx >= pl022->rx_end) { 1262 writew(DISABLE_ALL_INTERRUPTS, 1263 SSP_IMSC(pl022->virtbase)); 1264 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1265 if (unlikely(pl022->rx > pl022->rx_end)) { 1266 dev_warn(&pl022->adev->dev, "read %u surplus " 1267 "bytes (did you request an odd " 1268 "number of bytes on a 16bit bus?)\n", 1269 (u32) (pl022->rx - pl022->rx_end)); 1270 } 1271 /* Update total bytes transferred */ 1272 msg->actual_length += pl022->cur_transfer->len; 1273 if (pl022->cur_transfer->cs_change) 1274 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1275 /* Move to next transfer */ 1276 msg->state = next_transfer(pl022); 1277 tasklet_schedule(&pl022->pump_transfers); 1278 return IRQ_HANDLED; 1279 } 1280 1281 return IRQ_HANDLED; 1282 } 1283 1284 /** 1285 * This sets up the pointers to memory for the next message to 1286 * send out on the SPI bus. 1287 */ 1288 static int set_up_next_transfer(struct pl022 *pl022, 1289 struct spi_transfer *transfer) 1290 { 1291 int residue; 1292 1293 /* Sanity check the message for this bus width */ 1294 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1295 if (unlikely(residue != 0)) { 1296 dev_err(&pl022->adev->dev, 1297 "message of %u bytes to transmit but the current " 1298 "chip bus has a data width of %u bytes!\n", 1299 pl022->cur_transfer->len, 1300 pl022->cur_chip->n_bytes); 1301 dev_err(&pl022->adev->dev, "skipping this message\n"); 1302 return -EIO; 1303 } 1304 pl022->tx = (void *)transfer->tx_buf; 1305 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1306 pl022->rx = (void *)transfer->rx_buf; 1307 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1308 pl022->write = 1309 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1310 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1311 return 0; 1312 } 1313 1314 /** 1315 * pump_transfers - Tasklet function which schedules next transfer 1316 * when running in interrupt or DMA transfer mode. 1317 * @data: SSP driver private data structure 1318 * 1319 */ 1320 static void pump_transfers(unsigned long data) 1321 { 1322 struct pl022 *pl022 = (struct pl022 *) data; 1323 struct spi_message *message = NULL; 1324 struct spi_transfer *transfer = NULL; 1325 struct spi_transfer *previous = NULL; 1326 1327 /* Get current state information */ 1328 message = pl022->cur_msg; 1329 transfer = pl022->cur_transfer; 1330 1331 /* Handle for abort */ 1332 if (message->state == STATE_ERROR) { 1333 message->status = -EIO; 1334 giveback(pl022); 1335 return; 1336 } 1337 1338 /* Handle end of message */ 1339 if (message->state == STATE_DONE) { 1340 message->status = 0; 1341 giveback(pl022); 1342 return; 1343 } 1344 1345 /* Delay if requested at end of transfer before CS change */ 1346 if (message->state == STATE_RUNNING) { 1347 previous = list_entry(transfer->transfer_list.prev, 1348 struct spi_transfer, 1349 transfer_list); 1350 if (previous->delay_usecs) 1351 /* 1352 * FIXME: This runs in interrupt context. 1353 * Is this really smart? 1354 */ 1355 udelay(previous->delay_usecs); 1356 1357 /* Reselect chip select only if cs_change was requested */ 1358 if (previous->cs_change) 1359 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1360 } else { 1361 /* STATE_START */ 1362 message->state = STATE_RUNNING; 1363 } 1364 1365 if (set_up_next_transfer(pl022, transfer)) { 1366 message->state = STATE_ERROR; 1367 message->status = -EIO; 1368 giveback(pl022); 1369 return; 1370 } 1371 /* Flush the FIFOs and let's go! */ 1372 flush(pl022); 1373 1374 if (pl022->cur_chip->enable_dma) { 1375 if (configure_dma(pl022)) { 1376 dev_dbg(&pl022->adev->dev, 1377 "configuration of DMA failed, fall back to interrupt mode\n"); 1378 goto err_config_dma; 1379 } 1380 return; 1381 } 1382 1383 err_config_dma: 1384 /* enable all interrupts except RX */ 1385 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1386 } 1387 1388 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1389 { 1390 /* 1391 * Default is to enable all interrupts except RX - 1392 * this will be enabled once TX is complete 1393 */ 1394 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1395 1396 /* Enable target chip, if not already active */ 1397 if (!pl022->next_msg_cs_active) 1398 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1399 1400 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1401 /* Error path */ 1402 pl022->cur_msg->state = STATE_ERROR; 1403 pl022->cur_msg->status = -EIO; 1404 giveback(pl022); 1405 return; 1406 } 1407 /* If we're using DMA, set up DMA here */ 1408 if (pl022->cur_chip->enable_dma) { 1409 /* Configure DMA transfer */ 1410 if (configure_dma(pl022)) { 1411 dev_dbg(&pl022->adev->dev, 1412 "configuration of DMA failed, fall back to interrupt mode\n"); 1413 goto err_config_dma; 1414 } 1415 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1416 irqflags = DISABLE_ALL_INTERRUPTS; 1417 } 1418 err_config_dma: 1419 /* Enable SSP, turn on interrupts */ 1420 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1421 SSP_CR1(pl022->virtbase)); 1422 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1423 } 1424 1425 static void do_polling_transfer(struct pl022 *pl022) 1426 { 1427 struct spi_message *message = NULL; 1428 struct spi_transfer *transfer = NULL; 1429 struct spi_transfer *previous = NULL; 1430 struct chip_data *chip; 1431 unsigned long time, timeout; 1432 1433 chip = pl022->cur_chip; 1434 message = pl022->cur_msg; 1435 1436 while (message->state != STATE_DONE) { 1437 /* Handle for abort */ 1438 if (message->state == STATE_ERROR) 1439 break; 1440 transfer = pl022->cur_transfer; 1441 1442 /* Delay if requested at end of transfer */ 1443 if (message->state == STATE_RUNNING) { 1444 previous = 1445 list_entry(transfer->transfer_list.prev, 1446 struct spi_transfer, transfer_list); 1447 if (previous->delay_usecs) 1448 udelay(previous->delay_usecs); 1449 if (previous->cs_change) 1450 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1451 } else { 1452 /* STATE_START */ 1453 message->state = STATE_RUNNING; 1454 if (!pl022->next_msg_cs_active) 1455 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1456 } 1457 1458 /* Configuration Changing Per Transfer */ 1459 if (set_up_next_transfer(pl022, transfer)) { 1460 /* Error path */ 1461 message->state = STATE_ERROR; 1462 break; 1463 } 1464 /* Flush FIFOs and enable SSP */ 1465 flush(pl022); 1466 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1467 SSP_CR1(pl022->virtbase)); 1468 1469 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1470 1471 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1472 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1473 time = jiffies; 1474 readwriter(pl022); 1475 if (time_after(time, timeout)) { 1476 dev_warn(&pl022->adev->dev, 1477 "%s: timeout!\n", __func__); 1478 message->state = STATE_ERROR; 1479 goto out; 1480 } 1481 cpu_relax(); 1482 } 1483 1484 /* Update total byte transferred */ 1485 message->actual_length += pl022->cur_transfer->len; 1486 if (pl022->cur_transfer->cs_change) 1487 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1488 /* Move to next transfer */ 1489 message->state = next_transfer(pl022); 1490 } 1491 out: 1492 /* Handle end of message */ 1493 if (message->state == STATE_DONE) 1494 message->status = 0; 1495 else 1496 message->status = -EIO; 1497 1498 giveback(pl022); 1499 return; 1500 } 1501 1502 static int pl022_transfer_one_message(struct spi_master *master, 1503 struct spi_message *msg) 1504 { 1505 struct pl022 *pl022 = spi_master_get_devdata(master); 1506 1507 /* Initial message state */ 1508 pl022->cur_msg = msg; 1509 msg->state = STATE_START; 1510 1511 pl022->cur_transfer = list_entry(msg->transfers.next, 1512 struct spi_transfer, transfer_list); 1513 1514 /* Setup the SPI using the per chip configuration */ 1515 pl022->cur_chip = spi_get_ctldata(msg->spi); 1516 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; 1517 1518 restore_state(pl022); 1519 flush(pl022); 1520 1521 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1522 do_polling_transfer(pl022); 1523 else 1524 do_interrupt_dma_transfer(pl022); 1525 1526 return 0; 1527 } 1528 1529 static int pl022_prepare_transfer_hardware(struct spi_master *master) 1530 { 1531 struct pl022 *pl022 = spi_master_get_devdata(master); 1532 1533 /* 1534 * Just make sure we have all we need to run the transfer by syncing 1535 * with the runtime PM framework. 1536 */ 1537 pm_runtime_get_sync(&pl022->adev->dev); 1538 return 0; 1539 } 1540 1541 static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1542 { 1543 struct pl022 *pl022 = spi_master_get_devdata(master); 1544 1545 /* nothing more to do - disable spi/ssp and power off */ 1546 writew((readw(SSP_CR1(pl022->virtbase)) & 1547 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1548 1549 if (pl022->master_info->autosuspend_delay > 0) { 1550 pm_runtime_mark_last_busy(&pl022->adev->dev); 1551 pm_runtime_put_autosuspend(&pl022->adev->dev); 1552 } else { 1553 pm_runtime_put(&pl022->adev->dev); 1554 } 1555 1556 return 0; 1557 } 1558 1559 static int verify_controller_parameters(struct pl022 *pl022, 1560 struct pl022_config_chip const *chip_info) 1561 { 1562 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1563 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1564 dev_err(&pl022->adev->dev, 1565 "interface is configured incorrectly\n"); 1566 return -EINVAL; 1567 } 1568 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1569 (!pl022->vendor->unidir)) { 1570 dev_err(&pl022->adev->dev, 1571 "unidirectional mode not supported in this " 1572 "hardware version\n"); 1573 return -EINVAL; 1574 } 1575 if ((chip_info->hierarchy != SSP_MASTER) 1576 && (chip_info->hierarchy != SSP_SLAVE)) { 1577 dev_err(&pl022->adev->dev, 1578 "hierarchy is configured incorrectly\n"); 1579 return -EINVAL; 1580 } 1581 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1582 && (chip_info->com_mode != DMA_TRANSFER) 1583 && (chip_info->com_mode != POLLING_TRANSFER)) { 1584 dev_err(&pl022->adev->dev, 1585 "Communication mode is configured incorrectly\n"); 1586 return -EINVAL; 1587 } 1588 switch (chip_info->rx_lev_trig) { 1589 case SSP_RX_1_OR_MORE_ELEM: 1590 case SSP_RX_4_OR_MORE_ELEM: 1591 case SSP_RX_8_OR_MORE_ELEM: 1592 /* These are always OK, all variants can handle this */ 1593 break; 1594 case SSP_RX_16_OR_MORE_ELEM: 1595 if (pl022->vendor->fifodepth < 16) { 1596 dev_err(&pl022->adev->dev, 1597 "RX FIFO Trigger Level is configured incorrectly\n"); 1598 return -EINVAL; 1599 } 1600 break; 1601 case SSP_RX_32_OR_MORE_ELEM: 1602 if (pl022->vendor->fifodepth < 32) { 1603 dev_err(&pl022->adev->dev, 1604 "RX FIFO Trigger Level is configured incorrectly\n"); 1605 return -EINVAL; 1606 } 1607 break; 1608 default: 1609 dev_err(&pl022->adev->dev, 1610 "RX FIFO Trigger Level is configured incorrectly\n"); 1611 return -EINVAL; 1612 break; 1613 } 1614 switch (chip_info->tx_lev_trig) { 1615 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1616 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1617 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1618 /* These are always OK, all variants can handle this */ 1619 break; 1620 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1621 if (pl022->vendor->fifodepth < 16) { 1622 dev_err(&pl022->adev->dev, 1623 "TX FIFO Trigger Level is configured incorrectly\n"); 1624 return -EINVAL; 1625 } 1626 break; 1627 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1628 if (pl022->vendor->fifodepth < 32) { 1629 dev_err(&pl022->adev->dev, 1630 "TX FIFO Trigger Level is configured incorrectly\n"); 1631 return -EINVAL; 1632 } 1633 break; 1634 default: 1635 dev_err(&pl022->adev->dev, 1636 "TX FIFO Trigger Level is configured incorrectly\n"); 1637 return -EINVAL; 1638 break; 1639 } 1640 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1641 if ((chip_info->ctrl_len < SSP_BITS_4) 1642 || (chip_info->ctrl_len > SSP_BITS_32)) { 1643 dev_err(&pl022->adev->dev, 1644 "CTRL LEN is configured incorrectly\n"); 1645 return -EINVAL; 1646 } 1647 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1648 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1649 dev_err(&pl022->adev->dev, 1650 "Wait State is configured incorrectly\n"); 1651 return -EINVAL; 1652 } 1653 /* Half duplex is only available in the ST Micro version */ 1654 if (pl022->vendor->extended_cr) { 1655 if ((chip_info->duplex != 1656 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1657 && (chip_info->duplex != 1658 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1659 dev_err(&pl022->adev->dev, 1660 "Microwire duplex mode is configured incorrectly\n"); 1661 return -EINVAL; 1662 } 1663 } else { 1664 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1665 dev_err(&pl022->adev->dev, 1666 "Microwire half duplex mode requested," 1667 " but this is only available in the" 1668 " ST version of PL022\n"); 1669 return -EINVAL; 1670 } 1671 } 1672 return 0; 1673 } 1674 1675 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1676 { 1677 return rate / (cpsdvsr * (1 + scr)); 1678 } 1679 1680 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1681 ssp_clock_params * clk_freq) 1682 { 1683 /* Lets calculate the frequency parameters */ 1684 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1685 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1686 best_scr = 0, tmp, found = 0; 1687 1688 rate = clk_get_rate(pl022->clk); 1689 /* cpsdvscr = 2 & scr 0 */ 1690 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1691 /* cpsdvsr = 254 & scr = 255 */ 1692 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1693 1694 if (freq > max_tclk) 1695 dev_warn(&pl022->adev->dev, 1696 "Max speed that can be programmed is %d Hz, you requested %d\n", 1697 max_tclk, freq); 1698 1699 if (freq < min_tclk) { 1700 dev_err(&pl022->adev->dev, 1701 "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1702 freq, min_tclk); 1703 return -EINVAL; 1704 } 1705 1706 /* 1707 * best_freq will give closest possible available rate (<= requested 1708 * freq) for all values of scr & cpsdvsr. 1709 */ 1710 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1711 while (scr <= SCR_MAX) { 1712 tmp = spi_rate(rate, cpsdvsr, scr); 1713 1714 if (tmp > freq) { 1715 /* we need lower freq */ 1716 scr++; 1717 continue; 1718 } 1719 1720 /* 1721 * If found exact value, mark found and break. 1722 * If found more closer value, update and break. 1723 */ 1724 if (tmp > best_freq) { 1725 best_freq = tmp; 1726 best_cpsdvsr = cpsdvsr; 1727 best_scr = scr; 1728 1729 if (tmp == freq) 1730 found = 1; 1731 } 1732 /* 1733 * increased scr will give lower rates, which are not 1734 * required 1735 */ 1736 break; 1737 } 1738 cpsdvsr += 2; 1739 scr = SCR_MIN; 1740 } 1741 1742 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 1743 freq); 1744 1745 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1746 clk_freq->scr = (u8) (best_scr & 0xFF); 1747 dev_dbg(&pl022->adev->dev, 1748 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1749 freq, best_freq); 1750 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1751 clk_freq->cpsdvsr, clk_freq->scr); 1752 1753 return 0; 1754 } 1755 1756 /* 1757 * A piece of default chip info unless the platform 1758 * supplies it. 1759 */ 1760 static const struct pl022_config_chip pl022_default_chip_info = { 1761 .com_mode = POLLING_TRANSFER, 1762 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1763 .hierarchy = SSP_SLAVE, 1764 .slave_tx_disable = DO_NOT_DRIVE_TX, 1765 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1766 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1767 .ctrl_len = SSP_BITS_8, 1768 .wait_state = SSP_MWIRE_WAIT_ZERO, 1769 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1770 .cs_control = null_cs_control, 1771 }; 1772 1773 /** 1774 * pl022_setup - setup function registered to SPI master framework 1775 * @spi: spi device which is requesting setup 1776 * 1777 * This function is registered to the SPI framework for this SPI master 1778 * controller. If it is the first time when setup is called by this device, 1779 * this function will initialize the runtime state for this chip and save 1780 * the same in the device structure. Else it will update the runtime info 1781 * with the updated chip info. Nothing is really being written to the 1782 * controller hardware here, that is not done until the actual transfer 1783 * commence. 1784 */ 1785 static int pl022_setup(struct spi_device *spi) 1786 { 1787 struct pl022_config_chip const *chip_info; 1788 struct pl022_config_chip chip_info_dt; 1789 struct chip_data *chip; 1790 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1791 int status = 0; 1792 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1793 unsigned int bits = spi->bits_per_word; 1794 u32 tmp; 1795 struct device_node *np = spi->dev.of_node; 1796 1797 if (!spi->max_speed_hz) 1798 return -EINVAL; 1799 1800 /* Get controller_state if one is supplied */ 1801 chip = spi_get_ctldata(spi); 1802 1803 if (chip == NULL) { 1804 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1805 if (!chip) { 1806 dev_err(&spi->dev, 1807 "cannot allocate controller state\n"); 1808 return -ENOMEM; 1809 } 1810 dev_dbg(&spi->dev, 1811 "allocated memory for controller's runtime state\n"); 1812 } 1813 1814 /* Get controller data if one is supplied */ 1815 chip_info = spi->controller_data; 1816 1817 if (chip_info == NULL) { 1818 if (np) { 1819 chip_info_dt = pl022_default_chip_info; 1820 1821 chip_info_dt.hierarchy = SSP_MASTER; 1822 of_property_read_u32(np, "pl022,interface", 1823 &chip_info_dt.iface); 1824 of_property_read_u32(np, "pl022,com-mode", 1825 &chip_info_dt.com_mode); 1826 of_property_read_u32(np, "pl022,rx-level-trig", 1827 &chip_info_dt.rx_lev_trig); 1828 of_property_read_u32(np, "pl022,tx-level-trig", 1829 &chip_info_dt.tx_lev_trig); 1830 of_property_read_u32(np, "pl022,ctrl-len", 1831 &chip_info_dt.ctrl_len); 1832 of_property_read_u32(np, "pl022,wait-state", 1833 &chip_info_dt.wait_state); 1834 of_property_read_u32(np, "pl022,duplex", 1835 &chip_info_dt.duplex); 1836 1837 chip_info = &chip_info_dt; 1838 } else { 1839 chip_info = &pl022_default_chip_info; 1840 /* spi_board_info.controller_data not is supplied */ 1841 dev_dbg(&spi->dev, 1842 "using default controller_data settings\n"); 1843 } 1844 } else 1845 dev_dbg(&spi->dev, 1846 "using user supplied controller_data settings\n"); 1847 1848 /* 1849 * We can override with custom divisors, else we use the board 1850 * frequency setting 1851 */ 1852 if ((0 == chip_info->clk_freq.cpsdvsr) 1853 && (0 == chip_info->clk_freq.scr)) { 1854 status = calculate_effective_freq(pl022, 1855 spi->max_speed_hz, 1856 &clk_freq); 1857 if (status < 0) 1858 goto err_config_params; 1859 } else { 1860 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1861 if ((clk_freq.cpsdvsr % 2) != 0) 1862 clk_freq.cpsdvsr = 1863 clk_freq.cpsdvsr - 1; 1864 } 1865 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1866 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1867 status = -EINVAL; 1868 dev_err(&spi->dev, 1869 "cpsdvsr is configured incorrectly\n"); 1870 goto err_config_params; 1871 } 1872 1873 status = verify_controller_parameters(pl022, chip_info); 1874 if (status) { 1875 dev_err(&spi->dev, "controller data is incorrect"); 1876 goto err_config_params; 1877 } 1878 1879 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1880 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1881 1882 /* Now set controller state based on controller data */ 1883 chip->xfer_type = chip_info->com_mode; 1884 if (!chip_info->cs_control) { 1885 chip->cs_control = null_cs_control; 1886 if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) 1887 dev_warn(&spi->dev, 1888 "invalid chip select\n"); 1889 } else 1890 chip->cs_control = chip_info->cs_control; 1891 1892 /* Check bits per word with vendor specific range */ 1893 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1894 status = -ENOTSUPP; 1895 dev_err(&spi->dev, "illegal data size for this controller!\n"); 1896 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1897 pl022->vendor->max_bpw); 1898 goto err_config_params; 1899 } else if (bits <= 8) { 1900 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1901 chip->n_bytes = 1; 1902 chip->read = READING_U8; 1903 chip->write = WRITING_U8; 1904 } else if (bits <= 16) { 1905 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1906 chip->n_bytes = 2; 1907 chip->read = READING_U16; 1908 chip->write = WRITING_U16; 1909 } else { 1910 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1911 chip->n_bytes = 4; 1912 chip->read = READING_U32; 1913 chip->write = WRITING_U32; 1914 } 1915 1916 /* Now Initialize all register settings required for this chip */ 1917 chip->cr0 = 0; 1918 chip->cr1 = 0; 1919 chip->dmacr = 0; 1920 chip->cpsr = 0; 1921 if ((chip_info->com_mode == DMA_TRANSFER) 1922 && ((pl022->master_info)->enable_dma)) { 1923 chip->enable_dma = true; 1924 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1925 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1926 SSP_DMACR_MASK_RXDMAE, 0); 1927 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1928 SSP_DMACR_MASK_TXDMAE, 1); 1929 } else { 1930 chip->enable_dma = false; 1931 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1932 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1933 SSP_DMACR_MASK_RXDMAE, 0); 1934 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1935 SSP_DMACR_MASK_TXDMAE, 1); 1936 } 1937 1938 chip->cpsr = clk_freq.cpsdvsr; 1939 1940 /* Special setup for the ST micro extended control registers */ 1941 if (pl022->vendor->extended_cr) { 1942 u32 etx; 1943 1944 if (pl022->vendor->pl023) { 1945 /* These bits are only in the PL023 */ 1946 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1947 SSP_CR1_MASK_FBCLKDEL_ST, 13); 1948 } else { 1949 /* These bits are in the PL022 but not PL023 */ 1950 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1951 SSP_CR0_MASK_HALFDUP_ST, 5); 1952 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1953 SSP_CR0_MASK_CSS_ST, 16); 1954 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1955 SSP_CR0_MASK_FRF_ST, 21); 1956 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 1957 SSP_CR1_MASK_MWAIT_ST, 6); 1958 } 1959 SSP_WRITE_BITS(chip->cr0, bits - 1, 1960 SSP_CR0_MASK_DSS_ST, 0); 1961 1962 if (spi->mode & SPI_LSB_FIRST) { 1963 tmp = SSP_RX_LSB; 1964 etx = SSP_TX_LSB; 1965 } else { 1966 tmp = SSP_RX_MSB; 1967 etx = SSP_TX_MSB; 1968 } 1969 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 1970 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 1971 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 1972 SSP_CR1_MASK_RXIFLSEL_ST, 7); 1973 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 1974 SSP_CR1_MASK_TXIFLSEL_ST, 10); 1975 } else { 1976 SSP_WRITE_BITS(chip->cr0, bits - 1, 1977 SSP_CR0_MASK_DSS, 0); 1978 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1979 SSP_CR0_MASK_FRF, 4); 1980 } 1981 1982 /* Stuff that is common for all versions */ 1983 if (spi->mode & SPI_CPOL) 1984 tmp = SSP_CLK_POL_IDLE_HIGH; 1985 else 1986 tmp = SSP_CLK_POL_IDLE_LOW; 1987 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 1988 1989 if (spi->mode & SPI_CPHA) 1990 tmp = SSP_CLK_SECOND_EDGE; 1991 else 1992 tmp = SSP_CLK_FIRST_EDGE; 1993 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 1994 1995 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 1996 /* Loopback is available on all versions except PL023 */ 1997 if (pl022->vendor->loopback) { 1998 if (spi->mode & SPI_LOOP) 1999 tmp = LOOPBACK_ENABLED; 2000 else 2001 tmp = LOOPBACK_DISABLED; 2002 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2003 } 2004 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2005 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2006 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2007 3); 2008 2009 /* Save controller_state */ 2010 spi_set_ctldata(spi, chip); 2011 return status; 2012 err_config_params: 2013 spi_set_ctldata(spi, NULL); 2014 kfree(chip); 2015 return status; 2016 } 2017 2018 /** 2019 * pl022_cleanup - cleanup function registered to SPI master framework 2020 * @spi: spi device which is requesting cleanup 2021 * 2022 * This function is registered to the SPI framework for this SPI master 2023 * controller. It will free the runtime state of chip. 2024 */ 2025 static void pl022_cleanup(struct spi_device *spi) 2026 { 2027 struct chip_data *chip = spi_get_ctldata(spi); 2028 2029 spi_set_ctldata(spi, NULL); 2030 kfree(chip); 2031 } 2032 2033 static struct pl022_ssp_controller * 2034 pl022_platform_data_dt_get(struct device *dev) 2035 { 2036 struct device_node *np = dev->of_node; 2037 struct pl022_ssp_controller *pd; 2038 u32 tmp; 2039 2040 if (!np) { 2041 dev_err(dev, "no dt node defined\n"); 2042 return NULL; 2043 } 2044 2045 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); 2046 if (!pd) { 2047 dev_err(dev, "cannot allocate platform data memory\n"); 2048 return NULL; 2049 } 2050 2051 pd->bus_id = -1; 2052 of_property_read_u32(np, "num-cs", &tmp); 2053 pd->num_chipselect = tmp; 2054 of_property_read_u32(np, "pl022,autosuspend-delay", 2055 &pd->autosuspend_delay); 2056 pd->rt = of_property_read_bool(np, "pl022,rt"); 2057 2058 return pd; 2059 } 2060 2061 static int pl022_probe(struct amba_device *adev, const struct amba_id *id) 2062 { 2063 struct device *dev = &adev->dev; 2064 struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2065 struct spi_master *master; 2066 struct pl022 *pl022 = NULL; /*Data for this driver */ 2067 struct device_node *np = adev->dev.of_node; 2068 int status = 0, i, num_cs; 2069 2070 dev_info(&adev->dev, 2071 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2072 if (!platform_info && IS_ENABLED(CONFIG_OF)) 2073 platform_info = pl022_platform_data_dt_get(dev); 2074 2075 if (!platform_info) { 2076 dev_err(dev, "probe: no platform data defined\n"); 2077 return -ENODEV; 2078 } 2079 2080 if (platform_info->num_chipselect) { 2081 num_cs = platform_info->num_chipselect; 2082 } else { 2083 dev_err(dev, "probe: no chip select defined\n"); 2084 return -ENODEV; 2085 } 2086 2087 /* Allocate master with space for data */ 2088 master = spi_alloc_master(dev, sizeof(struct pl022)); 2089 if (master == NULL) { 2090 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2091 return -ENOMEM; 2092 } 2093 2094 pl022 = spi_master_get_devdata(master); 2095 pl022->master = master; 2096 pl022->master_info = platform_info; 2097 pl022->adev = adev; 2098 pl022->vendor = id->data; 2099 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), 2100 GFP_KERNEL); 2101 2102 pl022->pinctrl = devm_pinctrl_get(dev); 2103 if (IS_ERR(pl022->pinctrl)) { 2104 status = PTR_ERR(pl022->pinctrl); 2105 goto err_no_pinctrl; 2106 } 2107 2108 pl022->pins_default = pinctrl_lookup_state(pl022->pinctrl, 2109 PINCTRL_STATE_DEFAULT); 2110 /* enable pins to be muxed in and configured */ 2111 if (!IS_ERR(pl022->pins_default)) { 2112 status = pinctrl_select_state(pl022->pinctrl, 2113 pl022->pins_default); 2114 if (status) 2115 dev_err(dev, "could not set default pins\n"); 2116 } else 2117 dev_err(dev, "could not get default pinstate\n"); 2118 2119 pl022->pins_idle = pinctrl_lookup_state(pl022->pinctrl, 2120 PINCTRL_STATE_IDLE); 2121 if (IS_ERR(pl022->pins_idle)) 2122 dev_dbg(dev, "could not get idle pinstate\n"); 2123 2124 pl022->pins_sleep = pinctrl_lookup_state(pl022->pinctrl, 2125 PINCTRL_STATE_SLEEP); 2126 if (IS_ERR(pl022->pins_sleep)) 2127 dev_dbg(dev, "could not get sleep pinstate\n"); 2128 2129 /* 2130 * Bus Number Which has been Assigned to this SSP controller 2131 * on this board 2132 */ 2133 master->bus_num = platform_info->bus_id; 2134 master->num_chipselect = num_cs; 2135 master->cleanup = pl022_cleanup; 2136 master->setup = pl022_setup; 2137 master->prepare_transfer_hardware = pl022_prepare_transfer_hardware; 2138 master->transfer_one_message = pl022_transfer_one_message; 2139 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2140 master->rt = platform_info->rt; 2141 master->dev.of_node = dev->of_node; 2142 2143 if (platform_info->num_chipselect && platform_info->chipselects) { 2144 for (i = 0; i < num_cs; i++) 2145 pl022->chipselects[i] = platform_info->chipselects[i]; 2146 } else if (IS_ENABLED(CONFIG_OF)) { 2147 for (i = 0; i < num_cs; i++) { 2148 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 2149 2150 if (cs_gpio == -EPROBE_DEFER) { 2151 status = -EPROBE_DEFER; 2152 goto err_no_gpio; 2153 } 2154 2155 pl022->chipselects[i] = cs_gpio; 2156 2157 if (gpio_is_valid(cs_gpio)) { 2158 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) 2159 dev_err(&adev->dev, 2160 "could not request %d gpio\n", 2161 cs_gpio); 2162 else if (gpio_direction_output(cs_gpio, 1)) 2163 dev_err(&adev->dev, 2164 "could set gpio %d as output\n", 2165 cs_gpio); 2166 } 2167 } 2168 } 2169 2170 /* 2171 * Supports mode 0-3, loopback, and active low CS. Transfers are 2172 * always MS bit first on the original pl022. 2173 */ 2174 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2175 if (pl022->vendor->extended_cr) 2176 master->mode_bits |= SPI_LSB_FIRST; 2177 2178 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2179 2180 status = amba_request_regions(adev, NULL); 2181 if (status) 2182 goto err_no_ioregion; 2183 2184 pl022->phybase = adev->res.start; 2185 pl022->virtbase = devm_ioremap(dev, adev->res.start, 2186 resource_size(&adev->res)); 2187 if (pl022->virtbase == NULL) { 2188 status = -ENOMEM; 2189 goto err_no_ioremap; 2190 } 2191 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2192 adev->res.start, pl022->virtbase); 2193 2194 pl022->clk = devm_clk_get(&adev->dev, NULL); 2195 if (IS_ERR(pl022->clk)) { 2196 status = PTR_ERR(pl022->clk); 2197 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2198 goto err_no_clk; 2199 } 2200 2201 status = clk_prepare(pl022->clk); 2202 if (status) { 2203 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 2204 goto err_clk_prep; 2205 } 2206 2207 status = clk_enable(pl022->clk); 2208 if (status) { 2209 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2210 goto err_no_clk_en; 2211 } 2212 2213 /* Initialize transfer pump */ 2214 tasklet_init(&pl022->pump_transfers, pump_transfers, 2215 (unsigned long)pl022); 2216 2217 /* Disable SSP */ 2218 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2219 SSP_CR1(pl022->virtbase)); 2220 load_ssp_default_config(pl022); 2221 2222 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, 2223 0, "pl022", pl022); 2224 if (status < 0) { 2225 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2226 goto err_no_irq; 2227 } 2228 2229 /* Get DMA channels */ 2230 if (platform_info->enable_dma) { 2231 status = pl022_dma_probe(pl022); 2232 if (status != 0) 2233 platform_info->enable_dma = 0; 2234 } 2235 2236 /* Register with the SPI framework */ 2237 amba_set_drvdata(adev, pl022); 2238 status = spi_register_master(master); 2239 if (status != 0) { 2240 dev_err(&adev->dev, 2241 "probe - problem registering spi master\n"); 2242 goto err_spi_register; 2243 } 2244 dev_dbg(dev, "probe succeeded\n"); 2245 2246 /* let runtime pm put suspend */ 2247 if (platform_info->autosuspend_delay > 0) { 2248 dev_info(&adev->dev, 2249 "will use autosuspend for runtime pm, delay %dms\n", 2250 platform_info->autosuspend_delay); 2251 pm_runtime_set_autosuspend_delay(dev, 2252 platform_info->autosuspend_delay); 2253 pm_runtime_use_autosuspend(dev); 2254 } 2255 pm_runtime_put(dev); 2256 2257 return 0; 2258 2259 err_spi_register: 2260 if (platform_info->enable_dma) 2261 pl022_dma_remove(pl022); 2262 err_no_irq: 2263 clk_disable(pl022->clk); 2264 err_no_clk_en: 2265 clk_unprepare(pl022->clk); 2266 err_clk_prep: 2267 err_no_clk: 2268 err_no_ioremap: 2269 amba_release_regions(adev); 2270 err_no_ioregion: 2271 err_no_gpio: 2272 err_no_pinctrl: 2273 spi_master_put(master); 2274 return status; 2275 } 2276 2277 static int 2278 pl022_remove(struct amba_device *adev) 2279 { 2280 struct pl022 *pl022 = amba_get_drvdata(adev); 2281 2282 if (!pl022) 2283 return 0; 2284 2285 /* 2286 * undo pm_runtime_put() in probe. I assume that we're not 2287 * accessing the primecell here. 2288 */ 2289 pm_runtime_get_noresume(&adev->dev); 2290 2291 load_ssp_default_config(pl022); 2292 if (pl022->master_info->enable_dma) 2293 pl022_dma_remove(pl022); 2294 2295 clk_disable(pl022->clk); 2296 clk_unprepare(pl022->clk); 2297 amba_release_regions(adev); 2298 tasklet_disable(&pl022->pump_transfers); 2299 spi_unregister_master(pl022->master); 2300 amba_set_drvdata(adev, NULL); 2301 return 0; 2302 } 2303 2304 #if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME) 2305 /* 2306 * These two functions are used from both suspend/resume and 2307 * the runtime counterparts to handle external resources like 2308 * clocks, pins and regulators when going to sleep. 2309 */ 2310 static void pl022_suspend_resources(struct pl022 *pl022, bool runtime) 2311 { 2312 int ret; 2313 struct pinctrl_state *pins_state; 2314 2315 clk_disable(pl022->clk); 2316 2317 pins_state = runtime ? pl022->pins_idle : pl022->pins_sleep; 2318 /* Optionally let pins go into sleep states */ 2319 if (!IS_ERR(pins_state)) { 2320 ret = pinctrl_select_state(pl022->pinctrl, pins_state); 2321 if (ret) 2322 dev_err(&pl022->adev->dev, "could not set %s pins\n", 2323 runtime ? "idle" : "sleep"); 2324 } 2325 } 2326 2327 static void pl022_resume_resources(struct pl022 *pl022, bool runtime) 2328 { 2329 int ret; 2330 2331 /* Optionaly enable pins to be muxed in and configured */ 2332 /* First go to the default state */ 2333 if (!IS_ERR(pl022->pins_default)) { 2334 ret = pinctrl_select_state(pl022->pinctrl, pl022->pins_default); 2335 if (ret) 2336 dev_err(&pl022->adev->dev, 2337 "could not set default pins\n"); 2338 } 2339 2340 if (!runtime) { 2341 /* Then let's idle the pins until the next transfer happens */ 2342 if (!IS_ERR(pl022->pins_idle)) { 2343 ret = pinctrl_select_state(pl022->pinctrl, 2344 pl022->pins_idle); 2345 if (ret) 2346 dev_err(&pl022->adev->dev, 2347 "could not set idle pins\n"); 2348 } 2349 } 2350 2351 clk_enable(pl022->clk); 2352 } 2353 #endif 2354 2355 #ifdef CONFIG_SUSPEND 2356 static int pl022_suspend(struct device *dev) 2357 { 2358 struct pl022 *pl022 = dev_get_drvdata(dev); 2359 int ret; 2360 2361 ret = spi_master_suspend(pl022->master); 2362 if (ret) { 2363 dev_warn(dev, "cannot suspend master\n"); 2364 return ret; 2365 } 2366 2367 pm_runtime_get_sync(dev); 2368 pl022_suspend_resources(pl022, false); 2369 2370 dev_dbg(dev, "suspended\n"); 2371 return 0; 2372 } 2373 2374 static int pl022_resume(struct device *dev) 2375 { 2376 struct pl022 *pl022 = dev_get_drvdata(dev); 2377 int ret; 2378 2379 pl022_resume_resources(pl022, false); 2380 pm_runtime_put(dev); 2381 2382 /* Start the queue running */ 2383 ret = spi_master_resume(pl022->master); 2384 if (ret) 2385 dev_err(dev, "problem starting queue (%d)\n", ret); 2386 else 2387 dev_dbg(dev, "resumed\n"); 2388 2389 return ret; 2390 } 2391 #endif /* CONFIG_PM */ 2392 2393 #ifdef CONFIG_PM_RUNTIME 2394 static int pl022_runtime_suspend(struct device *dev) 2395 { 2396 struct pl022 *pl022 = dev_get_drvdata(dev); 2397 2398 pl022_suspend_resources(pl022, true); 2399 return 0; 2400 } 2401 2402 static int pl022_runtime_resume(struct device *dev) 2403 { 2404 struct pl022 *pl022 = dev_get_drvdata(dev); 2405 2406 pl022_resume_resources(pl022, true); 2407 return 0; 2408 } 2409 #endif 2410 2411 static const struct dev_pm_ops pl022_dev_pm_ops = { 2412 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2413 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2414 }; 2415 2416 static struct vendor_data vendor_arm = { 2417 .fifodepth = 8, 2418 .max_bpw = 16, 2419 .unidir = false, 2420 .extended_cr = false, 2421 .pl023 = false, 2422 .loopback = true, 2423 }; 2424 2425 static struct vendor_data vendor_st = { 2426 .fifodepth = 32, 2427 .max_bpw = 32, 2428 .unidir = false, 2429 .extended_cr = true, 2430 .pl023 = false, 2431 .loopback = true, 2432 }; 2433 2434 static struct vendor_data vendor_st_pl023 = { 2435 .fifodepth = 32, 2436 .max_bpw = 32, 2437 .unidir = false, 2438 .extended_cr = true, 2439 .pl023 = true, 2440 .loopback = false, 2441 }; 2442 2443 static struct amba_id pl022_ids[] = { 2444 { 2445 /* 2446 * ARM PL022 variant, this has a 16bit wide 2447 * and 8 locations deep TX/RX FIFO 2448 */ 2449 .id = 0x00041022, 2450 .mask = 0x000fffff, 2451 .data = &vendor_arm, 2452 }, 2453 { 2454 /* 2455 * ST Micro derivative, this has 32bit wide 2456 * and 32 locations deep TX/RX FIFO 2457 */ 2458 .id = 0x01080022, 2459 .mask = 0xffffffff, 2460 .data = &vendor_st, 2461 }, 2462 { 2463 /* 2464 * ST-Ericsson derivative "PL023" (this is not 2465 * an official ARM number), this is a PL022 SSP block 2466 * stripped to SPI mode only, it has 32bit wide 2467 * and 32 locations deep TX/RX FIFO but no extended 2468 * CR0/CR1 register 2469 */ 2470 .id = 0x00080023, 2471 .mask = 0xffffffff, 2472 .data = &vendor_st_pl023, 2473 }, 2474 { 0, 0 }, 2475 }; 2476 2477 MODULE_DEVICE_TABLE(amba, pl022_ids); 2478 2479 static struct amba_driver pl022_driver = { 2480 .drv = { 2481 .name = "ssp-pl022", 2482 .pm = &pl022_dev_pm_ops, 2483 }, 2484 .id_table = pl022_ids, 2485 .probe = pl022_probe, 2486 .remove = pl022_remove, 2487 }; 2488 2489 static int __init pl022_init(void) 2490 { 2491 return amba_driver_register(&pl022_driver); 2492 } 2493 subsys_initcall(pl022_init); 2494 2495 static void __exit pl022_exit(void) 2496 { 2497 amba_driver_unregister(&pl022_driver); 2498 } 2499 module_exit(pl022_exit); 2500 2501 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2502 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2503 MODULE_LICENSE("GPL"); 2504