1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 4 * 5 * Copyright (C) 2008-2012 ST-Ericsson AB 6 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 7 * 8 * Author: Linus Walleij <linus.walleij@stericsson.com> 9 * 10 * Initial version inspired by: 11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 12 * Initial adoption to PL022 by: 13 * Sachin Verma <sachin.verma@st.com> 14 */ 15 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/device.h> 19 #include <linux/ioport.h> 20 #include <linux/errno.h> 21 #include <linux/interrupt.h> 22 #include <linux/spi/spi.h> 23 #include <linux/delay.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 #include <linux/amba/bus.h> 27 #include <linux/amba/pl022.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/dmaengine.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/scatterlist.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/gpio.h> 35 #include <linux/of_gpio.h> 36 #include <linux/pinctrl/consumer.h> 37 38 /* 39 * This macro is used to define some register default values. 40 * reg is masked with mask, the OR:ed with an (again masked) 41 * val shifted sb steps to the left. 42 */ 43 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 44 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 45 46 /* 47 * This macro is also used to define some default values. 48 * It will just shift val by sb steps to the left and mask 49 * the result with mask. 50 */ 51 #define GEN_MASK_BITS(val, mask, sb) \ 52 (((val)<<(sb)) & (mask)) 53 54 #define DRIVE_TX 0 55 #define DO_NOT_DRIVE_TX 1 56 57 #define DO_NOT_QUEUE_DMA 0 58 #define QUEUE_DMA 1 59 60 #define RX_TRANSFER 1 61 #define TX_TRANSFER 2 62 63 /* 64 * Macros to access SSP Registers with their offsets 65 */ 66 #define SSP_CR0(r) (r + 0x000) 67 #define SSP_CR1(r) (r + 0x004) 68 #define SSP_DR(r) (r + 0x008) 69 #define SSP_SR(r) (r + 0x00C) 70 #define SSP_CPSR(r) (r + 0x010) 71 #define SSP_IMSC(r) (r + 0x014) 72 #define SSP_RIS(r) (r + 0x018) 73 #define SSP_MIS(r) (r + 0x01C) 74 #define SSP_ICR(r) (r + 0x020) 75 #define SSP_DMACR(r) (r + 0x024) 76 #define SSP_CSR(r) (r + 0x030) /* vendor extension */ 77 #define SSP_ITCR(r) (r + 0x080) 78 #define SSP_ITIP(r) (r + 0x084) 79 #define SSP_ITOP(r) (r + 0x088) 80 #define SSP_TDR(r) (r + 0x08C) 81 82 #define SSP_PID0(r) (r + 0xFE0) 83 #define SSP_PID1(r) (r + 0xFE4) 84 #define SSP_PID2(r) (r + 0xFE8) 85 #define SSP_PID3(r) (r + 0xFEC) 86 87 #define SSP_CID0(r) (r + 0xFF0) 88 #define SSP_CID1(r) (r + 0xFF4) 89 #define SSP_CID2(r) (r + 0xFF8) 90 #define SSP_CID3(r) (r + 0xFFC) 91 92 /* 93 * SSP Control Register 0 - SSP_CR0 94 */ 95 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 96 #define SSP_CR0_MASK_FRF (0x3UL << 4) 97 #define SSP_CR0_MASK_SPO (0x1UL << 6) 98 #define SSP_CR0_MASK_SPH (0x1UL << 7) 99 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 100 101 /* 102 * The ST version of this block moves som bits 103 * in SSP_CR0 and extends it to 32 bits 104 */ 105 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 106 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 107 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 108 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 109 110 /* 111 * SSP Control Register 0 - SSP_CR1 112 */ 113 #define SSP_CR1_MASK_LBM (0x1UL << 0) 114 #define SSP_CR1_MASK_SSE (0x1UL << 1) 115 #define SSP_CR1_MASK_MS (0x1UL << 2) 116 #define SSP_CR1_MASK_SOD (0x1UL << 3) 117 118 /* 119 * The ST version of this block adds some bits 120 * in SSP_CR1 121 */ 122 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 123 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 124 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 125 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 126 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 127 /* This one is only in the PL023 variant */ 128 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 129 130 /* 131 * SSP Status Register - SSP_SR 132 */ 133 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 134 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 135 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 136 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 137 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 138 139 /* 140 * SSP Clock Prescale Register - SSP_CPSR 141 */ 142 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 143 144 /* 145 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 146 */ 147 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 148 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 149 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 150 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 151 152 /* 153 * SSP Raw Interrupt Status Register - SSP_RIS 154 */ 155 /* Receive Overrun Raw Interrupt status */ 156 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 157 /* Receive Timeout Raw Interrupt status */ 158 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 159 /* Receive FIFO Raw Interrupt status */ 160 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 161 /* Transmit FIFO Raw Interrupt status */ 162 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 163 164 /* 165 * SSP Masked Interrupt Status Register - SSP_MIS 166 */ 167 /* Receive Overrun Masked Interrupt status */ 168 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 169 /* Receive Timeout Masked Interrupt status */ 170 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 171 /* Receive FIFO Masked Interrupt status */ 172 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 173 /* Transmit FIFO Masked Interrupt status */ 174 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 175 176 /* 177 * SSP Interrupt Clear Register - SSP_ICR 178 */ 179 /* Receive Overrun Raw Clear Interrupt bit */ 180 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 181 /* Receive Timeout Clear Interrupt bit */ 182 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 183 184 /* 185 * SSP DMA Control Register - SSP_DMACR 186 */ 187 /* Receive DMA Enable bit */ 188 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 189 /* Transmit DMA Enable bit */ 190 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 191 192 /* 193 * SSP Chip Select Control Register - SSP_CSR 194 * (vendor extension) 195 */ 196 #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0) 197 198 /* 199 * SSP Integration Test control Register - SSP_ITCR 200 */ 201 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 202 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 203 204 /* 205 * SSP Integration Test Input Register - SSP_ITIP 206 */ 207 #define ITIP_MASK_SSPRXD (0x1UL << 0) 208 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 209 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 210 #define ITIP_MASK_RXDMAC (0x1UL << 3) 211 #define ITIP_MASK_TXDMAC (0x1UL << 4) 212 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 213 214 /* 215 * SSP Integration Test output Register - SSP_ITOP 216 */ 217 #define ITOP_MASK_SSPTXD (0x1UL << 0) 218 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 219 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 220 #define ITOP_MASK_SSPOEn (0x1UL << 3) 221 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 222 #define ITOP_MASK_RORINTR (0x1UL << 5) 223 #define ITOP_MASK_RTINTR (0x1UL << 6) 224 #define ITOP_MASK_RXINTR (0x1UL << 7) 225 #define ITOP_MASK_TXINTR (0x1UL << 8) 226 #define ITOP_MASK_INTR (0x1UL << 9) 227 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 228 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 229 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 230 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 231 232 /* 233 * SSP Test Data Register - SSP_TDR 234 */ 235 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 236 237 /* 238 * Message State 239 * we use the spi_message.state (void *) pointer to 240 * hold a single state value, that's why all this 241 * (void *) casting is done here. 242 */ 243 #define STATE_START ((void *) 0) 244 #define STATE_RUNNING ((void *) 1) 245 #define STATE_DONE ((void *) 2) 246 #define STATE_ERROR ((void *) -1) 247 #define STATE_TIMEOUT ((void *) -2) 248 249 /* 250 * SSP State - Whether Enabled or Disabled 251 */ 252 #define SSP_DISABLED (0) 253 #define SSP_ENABLED (1) 254 255 /* 256 * SSP DMA State - Whether DMA Enabled or Disabled 257 */ 258 #define SSP_DMA_DISABLED (0) 259 #define SSP_DMA_ENABLED (1) 260 261 /* 262 * SSP Clock Defaults 263 */ 264 #define SSP_DEFAULT_CLKRATE 0x2 265 #define SSP_DEFAULT_PRESCALE 0x40 266 267 /* 268 * SSP Clock Parameter ranges 269 */ 270 #define CPSDVR_MIN 0x02 271 #define CPSDVR_MAX 0xFE 272 #define SCR_MIN 0x00 273 #define SCR_MAX 0xFF 274 275 /* 276 * SSP Interrupt related Macros 277 */ 278 #define DEFAULT_SSP_REG_IMSC 0x0UL 279 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 280 #define ENABLE_ALL_INTERRUPTS ( \ 281 SSP_IMSC_MASK_RORIM | \ 282 SSP_IMSC_MASK_RTIM | \ 283 SSP_IMSC_MASK_RXIM | \ 284 SSP_IMSC_MASK_TXIM \ 285 ) 286 287 #define CLEAR_ALL_INTERRUPTS 0x3 288 289 #define SPI_POLLING_TIMEOUT 1000 290 291 /* 292 * The type of reading going on on this chip 293 */ 294 enum ssp_reading { 295 READING_NULL, 296 READING_U8, 297 READING_U16, 298 READING_U32 299 }; 300 301 /* 302 * The type of writing going on on this chip 303 */ 304 enum ssp_writing { 305 WRITING_NULL, 306 WRITING_U8, 307 WRITING_U16, 308 WRITING_U32 309 }; 310 311 /** 312 * struct vendor_data - vendor-specific config parameters 313 * for PL022 derivates 314 * @fifodepth: depth of FIFOs (both) 315 * @max_bpw: maximum number of bits per word 316 * @unidir: supports unidirection transfers 317 * @extended_cr: 32 bit wide control register 0 with extra 318 * features and extra features in CR1 as found in the ST variants 319 * @pl023: supports a subset of the ST extensions called "PL023" 320 * @loopback: supports loopback mode 321 * @internal_cs_ctrl: supports chip select control register 322 */ 323 struct vendor_data { 324 int fifodepth; 325 int max_bpw; 326 bool unidir; 327 bool extended_cr; 328 bool pl023; 329 bool loopback; 330 bool internal_cs_ctrl; 331 }; 332 333 /** 334 * struct pl022 - This is the private SSP driver data structure 335 * @adev: AMBA device model hookup 336 * @vendor: vendor data for the IP block 337 * @phybase: the physical memory where the SSP device resides 338 * @virtbase: the virtual memory where the SSP is mapped 339 * @clk: outgoing clock "SPICLK" for the SPI bus 340 * @master: SPI framework hookup 341 * @master_info: controller-specific data from machine setup 342 * @pump_transfers: Tasklet used in Interrupt Transfer mode 343 * @cur_msg: Pointer to current spi_message being processed 344 * @cur_transfer: Pointer to current spi_transfer 345 * @cur_chip: pointer to current clients chip(assigned from controller_state) 346 * @next_msg_cs_active: the next message in the queue has been examined 347 * and it was found that it uses the same chip select as the previous 348 * message, so we left it active after the previous transfer, and it's 349 * active already. 350 * @tx: current position in TX buffer to be read 351 * @tx_end: end position in TX buffer to be read 352 * @rx: current position in RX buffer to be written 353 * @rx_end: end position in RX buffer to be written 354 * @read: the type of read currently going on 355 * @write: the type of write currently going on 356 * @exp_fifo_level: expected FIFO level 357 * @rx_lev_trig: receive FIFO watermark level which triggers IRQ 358 * @tx_lev_trig: transmit FIFO watermark level which triggers IRQ 359 * @dma_rx_channel: optional channel for RX DMA 360 * @dma_tx_channel: optional channel for TX DMA 361 * @sgt_rx: scattertable for the RX transfer 362 * @sgt_tx: scattertable for the TX transfer 363 * @dummypage: a dummy page used for driving data on the bus with DMA 364 * @dma_running: indicates whether DMA is in operation 365 * @cur_cs: current chip select (gpio) 366 * @chipselects: list of chipselects (gpios) 367 */ 368 struct pl022 { 369 struct amba_device *adev; 370 struct vendor_data *vendor; 371 resource_size_t phybase; 372 void __iomem *virtbase; 373 struct clk *clk; 374 struct spi_master *master; 375 struct pl022_ssp_controller *master_info; 376 /* Message per-transfer pump */ 377 struct tasklet_struct pump_transfers; 378 struct spi_message *cur_msg; 379 struct spi_transfer *cur_transfer; 380 struct chip_data *cur_chip; 381 bool next_msg_cs_active; 382 void *tx; 383 void *tx_end; 384 void *rx; 385 void *rx_end; 386 enum ssp_reading read; 387 enum ssp_writing write; 388 u32 exp_fifo_level; 389 enum ssp_rx_level_trig rx_lev_trig; 390 enum ssp_tx_level_trig tx_lev_trig; 391 /* DMA settings */ 392 #ifdef CONFIG_DMA_ENGINE 393 struct dma_chan *dma_rx_channel; 394 struct dma_chan *dma_tx_channel; 395 struct sg_table sgt_rx; 396 struct sg_table sgt_tx; 397 char *dummypage; 398 bool dma_running; 399 #endif 400 int cur_cs; 401 int *chipselects; 402 }; 403 404 /** 405 * struct chip_data - To maintain runtime state of SSP for each client chip 406 * @cr0: Value of control register CR0 of SSP - on later ST variants this 407 * register is 32 bits wide rather than just 16 408 * @cr1: Value of control register CR1 of SSP 409 * @dmacr: Value of DMA control Register of SSP 410 * @cpsr: Value of Clock prescale register 411 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 412 * @enable_dma: Whether to enable DMA or not 413 * @read: function ptr to be used to read when doing xfer for this chip 414 * @write: function ptr to be used to write when doing xfer for this chip 415 * @cs_control: chip select callback provided by chip 416 * @xfer_type: polling/interrupt/DMA 417 * 418 * Runtime state of the SSP controller, maintained per chip, 419 * This would be set according to the current message that would be served 420 */ 421 struct chip_data { 422 u32 cr0; 423 u16 cr1; 424 u16 dmacr; 425 u16 cpsr; 426 u8 n_bytes; 427 bool enable_dma; 428 enum ssp_reading read; 429 enum ssp_writing write; 430 void (*cs_control) (u32 command); 431 int xfer_type; 432 }; 433 434 /** 435 * null_cs_control - Dummy chip select function 436 * @command: select/delect the chip 437 * 438 * If no chip select function is provided by client this is used as dummy 439 * chip select 440 */ 441 static void null_cs_control(u32 command) 442 { 443 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 444 } 445 446 /** 447 * internal_cs_control - Control chip select signals via SSP_CSR. 448 * @pl022: SSP driver private data structure 449 * @command: select/delect the chip 450 * 451 * Used on controller with internal chip select control via SSP_CSR register 452 * (vendor extension). Each of the 5 LSB in the register controls one chip 453 * select signal. 454 */ 455 static void internal_cs_control(struct pl022 *pl022, u32 command) 456 { 457 u32 tmp; 458 459 tmp = readw(SSP_CSR(pl022->virtbase)); 460 if (command == SSP_CHIP_SELECT) 461 tmp &= ~BIT(pl022->cur_cs); 462 else 463 tmp |= BIT(pl022->cur_cs); 464 writew(tmp, SSP_CSR(pl022->virtbase)); 465 } 466 467 static void pl022_cs_control(struct pl022 *pl022, u32 command) 468 { 469 if (pl022->vendor->internal_cs_ctrl) 470 internal_cs_control(pl022, command); 471 else if (gpio_is_valid(pl022->cur_cs)) 472 gpio_set_value(pl022->cur_cs, command); 473 else 474 pl022->cur_chip->cs_control(command); 475 } 476 477 /** 478 * giveback - current spi_message is over, schedule next message and call 479 * callback of this message. Assumes that caller already 480 * set message->status; dma and pio irqs are blocked 481 * @pl022: SSP driver private data structure 482 */ 483 static void giveback(struct pl022 *pl022) 484 { 485 struct spi_transfer *last_transfer; 486 pl022->next_msg_cs_active = false; 487 488 last_transfer = list_last_entry(&pl022->cur_msg->transfers, 489 struct spi_transfer, transfer_list); 490 491 /* Delay if requested before any change in chip select */ 492 /* 493 * FIXME: This runs in interrupt context. 494 * Is this really smart? 495 */ 496 spi_transfer_delay_exec(last_transfer); 497 498 if (!last_transfer->cs_change) { 499 struct spi_message *next_msg; 500 501 /* 502 * cs_change was not set. We can keep the chip select 503 * enabled if there is message in the queue and it is 504 * for the same spi device. 505 * 506 * We cannot postpone this until pump_messages, because 507 * after calling msg->complete (below) the driver that 508 * sent the current message could be unloaded, which 509 * could invalidate the cs_control() callback... 510 */ 511 /* get a pointer to the next message, if any */ 512 next_msg = spi_get_next_queued_message(pl022->master); 513 514 /* 515 * see if the next and current messages point 516 * to the same spi device. 517 */ 518 if (next_msg && next_msg->spi != pl022->cur_msg->spi) 519 next_msg = NULL; 520 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 521 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 522 else 523 pl022->next_msg_cs_active = true; 524 525 } 526 527 pl022->cur_msg = NULL; 528 pl022->cur_transfer = NULL; 529 pl022->cur_chip = NULL; 530 531 /* disable the SPI/SSP operation */ 532 writew((readw(SSP_CR1(pl022->virtbase)) & 533 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 534 535 spi_finalize_current_message(pl022->master); 536 } 537 538 /** 539 * flush - flush the FIFO to reach a clean state 540 * @pl022: SSP driver private data structure 541 */ 542 static int flush(struct pl022 *pl022) 543 { 544 unsigned long limit = loops_per_jiffy << 1; 545 546 dev_dbg(&pl022->adev->dev, "flush\n"); 547 do { 548 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 549 readw(SSP_DR(pl022->virtbase)); 550 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 551 552 pl022->exp_fifo_level = 0; 553 554 return limit; 555 } 556 557 /** 558 * restore_state - Load configuration of current chip 559 * @pl022: SSP driver private data structure 560 */ 561 static void restore_state(struct pl022 *pl022) 562 { 563 struct chip_data *chip = pl022->cur_chip; 564 565 if (pl022->vendor->extended_cr) 566 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 567 else 568 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 569 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 570 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 571 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 572 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 573 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 574 } 575 576 /* 577 * Default SSP Register Values 578 */ 579 #define DEFAULT_SSP_REG_CR0 ( \ 580 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 581 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 582 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 583 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 584 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 585 ) 586 587 /* ST versions have slightly different bit layout */ 588 #define DEFAULT_SSP_REG_CR0_ST ( \ 589 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 590 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 591 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 592 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 593 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 594 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 595 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 596 ) 597 598 /* The PL023 version is slightly different again */ 599 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 600 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 601 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 602 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 603 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 604 ) 605 606 #define DEFAULT_SSP_REG_CR1 ( \ 607 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 608 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 609 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 610 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 611 ) 612 613 /* ST versions extend this register to use all 16 bits */ 614 #define DEFAULT_SSP_REG_CR1_ST ( \ 615 DEFAULT_SSP_REG_CR1 | \ 616 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 617 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 618 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 619 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 620 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 621 ) 622 623 /* 624 * The PL023 variant has further differences: no loopback mode, no microwire 625 * support, and a new clock feedback delay setting. 626 */ 627 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 628 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 629 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 630 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 631 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 632 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 633 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 634 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 635 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 636 ) 637 638 #define DEFAULT_SSP_REG_CPSR ( \ 639 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 640 ) 641 642 #define DEFAULT_SSP_REG_DMACR (\ 643 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 644 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 645 ) 646 647 /** 648 * load_ssp_default_config - Load default configuration for SSP 649 * @pl022: SSP driver private data structure 650 */ 651 static void load_ssp_default_config(struct pl022 *pl022) 652 { 653 if (pl022->vendor->pl023) { 654 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 655 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 656 } else if (pl022->vendor->extended_cr) { 657 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 658 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 659 } else { 660 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 661 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 662 } 663 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 664 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 665 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 666 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 667 } 668 669 /* 670 * This will write to TX and read from RX according to the parameters 671 * set in pl022. 672 */ 673 static void readwriter(struct pl022 *pl022) 674 { 675 676 /* 677 * The FIFO depth is different between primecell variants. 678 * I believe filling in too much in the FIFO might cause 679 * errons in 8bit wide transfers on ARM variants (just 8 words 680 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 681 * 682 * To prevent this issue, the TX FIFO is only filled to the 683 * unused RX FIFO fill length, regardless of what the TX 684 * FIFO status flag indicates. 685 */ 686 dev_dbg(&pl022->adev->dev, 687 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 688 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 689 690 /* Read as much as you can */ 691 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 692 && (pl022->rx < pl022->rx_end)) { 693 switch (pl022->read) { 694 case READING_NULL: 695 readw(SSP_DR(pl022->virtbase)); 696 break; 697 case READING_U8: 698 *(u8 *) (pl022->rx) = 699 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 700 break; 701 case READING_U16: 702 *(u16 *) (pl022->rx) = 703 (u16) readw(SSP_DR(pl022->virtbase)); 704 break; 705 case READING_U32: 706 *(u32 *) (pl022->rx) = 707 readl(SSP_DR(pl022->virtbase)); 708 break; 709 } 710 pl022->rx += (pl022->cur_chip->n_bytes); 711 pl022->exp_fifo_level--; 712 } 713 /* 714 * Write as much as possible up to the RX FIFO size 715 */ 716 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 717 && (pl022->tx < pl022->tx_end)) { 718 switch (pl022->write) { 719 case WRITING_NULL: 720 writew(0x0, SSP_DR(pl022->virtbase)); 721 break; 722 case WRITING_U8: 723 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 724 break; 725 case WRITING_U16: 726 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 727 break; 728 case WRITING_U32: 729 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 730 break; 731 } 732 pl022->tx += (pl022->cur_chip->n_bytes); 733 pl022->exp_fifo_level++; 734 /* 735 * This inner reader takes care of things appearing in the RX 736 * FIFO as we're transmitting. This will happen a lot since the 737 * clock starts running when you put things into the TX FIFO, 738 * and then things are continuously clocked into the RX FIFO. 739 */ 740 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 741 && (pl022->rx < pl022->rx_end)) { 742 switch (pl022->read) { 743 case READING_NULL: 744 readw(SSP_DR(pl022->virtbase)); 745 break; 746 case READING_U8: 747 *(u8 *) (pl022->rx) = 748 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 749 break; 750 case READING_U16: 751 *(u16 *) (pl022->rx) = 752 (u16) readw(SSP_DR(pl022->virtbase)); 753 break; 754 case READING_U32: 755 *(u32 *) (pl022->rx) = 756 readl(SSP_DR(pl022->virtbase)); 757 break; 758 } 759 pl022->rx += (pl022->cur_chip->n_bytes); 760 pl022->exp_fifo_level--; 761 } 762 } 763 /* 764 * When we exit here the TX FIFO should be full and the RX FIFO 765 * should be empty 766 */ 767 } 768 769 /** 770 * next_transfer - Move to the Next transfer in the current spi message 771 * @pl022: SSP driver private data structure 772 * 773 * This function moves though the linked list of spi transfers in the 774 * current spi message and returns with the state of current spi 775 * message i.e whether its last transfer is done(STATE_DONE) or 776 * Next transfer is ready(STATE_RUNNING) 777 */ 778 static void *next_transfer(struct pl022 *pl022) 779 { 780 struct spi_message *msg = pl022->cur_msg; 781 struct spi_transfer *trans = pl022->cur_transfer; 782 783 /* Move to next transfer */ 784 if (trans->transfer_list.next != &msg->transfers) { 785 pl022->cur_transfer = 786 list_entry(trans->transfer_list.next, 787 struct spi_transfer, transfer_list); 788 return STATE_RUNNING; 789 } 790 return STATE_DONE; 791 } 792 793 /* 794 * This DMA functionality is only compiled in if we have 795 * access to the generic DMA devices/DMA engine. 796 */ 797 #ifdef CONFIG_DMA_ENGINE 798 static void unmap_free_dma_scatter(struct pl022 *pl022) 799 { 800 /* Unmap and free the SG tables */ 801 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 802 pl022->sgt_tx.nents, DMA_TO_DEVICE); 803 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 804 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 805 sg_free_table(&pl022->sgt_rx); 806 sg_free_table(&pl022->sgt_tx); 807 } 808 809 static void dma_callback(void *data) 810 { 811 struct pl022 *pl022 = data; 812 struct spi_message *msg = pl022->cur_msg; 813 814 BUG_ON(!pl022->sgt_rx.sgl); 815 816 #ifdef VERBOSE_DEBUG 817 /* 818 * Optionally dump out buffers to inspect contents, this is 819 * good if you want to convince yourself that the loopback 820 * read/write contents are the same, when adopting to a new 821 * DMA engine. 822 */ 823 { 824 struct scatterlist *sg; 825 unsigned int i; 826 827 dma_sync_sg_for_cpu(&pl022->adev->dev, 828 pl022->sgt_rx.sgl, 829 pl022->sgt_rx.nents, 830 DMA_FROM_DEVICE); 831 832 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 833 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 834 print_hex_dump(KERN_ERR, "SPI RX: ", 835 DUMP_PREFIX_OFFSET, 836 16, 837 1, 838 sg_virt(sg), 839 sg_dma_len(sg), 840 1); 841 } 842 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 843 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 844 print_hex_dump(KERN_ERR, "SPI TX: ", 845 DUMP_PREFIX_OFFSET, 846 16, 847 1, 848 sg_virt(sg), 849 sg_dma_len(sg), 850 1); 851 } 852 } 853 #endif 854 855 unmap_free_dma_scatter(pl022); 856 857 /* Update total bytes transferred */ 858 msg->actual_length += pl022->cur_transfer->len; 859 /* Move to next transfer */ 860 msg->state = next_transfer(pl022); 861 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) 862 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 863 tasklet_schedule(&pl022->pump_transfers); 864 } 865 866 static void setup_dma_scatter(struct pl022 *pl022, 867 void *buffer, 868 unsigned int length, 869 struct sg_table *sgtab) 870 { 871 struct scatterlist *sg; 872 int bytesleft = length; 873 void *bufp = buffer; 874 int mapbytes; 875 int i; 876 877 if (buffer) { 878 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 879 /* 880 * If there are less bytes left than what fits 881 * in the current page (plus page alignment offset) 882 * we just feed in this, else we stuff in as much 883 * as we can. 884 */ 885 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 886 mapbytes = bytesleft; 887 else 888 mapbytes = PAGE_SIZE - offset_in_page(bufp); 889 sg_set_page(sg, virt_to_page(bufp), 890 mapbytes, offset_in_page(bufp)); 891 bufp += mapbytes; 892 bytesleft -= mapbytes; 893 dev_dbg(&pl022->adev->dev, 894 "set RX/TX target page @ %p, %d bytes, %d left\n", 895 bufp, mapbytes, bytesleft); 896 } 897 } else { 898 /* Map the dummy buffer on every page */ 899 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 900 if (bytesleft < PAGE_SIZE) 901 mapbytes = bytesleft; 902 else 903 mapbytes = PAGE_SIZE; 904 sg_set_page(sg, virt_to_page(pl022->dummypage), 905 mapbytes, 0); 906 bytesleft -= mapbytes; 907 dev_dbg(&pl022->adev->dev, 908 "set RX/TX to dummy page %d bytes, %d left\n", 909 mapbytes, bytesleft); 910 911 } 912 } 913 BUG_ON(bytesleft); 914 } 915 916 /** 917 * configure_dma - configures the channels for the next transfer 918 * @pl022: SSP driver's private data structure 919 */ 920 static int configure_dma(struct pl022 *pl022) 921 { 922 struct dma_slave_config rx_conf = { 923 .src_addr = SSP_DR(pl022->phybase), 924 .direction = DMA_DEV_TO_MEM, 925 .device_fc = false, 926 }; 927 struct dma_slave_config tx_conf = { 928 .dst_addr = SSP_DR(pl022->phybase), 929 .direction = DMA_MEM_TO_DEV, 930 .device_fc = false, 931 }; 932 unsigned int pages; 933 int ret; 934 int rx_sglen, tx_sglen; 935 struct dma_chan *rxchan = pl022->dma_rx_channel; 936 struct dma_chan *txchan = pl022->dma_tx_channel; 937 struct dma_async_tx_descriptor *rxdesc; 938 struct dma_async_tx_descriptor *txdesc; 939 940 /* Check that the channels are available */ 941 if (!rxchan || !txchan) 942 return -ENODEV; 943 944 /* 945 * If supplied, the DMA burstsize should equal the FIFO trigger level. 946 * Notice that the DMA engine uses one-to-one mapping. Since we can 947 * not trigger on 2 elements this needs explicit mapping rather than 948 * calculation. 949 */ 950 switch (pl022->rx_lev_trig) { 951 case SSP_RX_1_OR_MORE_ELEM: 952 rx_conf.src_maxburst = 1; 953 break; 954 case SSP_RX_4_OR_MORE_ELEM: 955 rx_conf.src_maxburst = 4; 956 break; 957 case SSP_RX_8_OR_MORE_ELEM: 958 rx_conf.src_maxburst = 8; 959 break; 960 case SSP_RX_16_OR_MORE_ELEM: 961 rx_conf.src_maxburst = 16; 962 break; 963 case SSP_RX_32_OR_MORE_ELEM: 964 rx_conf.src_maxburst = 32; 965 break; 966 default: 967 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 968 break; 969 } 970 971 switch (pl022->tx_lev_trig) { 972 case SSP_TX_1_OR_MORE_EMPTY_LOC: 973 tx_conf.dst_maxburst = 1; 974 break; 975 case SSP_TX_4_OR_MORE_EMPTY_LOC: 976 tx_conf.dst_maxburst = 4; 977 break; 978 case SSP_TX_8_OR_MORE_EMPTY_LOC: 979 tx_conf.dst_maxburst = 8; 980 break; 981 case SSP_TX_16_OR_MORE_EMPTY_LOC: 982 tx_conf.dst_maxburst = 16; 983 break; 984 case SSP_TX_32_OR_MORE_EMPTY_LOC: 985 tx_conf.dst_maxburst = 32; 986 break; 987 default: 988 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 989 break; 990 } 991 992 switch (pl022->read) { 993 case READING_NULL: 994 /* Use the same as for writing */ 995 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 996 break; 997 case READING_U8: 998 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 999 break; 1000 case READING_U16: 1001 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1002 break; 1003 case READING_U32: 1004 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1005 break; 1006 } 1007 1008 switch (pl022->write) { 1009 case WRITING_NULL: 1010 /* Use the same as for reading */ 1011 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1012 break; 1013 case WRITING_U8: 1014 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1015 break; 1016 case WRITING_U16: 1017 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1018 break; 1019 case WRITING_U32: 1020 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1021 break; 1022 } 1023 1024 /* SPI pecularity: we need to read and write the same width */ 1025 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1026 rx_conf.src_addr_width = tx_conf.dst_addr_width; 1027 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1028 tx_conf.dst_addr_width = rx_conf.src_addr_width; 1029 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1030 1031 dmaengine_slave_config(rxchan, &rx_conf); 1032 dmaengine_slave_config(txchan, &tx_conf); 1033 1034 /* Create sglists for the transfers */ 1035 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1036 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1037 1038 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1039 if (ret) 1040 goto err_alloc_rx_sg; 1041 1042 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1043 if (ret) 1044 goto err_alloc_tx_sg; 1045 1046 /* Fill in the scatterlists for the RX+TX buffers */ 1047 setup_dma_scatter(pl022, pl022->rx, 1048 pl022->cur_transfer->len, &pl022->sgt_rx); 1049 setup_dma_scatter(pl022, pl022->tx, 1050 pl022->cur_transfer->len, &pl022->sgt_tx); 1051 1052 /* Map DMA buffers */ 1053 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1054 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1055 if (!rx_sglen) 1056 goto err_rx_sgmap; 1057 1058 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1059 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1060 if (!tx_sglen) 1061 goto err_tx_sgmap; 1062 1063 /* Send both scatterlists */ 1064 rxdesc = dmaengine_prep_slave_sg(rxchan, 1065 pl022->sgt_rx.sgl, 1066 rx_sglen, 1067 DMA_DEV_TO_MEM, 1068 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1069 if (!rxdesc) 1070 goto err_rxdesc; 1071 1072 txdesc = dmaengine_prep_slave_sg(txchan, 1073 pl022->sgt_tx.sgl, 1074 tx_sglen, 1075 DMA_MEM_TO_DEV, 1076 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1077 if (!txdesc) 1078 goto err_txdesc; 1079 1080 /* Put the callback on the RX transfer only, that should finish last */ 1081 rxdesc->callback = dma_callback; 1082 rxdesc->callback_param = pl022; 1083 1084 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1085 dmaengine_submit(rxdesc); 1086 dmaengine_submit(txdesc); 1087 dma_async_issue_pending(rxchan); 1088 dma_async_issue_pending(txchan); 1089 pl022->dma_running = true; 1090 1091 return 0; 1092 1093 err_txdesc: 1094 dmaengine_terminate_all(txchan); 1095 err_rxdesc: 1096 dmaengine_terminate_all(rxchan); 1097 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1098 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1099 err_tx_sgmap: 1100 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1101 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1102 err_rx_sgmap: 1103 sg_free_table(&pl022->sgt_tx); 1104 err_alloc_tx_sg: 1105 sg_free_table(&pl022->sgt_rx); 1106 err_alloc_rx_sg: 1107 return -ENOMEM; 1108 } 1109 1110 static int pl022_dma_probe(struct pl022 *pl022) 1111 { 1112 dma_cap_mask_t mask; 1113 1114 /* Try to acquire a generic DMA engine slave channel */ 1115 dma_cap_zero(mask); 1116 dma_cap_set(DMA_SLAVE, mask); 1117 /* 1118 * We need both RX and TX channels to do DMA, else do none 1119 * of them. 1120 */ 1121 pl022->dma_rx_channel = dma_request_channel(mask, 1122 pl022->master_info->dma_filter, 1123 pl022->master_info->dma_rx_param); 1124 if (!pl022->dma_rx_channel) { 1125 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1126 goto err_no_rxchan; 1127 } 1128 1129 pl022->dma_tx_channel = dma_request_channel(mask, 1130 pl022->master_info->dma_filter, 1131 pl022->master_info->dma_tx_param); 1132 if (!pl022->dma_tx_channel) { 1133 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1134 goto err_no_txchan; 1135 } 1136 1137 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1138 if (!pl022->dummypage) 1139 goto err_no_dummypage; 1140 1141 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1142 dma_chan_name(pl022->dma_rx_channel), 1143 dma_chan_name(pl022->dma_tx_channel)); 1144 1145 return 0; 1146 1147 err_no_dummypage: 1148 dma_release_channel(pl022->dma_tx_channel); 1149 err_no_txchan: 1150 dma_release_channel(pl022->dma_rx_channel); 1151 pl022->dma_rx_channel = NULL; 1152 err_no_rxchan: 1153 dev_err(&pl022->adev->dev, 1154 "Failed to work in dma mode, work without dma!\n"); 1155 return -ENODEV; 1156 } 1157 1158 static int pl022_dma_autoprobe(struct pl022 *pl022) 1159 { 1160 struct device *dev = &pl022->adev->dev; 1161 struct dma_chan *chan; 1162 int err; 1163 1164 /* automatically configure DMA channels from platform, normally using DT */ 1165 chan = dma_request_chan(dev, "rx"); 1166 if (IS_ERR(chan)) { 1167 err = PTR_ERR(chan); 1168 goto err_no_rxchan; 1169 } 1170 1171 pl022->dma_rx_channel = chan; 1172 1173 chan = dma_request_chan(dev, "tx"); 1174 if (IS_ERR(chan)) { 1175 err = PTR_ERR(chan); 1176 goto err_no_txchan; 1177 } 1178 1179 pl022->dma_tx_channel = chan; 1180 1181 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1182 if (!pl022->dummypage) { 1183 err = -ENOMEM; 1184 goto err_no_dummypage; 1185 } 1186 1187 return 0; 1188 1189 err_no_dummypage: 1190 dma_release_channel(pl022->dma_tx_channel); 1191 pl022->dma_tx_channel = NULL; 1192 err_no_txchan: 1193 dma_release_channel(pl022->dma_rx_channel); 1194 pl022->dma_rx_channel = NULL; 1195 err_no_rxchan: 1196 return err; 1197 } 1198 1199 static void terminate_dma(struct pl022 *pl022) 1200 { 1201 struct dma_chan *rxchan = pl022->dma_rx_channel; 1202 struct dma_chan *txchan = pl022->dma_tx_channel; 1203 1204 dmaengine_terminate_all(rxchan); 1205 dmaengine_terminate_all(txchan); 1206 unmap_free_dma_scatter(pl022); 1207 pl022->dma_running = false; 1208 } 1209 1210 static void pl022_dma_remove(struct pl022 *pl022) 1211 { 1212 if (pl022->dma_running) 1213 terminate_dma(pl022); 1214 if (pl022->dma_tx_channel) 1215 dma_release_channel(pl022->dma_tx_channel); 1216 if (pl022->dma_rx_channel) 1217 dma_release_channel(pl022->dma_rx_channel); 1218 kfree(pl022->dummypage); 1219 } 1220 1221 #else 1222 static inline int configure_dma(struct pl022 *pl022) 1223 { 1224 return -ENODEV; 1225 } 1226 1227 static inline int pl022_dma_autoprobe(struct pl022 *pl022) 1228 { 1229 return 0; 1230 } 1231 1232 static inline int pl022_dma_probe(struct pl022 *pl022) 1233 { 1234 return 0; 1235 } 1236 1237 static inline void pl022_dma_remove(struct pl022 *pl022) 1238 { 1239 } 1240 #endif 1241 1242 /** 1243 * pl022_interrupt_handler - Interrupt handler for SSP controller 1244 * @irq: IRQ number 1245 * @dev_id: Local device data 1246 * 1247 * This function handles interrupts generated for an interrupt based transfer. 1248 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1249 * current message's state as STATE_ERROR and schedule the tasklet 1250 * pump_transfers which will do the postprocessing of the current message by 1251 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1252 * more data, and writes data in TX FIFO till it is not full. If we complete 1253 * the transfer we move to the next transfer and schedule the tasklet. 1254 */ 1255 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1256 { 1257 struct pl022 *pl022 = dev_id; 1258 struct spi_message *msg = pl022->cur_msg; 1259 u16 irq_status = 0; 1260 1261 if (unlikely(!msg)) { 1262 dev_err(&pl022->adev->dev, 1263 "bad message state in interrupt handler"); 1264 /* Never fail */ 1265 return IRQ_HANDLED; 1266 } 1267 1268 /* Read the Interrupt Status Register */ 1269 irq_status = readw(SSP_MIS(pl022->virtbase)); 1270 1271 if (unlikely(!irq_status)) 1272 return IRQ_NONE; 1273 1274 /* 1275 * This handles the FIFO interrupts, the timeout 1276 * interrupts are flatly ignored, they cannot be 1277 * trusted. 1278 */ 1279 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1280 /* 1281 * Overrun interrupt - bail out since our Data has been 1282 * corrupted 1283 */ 1284 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1285 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1286 dev_err(&pl022->adev->dev, 1287 "RXFIFO is full\n"); 1288 1289 /* 1290 * Disable and clear interrupts, disable SSP, 1291 * mark message with bad status so it can be 1292 * retried. 1293 */ 1294 writew(DISABLE_ALL_INTERRUPTS, 1295 SSP_IMSC(pl022->virtbase)); 1296 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1297 writew((readw(SSP_CR1(pl022->virtbase)) & 1298 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1299 msg->state = STATE_ERROR; 1300 1301 /* Schedule message queue handler */ 1302 tasklet_schedule(&pl022->pump_transfers); 1303 return IRQ_HANDLED; 1304 } 1305 1306 readwriter(pl022); 1307 1308 if (pl022->tx == pl022->tx_end) { 1309 /* Disable Transmit interrupt, enable receive interrupt */ 1310 writew((readw(SSP_IMSC(pl022->virtbase)) & 1311 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1312 SSP_IMSC(pl022->virtbase)); 1313 } 1314 1315 /* 1316 * Since all transactions must write as much as shall be read, 1317 * we can conclude the entire transaction once RX is complete. 1318 * At this point, all TX will always be finished. 1319 */ 1320 if (pl022->rx >= pl022->rx_end) { 1321 writew(DISABLE_ALL_INTERRUPTS, 1322 SSP_IMSC(pl022->virtbase)); 1323 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1324 if (unlikely(pl022->rx > pl022->rx_end)) { 1325 dev_warn(&pl022->adev->dev, "read %u surplus " 1326 "bytes (did you request an odd " 1327 "number of bytes on a 16bit bus?)\n", 1328 (u32) (pl022->rx - pl022->rx_end)); 1329 } 1330 /* Update total bytes transferred */ 1331 msg->actual_length += pl022->cur_transfer->len; 1332 /* Move to next transfer */ 1333 msg->state = next_transfer(pl022); 1334 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) 1335 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1336 tasklet_schedule(&pl022->pump_transfers); 1337 return IRQ_HANDLED; 1338 } 1339 1340 return IRQ_HANDLED; 1341 } 1342 1343 /* 1344 * This sets up the pointers to memory for the next message to 1345 * send out on the SPI bus. 1346 */ 1347 static int set_up_next_transfer(struct pl022 *pl022, 1348 struct spi_transfer *transfer) 1349 { 1350 int residue; 1351 1352 /* Sanity check the message for this bus width */ 1353 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1354 if (unlikely(residue != 0)) { 1355 dev_err(&pl022->adev->dev, 1356 "message of %u bytes to transmit but the current " 1357 "chip bus has a data width of %u bytes!\n", 1358 pl022->cur_transfer->len, 1359 pl022->cur_chip->n_bytes); 1360 dev_err(&pl022->adev->dev, "skipping this message\n"); 1361 return -EIO; 1362 } 1363 pl022->tx = (void *)transfer->tx_buf; 1364 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1365 pl022->rx = (void *)transfer->rx_buf; 1366 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1367 pl022->write = 1368 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1369 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1370 return 0; 1371 } 1372 1373 /** 1374 * pump_transfers - Tasklet function which schedules next transfer 1375 * when running in interrupt or DMA transfer mode. 1376 * @data: SSP driver private data structure 1377 * 1378 */ 1379 static void pump_transfers(unsigned long data) 1380 { 1381 struct pl022 *pl022 = (struct pl022 *) data; 1382 struct spi_message *message = NULL; 1383 struct spi_transfer *transfer = NULL; 1384 struct spi_transfer *previous = NULL; 1385 1386 /* Get current state information */ 1387 message = pl022->cur_msg; 1388 transfer = pl022->cur_transfer; 1389 1390 /* Handle for abort */ 1391 if (message->state == STATE_ERROR) { 1392 message->status = -EIO; 1393 giveback(pl022); 1394 return; 1395 } 1396 1397 /* Handle end of message */ 1398 if (message->state == STATE_DONE) { 1399 message->status = 0; 1400 giveback(pl022); 1401 return; 1402 } 1403 1404 /* Delay if requested at end of transfer before CS change */ 1405 if (message->state == STATE_RUNNING) { 1406 previous = list_entry(transfer->transfer_list.prev, 1407 struct spi_transfer, 1408 transfer_list); 1409 /* 1410 * FIXME: This runs in interrupt context. 1411 * Is this really smart? 1412 */ 1413 spi_transfer_delay_exec(previous); 1414 1415 /* Reselect chip select only if cs_change was requested */ 1416 if (previous->cs_change) 1417 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1418 } else { 1419 /* STATE_START */ 1420 message->state = STATE_RUNNING; 1421 } 1422 1423 if (set_up_next_transfer(pl022, transfer)) { 1424 message->state = STATE_ERROR; 1425 message->status = -EIO; 1426 giveback(pl022); 1427 return; 1428 } 1429 /* Flush the FIFOs and let's go! */ 1430 flush(pl022); 1431 1432 if (pl022->cur_chip->enable_dma) { 1433 if (configure_dma(pl022)) { 1434 dev_dbg(&pl022->adev->dev, 1435 "configuration of DMA failed, fall back to interrupt mode\n"); 1436 goto err_config_dma; 1437 } 1438 return; 1439 } 1440 1441 err_config_dma: 1442 /* enable all interrupts except RX */ 1443 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1444 } 1445 1446 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1447 { 1448 /* 1449 * Default is to enable all interrupts except RX - 1450 * this will be enabled once TX is complete 1451 */ 1452 u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM); 1453 1454 /* Enable target chip, if not already active */ 1455 if (!pl022->next_msg_cs_active) 1456 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1457 1458 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1459 /* Error path */ 1460 pl022->cur_msg->state = STATE_ERROR; 1461 pl022->cur_msg->status = -EIO; 1462 giveback(pl022); 1463 return; 1464 } 1465 /* If we're using DMA, set up DMA here */ 1466 if (pl022->cur_chip->enable_dma) { 1467 /* Configure DMA transfer */ 1468 if (configure_dma(pl022)) { 1469 dev_dbg(&pl022->adev->dev, 1470 "configuration of DMA failed, fall back to interrupt mode\n"); 1471 goto err_config_dma; 1472 } 1473 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1474 irqflags = DISABLE_ALL_INTERRUPTS; 1475 } 1476 err_config_dma: 1477 /* Enable SSP, turn on interrupts */ 1478 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1479 SSP_CR1(pl022->virtbase)); 1480 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1481 } 1482 1483 static void print_current_status(struct pl022 *pl022) 1484 { 1485 u32 read_cr0; 1486 u16 read_cr1, read_dmacr, read_sr; 1487 1488 if (pl022->vendor->extended_cr) 1489 read_cr0 = readl(SSP_CR0(pl022->virtbase)); 1490 else 1491 read_cr0 = readw(SSP_CR0(pl022->virtbase)); 1492 read_cr1 = readw(SSP_CR1(pl022->virtbase)); 1493 read_dmacr = readw(SSP_DMACR(pl022->virtbase)); 1494 read_sr = readw(SSP_SR(pl022->virtbase)); 1495 1496 dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0); 1497 dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1); 1498 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr); 1499 dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr); 1500 dev_warn(&pl022->adev->dev, 1501 "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n", 1502 pl022->exp_fifo_level, 1503 pl022->vendor->fifodepth); 1504 1505 } 1506 1507 static void do_polling_transfer(struct pl022 *pl022) 1508 { 1509 struct spi_message *message = NULL; 1510 struct spi_transfer *transfer = NULL; 1511 struct spi_transfer *previous = NULL; 1512 unsigned long time, timeout; 1513 1514 message = pl022->cur_msg; 1515 1516 while (message->state != STATE_DONE) { 1517 /* Handle for abort */ 1518 if (message->state == STATE_ERROR) 1519 break; 1520 transfer = pl022->cur_transfer; 1521 1522 /* Delay if requested at end of transfer */ 1523 if (message->state == STATE_RUNNING) { 1524 previous = 1525 list_entry(transfer->transfer_list.prev, 1526 struct spi_transfer, transfer_list); 1527 spi_transfer_delay_exec(previous); 1528 if (previous->cs_change) 1529 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1530 } else { 1531 /* STATE_START */ 1532 message->state = STATE_RUNNING; 1533 if (!pl022->next_msg_cs_active) 1534 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1535 } 1536 1537 /* Configuration Changing Per Transfer */ 1538 if (set_up_next_transfer(pl022, transfer)) { 1539 /* Error path */ 1540 message->state = STATE_ERROR; 1541 break; 1542 } 1543 /* Flush FIFOs and enable SSP */ 1544 flush(pl022); 1545 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1546 SSP_CR1(pl022->virtbase)); 1547 1548 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1549 1550 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1551 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1552 time = jiffies; 1553 readwriter(pl022); 1554 if (time_after(time, timeout)) { 1555 dev_warn(&pl022->adev->dev, 1556 "%s: timeout!\n", __func__); 1557 message->state = STATE_TIMEOUT; 1558 print_current_status(pl022); 1559 goto out; 1560 } 1561 cpu_relax(); 1562 } 1563 1564 /* Update total byte transferred */ 1565 message->actual_length += pl022->cur_transfer->len; 1566 /* Move to next transfer */ 1567 message->state = next_transfer(pl022); 1568 if (message->state != STATE_DONE 1569 && pl022->cur_transfer->cs_change) 1570 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1571 } 1572 out: 1573 /* Handle end of message */ 1574 if (message->state == STATE_DONE) 1575 message->status = 0; 1576 else if (message->state == STATE_TIMEOUT) 1577 message->status = -EAGAIN; 1578 else 1579 message->status = -EIO; 1580 1581 giveback(pl022); 1582 return; 1583 } 1584 1585 static int pl022_transfer_one_message(struct spi_master *master, 1586 struct spi_message *msg) 1587 { 1588 struct pl022 *pl022 = spi_master_get_devdata(master); 1589 1590 /* Initial message state */ 1591 pl022->cur_msg = msg; 1592 msg->state = STATE_START; 1593 1594 pl022->cur_transfer = list_entry(msg->transfers.next, 1595 struct spi_transfer, transfer_list); 1596 1597 /* Setup the SPI using the per chip configuration */ 1598 pl022->cur_chip = spi_get_ctldata(msg->spi); 1599 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; 1600 1601 restore_state(pl022); 1602 flush(pl022); 1603 1604 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1605 do_polling_transfer(pl022); 1606 else 1607 do_interrupt_dma_transfer(pl022); 1608 1609 return 0; 1610 } 1611 1612 static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1613 { 1614 struct pl022 *pl022 = spi_master_get_devdata(master); 1615 1616 /* nothing more to do - disable spi/ssp and power off */ 1617 writew((readw(SSP_CR1(pl022->virtbase)) & 1618 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1619 1620 return 0; 1621 } 1622 1623 static int verify_controller_parameters(struct pl022 *pl022, 1624 struct pl022_config_chip const *chip_info) 1625 { 1626 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1627 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1628 dev_err(&pl022->adev->dev, 1629 "interface is configured incorrectly\n"); 1630 return -EINVAL; 1631 } 1632 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1633 (!pl022->vendor->unidir)) { 1634 dev_err(&pl022->adev->dev, 1635 "unidirectional mode not supported in this " 1636 "hardware version\n"); 1637 return -EINVAL; 1638 } 1639 if ((chip_info->hierarchy != SSP_MASTER) 1640 && (chip_info->hierarchy != SSP_SLAVE)) { 1641 dev_err(&pl022->adev->dev, 1642 "hierarchy is configured incorrectly\n"); 1643 return -EINVAL; 1644 } 1645 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1646 && (chip_info->com_mode != DMA_TRANSFER) 1647 && (chip_info->com_mode != POLLING_TRANSFER)) { 1648 dev_err(&pl022->adev->dev, 1649 "Communication mode is configured incorrectly\n"); 1650 return -EINVAL; 1651 } 1652 switch (chip_info->rx_lev_trig) { 1653 case SSP_RX_1_OR_MORE_ELEM: 1654 case SSP_RX_4_OR_MORE_ELEM: 1655 case SSP_RX_8_OR_MORE_ELEM: 1656 /* These are always OK, all variants can handle this */ 1657 break; 1658 case SSP_RX_16_OR_MORE_ELEM: 1659 if (pl022->vendor->fifodepth < 16) { 1660 dev_err(&pl022->adev->dev, 1661 "RX FIFO Trigger Level is configured incorrectly\n"); 1662 return -EINVAL; 1663 } 1664 break; 1665 case SSP_RX_32_OR_MORE_ELEM: 1666 if (pl022->vendor->fifodepth < 32) { 1667 dev_err(&pl022->adev->dev, 1668 "RX FIFO Trigger Level is configured incorrectly\n"); 1669 return -EINVAL; 1670 } 1671 break; 1672 default: 1673 dev_err(&pl022->adev->dev, 1674 "RX FIFO Trigger Level is configured incorrectly\n"); 1675 return -EINVAL; 1676 } 1677 switch (chip_info->tx_lev_trig) { 1678 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1679 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1680 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1681 /* These are always OK, all variants can handle this */ 1682 break; 1683 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1684 if (pl022->vendor->fifodepth < 16) { 1685 dev_err(&pl022->adev->dev, 1686 "TX FIFO Trigger Level is configured incorrectly\n"); 1687 return -EINVAL; 1688 } 1689 break; 1690 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1691 if (pl022->vendor->fifodepth < 32) { 1692 dev_err(&pl022->adev->dev, 1693 "TX FIFO Trigger Level is configured incorrectly\n"); 1694 return -EINVAL; 1695 } 1696 break; 1697 default: 1698 dev_err(&pl022->adev->dev, 1699 "TX FIFO Trigger Level is configured incorrectly\n"); 1700 return -EINVAL; 1701 } 1702 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1703 if ((chip_info->ctrl_len < SSP_BITS_4) 1704 || (chip_info->ctrl_len > SSP_BITS_32)) { 1705 dev_err(&pl022->adev->dev, 1706 "CTRL LEN is configured incorrectly\n"); 1707 return -EINVAL; 1708 } 1709 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1710 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1711 dev_err(&pl022->adev->dev, 1712 "Wait State is configured incorrectly\n"); 1713 return -EINVAL; 1714 } 1715 /* Half duplex is only available in the ST Micro version */ 1716 if (pl022->vendor->extended_cr) { 1717 if ((chip_info->duplex != 1718 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1719 && (chip_info->duplex != 1720 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1721 dev_err(&pl022->adev->dev, 1722 "Microwire duplex mode is configured incorrectly\n"); 1723 return -EINVAL; 1724 } 1725 } else { 1726 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1727 dev_err(&pl022->adev->dev, 1728 "Microwire half duplex mode requested," 1729 " but this is only available in the" 1730 " ST version of PL022\n"); 1731 return -EINVAL; 1732 } 1733 } 1734 return 0; 1735 } 1736 1737 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1738 { 1739 return rate / (cpsdvsr * (1 + scr)); 1740 } 1741 1742 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1743 ssp_clock_params * clk_freq) 1744 { 1745 /* Lets calculate the frequency parameters */ 1746 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1747 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1748 best_scr = 0, tmp, found = 0; 1749 1750 rate = clk_get_rate(pl022->clk); 1751 /* cpsdvscr = 2 & scr 0 */ 1752 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1753 /* cpsdvsr = 254 & scr = 255 */ 1754 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1755 1756 if (freq > max_tclk) 1757 dev_warn(&pl022->adev->dev, 1758 "Max speed that can be programmed is %d Hz, you requested %d\n", 1759 max_tclk, freq); 1760 1761 if (freq < min_tclk) { 1762 dev_err(&pl022->adev->dev, 1763 "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1764 freq, min_tclk); 1765 return -EINVAL; 1766 } 1767 1768 /* 1769 * best_freq will give closest possible available rate (<= requested 1770 * freq) for all values of scr & cpsdvsr. 1771 */ 1772 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1773 while (scr <= SCR_MAX) { 1774 tmp = spi_rate(rate, cpsdvsr, scr); 1775 1776 if (tmp > freq) { 1777 /* we need lower freq */ 1778 scr++; 1779 continue; 1780 } 1781 1782 /* 1783 * If found exact value, mark found and break. 1784 * If found more closer value, update and break. 1785 */ 1786 if (tmp > best_freq) { 1787 best_freq = tmp; 1788 best_cpsdvsr = cpsdvsr; 1789 best_scr = scr; 1790 1791 if (tmp == freq) 1792 found = 1; 1793 } 1794 /* 1795 * increased scr will give lower rates, which are not 1796 * required 1797 */ 1798 break; 1799 } 1800 cpsdvsr += 2; 1801 scr = SCR_MIN; 1802 } 1803 1804 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 1805 freq); 1806 1807 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1808 clk_freq->scr = (u8) (best_scr & 0xFF); 1809 dev_dbg(&pl022->adev->dev, 1810 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1811 freq, best_freq); 1812 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1813 clk_freq->cpsdvsr, clk_freq->scr); 1814 1815 return 0; 1816 } 1817 1818 /* 1819 * A piece of default chip info unless the platform 1820 * supplies it. 1821 */ 1822 static const struct pl022_config_chip pl022_default_chip_info = { 1823 .com_mode = POLLING_TRANSFER, 1824 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1825 .hierarchy = SSP_SLAVE, 1826 .slave_tx_disable = DO_NOT_DRIVE_TX, 1827 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1828 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1829 .ctrl_len = SSP_BITS_8, 1830 .wait_state = SSP_MWIRE_WAIT_ZERO, 1831 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1832 .cs_control = null_cs_control, 1833 }; 1834 1835 /** 1836 * pl022_setup - setup function registered to SPI master framework 1837 * @spi: spi device which is requesting setup 1838 * 1839 * This function is registered to the SPI framework for this SPI master 1840 * controller. If it is the first time when setup is called by this device, 1841 * this function will initialize the runtime state for this chip and save 1842 * the same in the device structure. Else it will update the runtime info 1843 * with the updated chip info. Nothing is really being written to the 1844 * controller hardware here, that is not done until the actual transfer 1845 * commence. 1846 */ 1847 static int pl022_setup(struct spi_device *spi) 1848 { 1849 struct pl022_config_chip const *chip_info; 1850 struct pl022_config_chip chip_info_dt; 1851 struct chip_data *chip; 1852 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1853 int status = 0; 1854 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1855 unsigned int bits = spi->bits_per_word; 1856 u32 tmp; 1857 struct device_node *np = spi->dev.of_node; 1858 1859 if (!spi->max_speed_hz) 1860 return -EINVAL; 1861 1862 /* Get controller_state if one is supplied */ 1863 chip = spi_get_ctldata(spi); 1864 1865 if (chip == NULL) { 1866 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1867 if (!chip) 1868 return -ENOMEM; 1869 dev_dbg(&spi->dev, 1870 "allocated memory for controller's runtime state\n"); 1871 } 1872 1873 /* Get controller data if one is supplied */ 1874 chip_info = spi->controller_data; 1875 1876 if (chip_info == NULL) { 1877 if (np) { 1878 chip_info_dt = pl022_default_chip_info; 1879 1880 chip_info_dt.hierarchy = SSP_MASTER; 1881 of_property_read_u32(np, "pl022,interface", 1882 &chip_info_dt.iface); 1883 of_property_read_u32(np, "pl022,com-mode", 1884 &chip_info_dt.com_mode); 1885 of_property_read_u32(np, "pl022,rx-level-trig", 1886 &chip_info_dt.rx_lev_trig); 1887 of_property_read_u32(np, "pl022,tx-level-trig", 1888 &chip_info_dt.tx_lev_trig); 1889 of_property_read_u32(np, "pl022,ctrl-len", 1890 &chip_info_dt.ctrl_len); 1891 of_property_read_u32(np, "pl022,wait-state", 1892 &chip_info_dt.wait_state); 1893 of_property_read_u32(np, "pl022,duplex", 1894 &chip_info_dt.duplex); 1895 1896 chip_info = &chip_info_dt; 1897 } else { 1898 chip_info = &pl022_default_chip_info; 1899 /* spi_board_info.controller_data not is supplied */ 1900 dev_dbg(&spi->dev, 1901 "using default controller_data settings\n"); 1902 } 1903 } else 1904 dev_dbg(&spi->dev, 1905 "using user supplied controller_data settings\n"); 1906 1907 /* 1908 * We can override with custom divisors, else we use the board 1909 * frequency setting 1910 */ 1911 if ((0 == chip_info->clk_freq.cpsdvsr) 1912 && (0 == chip_info->clk_freq.scr)) { 1913 status = calculate_effective_freq(pl022, 1914 spi->max_speed_hz, 1915 &clk_freq); 1916 if (status < 0) 1917 goto err_config_params; 1918 } else { 1919 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1920 if ((clk_freq.cpsdvsr % 2) != 0) 1921 clk_freq.cpsdvsr = 1922 clk_freq.cpsdvsr - 1; 1923 } 1924 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1925 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1926 status = -EINVAL; 1927 dev_err(&spi->dev, 1928 "cpsdvsr is configured incorrectly\n"); 1929 goto err_config_params; 1930 } 1931 1932 status = verify_controller_parameters(pl022, chip_info); 1933 if (status) { 1934 dev_err(&spi->dev, "controller data is incorrect"); 1935 goto err_config_params; 1936 } 1937 1938 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1939 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1940 1941 /* Now set controller state based on controller data */ 1942 chip->xfer_type = chip_info->com_mode; 1943 if (!chip_info->cs_control) { 1944 chip->cs_control = null_cs_control; 1945 if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) 1946 dev_warn(&spi->dev, 1947 "invalid chip select\n"); 1948 } else 1949 chip->cs_control = chip_info->cs_control; 1950 1951 /* Check bits per word with vendor specific range */ 1952 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1953 status = -ENOTSUPP; 1954 dev_err(&spi->dev, "illegal data size for this controller!\n"); 1955 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1956 pl022->vendor->max_bpw); 1957 goto err_config_params; 1958 } else if (bits <= 8) { 1959 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1960 chip->n_bytes = 1; 1961 chip->read = READING_U8; 1962 chip->write = WRITING_U8; 1963 } else if (bits <= 16) { 1964 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1965 chip->n_bytes = 2; 1966 chip->read = READING_U16; 1967 chip->write = WRITING_U16; 1968 } else { 1969 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1970 chip->n_bytes = 4; 1971 chip->read = READING_U32; 1972 chip->write = WRITING_U32; 1973 } 1974 1975 /* Now Initialize all register settings required for this chip */ 1976 chip->cr0 = 0; 1977 chip->cr1 = 0; 1978 chip->dmacr = 0; 1979 chip->cpsr = 0; 1980 if ((chip_info->com_mode == DMA_TRANSFER) 1981 && ((pl022->master_info)->enable_dma)) { 1982 chip->enable_dma = true; 1983 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1984 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1985 SSP_DMACR_MASK_RXDMAE, 0); 1986 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1987 SSP_DMACR_MASK_TXDMAE, 1); 1988 } else { 1989 chip->enable_dma = false; 1990 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1991 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1992 SSP_DMACR_MASK_RXDMAE, 0); 1993 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1994 SSP_DMACR_MASK_TXDMAE, 1); 1995 } 1996 1997 chip->cpsr = clk_freq.cpsdvsr; 1998 1999 /* Special setup for the ST micro extended control registers */ 2000 if (pl022->vendor->extended_cr) { 2001 u32 etx; 2002 2003 if (pl022->vendor->pl023) { 2004 /* These bits are only in the PL023 */ 2005 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 2006 SSP_CR1_MASK_FBCLKDEL_ST, 13); 2007 } else { 2008 /* These bits are in the PL022 but not PL023 */ 2009 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 2010 SSP_CR0_MASK_HALFDUP_ST, 5); 2011 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 2012 SSP_CR0_MASK_CSS_ST, 16); 2013 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2014 SSP_CR0_MASK_FRF_ST, 21); 2015 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 2016 SSP_CR1_MASK_MWAIT_ST, 6); 2017 } 2018 SSP_WRITE_BITS(chip->cr0, bits - 1, 2019 SSP_CR0_MASK_DSS_ST, 0); 2020 2021 if (spi->mode & SPI_LSB_FIRST) { 2022 tmp = SSP_RX_LSB; 2023 etx = SSP_TX_LSB; 2024 } else { 2025 tmp = SSP_RX_MSB; 2026 etx = SSP_TX_MSB; 2027 } 2028 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2029 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2030 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2031 SSP_CR1_MASK_RXIFLSEL_ST, 7); 2032 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2033 SSP_CR1_MASK_TXIFLSEL_ST, 10); 2034 } else { 2035 SSP_WRITE_BITS(chip->cr0, bits - 1, 2036 SSP_CR0_MASK_DSS, 0); 2037 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2038 SSP_CR0_MASK_FRF, 4); 2039 } 2040 2041 /* Stuff that is common for all versions */ 2042 if (spi->mode & SPI_CPOL) 2043 tmp = SSP_CLK_POL_IDLE_HIGH; 2044 else 2045 tmp = SSP_CLK_POL_IDLE_LOW; 2046 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2047 2048 if (spi->mode & SPI_CPHA) 2049 tmp = SSP_CLK_SECOND_EDGE; 2050 else 2051 tmp = SSP_CLK_FIRST_EDGE; 2052 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2053 2054 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2055 /* Loopback is available on all versions except PL023 */ 2056 if (pl022->vendor->loopback) { 2057 if (spi->mode & SPI_LOOP) 2058 tmp = LOOPBACK_ENABLED; 2059 else 2060 tmp = LOOPBACK_DISABLED; 2061 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2062 } 2063 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2064 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2065 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2066 3); 2067 2068 /* Save controller_state */ 2069 spi_set_ctldata(spi, chip); 2070 return status; 2071 err_config_params: 2072 spi_set_ctldata(spi, NULL); 2073 kfree(chip); 2074 return status; 2075 } 2076 2077 /** 2078 * pl022_cleanup - cleanup function registered to SPI master framework 2079 * @spi: spi device which is requesting cleanup 2080 * 2081 * This function is registered to the SPI framework for this SPI master 2082 * controller. It will free the runtime state of chip. 2083 */ 2084 static void pl022_cleanup(struct spi_device *spi) 2085 { 2086 struct chip_data *chip = spi_get_ctldata(spi); 2087 2088 spi_set_ctldata(spi, NULL); 2089 kfree(chip); 2090 } 2091 2092 static struct pl022_ssp_controller * 2093 pl022_platform_data_dt_get(struct device *dev) 2094 { 2095 struct device_node *np = dev->of_node; 2096 struct pl022_ssp_controller *pd; 2097 u32 tmp = 0; 2098 2099 if (!np) { 2100 dev_err(dev, "no dt node defined\n"); 2101 return NULL; 2102 } 2103 2104 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); 2105 if (!pd) 2106 return NULL; 2107 2108 pd->bus_id = -1; 2109 pd->enable_dma = 1; 2110 of_property_read_u32(np, "num-cs", &tmp); 2111 pd->num_chipselect = tmp; 2112 of_property_read_u32(np, "pl022,autosuspend-delay", 2113 &pd->autosuspend_delay); 2114 pd->rt = of_property_read_bool(np, "pl022,rt"); 2115 2116 return pd; 2117 } 2118 2119 static int pl022_probe(struct amba_device *adev, const struct amba_id *id) 2120 { 2121 struct device *dev = &adev->dev; 2122 struct pl022_ssp_controller *platform_info = 2123 dev_get_platdata(&adev->dev); 2124 struct spi_master *master; 2125 struct pl022 *pl022 = NULL; /*Data for this driver */ 2126 struct device_node *np = adev->dev.of_node; 2127 int status = 0, i, num_cs; 2128 2129 dev_info(&adev->dev, 2130 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2131 if (!platform_info && IS_ENABLED(CONFIG_OF)) 2132 platform_info = pl022_platform_data_dt_get(dev); 2133 2134 if (!platform_info) { 2135 dev_err(dev, "probe: no platform data defined\n"); 2136 return -ENODEV; 2137 } 2138 2139 if (platform_info->num_chipselect) { 2140 num_cs = platform_info->num_chipselect; 2141 } else { 2142 dev_err(dev, "probe: no chip select defined\n"); 2143 return -ENODEV; 2144 } 2145 2146 /* Allocate master with space for data */ 2147 master = spi_alloc_master(dev, sizeof(struct pl022)); 2148 if (master == NULL) { 2149 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2150 return -ENOMEM; 2151 } 2152 2153 pl022 = spi_master_get_devdata(master); 2154 pl022->master = master; 2155 pl022->master_info = platform_info; 2156 pl022->adev = adev; 2157 pl022->vendor = id->data; 2158 pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int), 2159 GFP_KERNEL); 2160 if (!pl022->chipselects) { 2161 status = -ENOMEM; 2162 goto err_no_mem; 2163 } 2164 2165 /* 2166 * Bus Number Which has been Assigned to this SSP controller 2167 * on this board 2168 */ 2169 master->bus_num = platform_info->bus_id; 2170 master->num_chipselect = num_cs; 2171 master->cleanup = pl022_cleanup; 2172 master->setup = pl022_setup; 2173 master->auto_runtime_pm = true; 2174 master->transfer_one_message = pl022_transfer_one_message; 2175 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2176 master->rt = platform_info->rt; 2177 master->dev.of_node = dev->of_node; 2178 2179 if (platform_info->num_chipselect && platform_info->chipselects) { 2180 for (i = 0; i < num_cs; i++) 2181 pl022->chipselects[i] = platform_info->chipselects[i]; 2182 } else if (pl022->vendor->internal_cs_ctrl) { 2183 for (i = 0; i < num_cs; i++) 2184 pl022->chipselects[i] = i; 2185 } else if (IS_ENABLED(CONFIG_OF)) { 2186 for (i = 0; i < num_cs; i++) { 2187 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 2188 2189 if (cs_gpio == -EPROBE_DEFER) { 2190 status = -EPROBE_DEFER; 2191 goto err_no_gpio; 2192 } 2193 2194 pl022->chipselects[i] = cs_gpio; 2195 2196 if (gpio_is_valid(cs_gpio)) { 2197 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) 2198 dev_err(&adev->dev, 2199 "could not request %d gpio\n", 2200 cs_gpio); 2201 else if (gpio_direction_output(cs_gpio, 1)) 2202 dev_err(&adev->dev, 2203 "could not set gpio %d as output\n", 2204 cs_gpio); 2205 } 2206 } 2207 } 2208 2209 /* 2210 * Supports mode 0-3, loopback, and active low CS. Transfers are 2211 * always MS bit first on the original pl022. 2212 */ 2213 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2214 if (pl022->vendor->extended_cr) 2215 master->mode_bits |= SPI_LSB_FIRST; 2216 2217 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2218 2219 status = amba_request_regions(adev, NULL); 2220 if (status) 2221 goto err_no_ioregion; 2222 2223 pl022->phybase = adev->res.start; 2224 pl022->virtbase = devm_ioremap(dev, adev->res.start, 2225 resource_size(&adev->res)); 2226 if (pl022->virtbase == NULL) { 2227 status = -ENOMEM; 2228 goto err_no_ioremap; 2229 } 2230 dev_info(&adev->dev, "mapped registers from %pa to %p\n", 2231 &adev->res.start, pl022->virtbase); 2232 2233 pl022->clk = devm_clk_get(&adev->dev, NULL); 2234 if (IS_ERR(pl022->clk)) { 2235 status = PTR_ERR(pl022->clk); 2236 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2237 goto err_no_clk; 2238 } 2239 2240 status = clk_prepare_enable(pl022->clk); 2241 if (status) { 2242 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2243 goto err_no_clk_en; 2244 } 2245 2246 /* Initialize transfer pump */ 2247 tasklet_init(&pl022->pump_transfers, pump_transfers, 2248 (unsigned long)pl022); 2249 2250 /* Disable SSP */ 2251 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2252 SSP_CR1(pl022->virtbase)); 2253 load_ssp_default_config(pl022); 2254 2255 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, 2256 0, "pl022", pl022); 2257 if (status < 0) { 2258 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2259 goto err_no_irq; 2260 } 2261 2262 /* Get DMA channels, try autoconfiguration first */ 2263 status = pl022_dma_autoprobe(pl022); 2264 if (status == -EPROBE_DEFER) { 2265 dev_dbg(dev, "deferring probe to get DMA channel\n"); 2266 goto err_no_irq; 2267 } 2268 2269 /* If that failed, use channels from platform_info */ 2270 if (status == 0) 2271 platform_info->enable_dma = 1; 2272 else if (platform_info->enable_dma) { 2273 status = pl022_dma_probe(pl022); 2274 if (status != 0) 2275 platform_info->enable_dma = 0; 2276 } 2277 2278 /* Register with the SPI framework */ 2279 amba_set_drvdata(adev, pl022); 2280 status = devm_spi_register_master(&adev->dev, master); 2281 if (status != 0) { 2282 dev_err(&adev->dev, 2283 "probe - problem registering spi master\n"); 2284 goto err_spi_register; 2285 } 2286 dev_dbg(dev, "probe succeeded\n"); 2287 2288 /* let runtime pm put suspend */ 2289 if (platform_info->autosuspend_delay > 0) { 2290 dev_info(&adev->dev, 2291 "will use autosuspend for runtime pm, delay %dms\n", 2292 platform_info->autosuspend_delay); 2293 pm_runtime_set_autosuspend_delay(dev, 2294 platform_info->autosuspend_delay); 2295 pm_runtime_use_autosuspend(dev); 2296 } 2297 pm_runtime_put(dev); 2298 2299 return 0; 2300 2301 err_spi_register: 2302 if (platform_info->enable_dma) 2303 pl022_dma_remove(pl022); 2304 err_no_irq: 2305 clk_disable_unprepare(pl022->clk); 2306 err_no_clk_en: 2307 err_no_clk: 2308 err_no_ioremap: 2309 amba_release_regions(adev); 2310 err_no_ioregion: 2311 err_no_gpio: 2312 err_no_mem: 2313 spi_master_put(master); 2314 return status; 2315 } 2316 2317 static int 2318 pl022_remove(struct amba_device *adev) 2319 { 2320 struct pl022 *pl022 = amba_get_drvdata(adev); 2321 2322 if (!pl022) 2323 return 0; 2324 2325 /* 2326 * undo pm_runtime_put() in probe. I assume that we're not 2327 * accessing the primecell here. 2328 */ 2329 pm_runtime_get_noresume(&adev->dev); 2330 2331 load_ssp_default_config(pl022); 2332 if (pl022->master_info->enable_dma) 2333 pl022_dma_remove(pl022); 2334 2335 clk_disable_unprepare(pl022->clk); 2336 amba_release_regions(adev); 2337 tasklet_disable(&pl022->pump_transfers); 2338 return 0; 2339 } 2340 2341 #ifdef CONFIG_PM_SLEEP 2342 static int pl022_suspend(struct device *dev) 2343 { 2344 struct pl022 *pl022 = dev_get_drvdata(dev); 2345 int ret; 2346 2347 ret = spi_master_suspend(pl022->master); 2348 if (ret) 2349 return ret; 2350 2351 ret = pm_runtime_force_suspend(dev); 2352 if (ret) { 2353 spi_master_resume(pl022->master); 2354 return ret; 2355 } 2356 2357 pinctrl_pm_select_sleep_state(dev); 2358 2359 dev_dbg(dev, "suspended\n"); 2360 return 0; 2361 } 2362 2363 static int pl022_resume(struct device *dev) 2364 { 2365 struct pl022 *pl022 = dev_get_drvdata(dev); 2366 int ret; 2367 2368 ret = pm_runtime_force_resume(dev); 2369 if (ret) 2370 dev_err(dev, "problem resuming\n"); 2371 2372 /* Start the queue running */ 2373 ret = spi_master_resume(pl022->master); 2374 if (!ret) 2375 dev_dbg(dev, "resumed\n"); 2376 2377 return ret; 2378 } 2379 #endif 2380 2381 #ifdef CONFIG_PM 2382 static int pl022_runtime_suspend(struct device *dev) 2383 { 2384 struct pl022 *pl022 = dev_get_drvdata(dev); 2385 2386 clk_disable_unprepare(pl022->clk); 2387 pinctrl_pm_select_idle_state(dev); 2388 2389 return 0; 2390 } 2391 2392 static int pl022_runtime_resume(struct device *dev) 2393 { 2394 struct pl022 *pl022 = dev_get_drvdata(dev); 2395 2396 pinctrl_pm_select_default_state(dev); 2397 clk_prepare_enable(pl022->clk); 2398 2399 return 0; 2400 } 2401 #endif 2402 2403 static const struct dev_pm_ops pl022_dev_pm_ops = { 2404 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2405 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2406 }; 2407 2408 static struct vendor_data vendor_arm = { 2409 .fifodepth = 8, 2410 .max_bpw = 16, 2411 .unidir = false, 2412 .extended_cr = false, 2413 .pl023 = false, 2414 .loopback = true, 2415 .internal_cs_ctrl = false, 2416 }; 2417 2418 static struct vendor_data vendor_st = { 2419 .fifodepth = 32, 2420 .max_bpw = 32, 2421 .unidir = false, 2422 .extended_cr = true, 2423 .pl023 = false, 2424 .loopback = true, 2425 .internal_cs_ctrl = false, 2426 }; 2427 2428 static struct vendor_data vendor_st_pl023 = { 2429 .fifodepth = 32, 2430 .max_bpw = 32, 2431 .unidir = false, 2432 .extended_cr = true, 2433 .pl023 = true, 2434 .loopback = false, 2435 .internal_cs_ctrl = false, 2436 }; 2437 2438 static struct vendor_data vendor_lsi = { 2439 .fifodepth = 8, 2440 .max_bpw = 16, 2441 .unidir = false, 2442 .extended_cr = false, 2443 .pl023 = false, 2444 .loopback = true, 2445 .internal_cs_ctrl = true, 2446 }; 2447 2448 static const struct amba_id pl022_ids[] = { 2449 { 2450 /* 2451 * ARM PL022 variant, this has a 16bit wide 2452 * and 8 locations deep TX/RX FIFO 2453 */ 2454 .id = 0x00041022, 2455 .mask = 0x000fffff, 2456 .data = &vendor_arm, 2457 }, 2458 { 2459 /* 2460 * ST Micro derivative, this has 32bit wide 2461 * and 32 locations deep TX/RX FIFO 2462 */ 2463 .id = 0x01080022, 2464 .mask = 0xffffffff, 2465 .data = &vendor_st, 2466 }, 2467 { 2468 /* 2469 * ST-Ericsson derivative "PL023" (this is not 2470 * an official ARM number), this is a PL022 SSP block 2471 * stripped to SPI mode only, it has 32bit wide 2472 * and 32 locations deep TX/RX FIFO but no extended 2473 * CR0/CR1 register 2474 */ 2475 .id = 0x00080023, 2476 .mask = 0xffffffff, 2477 .data = &vendor_st_pl023, 2478 }, 2479 { 2480 /* 2481 * PL022 variant that has a chip select control register whih 2482 * allows control of 5 output signals nCS[0:4]. 2483 */ 2484 .id = 0x000b6022, 2485 .mask = 0x000fffff, 2486 .data = &vendor_lsi, 2487 }, 2488 { 0, 0 }, 2489 }; 2490 2491 MODULE_DEVICE_TABLE(amba, pl022_ids); 2492 2493 static struct amba_driver pl022_driver = { 2494 .drv = { 2495 .name = "ssp-pl022", 2496 .pm = &pl022_dev_pm_ops, 2497 }, 2498 .id_table = pl022_ids, 2499 .probe = pl022_probe, 2500 .remove = pl022_remove, 2501 }; 2502 2503 static int __init pl022_init(void) 2504 { 2505 return amba_driver_register(&pl022_driver); 2506 } 2507 subsys_initcall(pl022_init); 2508 2509 static void __exit pl022_exit(void) 2510 { 2511 amba_driver_unregister(&pl022_driver); 2512 } 2513 module_exit(pl022_exit); 2514 2515 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2516 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2517 MODULE_LICENSE("GPL"); 2518