1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2009 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/delay.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/amba/bus.h> 36 #include <linux/amba/pl022.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 #include <linux/dmaengine.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/scatterlist.h> 42 #include <linux/pm_runtime.h> 43 44 /* 45 * This macro is used to define some register default values. 46 * reg is masked with mask, the OR:ed with an (again masked) 47 * val shifted sb steps to the left. 48 */ 49 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 50 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 51 52 /* 53 * This macro is also used to define some default values. 54 * It will just shift val by sb steps to the left and mask 55 * the result with mask. 56 */ 57 #define GEN_MASK_BITS(val, mask, sb) \ 58 (((val)<<(sb)) & (mask)) 59 60 #define DRIVE_TX 0 61 #define DO_NOT_DRIVE_TX 1 62 63 #define DO_NOT_QUEUE_DMA 0 64 #define QUEUE_DMA 1 65 66 #define RX_TRANSFER 1 67 #define TX_TRANSFER 2 68 69 /* 70 * Macros to access SSP Registers with their offsets 71 */ 72 #define SSP_CR0(r) (r + 0x000) 73 #define SSP_CR1(r) (r + 0x004) 74 #define SSP_DR(r) (r + 0x008) 75 #define SSP_SR(r) (r + 0x00C) 76 #define SSP_CPSR(r) (r + 0x010) 77 #define SSP_IMSC(r) (r + 0x014) 78 #define SSP_RIS(r) (r + 0x018) 79 #define SSP_MIS(r) (r + 0x01C) 80 #define SSP_ICR(r) (r + 0x020) 81 #define SSP_DMACR(r) (r + 0x024) 82 #define SSP_ITCR(r) (r + 0x080) 83 #define SSP_ITIP(r) (r + 0x084) 84 #define SSP_ITOP(r) (r + 0x088) 85 #define SSP_TDR(r) (r + 0x08C) 86 87 #define SSP_PID0(r) (r + 0xFE0) 88 #define SSP_PID1(r) (r + 0xFE4) 89 #define SSP_PID2(r) (r + 0xFE8) 90 #define SSP_PID3(r) (r + 0xFEC) 91 92 #define SSP_CID0(r) (r + 0xFF0) 93 #define SSP_CID1(r) (r + 0xFF4) 94 #define SSP_CID2(r) (r + 0xFF8) 95 #define SSP_CID3(r) (r + 0xFFC) 96 97 /* 98 * SSP Control Register 0 - SSP_CR0 99 */ 100 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 101 #define SSP_CR0_MASK_FRF (0x3UL << 4) 102 #define SSP_CR0_MASK_SPO (0x1UL << 6) 103 #define SSP_CR0_MASK_SPH (0x1UL << 7) 104 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 105 106 /* 107 * The ST version of this block moves som bits 108 * in SSP_CR0 and extends it to 32 bits 109 */ 110 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 111 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 112 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 113 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 114 115 /* 116 * SSP Control Register 0 - SSP_CR1 117 */ 118 #define SSP_CR1_MASK_LBM (0x1UL << 0) 119 #define SSP_CR1_MASK_SSE (0x1UL << 1) 120 #define SSP_CR1_MASK_MS (0x1UL << 2) 121 #define SSP_CR1_MASK_SOD (0x1UL << 3) 122 123 /* 124 * The ST version of this block adds some bits 125 * in SSP_CR1 126 */ 127 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 128 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 129 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 130 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 131 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 132 /* This one is only in the PL023 variant */ 133 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 134 135 /* 136 * SSP Status Register - SSP_SR 137 */ 138 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 139 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 140 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 141 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 142 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 143 144 /* 145 * SSP Clock Prescale Register - SSP_CPSR 146 */ 147 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 148 149 /* 150 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 151 */ 152 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 153 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 154 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 155 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 156 157 /* 158 * SSP Raw Interrupt Status Register - SSP_RIS 159 */ 160 /* Receive Overrun Raw Interrupt status */ 161 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 162 /* Receive Timeout Raw Interrupt status */ 163 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 164 /* Receive FIFO Raw Interrupt status */ 165 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 166 /* Transmit FIFO Raw Interrupt status */ 167 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 168 169 /* 170 * SSP Masked Interrupt Status Register - SSP_MIS 171 */ 172 /* Receive Overrun Masked Interrupt status */ 173 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 174 /* Receive Timeout Masked Interrupt status */ 175 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 176 /* Receive FIFO Masked Interrupt status */ 177 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 178 /* Transmit FIFO Masked Interrupt status */ 179 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 180 181 /* 182 * SSP Interrupt Clear Register - SSP_ICR 183 */ 184 /* Receive Overrun Raw Clear Interrupt bit */ 185 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 186 /* Receive Timeout Clear Interrupt bit */ 187 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 188 189 /* 190 * SSP DMA Control Register - SSP_DMACR 191 */ 192 /* Receive DMA Enable bit */ 193 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 194 /* Transmit DMA Enable bit */ 195 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 196 197 /* 198 * SSP Integration Test control Register - SSP_ITCR 199 */ 200 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 201 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 202 203 /* 204 * SSP Integration Test Input Register - SSP_ITIP 205 */ 206 #define ITIP_MASK_SSPRXD (0x1UL << 0) 207 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 208 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 209 #define ITIP_MASK_RXDMAC (0x1UL << 3) 210 #define ITIP_MASK_TXDMAC (0x1UL << 4) 211 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 212 213 /* 214 * SSP Integration Test output Register - SSP_ITOP 215 */ 216 #define ITOP_MASK_SSPTXD (0x1UL << 0) 217 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 218 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 219 #define ITOP_MASK_SSPOEn (0x1UL << 3) 220 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 221 #define ITOP_MASK_RORINTR (0x1UL << 5) 222 #define ITOP_MASK_RTINTR (0x1UL << 6) 223 #define ITOP_MASK_RXINTR (0x1UL << 7) 224 #define ITOP_MASK_TXINTR (0x1UL << 8) 225 #define ITOP_MASK_INTR (0x1UL << 9) 226 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 227 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 228 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 229 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 230 231 /* 232 * SSP Test Data Register - SSP_TDR 233 */ 234 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 235 236 /* 237 * Message State 238 * we use the spi_message.state (void *) pointer to 239 * hold a single state value, that's why all this 240 * (void *) casting is done here. 241 */ 242 #define STATE_START ((void *) 0) 243 #define STATE_RUNNING ((void *) 1) 244 #define STATE_DONE ((void *) 2) 245 #define STATE_ERROR ((void *) -1) 246 247 /* 248 * SSP State - Whether Enabled or Disabled 249 */ 250 #define SSP_DISABLED (0) 251 #define SSP_ENABLED (1) 252 253 /* 254 * SSP DMA State - Whether DMA Enabled or Disabled 255 */ 256 #define SSP_DMA_DISABLED (0) 257 #define SSP_DMA_ENABLED (1) 258 259 /* 260 * SSP Clock Defaults 261 */ 262 #define SSP_DEFAULT_CLKRATE 0x2 263 #define SSP_DEFAULT_PRESCALE 0x40 264 265 /* 266 * SSP Clock Parameter ranges 267 */ 268 #define CPSDVR_MIN 0x02 269 #define CPSDVR_MAX 0xFE 270 #define SCR_MIN 0x00 271 #define SCR_MAX 0xFF 272 273 /* 274 * SSP Interrupt related Macros 275 */ 276 #define DEFAULT_SSP_REG_IMSC 0x0UL 277 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 278 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 279 280 #define CLEAR_ALL_INTERRUPTS 0x3 281 282 #define SPI_POLLING_TIMEOUT 1000 283 284 /* 285 * The type of reading going on on this chip 286 */ 287 enum ssp_reading { 288 READING_NULL, 289 READING_U8, 290 READING_U16, 291 READING_U32 292 }; 293 294 /** 295 * The type of writing going on on this chip 296 */ 297 enum ssp_writing { 298 WRITING_NULL, 299 WRITING_U8, 300 WRITING_U16, 301 WRITING_U32 302 }; 303 304 /** 305 * struct vendor_data - vendor-specific config parameters 306 * for PL022 derivates 307 * @fifodepth: depth of FIFOs (both) 308 * @max_bpw: maximum number of bits per word 309 * @unidir: supports unidirection transfers 310 * @extended_cr: 32 bit wide control register 0 with extra 311 * features and extra features in CR1 as found in the ST variants 312 * @pl023: supports a subset of the ST extensions called "PL023" 313 */ 314 struct vendor_data { 315 int fifodepth; 316 int max_bpw; 317 bool unidir; 318 bool extended_cr; 319 bool pl023; 320 bool loopback; 321 }; 322 323 /** 324 * struct pl022 - This is the private SSP driver data structure 325 * @adev: AMBA device model hookup 326 * @vendor: vendor data for the IP block 327 * @phybase: the physical memory where the SSP device resides 328 * @virtbase: the virtual memory where the SSP is mapped 329 * @clk: outgoing clock "SPICLK" for the SPI bus 330 * @master: SPI framework hookup 331 * @master_info: controller-specific data from machine setup 332 * @kworker: thread struct for message pump 333 * @kworker_task: pointer to task for message pump kworker thread 334 * @pump_messages: work struct for scheduling work to the message pump 335 * @queue_lock: spinlock to syncronise access to message queue 336 * @queue: message queue 337 * @busy: message pump is busy 338 * @running: message pump is running 339 * @pump_transfers: Tasklet used in Interrupt Transfer mode 340 * @cur_msg: Pointer to current spi_message being processed 341 * @cur_transfer: Pointer to current spi_transfer 342 * @cur_chip: pointer to current clients chip(assigned from controller_state) 343 * @next_msg_cs_active: the next message in the queue has been examined 344 * and it was found that it uses the same chip select as the previous 345 * message, so we left it active after the previous transfer, and it's 346 * active already. 347 * @tx: current position in TX buffer to be read 348 * @tx_end: end position in TX buffer to be read 349 * @rx: current position in RX buffer to be written 350 * @rx_end: end position in RX buffer to be written 351 * @read: the type of read currently going on 352 * @write: the type of write currently going on 353 * @exp_fifo_level: expected FIFO level 354 * @dma_rx_channel: optional channel for RX DMA 355 * @dma_tx_channel: optional channel for TX DMA 356 * @sgt_rx: scattertable for the RX transfer 357 * @sgt_tx: scattertable for the TX transfer 358 * @dummypage: a dummy page used for driving data on the bus with DMA 359 */ 360 struct pl022 { 361 struct amba_device *adev; 362 struct vendor_data *vendor; 363 resource_size_t phybase; 364 void __iomem *virtbase; 365 struct clk *clk; 366 struct spi_master *master; 367 struct pl022_ssp_controller *master_info; 368 /* Message per-transfer pump */ 369 struct tasklet_struct pump_transfers; 370 struct spi_message *cur_msg; 371 struct spi_transfer *cur_transfer; 372 struct chip_data *cur_chip; 373 bool next_msg_cs_active; 374 void *tx; 375 void *tx_end; 376 void *rx; 377 void *rx_end; 378 enum ssp_reading read; 379 enum ssp_writing write; 380 u32 exp_fifo_level; 381 enum ssp_rx_level_trig rx_lev_trig; 382 enum ssp_tx_level_trig tx_lev_trig; 383 /* DMA settings */ 384 #ifdef CONFIG_DMA_ENGINE 385 struct dma_chan *dma_rx_channel; 386 struct dma_chan *dma_tx_channel; 387 struct sg_table sgt_rx; 388 struct sg_table sgt_tx; 389 char *dummypage; 390 bool dma_running; 391 #endif 392 }; 393 394 /** 395 * struct chip_data - To maintain runtime state of SSP for each client chip 396 * @cr0: Value of control register CR0 of SSP - on later ST variants this 397 * register is 32 bits wide rather than just 16 398 * @cr1: Value of control register CR1 of SSP 399 * @dmacr: Value of DMA control Register of SSP 400 * @cpsr: Value of Clock prescale register 401 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 402 * @enable_dma: Whether to enable DMA or not 403 * @read: function ptr to be used to read when doing xfer for this chip 404 * @write: function ptr to be used to write when doing xfer for this chip 405 * @cs_control: chip select callback provided by chip 406 * @xfer_type: polling/interrupt/DMA 407 * 408 * Runtime state of the SSP controller, maintained per chip, 409 * This would be set according to the current message that would be served 410 */ 411 struct chip_data { 412 u32 cr0; 413 u16 cr1; 414 u16 dmacr; 415 u16 cpsr; 416 u8 n_bytes; 417 bool enable_dma; 418 enum ssp_reading read; 419 enum ssp_writing write; 420 void (*cs_control) (u32 command); 421 int xfer_type; 422 }; 423 424 /** 425 * null_cs_control - Dummy chip select function 426 * @command: select/delect the chip 427 * 428 * If no chip select function is provided by client this is used as dummy 429 * chip select 430 */ 431 static void null_cs_control(u32 command) 432 { 433 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 434 } 435 436 /** 437 * giveback - current spi_message is over, schedule next message and call 438 * callback of this message. Assumes that caller already 439 * set message->status; dma and pio irqs are blocked 440 * @pl022: SSP driver private data structure 441 */ 442 static void giveback(struct pl022 *pl022) 443 { 444 struct spi_transfer *last_transfer; 445 pl022->next_msg_cs_active = false; 446 447 last_transfer = list_entry(pl022->cur_msg->transfers.prev, 448 struct spi_transfer, 449 transfer_list); 450 451 /* Delay if requested before any change in chip select */ 452 if (last_transfer->delay_usecs) 453 /* 454 * FIXME: This runs in interrupt context. 455 * Is this really smart? 456 */ 457 udelay(last_transfer->delay_usecs); 458 459 if (!last_transfer->cs_change) { 460 struct spi_message *next_msg; 461 462 /* 463 * cs_change was not set. We can keep the chip select 464 * enabled if there is message in the queue and it is 465 * for the same spi device. 466 * 467 * We cannot postpone this until pump_messages, because 468 * after calling msg->complete (below) the driver that 469 * sent the current message could be unloaded, which 470 * could invalidate the cs_control() callback... 471 */ 472 /* get a pointer to the next message, if any */ 473 next_msg = spi_get_next_queued_message(pl022->master); 474 475 /* 476 * see if the next and current messages point 477 * to the same spi device. 478 */ 479 if (next_msg && next_msg->spi != pl022->cur_msg->spi) 480 next_msg = NULL; 481 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 482 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 483 else 484 pl022->next_msg_cs_active = true; 485 486 } 487 488 pl022->cur_msg = NULL; 489 pl022->cur_transfer = NULL; 490 pl022->cur_chip = NULL; 491 spi_finalize_current_message(pl022->master); 492 } 493 494 /** 495 * flush - flush the FIFO to reach a clean state 496 * @pl022: SSP driver private data structure 497 */ 498 static int flush(struct pl022 *pl022) 499 { 500 unsigned long limit = loops_per_jiffy << 1; 501 502 dev_dbg(&pl022->adev->dev, "flush\n"); 503 do { 504 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 505 readw(SSP_DR(pl022->virtbase)); 506 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 507 508 pl022->exp_fifo_level = 0; 509 510 return limit; 511 } 512 513 /** 514 * restore_state - Load configuration of current chip 515 * @pl022: SSP driver private data structure 516 */ 517 static void restore_state(struct pl022 *pl022) 518 { 519 struct chip_data *chip = pl022->cur_chip; 520 521 if (pl022->vendor->extended_cr) 522 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 523 else 524 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 525 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 526 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 527 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 528 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 529 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 530 } 531 532 /* 533 * Default SSP Register Values 534 */ 535 #define DEFAULT_SSP_REG_CR0 ( \ 536 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 537 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 538 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 539 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 540 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 541 ) 542 543 /* ST versions have slightly different bit layout */ 544 #define DEFAULT_SSP_REG_CR0_ST ( \ 545 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 546 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 547 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 548 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 549 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 550 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 551 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 552 ) 553 554 /* The PL023 version is slightly different again */ 555 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 556 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 557 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 558 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 559 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 560 ) 561 562 #define DEFAULT_SSP_REG_CR1 ( \ 563 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 564 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 565 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 566 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 567 ) 568 569 /* ST versions extend this register to use all 16 bits */ 570 #define DEFAULT_SSP_REG_CR1_ST ( \ 571 DEFAULT_SSP_REG_CR1 | \ 572 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 573 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 574 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 575 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 576 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 577 ) 578 579 /* 580 * The PL023 variant has further differences: no loopback mode, no microwire 581 * support, and a new clock feedback delay setting. 582 */ 583 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 584 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 585 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 586 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 587 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 588 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 589 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 590 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 591 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 592 ) 593 594 #define DEFAULT_SSP_REG_CPSR ( \ 595 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 596 ) 597 598 #define DEFAULT_SSP_REG_DMACR (\ 599 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 600 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 601 ) 602 603 /** 604 * load_ssp_default_config - Load default configuration for SSP 605 * @pl022: SSP driver private data structure 606 */ 607 static void load_ssp_default_config(struct pl022 *pl022) 608 { 609 if (pl022->vendor->pl023) { 610 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 611 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 612 } else if (pl022->vendor->extended_cr) { 613 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 614 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 615 } else { 616 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 617 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 618 } 619 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 620 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 621 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 622 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 623 } 624 625 /** 626 * This will write to TX and read from RX according to the parameters 627 * set in pl022. 628 */ 629 static void readwriter(struct pl022 *pl022) 630 { 631 632 /* 633 * The FIFO depth is different between primecell variants. 634 * I believe filling in too much in the FIFO might cause 635 * errons in 8bit wide transfers on ARM variants (just 8 words 636 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 637 * 638 * To prevent this issue, the TX FIFO is only filled to the 639 * unused RX FIFO fill length, regardless of what the TX 640 * FIFO status flag indicates. 641 */ 642 dev_dbg(&pl022->adev->dev, 643 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 644 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 645 646 /* Read as much as you can */ 647 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 648 && (pl022->rx < pl022->rx_end)) { 649 switch (pl022->read) { 650 case READING_NULL: 651 readw(SSP_DR(pl022->virtbase)); 652 break; 653 case READING_U8: 654 *(u8 *) (pl022->rx) = 655 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 656 break; 657 case READING_U16: 658 *(u16 *) (pl022->rx) = 659 (u16) readw(SSP_DR(pl022->virtbase)); 660 break; 661 case READING_U32: 662 *(u32 *) (pl022->rx) = 663 readl(SSP_DR(pl022->virtbase)); 664 break; 665 } 666 pl022->rx += (pl022->cur_chip->n_bytes); 667 pl022->exp_fifo_level--; 668 } 669 /* 670 * Write as much as possible up to the RX FIFO size 671 */ 672 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 673 && (pl022->tx < pl022->tx_end)) { 674 switch (pl022->write) { 675 case WRITING_NULL: 676 writew(0x0, SSP_DR(pl022->virtbase)); 677 break; 678 case WRITING_U8: 679 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 680 break; 681 case WRITING_U16: 682 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 683 break; 684 case WRITING_U32: 685 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 686 break; 687 } 688 pl022->tx += (pl022->cur_chip->n_bytes); 689 pl022->exp_fifo_level++; 690 /* 691 * This inner reader takes care of things appearing in the RX 692 * FIFO as we're transmitting. This will happen a lot since the 693 * clock starts running when you put things into the TX FIFO, 694 * and then things are continuously clocked into the RX FIFO. 695 */ 696 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 697 && (pl022->rx < pl022->rx_end)) { 698 switch (pl022->read) { 699 case READING_NULL: 700 readw(SSP_DR(pl022->virtbase)); 701 break; 702 case READING_U8: 703 *(u8 *) (pl022->rx) = 704 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 705 break; 706 case READING_U16: 707 *(u16 *) (pl022->rx) = 708 (u16) readw(SSP_DR(pl022->virtbase)); 709 break; 710 case READING_U32: 711 *(u32 *) (pl022->rx) = 712 readl(SSP_DR(pl022->virtbase)); 713 break; 714 } 715 pl022->rx += (pl022->cur_chip->n_bytes); 716 pl022->exp_fifo_level--; 717 } 718 } 719 /* 720 * When we exit here the TX FIFO should be full and the RX FIFO 721 * should be empty 722 */ 723 } 724 725 /** 726 * next_transfer - Move to the Next transfer in the current spi message 727 * @pl022: SSP driver private data structure 728 * 729 * This function moves though the linked list of spi transfers in the 730 * current spi message and returns with the state of current spi 731 * message i.e whether its last transfer is done(STATE_DONE) or 732 * Next transfer is ready(STATE_RUNNING) 733 */ 734 static void *next_transfer(struct pl022 *pl022) 735 { 736 struct spi_message *msg = pl022->cur_msg; 737 struct spi_transfer *trans = pl022->cur_transfer; 738 739 /* Move to next transfer */ 740 if (trans->transfer_list.next != &msg->transfers) { 741 pl022->cur_transfer = 742 list_entry(trans->transfer_list.next, 743 struct spi_transfer, transfer_list); 744 return STATE_RUNNING; 745 } 746 return STATE_DONE; 747 } 748 749 /* 750 * This DMA functionality is only compiled in if we have 751 * access to the generic DMA devices/DMA engine. 752 */ 753 #ifdef CONFIG_DMA_ENGINE 754 static void unmap_free_dma_scatter(struct pl022 *pl022) 755 { 756 /* Unmap and free the SG tables */ 757 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 758 pl022->sgt_tx.nents, DMA_TO_DEVICE); 759 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 760 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 761 sg_free_table(&pl022->sgt_rx); 762 sg_free_table(&pl022->sgt_tx); 763 } 764 765 static void dma_callback(void *data) 766 { 767 struct pl022 *pl022 = data; 768 struct spi_message *msg = pl022->cur_msg; 769 770 BUG_ON(!pl022->sgt_rx.sgl); 771 772 #ifdef VERBOSE_DEBUG 773 /* 774 * Optionally dump out buffers to inspect contents, this is 775 * good if you want to convince yourself that the loopback 776 * read/write contents are the same, when adopting to a new 777 * DMA engine. 778 */ 779 { 780 struct scatterlist *sg; 781 unsigned int i; 782 783 dma_sync_sg_for_cpu(&pl022->adev->dev, 784 pl022->sgt_rx.sgl, 785 pl022->sgt_rx.nents, 786 DMA_FROM_DEVICE); 787 788 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 789 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 790 print_hex_dump(KERN_ERR, "SPI RX: ", 791 DUMP_PREFIX_OFFSET, 792 16, 793 1, 794 sg_virt(sg), 795 sg_dma_len(sg), 796 1); 797 } 798 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 799 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 800 print_hex_dump(KERN_ERR, "SPI TX: ", 801 DUMP_PREFIX_OFFSET, 802 16, 803 1, 804 sg_virt(sg), 805 sg_dma_len(sg), 806 1); 807 } 808 } 809 #endif 810 811 unmap_free_dma_scatter(pl022); 812 813 /* Update total bytes transferred */ 814 msg->actual_length += pl022->cur_transfer->len; 815 if (pl022->cur_transfer->cs_change) 816 pl022->cur_chip-> 817 cs_control(SSP_CHIP_DESELECT); 818 819 /* Move to next transfer */ 820 msg->state = next_transfer(pl022); 821 tasklet_schedule(&pl022->pump_transfers); 822 } 823 824 static void setup_dma_scatter(struct pl022 *pl022, 825 void *buffer, 826 unsigned int length, 827 struct sg_table *sgtab) 828 { 829 struct scatterlist *sg; 830 int bytesleft = length; 831 void *bufp = buffer; 832 int mapbytes; 833 int i; 834 835 if (buffer) { 836 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 837 /* 838 * If there are less bytes left than what fits 839 * in the current page (plus page alignment offset) 840 * we just feed in this, else we stuff in as much 841 * as we can. 842 */ 843 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 844 mapbytes = bytesleft; 845 else 846 mapbytes = PAGE_SIZE - offset_in_page(bufp); 847 sg_set_page(sg, virt_to_page(bufp), 848 mapbytes, offset_in_page(bufp)); 849 bufp += mapbytes; 850 bytesleft -= mapbytes; 851 dev_dbg(&pl022->adev->dev, 852 "set RX/TX target page @ %p, %d bytes, %d left\n", 853 bufp, mapbytes, bytesleft); 854 } 855 } else { 856 /* Map the dummy buffer on every page */ 857 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 858 if (bytesleft < PAGE_SIZE) 859 mapbytes = bytesleft; 860 else 861 mapbytes = PAGE_SIZE; 862 sg_set_page(sg, virt_to_page(pl022->dummypage), 863 mapbytes, 0); 864 bytesleft -= mapbytes; 865 dev_dbg(&pl022->adev->dev, 866 "set RX/TX to dummy page %d bytes, %d left\n", 867 mapbytes, bytesleft); 868 869 } 870 } 871 BUG_ON(bytesleft); 872 } 873 874 /** 875 * configure_dma - configures the channels for the next transfer 876 * @pl022: SSP driver's private data structure 877 */ 878 static int configure_dma(struct pl022 *pl022) 879 { 880 struct dma_slave_config rx_conf = { 881 .src_addr = SSP_DR(pl022->phybase), 882 .direction = DMA_DEV_TO_MEM, 883 .device_fc = false, 884 }; 885 struct dma_slave_config tx_conf = { 886 .dst_addr = SSP_DR(pl022->phybase), 887 .direction = DMA_MEM_TO_DEV, 888 .device_fc = false, 889 }; 890 unsigned int pages; 891 int ret; 892 int rx_sglen, tx_sglen; 893 struct dma_chan *rxchan = pl022->dma_rx_channel; 894 struct dma_chan *txchan = pl022->dma_tx_channel; 895 struct dma_async_tx_descriptor *rxdesc; 896 struct dma_async_tx_descriptor *txdesc; 897 898 /* Check that the channels are available */ 899 if (!rxchan || !txchan) 900 return -ENODEV; 901 902 /* 903 * If supplied, the DMA burstsize should equal the FIFO trigger level. 904 * Notice that the DMA engine uses one-to-one mapping. Since we can 905 * not trigger on 2 elements this needs explicit mapping rather than 906 * calculation. 907 */ 908 switch (pl022->rx_lev_trig) { 909 case SSP_RX_1_OR_MORE_ELEM: 910 rx_conf.src_maxburst = 1; 911 break; 912 case SSP_RX_4_OR_MORE_ELEM: 913 rx_conf.src_maxburst = 4; 914 break; 915 case SSP_RX_8_OR_MORE_ELEM: 916 rx_conf.src_maxburst = 8; 917 break; 918 case SSP_RX_16_OR_MORE_ELEM: 919 rx_conf.src_maxburst = 16; 920 break; 921 case SSP_RX_32_OR_MORE_ELEM: 922 rx_conf.src_maxburst = 32; 923 break; 924 default: 925 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 926 break; 927 } 928 929 switch (pl022->tx_lev_trig) { 930 case SSP_TX_1_OR_MORE_EMPTY_LOC: 931 tx_conf.dst_maxburst = 1; 932 break; 933 case SSP_TX_4_OR_MORE_EMPTY_LOC: 934 tx_conf.dst_maxburst = 4; 935 break; 936 case SSP_TX_8_OR_MORE_EMPTY_LOC: 937 tx_conf.dst_maxburst = 8; 938 break; 939 case SSP_TX_16_OR_MORE_EMPTY_LOC: 940 tx_conf.dst_maxburst = 16; 941 break; 942 case SSP_TX_32_OR_MORE_EMPTY_LOC: 943 tx_conf.dst_maxburst = 32; 944 break; 945 default: 946 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 947 break; 948 } 949 950 switch (pl022->read) { 951 case READING_NULL: 952 /* Use the same as for writing */ 953 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 954 break; 955 case READING_U8: 956 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 957 break; 958 case READING_U16: 959 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 960 break; 961 case READING_U32: 962 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 963 break; 964 } 965 966 switch (pl022->write) { 967 case WRITING_NULL: 968 /* Use the same as for reading */ 969 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 970 break; 971 case WRITING_U8: 972 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 973 break; 974 case WRITING_U16: 975 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 976 break; 977 case WRITING_U32: 978 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 979 break; 980 } 981 982 /* SPI pecularity: we need to read and write the same width */ 983 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 984 rx_conf.src_addr_width = tx_conf.dst_addr_width; 985 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 986 tx_conf.dst_addr_width = rx_conf.src_addr_width; 987 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 988 989 dmaengine_slave_config(rxchan, &rx_conf); 990 dmaengine_slave_config(txchan, &tx_conf); 991 992 /* Create sglists for the transfers */ 993 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 994 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 995 996 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 997 if (ret) 998 goto err_alloc_rx_sg; 999 1000 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1001 if (ret) 1002 goto err_alloc_tx_sg; 1003 1004 /* Fill in the scatterlists for the RX+TX buffers */ 1005 setup_dma_scatter(pl022, pl022->rx, 1006 pl022->cur_transfer->len, &pl022->sgt_rx); 1007 setup_dma_scatter(pl022, pl022->tx, 1008 pl022->cur_transfer->len, &pl022->sgt_tx); 1009 1010 /* Map DMA buffers */ 1011 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1012 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1013 if (!rx_sglen) 1014 goto err_rx_sgmap; 1015 1016 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1017 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1018 if (!tx_sglen) 1019 goto err_tx_sgmap; 1020 1021 /* Send both scatterlists */ 1022 rxdesc = dmaengine_prep_slave_sg(rxchan, 1023 pl022->sgt_rx.sgl, 1024 rx_sglen, 1025 DMA_DEV_TO_MEM, 1026 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1027 if (!rxdesc) 1028 goto err_rxdesc; 1029 1030 txdesc = dmaengine_prep_slave_sg(txchan, 1031 pl022->sgt_tx.sgl, 1032 tx_sglen, 1033 DMA_MEM_TO_DEV, 1034 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1035 if (!txdesc) 1036 goto err_txdesc; 1037 1038 /* Put the callback on the RX transfer only, that should finish last */ 1039 rxdesc->callback = dma_callback; 1040 rxdesc->callback_param = pl022; 1041 1042 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1043 dmaengine_submit(rxdesc); 1044 dmaengine_submit(txdesc); 1045 dma_async_issue_pending(rxchan); 1046 dma_async_issue_pending(txchan); 1047 pl022->dma_running = true; 1048 1049 return 0; 1050 1051 err_txdesc: 1052 dmaengine_terminate_all(txchan); 1053 err_rxdesc: 1054 dmaengine_terminate_all(rxchan); 1055 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1056 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1057 err_tx_sgmap: 1058 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1059 pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1060 err_rx_sgmap: 1061 sg_free_table(&pl022->sgt_tx); 1062 err_alloc_tx_sg: 1063 sg_free_table(&pl022->sgt_rx); 1064 err_alloc_rx_sg: 1065 return -ENOMEM; 1066 } 1067 1068 static int __devinit pl022_dma_probe(struct pl022 *pl022) 1069 { 1070 dma_cap_mask_t mask; 1071 1072 /* Try to acquire a generic DMA engine slave channel */ 1073 dma_cap_zero(mask); 1074 dma_cap_set(DMA_SLAVE, mask); 1075 /* 1076 * We need both RX and TX channels to do DMA, else do none 1077 * of them. 1078 */ 1079 pl022->dma_rx_channel = dma_request_channel(mask, 1080 pl022->master_info->dma_filter, 1081 pl022->master_info->dma_rx_param); 1082 if (!pl022->dma_rx_channel) { 1083 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1084 goto err_no_rxchan; 1085 } 1086 1087 pl022->dma_tx_channel = dma_request_channel(mask, 1088 pl022->master_info->dma_filter, 1089 pl022->master_info->dma_tx_param); 1090 if (!pl022->dma_tx_channel) { 1091 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1092 goto err_no_txchan; 1093 } 1094 1095 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1096 if (!pl022->dummypage) { 1097 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1098 goto err_no_dummypage; 1099 } 1100 1101 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1102 dma_chan_name(pl022->dma_rx_channel), 1103 dma_chan_name(pl022->dma_tx_channel)); 1104 1105 return 0; 1106 1107 err_no_dummypage: 1108 dma_release_channel(pl022->dma_tx_channel); 1109 err_no_txchan: 1110 dma_release_channel(pl022->dma_rx_channel); 1111 pl022->dma_rx_channel = NULL; 1112 err_no_rxchan: 1113 dev_err(&pl022->adev->dev, 1114 "Failed to work in dma mode, work without dma!\n"); 1115 return -ENODEV; 1116 } 1117 1118 static void terminate_dma(struct pl022 *pl022) 1119 { 1120 struct dma_chan *rxchan = pl022->dma_rx_channel; 1121 struct dma_chan *txchan = pl022->dma_tx_channel; 1122 1123 dmaengine_terminate_all(rxchan); 1124 dmaengine_terminate_all(txchan); 1125 unmap_free_dma_scatter(pl022); 1126 pl022->dma_running = false; 1127 } 1128 1129 static void pl022_dma_remove(struct pl022 *pl022) 1130 { 1131 if (pl022->dma_running) 1132 terminate_dma(pl022); 1133 if (pl022->dma_tx_channel) 1134 dma_release_channel(pl022->dma_tx_channel); 1135 if (pl022->dma_rx_channel) 1136 dma_release_channel(pl022->dma_rx_channel); 1137 kfree(pl022->dummypage); 1138 } 1139 1140 #else 1141 static inline int configure_dma(struct pl022 *pl022) 1142 { 1143 return -ENODEV; 1144 } 1145 1146 static inline int pl022_dma_probe(struct pl022 *pl022) 1147 { 1148 return 0; 1149 } 1150 1151 static inline void pl022_dma_remove(struct pl022 *pl022) 1152 { 1153 } 1154 #endif 1155 1156 /** 1157 * pl022_interrupt_handler - Interrupt handler for SSP controller 1158 * 1159 * This function handles interrupts generated for an interrupt based transfer. 1160 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1161 * current message's state as STATE_ERROR and schedule the tasklet 1162 * pump_transfers which will do the postprocessing of the current message by 1163 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1164 * more data, and writes data in TX FIFO till it is not full. If we complete 1165 * the transfer we move to the next transfer and schedule the tasklet. 1166 */ 1167 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1168 { 1169 struct pl022 *pl022 = dev_id; 1170 struct spi_message *msg = pl022->cur_msg; 1171 u16 irq_status = 0; 1172 u16 flag = 0; 1173 1174 if (unlikely(!msg)) { 1175 dev_err(&pl022->adev->dev, 1176 "bad message state in interrupt handler"); 1177 /* Never fail */ 1178 return IRQ_HANDLED; 1179 } 1180 1181 /* Read the Interrupt Status Register */ 1182 irq_status = readw(SSP_MIS(pl022->virtbase)); 1183 1184 if (unlikely(!irq_status)) 1185 return IRQ_NONE; 1186 1187 /* 1188 * This handles the FIFO interrupts, the timeout 1189 * interrupts are flatly ignored, they cannot be 1190 * trusted. 1191 */ 1192 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1193 /* 1194 * Overrun interrupt - bail out since our Data has been 1195 * corrupted 1196 */ 1197 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1198 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1199 dev_err(&pl022->adev->dev, 1200 "RXFIFO is full\n"); 1201 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1202 dev_err(&pl022->adev->dev, 1203 "TXFIFO is full\n"); 1204 1205 /* 1206 * Disable and clear interrupts, disable SSP, 1207 * mark message with bad status so it can be 1208 * retried. 1209 */ 1210 writew(DISABLE_ALL_INTERRUPTS, 1211 SSP_IMSC(pl022->virtbase)); 1212 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1213 writew((readw(SSP_CR1(pl022->virtbase)) & 1214 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1215 msg->state = STATE_ERROR; 1216 1217 /* Schedule message queue handler */ 1218 tasklet_schedule(&pl022->pump_transfers); 1219 return IRQ_HANDLED; 1220 } 1221 1222 readwriter(pl022); 1223 1224 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1225 flag = 1; 1226 /* Disable Transmit interrupt, enable receive interrupt */ 1227 writew((readw(SSP_IMSC(pl022->virtbase)) & 1228 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1229 SSP_IMSC(pl022->virtbase)); 1230 } 1231 1232 /* 1233 * Since all transactions must write as much as shall be read, 1234 * we can conclude the entire transaction once RX is complete. 1235 * At this point, all TX will always be finished. 1236 */ 1237 if (pl022->rx >= pl022->rx_end) { 1238 writew(DISABLE_ALL_INTERRUPTS, 1239 SSP_IMSC(pl022->virtbase)); 1240 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1241 if (unlikely(pl022->rx > pl022->rx_end)) { 1242 dev_warn(&pl022->adev->dev, "read %u surplus " 1243 "bytes (did you request an odd " 1244 "number of bytes on a 16bit bus?)\n", 1245 (u32) (pl022->rx - pl022->rx_end)); 1246 } 1247 /* Update total bytes transferred */ 1248 msg->actual_length += pl022->cur_transfer->len; 1249 if (pl022->cur_transfer->cs_change) 1250 pl022->cur_chip-> 1251 cs_control(SSP_CHIP_DESELECT); 1252 /* Move to next transfer */ 1253 msg->state = next_transfer(pl022); 1254 tasklet_schedule(&pl022->pump_transfers); 1255 return IRQ_HANDLED; 1256 } 1257 1258 return IRQ_HANDLED; 1259 } 1260 1261 /** 1262 * This sets up the pointers to memory for the next message to 1263 * send out on the SPI bus. 1264 */ 1265 static int set_up_next_transfer(struct pl022 *pl022, 1266 struct spi_transfer *transfer) 1267 { 1268 int residue; 1269 1270 /* Sanity check the message for this bus width */ 1271 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1272 if (unlikely(residue != 0)) { 1273 dev_err(&pl022->adev->dev, 1274 "message of %u bytes to transmit but the current " 1275 "chip bus has a data width of %u bytes!\n", 1276 pl022->cur_transfer->len, 1277 pl022->cur_chip->n_bytes); 1278 dev_err(&pl022->adev->dev, "skipping this message\n"); 1279 return -EIO; 1280 } 1281 pl022->tx = (void *)transfer->tx_buf; 1282 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1283 pl022->rx = (void *)transfer->rx_buf; 1284 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1285 pl022->write = 1286 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1287 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1288 return 0; 1289 } 1290 1291 /** 1292 * pump_transfers - Tasklet function which schedules next transfer 1293 * when running in interrupt or DMA transfer mode. 1294 * @data: SSP driver private data structure 1295 * 1296 */ 1297 static void pump_transfers(unsigned long data) 1298 { 1299 struct pl022 *pl022 = (struct pl022 *) data; 1300 struct spi_message *message = NULL; 1301 struct spi_transfer *transfer = NULL; 1302 struct spi_transfer *previous = NULL; 1303 1304 /* Get current state information */ 1305 message = pl022->cur_msg; 1306 transfer = pl022->cur_transfer; 1307 1308 /* Handle for abort */ 1309 if (message->state == STATE_ERROR) { 1310 message->status = -EIO; 1311 giveback(pl022); 1312 return; 1313 } 1314 1315 /* Handle end of message */ 1316 if (message->state == STATE_DONE) { 1317 message->status = 0; 1318 giveback(pl022); 1319 return; 1320 } 1321 1322 /* Delay if requested at end of transfer before CS change */ 1323 if (message->state == STATE_RUNNING) { 1324 previous = list_entry(transfer->transfer_list.prev, 1325 struct spi_transfer, 1326 transfer_list); 1327 if (previous->delay_usecs) 1328 /* 1329 * FIXME: This runs in interrupt context. 1330 * Is this really smart? 1331 */ 1332 udelay(previous->delay_usecs); 1333 1334 /* Reselect chip select only if cs_change was requested */ 1335 if (previous->cs_change) 1336 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1337 } else { 1338 /* STATE_START */ 1339 message->state = STATE_RUNNING; 1340 } 1341 1342 if (set_up_next_transfer(pl022, transfer)) { 1343 message->state = STATE_ERROR; 1344 message->status = -EIO; 1345 giveback(pl022); 1346 return; 1347 } 1348 /* Flush the FIFOs and let's go! */ 1349 flush(pl022); 1350 1351 if (pl022->cur_chip->enable_dma) { 1352 if (configure_dma(pl022)) { 1353 dev_dbg(&pl022->adev->dev, 1354 "configuration of DMA failed, fall back to interrupt mode\n"); 1355 goto err_config_dma; 1356 } 1357 return; 1358 } 1359 1360 err_config_dma: 1361 /* enable all interrupts except RX */ 1362 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1363 } 1364 1365 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1366 { 1367 /* 1368 * Default is to enable all interrupts except RX - 1369 * this will be enabled once TX is complete 1370 */ 1371 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1372 1373 /* Enable target chip, if not already active */ 1374 if (!pl022->next_msg_cs_active) 1375 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1376 1377 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1378 /* Error path */ 1379 pl022->cur_msg->state = STATE_ERROR; 1380 pl022->cur_msg->status = -EIO; 1381 giveback(pl022); 1382 return; 1383 } 1384 /* If we're using DMA, set up DMA here */ 1385 if (pl022->cur_chip->enable_dma) { 1386 /* Configure DMA transfer */ 1387 if (configure_dma(pl022)) { 1388 dev_dbg(&pl022->adev->dev, 1389 "configuration of DMA failed, fall back to interrupt mode\n"); 1390 goto err_config_dma; 1391 } 1392 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1393 irqflags = DISABLE_ALL_INTERRUPTS; 1394 } 1395 err_config_dma: 1396 /* Enable SSP, turn on interrupts */ 1397 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1398 SSP_CR1(pl022->virtbase)); 1399 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1400 } 1401 1402 static void do_polling_transfer(struct pl022 *pl022) 1403 { 1404 struct spi_message *message = NULL; 1405 struct spi_transfer *transfer = NULL; 1406 struct spi_transfer *previous = NULL; 1407 struct chip_data *chip; 1408 unsigned long time, timeout; 1409 1410 chip = pl022->cur_chip; 1411 message = pl022->cur_msg; 1412 1413 while (message->state != STATE_DONE) { 1414 /* Handle for abort */ 1415 if (message->state == STATE_ERROR) 1416 break; 1417 transfer = pl022->cur_transfer; 1418 1419 /* Delay if requested at end of transfer */ 1420 if (message->state == STATE_RUNNING) { 1421 previous = 1422 list_entry(transfer->transfer_list.prev, 1423 struct spi_transfer, transfer_list); 1424 if (previous->delay_usecs) 1425 udelay(previous->delay_usecs); 1426 if (previous->cs_change) 1427 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1428 } else { 1429 /* STATE_START */ 1430 message->state = STATE_RUNNING; 1431 if (!pl022->next_msg_cs_active) 1432 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1433 } 1434 1435 /* Configuration Changing Per Transfer */ 1436 if (set_up_next_transfer(pl022, transfer)) { 1437 /* Error path */ 1438 message->state = STATE_ERROR; 1439 break; 1440 } 1441 /* Flush FIFOs and enable SSP */ 1442 flush(pl022); 1443 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1444 SSP_CR1(pl022->virtbase)); 1445 1446 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1447 1448 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1449 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1450 time = jiffies; 1451 readwriter(pl022); 1452 if (time_after(time, timeout)) { 1453 dev_warn(&pl022->adev->dev, 1454 "%s: timeout!\n", __func__); 1455 message->state = STATE_ERROR; 1456 goto out; 1457 } 1458 cpu_relax(); 1459 } 1460 1461 /* Update total byte transferred */ 1462 message->actual_length += pl022->cur_transfer->len; 1463 if (pl022->cur_transfer->cs_change) 1464 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 1465 /* Move to next transfer */ 1466 message->state = next_transfer(pl022); 1467 } 1468 out: 1469 /* Handle end of message */ 1470 if (message->state == STATE_DONE) 1471 message->status = 0; 1472 else 1473 message->status = -EIO; 1474 1475 giveback(pl022); 1476 return; 1477 } 1478 1479 static int pl022_transfer_one_message(struct spi_master *master, 1480 struct spi_message *msg) 1481 { 1482 struct pl022 *pl022 = spi_master_get_devdata(master); 1483 1484 /* Initial message state */ 1485 pl022->cur_msg = msg; 1486 msg->state = STATE_START; 1487 1488 pl022->cur_transfer = list_entry(msg->transfers.next, 1489 struct spi_transfer, transfer_list); 1490 1491 /* Setup the SPI using the per chip configuration */ 1492 pl022->cur_chip = spi_get_ctldata(msg->spi); 1493 1494 restore_state(pl022); 1495 flush(pl022); 1496 1497 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1498 do_polling_transfer(pl022); 1499 else 1500 do_interrupt_dma_transfer(pl022); 1501 1502 return 0; 1503 } 1504 1505 static int pl022_prepare_transfer_hardware(struct spi_master *master) 1506 { 1507 struct pl022 *pl022 = spi_master_get_devdata(master); 1508 1509 /* 1510 * Just make sure we have all we need to run the transfer by syncing 1511 * with the runtime PM framework. 1512 */ 1513 pm_runtime_get_sync(&pl022->adev->dev); 1514 return 0; 1515 } 1516 1517 static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1518 { 1519 struct pl022 *pl022 = spi_master_get_devdata(master); 1520 1521 /* nothing more to do - disable spi/ssp and power off */ 1522 writew((readw(SSP_CR1(pl022->virtbase)) & 1523 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1524 1525 if (pl022->master_info->autosuspend_delay > 0) { 1526 pm_runtime_mark_last_busy(&pl022->adev->dev); 1527 pm_runtime_put_autosuspend(&pl022->adev->dev); 1528 } else { 1529 pm_runtime_put(&pl022->adev->dev); 1530 } 1531 1532 return 0; 1533 } 1534 1535 static int verify_controller_parameters(struct pl022 *pl022, 1536 struct pl022_config_chip const *chip_info) 1537 { 1538 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1539 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1540 dev_err(&pl022->adev->dev, 1541 "interface is configured incorrectly\n"); 1542 return -EINVAL; 1543 } 1544 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1545 (!pl022->vendor->unidir)) { 1546 dev_err(&pl022->adev->dev, 1547 "unidirectional mode not supported in this " 1548 "hardware version\n"); 1549 return -EINVAL; 1550 } 1551 if ((chip_info->hierarchy != SSP_MASTER) 1552 && (chip_info->hierarchy != SSP_SLAVE)) { 1553 dev_err(&pl022->adev->dev, 1554 "hierarchy is configured incorrectly\n"); 1555 return -EINVAL; 1556 } 1557 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1558 && (chip_info->com_mode != DMA_TRANSFER) 1559 && (chip_info->com_mode != POLLING_TRANSFER)) { 1560 dev_err(&pl022->adev->dev, 1561 "Communication mode is configured incorrectly\n"); 1562 return -EINVAL; 1563 } 1564 switch (chip_info->rx_lev_trig) { 1565 case SSP_RX_1_OR_MORE_ELEM: 1566 case SSP_RX_4_OR_MORE_ELEM: 1567 case SSP_RX_8_OR_MORE_ELEM: 1568 /* These are always OK, all variants can handle this */ 1569 break; 1570 case SSP_RX_16_OR_MORE_ELEM: 1571 if (pl022->vendor->fifodepth < 16) { 1572 dev_err(&pl022->adev->dev, 1573 "RX FIFO Trigger Level is configured incorrectly\n"); 1574 return -EINVAL; 1575 } 1576 break; 1577 case SSP_RX_32_OR_MORE_ELEM: 1578 if (pl022->vendor->fifodepth < 32) { 1579 dev_err(&pl022->adev->dev, 1580 "RX FIFO Trigger Level is configured incorrectly\n"); 1581 return -EINVAL; 1582 } 1583 break; 1584 default: 1585 dev_err(&pl022->adev->dev, 1586 "RX FIFO Trigger Level is configured incorrectly\n"); 1587 return -EINVAL; 1588 break; 1589 } 1590 switch (chip_info->tx_lev_trig) { 1591 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1592 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1593 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1594 /* These are always OK, all variants can handle this */ 1595 break; 1596 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1597 if (pl022->vendor->fifodepth < 16) { 1598 dev_err(&pl022->adev->dev, 1599 "TX FIFO Trigger Level is configured incorrectly\n"); 1600 return -EINVAL; 1601 } 1602 break; 1603 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1604 if (pl022->vendor->fifodepth < 32) { 1605 dev_err(&pl022->adev->dev, 1606 "TX FIFO Trigger Level is configured incorrectly\n"); 1607 return -EINVAL; 1608 } 1609 break; 1610 default: 1611 dev_err(&pl022->adev->dev, 1612 "TX FIFO Trigger Level is configured incorrectly\n"); 1613 return -EINVAL; 1614 break; 1615 } 1616 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1617 if ((chip_info->ctrl_len < SSP_BITS_4) 1618 || (chip_info->ctrl_len > SSP_BITS_32)) { 1619 dev_err(&pl022->adev->dev, 1620 "CTRL LEN is configured incorrectly\n"); 1621 return -EINVAL; 1622 } 1623 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1624 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1625 dev_err(&pl022->adev->dev, 1626 "Wait State is configured incorrectly\n"); 1627 return -EINVAL; 1628 } 1629 /* Half duplex is only available in the ST Micro version */ 1630 if (pl022->vendor->extended_cr) { 1631 if ((chip_info->duplex != 1632 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1633 && (chip_info->duplex != 1634 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1635 dev_err(&pl022->adev->dev, 1636 "Microwire duplex mode is configured incorrectly\n"); 1637 return -EINVAL; 1638 } 1639 } else { 1640 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1641 dev_err(&pl022->adev->dev, 1642 "Microwire half duplex mode requested," 1643 " but this is only available in the" 1644 " ST version of PL022\n"); 1645 return -EINVAL; 1646 } 1647 } 1648 return 0; 1649 } 1650 1651 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1652 { 1653 return rate / (cpsdvsr * (1 + scr)); 1654 } 1655 1656 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1657 ssp_clock_params * clk_freq) 1658 { 1659 /* Lets calculate the frequency parameters */ 1660 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1661 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1662 best_scr = 0, tmp, found = 0; 1663 1664 rate = clk_get_rate(pl022->clk); 1665 /* cpsdvscr = 2 & scr 0 */ 1666 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1667 /* cpsdvsr = 254 & scr = 255 */ 1668 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1669 1670 if (!((freq <= max_tclk) && (freq >= min_tclk))) { 1671 dev_err(&pl022->adev->dev, 1672 "controller data is incorrect: out of range frequency"); 1673 return -EINVAL; 1674 } 1675 1676 /* 1677 * best_freq will give closest possible available rate (<= requested 1678 * freq) for all values of scr & cpsdvsr. 1679 */ 1680 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1681 while (scr <= SCR_MAX) { 1682 tmp = spi_rate(rate, cpsdvsr, scr); 1683 1684 if (tmp > freq) 1685 scr++; 1686 /* 1687 * If found exact value, update and break. 1688 * If found more closer value, update and continue. 1689 */ 1690 else if ((tmp == freq) || (tmp > best_freq)) { 1691 best_freq = tmp; 1692 best_cpsdvsr = cpsdvsr; 1693 best_scr = scr; 1694 1695 if (tmp == freq) 1696 break; 1697 } 1698 scr++; 1699 } 1700 cpsdvsr += 2; 1701 scr = SCR_MIN; 1702 } 1703 1704 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1705 clk_freq->scr = (u8) (best_scr & 0xFF); 1706 dev_dbg(&pl022->adev->dev, 1707 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1708 freq, best_freq); 1709 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1710 clk_freq->cpsdvsr, clk_freq->scr); 1711 1712 return 0; 1713 } 1714 1715 /* 1716 * A piece of default chip info unless the platform 1717 * supplies it. 1718 */ 1719 static const struct pl022_config_chip pl022_default_chip_info = { 1720 .com_mode = POLLING_TRANSFER, 1721 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1722 .hierarchy = SSP_SLAVE, 1723 .slave_tx_disable = DO_NOT_DRIVE_TX, 1724 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1725 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1726 .ctrl_len = SSP_BITS_8, 1727 .wait_state = SSP_MWIRE_WAIT_ZERO, 1728 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1729 .cs_control = null_cs_control, 1730 }; 1731 1732 /** 1733 * pl022_setup - setup function registered to SPI master framework 1734 * @spi: spi device which is requesting setup 1735 * 1736 * This function is registered to the SPI framework for this SPI master 1737 * controller. If it is the first time when setup is called by this device, 1738 * this function will initialize the runtime state for this chip and save 1739 * the same in the device structure. Else it will update the runtime info 1740 * with the updated chip info. Nothing is really being written to the 1741 * controller hardware here, that is not done until the actual transfer 1742 * commence. 1743 */ 1744 static int pl022_setup(struct spi_device *spi) 1745 { 1746 struct pl022_config_chip const *chip_info; 1747 struct chip_data *chip; 1748 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1749 int status = 0; 1750 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1751 unsigned int bits = spi->bits_per_word; 1752 u32 tmp; 1753 1754 if (!spi->max_speed_hz) 1755 return -EINVAL; 1756 1757 /* Get controller_state if one is supplied */ 1758 chip = spi_get_ctldata(spi); 1759 1760 if (chip == NULL) { 1761 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1762 if (!chip) { 1763 dev_err(&spi->dev, 1764 "cannot allocate controller state\n"); 1765 return -ENOMEM; 1766 } 1767 dev_dbg(&spi->dev, 1768 "allocated memory for controller's runtime state\n"); 1769 } 1770 1771 /* Get controller data if one is supplied */ 1772 chip_info = spi->controller_data; 1773 1774 if (chip_info == NULL) { 1775 chip_info = &pl022_default_chip_info; 1776 /* spi_board_info.controller_data not is supplied */ 1777 dev_dbg(&spi->dev, 1778 "using default controller_data settings\n"); 1779 } else 1780 dev_dbg(&spi->dev, 1781 "using user supplied controller_data settings\n"); 1782 1783 /* 1784 * We can override with custom divisors, else we use the board 1785 * frequency setting 1786 */ 1787 if ((0 == chip_info->clk_freq.cpsdvsr) 1788 && (0 == chip_info->clk_freq.scr)) { 1789 status = calculate_effective_freq(pl022, 1790 spi->max_speed_hz, 1791 &clk_freq); 1792 if (status < 0) 1793 goto err_config_params; 1794 } else { 1795 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1796 if ((clk_freq.cpsdvsr % 2) != 0) 1797 clk_freq.cpsdvsr = 1798 clk_freq.cpsdvsr - 1; 1799 } 1800 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1801 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1802 status = -EINVAL; 1803 dev_err(&spi->dev, 1804 "cpsdvsr is configured incorrectly\n"); 1805 goto err_config_params; 1806 } 1807 1808 status = verify_controller_parameters(pl022, chip_info); 1809 if (status) { 1810 dev_err(&spi->dev, "controller data is incorrect"); 1811 goto err_config_params; 1812 } 1813 1814 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1815 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1816 1817 /* Now set controller state based on controller data */ 1818 chip->xfer_type = chip_info->com_mode; 1819 if (!chip_info->cs_control) { 1820 chip->cs_control = null_cs_control; 1821 dev_warn(&spi->dev, 1822 "chip select function is NULL for this chip\n"); 1823 } else 1824 chip->cs_control = chip_info->cs_control; 1825 1826 /* Check bits per word with vendor specific range */ 1827 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1828 status = -ENOTSUPP; 1829 dev_err(&spi->dev, "illegal data size for this controller!\n"); 1830 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1831 pl022->vendor->max_bpw); 1832 goto err_config_params; 1833 } else if (bits <= 8) { 1834 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1835 chip->n_bytes = 1; 1836 chip->read = READING_U8; 1837 chip->write = WRITING_U8; 1838 } else if (bits <= 16) { 1839 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1840 chip->n_bytes = 2; 1841 chip->read = READING_U16; 1842 chip->write = WRITING_U16; 1843 } else { 1844 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1845 chip->n_bytes = 4; 1846 chip->read = READING_U32; 1847 chip->write = WRITING_U32; 1848 } 1849 1850 /* Now Initialize all register settings required for this chip */ 1851 chip->cr0 = 0; 1852 chip->cr1 = 0; 1853 chip->dmacr = 0; 1854 chip->cpsr = 0; 1855 if ((chip_info->com_mode == DMA_TRANSFER) 1856 && ((pl022->master_info)->enable_dma)) { 1857 chip->enable_dma = true; 1858 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1859 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1860 SSP_DMACR_MASK_RXDMAE, 0); 1861 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1862 SSP_DMACR_MASK_TXDMAE, 1); 1863 } else { 1864 chip->enable_dma = false; 1865 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1866 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1867 SSP_DMACR_MASK_RXDMAE, 0); 1868 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1869 SSP_DMACR_MASK_TXDMAE, 1); 1870 } 1871 1872 chip->cpsr = clk_freq.cpsdvsr; 1873 1874 /* Special setup for the ST micro extended control registers */ 1875 if (pl022->vendor->extended_cr) { 1876 u32 etx; 1877 1878 if (pl022->vendor->pl023) { 1879 /* These bits are only in the PL023 */ 1880 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1881 SSP_CR1_MASK_FBCLKDEL_ST, 13); 1882 } else { 1883 /* These bits are in the PL022 but not PL023 */ 1884 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1885 SSP_CR0_MASK_HALFDUP_ST, 5); 1886 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1887 SSP_CR0_MASK_CSS_ST, 16); 1888 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1889 SSP_CR0_MASK_FRF_ST, 21); 1890 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 1891 SSP_CR1_MASK_MWAIT_ST, 6); 1892 } 1893 SSP_WRITE_BITS(chip->cr0, bits - 1, 1894 SSP_CR0_MASK_DSS_ST, 0); 1895 1896 if (spi->mode & SPI_LSB_FIRST) { 1897 tmp = SSP_RX_LSB; 1898 etx = SSP_TX_LSB; 1899 } else { 1900 tmp = SSP_RX_MSB; 1901 etx = SSP_TX_MSB; 1902 } 1903 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 1904 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 1905 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 1906 SSP_CR1_MASK_RXIFLSEL_ST, 7); 1907 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 1908 SSP_CR1_MASK_TXIFLSEL_ST, 10); 1909 } else { 1910 SSP_WRITE_BITS(chip->cr0, bits - 1, 1911 SSP_CR0_MASK_DSS, 0); 1912 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1913 SSP_CR0_MASK_FRF, 4); 1914 } 1915 1916 /* Stuff that is common for all versions */ 1917 if (spi->mode & SPI_CPOL) 1918 tmp = SSP_CLK_POL_IDLE_HIGH; 1919 else 1920 tmp = SSP_CLK_POL_IDLE_LOW; 1921 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 1922 1923 if (spi->mode & SPI_CPHA) 1924 tmp = SSP_CLK_SECOND_EDGE; 1925 else 1926 tmp = SSP_CLK_FIRST_EDGE; 1927 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 1928 1929 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 1930 /* Loopback is available on all versions except PL023 */ 1931 if (pl022->vendor->loopback) { 1932 if (spi->mode & SPI_LOOP) 1933 tmp = LOOPBACK_ENABLED; 1934 else 1935 tmp = LOOPBACK_DISABLED; 1936 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 1937 } 1938 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 1939 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 1940 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 1941 3); 1942 1943 /* Save controller_state */ 1944 spi_set_ctldata(spi, chip); 1945 return status; 1946 err_config_params: 1947 spi_set_ctldata(spi, NULL); 1948 kfree(chip); 1949 return status; 1950 } 1951 1952 /** 1953 * pl022_cleanup - cleanup function registered to SPI master framework 1954 * @spi: spi device which is requesting cleanup 1955 * 1956 * This function is registered to the SPI framework for this SPI master 1957 * controller. It will free the runtime state of chip. 1958 */ 1959 static void pl022_cleanup(struct spi_device *spi) 1960 { 1961 struct chip_data *chip = spi_get_ctldata(spi); 1962 1963 spi_set_ctldata(spi, NULL); 1964 kfree(chip); 1965 } 1966 1967 static int __devinit 1968 pl022_probe(struct amba_device *adev, const struct amba_id *id) 1969 { 1970 struct device *dev = &adev->dev; 1971 struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 1972 struct spi_master *master; 1973 struct pl022 *pl022 = NULL; /*Data for this driver */ 1974 int status = 0; 1975 1976 dev_info(&adev->dev, 1977 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 1978 if (platform_info == NULL) { 1979 dev_err(&adev->dev, "probe - no platform data supplied\n"); 1980 status = -ENODEV; 1981 goto err_no_pdata; 1982 } 1983 1984 /* Allocate master with space for data */ 1985 master = spi_alloc_master(dev, sizeof(struct pl022)); 1986 if (master == NULL) { 1987 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 1988 status = -ENOMEM; 1989 goto err_no_master; 1990 } 1991 1992 pl022 = spi_master_get_devdata(master); 1993 pl022->master = master; 1994 pl022->master_info = platform_info; 1995 pl022->adev = adev; 1996 pl022->vendor = id->data; 1997 1998 /* 1999 * Bus Number Which has been Assigned to this SSP controller 2000 * on this board 2001 */ 2002 master->bus_num = platform_info->bus_id; 2003 master->num_chipselect = platform_info->num_chipselect; 2004 master->cleanup = pl022_cleanup; 2005 master->setup = pl022_setup; 2006 master->prepare_transfer_hardware = pl022_prepare_transfer_hardware; 2007 master->transfer_one_message = pl022_transfer_one_message; 2008 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2009 master->rt = platform_info->rt; 2010 2011 /* 2012 * Supports mode 0-3, loopback, and active low CS. Transfers are 2013 * always MS bit first on the original pl022. 2014 */ 2015 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2016 if (pl022->vendor->extended_cr) 2017 master->mode_bits |= SPI_LSB_FIRST; 2018 2019 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2020 2021 status = amba_request_regions(adev, NULL); 2022 if (status) 2023 goto err_no_ioregion; 2024 2025 pl022->phybase = adev->res.start; 2026 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2027 if (pl022->virtbase == NULL) { 2028 status = -ENOMEM; 2029 goto err_no_ioremap; 2030 } 2031 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2032 adev->res.start, pl022->virtbase); 2033 2034 pl022->clk = clk_get(&adev->dev, NULL); 2035 if (IS_ERR(pl022->clk)) { 2036 status = PTR_ERR(pl022->clk); 2037 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2038 goto err_no_clk; 2039 } 2040 2041 status = clk_prepare(pl022->clk); 2042 if (status) { 2043 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 2044 goto err_clk_prep; 2045 } 2046 2047 status = clk_enable(pl022->clk); 2048 if (status) { 2049 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2050 goto err_no_clk_en; 2051 } 2052 2053 /* Initialize transfer pump */ 2054 tasklet_init(&pl022->pump_transfers, pump_transfers, 2055 (unsigned long)pl022); 2056 2057 /* Disable SSP */ 2058 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2059 SSP_CR1(pl022->virtbase)); 2060 load_ssp_default_config(pl022); 2061 2062 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2063 pl022); 2064 if (status < 0) { 2065 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2066 goto err_no_irq; 2067 } 2068 2069 /* Get DMA channels */ 2070 if (platform_info->enable_dma) { 2071 status = pl022_dma_probe(pl022); 2072 if (status != 0) 2073 platform_info->enable_dma = 0; 2074 } 2075 2076 /* Register with the SPI framework */ 2077 amba_set_drvdata(adev, pl022); 2078 status = spi_register_master(master); 2079 if (status != 0) { 2080 dev_err(&adev->dev, 2081 "probe - problem registering spi master\n"); 2082 goto err_spi_register; 2083 } 2084 dev_dbg(dev, "probe succeeded\n"); 2085 2086 /* let runtime pm put suspend */ 2087 if (platform_info->autosuspend_delay > 0) { 2088 dev_info(&adev->dev, 2089 "will use autosuspend for runtime pm, delay %dms\n", 2090 platform_info->autosuspend_delay); 2091 pm_runtime_set_autosuspend_delay(dev, 2092 platform_info->autosuspend_delay); 2093 pm_runtime_use_autosuspend(dev); 2094 pm_runtime_put_autosuspend(dev); 2095 } else { 2096 pm_runtime_put(dev); 2097 } 2098 return 0; 2099 2100 err_spi_register: 2101 if (platform_info->enable_dma) 2102 pl022_dma_remove(pl022); 2103 2104 free_irq(adev->irq[0], pl022); 2105 err_no_irq: 2106 clk_disable(pl022->clk); 2107 err_no_clk_en: 2108 clk_unprepare(pl022->clk); 2109 err_clk_prep: 2110 clk_put(pl022->clk); 2111 err_no_clk: 2112 iounmap(pl022->virtbase); 2113 err_no_ioremap: 2114 amba_release_regions(adev); 2115 err_no_ioregion: 2116 spi_master_put(master); 2117 err_no_master: 2118 err_no_pdata: 2119 return status; 2120 } 2121 2122 static int __devexit 2123 pl022_remove(struct amba_device *adev) 2124 { 2125 struct pl022 *pl022 = amba_get_drvdata(adev); 2126 2127 if (!pl022) 2128 return 0; 2129 2130 /* 2131 * undo pm_runtime_put() in probe. I assume that we're not 2132 * accessing the primecell here. 2133 */ 2134 pm_runtime_get_noresume(&adev->dev); 2135 2136 load_ssp_default_config(pl022); 2137 if (pl022->master_info->enable_dma) 2138 pl022_dma_remove(pl022); 2139 2140 free_irq(adev->irq[0], pl022); 2141 clk_disable(pl022->clk); 2142 clk_unprepare(pl022->clk); 2143 clk_put(pl022->clk); 2144 iounmap(pl022->virtbase); 2145 amba_release_regions(adev); 2146 tasklet_disable(&pl022->pump_transfers); 2147 spi_unregister_master(pl022->master); 2148 spi_master_put(pl022->master); 2149 amba_set_drvdata(adev, NULL); 2150 return 0; 2151 } 2152 2153 #ifdef CONFIG_SUSPEND 2154 static int pl022_suspend(struct device *dev) 2155 { 2156 struct pl022 *pl022 = dev_get_drvdata(dev); 2157 int ret; 2158 2159 ret = spi_master_suspend(pl022->master); 2160 if (ret) { 2161 dev_warn(dev, "cannot suspend master\n"); 2162 return ret; 2163 } 2164 2165 dev_dbg(dev, "suspended\n"); 2166 return 0; 2167 } 2168 2169 static int pl022_resume(struct device *dev) 2170 { 2171 struct pl022 *pl022 = dev_get_drvdata(dev); 2172 int ret; 2173 2174 /* Start the queue running */ 2175 ret = spi_master_resume(pl022->master); 2176 if (ret) 2177 dev_err(dev, "problem starting queue (%d)\n", ret); 2178 else 2179 dev_dbg(dev, "resumed\n"); 2180 2181 return ret; 2182 } 2183 #endif /* CONFIG_PM */ 2184 2185 #ifdef CONFIG_PM_RUNTIME 2186 static int pl022_runtime_suspend(struct device *dev) 2187 { 2188 struct pl022 *pl022 = dev_get_drvdata(dev); 2189 2190 clk_disable(pl022->clk); 2191 2192 return 0; 2193 } 2194 2195 static int pl022_runtime_resume(struct device *dev) 2196 { 2197 struct pl022 *pl022 = dev_get_drvdata(dev); 2198 2199 clk_enable(pl022->clk); 2200 2201 return 0; 2202 } 2203 #endif 2204 2205 static const struct dev_pm_ops pl022_dev_pm_ops = { 2206 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2207 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2208 }; 2209 2210 static struct vendor_data vendor_arm = { 2211 .fifodepth = 8, 2212 .max_bpw = 16, 2213 .unidir = false, 2214 .extended_cr = false, 2215 .pl023 = false, 2216 .loopback = true, 2217 }; 2218 2219 static struct vendor_data vendor_st = { 2220 .fifodepth = 32, 2221 .max_bpw = 32, 2222 .unidir = false, 2223 .extended_cr = true, 2224 .pl023 = false, 2225 .loopback = true, 2226 }; 2227 2228 static struct vendor_data vendor_st_pl023 = { 2229 .fifodepth = 32, 2230 .max_bpw = 32, 2231 .unidir = false, 2232 .extended_cr = true, 2233 .pl023 = true, 2234 .loopback = false, 2235 }; 2236 2237 static struct vendor_data vendor_db5500_pl023 = { 2238 .fifodepth = 32, 2239 .max_bpw = 32, 2240 .unidir = false, 2241 .extended_cr = true, 2242 .pl023 = true, 2243 .loopback = true, 2244 }; 2245 2246 static struct amba_id pl022_ids[] = { 2247 { 2248 /* 2249 * ARM PL022 variant, this has a 16bit wide 2250 * and 8 locations deep TX/RX FIFO 2251 */ 2252 .id = 0x00041022, 2253 .mask = 0x000fffff, 2254 .data = &vendor_arm, 2255 }, 2256 { 2257 /* 2258 * ST Micro derivative, this has 32bit wide 2259 * and 32 locations deep TX/RX FIFO 2260 */ 2261 .id = 0x01080022, 2262 .mask = 0xffffffff, 2263 .data = &vendor_st, 2264 }, 2265 { 2266 /* 2267 * ST-Ericsson derivative "PL023" (this is not 2268 * an official ARM number), this is a PL022 SSP block 2269 * stripped to SPI mode only, it has 32bit wide 2270 * and 32 locations deep TX/RX FIFO but no extended 2271 * CR0/CR1 register 2272 */ 2273 .id = 0x00080023, 2274 .mask = 0xffffffff, 2275 .data = &vendor_st_pl023, 2276 }, 2277 { 2278 .id = 0x10080023, 2279 .mask = 0xffffffff, 2280 .data = &vendor_db5500_pl023, 2281 }, 2282 { 0, 0 }, 2283 }; 2284 2285 MODULE_DEVICE_TABLE(amba, pl022_ids); 2286 2287 static struct amba_driver pl022_driver = { 2288 .drv = { 2289 .name = "ssp-pl022", 2290 .pm = &pl022_dev_pm_ops, 2291 }, 2292 .id_table = pl022_ids, 2293 .probe = pl022_probe, 2294 .remove = __devexit_p(pl022_remove), 2295 }; 2296 2297 static int __init pl022_init(void) 2298 { 2299 return amba_driver_register(&pl022_driver); 2300 } 2301 subsys_initcall(pl022_init); 2302 2303 static void __exit pl022_exit(void) 2304 { 2305 amba_driver_unregister(&pl022_driver); 2306 } 2307 module_exit(pl022_exit); 2308 2309 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2310 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2311 MODULE_LICENSE("GPL"); 2312