1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2009 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/delay.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/amba/bus.h> 36 #include <linux/amba/pl022.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 #include <linux/dmaengine.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/scatterlist.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/gpio.h> 44 #include <linux/of_gpio.h> 45 46 /* 47 * This macro is used to define some register default values. 48 * reg is masked with mask, the OR:ed with an (again masked) 49 * val shifted sb steps to the left. 50 */ 51 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 52 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 53 54 /* 55 * This macro is also used to define some default values. 56 * It will just shift val by sb steps to the left and mask 57 * the result with mask. 58 */ 59 #define GEN_MASK_BITS(val, mask, sb) \ 60 (((val)<<(sb)) & (mask)) 61 62 #define DRIVE_TX 0 63 #define DO_NOT_DRIVE_TX 1 64 65 #define DO_NOT_QUEUE_DMA 0 66 #define QUEUE_DMA 1 67 68 #define RX_TRANSFER 1 69 #define TX_TRANSFER 2 70 71 /* 72 * Macros to access SSP Registers with their offsets 73 */ 74 #define SSP_CR0(r) (r + 0x000) 75 #define SSP_CR1(r) (r + 0x004) 76 #define SSP_DR(r) (r + 0x008) 77 #define SSP_SR(r) (r + 0x00C) 78 #define SSP_CPSR(r) (r + 0x010) 79 #define SSP_IMSC(r) (r + 0x014) 80 #define SSP_RIS(r) (r + 0x018) 81 #define SSP_MIS(r) (r + 0x01C) 82 #define SSP_ICR(r) (r + 0x020) 83 #define SSP_DMACR(r) (r + 0x024) 84 #define SSP_ITCR(r) (r + 0x080) 85 #define SSP_ITIP(r) (r + 0x084) 86 #define SSP_ITOP(r) (r + 0x088) 87 #define SSP_TDR(r) (r + 0x08C) 88 89 #define SSP_PID0(r) (r + 0xFE0) 90 #define SSP_PID1(r) (r + 0xFE4) 91 #define SSP_PID2(r) (r + 0xFE8) 92 #define SSP_PID3(r) (r + 0xFEC) 93 94 #define SSP_CID0(r) (r + 0xFF0) 95 #define SSP_CID1(r) (r + 0xFF4) 96 #define SSP_CID2(r) (r + 0xFF8) 97 #define SSP_CID3(r) (r + 0xFFC) 98 99 /* 100 * SSP Control Register 0 - SSP_CR0 101 */ 102 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 103 #define SSP_CR0_MASK_FRF (0x3UL << 4) 104 #define SSP_CR0_MASK_SPO (0x1UL << 6) 105 #define SSP_CR0_MASK_SPH (0x1UL << 7) 106 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 107 108 /* 109 * The ST version of this block moves som bits 110 * in SSP_CR0 and extends it to 32 bits 111 */ 112 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 113 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 114 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 115 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 116 117 /* 118 * SSP Control Register 0 - SSP_CR1 119 */ 120 #define SSP_CR1_MASK_LBM (0x1UL << 0) 121 #define SSP_CR1_MASK_SSE (0x1UL << 1) 122 #define SSP_CR1_MASK_MS (0x1UL << 2) 123 #define SSP_CR1_MASK_SOD (0x1UL << 3) 124 125 /* 126 * The ST version of this block adds some bits 127 * in SSP_CR1 128 */ 129 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 130 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 131 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 132 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 133 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 134 /* This one is only in the PL023 variant */ 135 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 136 137 /* 138 * SSP Status Register - SSP_SR 139 */ 140 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 141 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 142 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 143 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 144 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 145 146 /* 147 * SSP Clock Prescale Register - SSP_CPSR 148 */ 149 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 150 151 /* 152 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 153 */ 154 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 155 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 156 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 157 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 158 159 /* 160 * SSP Raw Interrupt Status Register - SSP_RIS 161 */ 162 /* Receive Overrun Raw Interrupt status */ 163 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 164 /* Receive Timeout Raw Interrupt status */ 165 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 166 /* Receive FIFO Raw Interrupt status */ 167 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 168 /* Transmit FIFO Raw Interrupt status */ 169 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 170 171 /* 172 * SSP Masked Interrupt Status Register - SSP_MIS 173 */ 174 /* Receive Overrun Masked Interrupt status */ 175 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 176 /* Receive Timeout Masked Interrupt status */ 177 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 178 /* Receive FIFO Masked Interrupt status */ 179 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 180 /* Transmit FIFO Masked Interrupt status */ 181 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 182 183 /* 184 * SSP Interrupt Clear Register - SSP_ICR 185 */ 186 /* Receive Overrun Raw Clear Interrupt bit */ 187 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 188 /* Receive Timeout Clear Interrupt bit */ 189 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 190 191 /* 192 * SSP DMA Control Register - SSP_DMACR 193 */ 194 /* Receive DMA Enable bit */ 195 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 196 /* Transmit DMA Enable bit */ 197 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 198 199 /* 200 * SSP Integration Test control Register - SSP_ITCR 201 */ 202 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 203 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 204 205 /* 206 * SSP Integration Test Input Register - SSP_ITIP 207 */ 208 #define ITIP_MASK_SSPRXD (0x1UL << 0) 209 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 210 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 211 #define ITIP_MASK_RXDMAC (0x1UL << 3) 212 #define ITIP_MASK_TXDMAC (0x1UL << 4) 213 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 214 215 /* 216 * SSP Integration Test output Register - SSP_ITOP 217 */ 218 #define ITOP_MASK_SSPTXD (0x1UL << 0) 219 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 220 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 221 #define ITOP_MASK_SSPOEn (0x1UL << 3) 222 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 223 #define ITOP_MASK_RORINTR (0x1UL << 5) 224 #define ITOP_MASK_RTINTR (0x1UL << 6) 225 #define ITOP_MASK_RXINTR (0x1UL << 7) 226 #define ITOP_MASK_TXINTR (0x1UL << 8) 227 #define ITOP_MASK_INTR (0x1UL << 9) 228 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 229 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 230 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 231 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 232 233 /* 234 * SSP Test Data Register - SSP_TDR 235 */ 236 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 237 238 /* 239 * Message State 240 * we use the spi_message.state (void *) pointer to 241 * hold a single state value, that's why all this 242 * (void *) casting is done here. 243 */ 244 #define STATE_START ((void *) 0) 245 #define STATE_RUNNING ((void *) 1) 246 #define STATE_DONE ((void *) 2) 247 #define STATE_ERROR ((void *) -1) 248 249 /* 250 * SSP State - Whether Enabled or Disabled 251 */ 252 #define SSP_DISABLED (0) 253 #define SSP_ENABLED (1) 254 255 /* 256 * SSP DMA State - Whether DMA Enabled or Disabled 257 */ 258 #define SSP_DMA_DISABLED (0) 259 #define SSP_DMA_ENABLED (1) 260 261 /* 262 * SSP Clock Defaults 263 */ 264 #define SSP_DEFAULT_CLKRATE 0x2 265 #define SSP_DEFAULT_PRESCALE 0x40 266 267 /* 268 * SSP Clock Parameter ranges 269 */ 270 #define CPSDVR_MIN 0x02 271 #define CPSDVR_MAX 0xFE 272 #define SCR_MIN 0x00 273 #define SCR_MAX 0xFF 274 275 /* 276 * SSP Interrupt related Macros 277 */ 278 #define DEFAULT_SSP_REG_IMSC 0x0UL 279 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 280 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 281 282 #define CLEAR_ALL_INTERRUPTS 0x3 283 284 #define SPI_POLLING_TIMEOUT 1000 285 286 /* 287 * The type of reading going on on this chip 288 */ 289 enum ssp_reading { 290 READING_NULL, 291 READING_U8, 292 READING_U16, 293 READING_U32 294 }; 295 296 /** 297 * The type of writing going on on this chip 298 */ 299 enum ssp_writing { 300 WRITING_NULL, 301 WRITING_U8, 302 WRITING_U16, 303 WRITING_U32 304 }; 305 306 /** 307 * struct vendor_data - vendor-specific config parameters 308 * for PL022 derivates 309 * @fifodepth: depth of FIFOs (both) 310 * @max_bpw: maximum number of bits per word 311 * @unidir: supports unidirection transfers 312 * @extended_cr: 32 bit wide control register 0 with extra 313 * features and extra features in CR1 as found in the ST variants 314 * @pl023: supports a subset of the ST extensions called "PL023" 315 */ 316 struct vendor_data { 317 int fifodepth; 318 int max_bpw; 319 bool unidir; 320 bool extended_cr; 321 bool pl023; 322 bool loopback; 323 }; 324 325 /** 326 * struct pl022 - This is the private SSP driver data structure 327 * @adev: AMBA device model hookup 328 * @vendor: vendor data for the IP block 329 * @phybase: the physical memory where the SSP device resides 330 * @virtbase: the virtual memory where the SSP is mapped 331 * @clk: outgoing clock "SPICLK" for the SPI bus 332 * @master: SPI framework hookup 333 * @master_info: controller-specific data from machine setup 334 * @kworker: thread struct for message pump 335 * @kworker_task: pointer to task for message pump kworker thread 336 * @pump_messages: work struct for scheduling work to the message pump 337 * @queue_lock: spinlock to syncronise access to message queue 338 * @queue: message queue 339 * @busy: message pump is busy 340 * @running: message pump is running 341 * @pump_transfers: Tasklet used in Interrupt Transfer mode 342 * @cur_msg: Pointer to current spi_message being processed 343 * @cur_transfer: Pointer to current spi_transfer 344 * @cur_chip: pointer to current clients chip(assigned from controller_state) 345 * @next_msg_cs_active: the next message in the queue has been examined 346 * and it was found that it uses the same chip select as the previous 347 * message, so we left it active after the previous transfer, and it's 348 * active already. 349 * @tx: current position in TX buffer to be read 350 * @tx_end: end position in TX buffer to be read 351 * @rx: current position in RX buffer to be written 352 * @rx_end: end position in RX buffer to be written 353 * @read: the type of read currently going on 354 * @write: the type of write currently going on 355 * @exp_fifo_level: expected FIFO level 356 * @dma_rx_channel: optional channel for RX DMA 357 * @dma_tx_channel: optional channel for TX DMA 358 * @sgt_rx: scattertable for the RX transfer 359 * @sgt_tx: scattertable for the TX transfer 360 * @dummypage: a dummy page used for driving data on the bus with DMA 361 * @cur_cs: current chip select (gpio) 362 * @chipselects: list of chipselects (gpios) 363 */ 364 struct pl022 { 365 struct amba_device *adev; 366 struct vendor_data *vendor; 367 resource_size_t phybase; 368 void __iomem *virtbase; 369 struct clk *clk; 370 struct spi_master *master; 371 struct pl022_ssp_controller *master_info; 372 /* Message per-transfer pump */ 373 struct tasklet_struct pump_transfers; 374 struct spi_message *cur_msg; 375 struct spi_transfer *cur_transfer; 376 struct chip_data *cur_chip; 377 bool next_msg_cs_active; 378 void *tx; 379 void *tx_end; 380 void *rx; 381 void *rx_end; 382 enum ssp_reading read; 383 enum ssp_writing write; 384 u32 exp_fifo_level; 385 enum ssp_rx_level_trig rx_lev_trig; 386 enum ssp_tx_level_trig tx_lev_trig; 387 /* DMA settings */ 388 #ifdef CONFIG_DMA_ENGINE 389 struct dma_chan *dma_rx_channel; 390 struct dma_chan *dma_tx_channel; 391 struct sg_table sgt_rx; 392 struct sg_table sgt_tx; 393 char *dummypage; 394 bool dma_running; 395 #endif 396 int cur_cs; 397 int *chipselects; 398 }; 399 400 /** 401 * struct chip_data - To maintain runtime state of SSP for each client chip 402 * @cr0: Value of control register CR0 of SSP - on later ST variants this 403 * register is 32 bits wide rather than just 16 404 * @cr1: Value of control register CR1 of SSP 405 * @dmacr: Value of DMA control Register of SSP 406 * @cpsr: Value of Clock prescale register 407 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 408 * @enable_dma: Whether to enable DMA or not 409 * @read: function ptr to be used to read when doing xfer for this chip 410 * @write: function ptr to be used to write when doing xfer for this chip 411 * @cs_control: chip select callback provided by chip 412 * @xfer_type: polling/interrupt/DMA 413 * 414 * Runtime state of the SSP controller, maintained per chip, 415 * This would be set according to the current message that would be served 416 */ 417 struct chip_data { 418 u32 cr0; 419 u16 cr1; 420 u16 dmacr; 421 u16 cpsr; 422 u8 n_bytes; 423 bool enable_dma; 424 enum ssp_reading read; 425 enum ssp_writing write; 426 void (*cs_control) (u32 command); 427 int xfer_type; 428 }; 429 430 /** 431 * null_cs_control - Dummy chip select function 432 * @command: select/delect the chip 433 * 434 * If no chip select function is provided by client this is used as dummy 435 * chip select 436 */ 437 static void null_cs_control(u32 command) 438 { 439 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 440 } 441 442 static void pl022_cs_control(struct pl022 *pl022, u32 command) 443 { 444 if (gpio_is_valid(pl022->cur_cs)) 445 gpio_set_value(pl022->cur_cs, command); 446 else 447 pl022->cur_chip->cs_control(command); 448 } 449 450 /** 451 * giveback - current spi_message is over, schedule next message and call 452 * callback of this message. Assumes that caller already 453 * set message->status; dma and pio irqs are blocked 454 * @pl022: SSP driver private data structure 455 */ 456 static void giveback(struct pl022 *pl022) 457 { 458 struct spi_transfer *last_transfer; 459 pl022->next_msg_cs_active = false; 460 461 last_transfer = list_entry(pl022->cur_msg->transfers.prev, 462 struct spi_transfer, 463 transfer_list); 464 465 /* Delay if requested before any change in chip select */ 466 if (last_transfer->delay_usecs) 467 /* 468 * FIXME: This runs in interrupt context. 469 * Is this really smart? 470 */ 471 udelay(last_transfer->delay_usecs); 472 473 if (!last_transfer->cs_change) { 474 struct spi_message *next_msg; 475 476 /* 477 * cs_change was not set. We can keep the chip select 478 * enabled if there is message in the queue and it is 479 * for the same spi device. 480 * 481 * We cannot postpone this until pump_messages, because 482 * after calling msg->complete (below) the driver that 483 * sent the current message could be unloaded, which 484 * could invalidate the cs_control() callback... 485 */ 486 /* get a pointer to the next message, if any */ 487 next_msg = spi_get_next_queued_message(pl022->master); 488 489 /* 490 * see if the next and current messages point 491 * to the same spi device. 492 */ 493 if (next_msg && next_msg->spi != pl022->cur_msg->spi) 494 next_msg = NULL; 495 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 496 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 497 else 498 pl022->next_msg_cs_active = true; 499 500 } 501 502 pl022->cur_msg = NULL; 503 pl022->cur_transfer = NULL; 504 pl022->cur_chip = NULL; 505 spi_finalize_current_message(pl022->master); 506 507 /* disable the SPI/SSP operation */ 508 writew((readw(SSP_CR1(pl022->virtbase)) & 509 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 510 511 } 512 513 /** 514 * flush - flush the FIFO to reach a clean state 515 * @pl022: SSP driver private data structure 516 */ 517 static int flush(struct pl022 *pl022) 518 { 519 unsigned long limit = loops_per_jiffy << 1; 520 521 dev_dbg(&pl022->adev->dev, "flush\n"); 522 do { 523 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 524 readw(SSP_DR(pl022->virtbase)); 525 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 526 527 pl022->exp_fifo_level = 0; 528 529 return limit; 530 } 531 532 /** 533 * restore_state - Load configuration of current chip 534 * @pl022: SSP driver private data structure 535 */ 536 static void restore_state(struct pl022 *pl022) 537 { 538 struct chip_data *chip = pl022->cur_chip; 539 540 if (pl022->vendor->extended_cr) 541 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 542 else 543 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 544 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 545 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 546 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 547 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 548 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 549 } 550 551 /* 552 * Default SSP Register Values 553 */ 554 #define DEFAULT_SSP_REG_CR0 ( \ 555 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 556 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 557 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 558 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 559 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 560 ) 561 562 /* ST versions have slightly different bit layout */ 563 #define DEFAULT_SSP_REG_CR0_ST ( \ 564 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 565 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 566 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 567 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 568 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 569 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 570 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 571 ) 572 573 /* The PL023 version is slightly different again */ 574 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 575 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 576 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 577 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 578 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 579 ) 580 581 #define DEFAULT_SSP_REG_CR1 ( \ 582 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 583 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 584 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 585 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 586 ) 587 588 /* ST versions extend this register to use all 16 bits */ 589 #define DEFAULT_SSP_REG_CR1_ST ( \ 590 DEFAULT_SSP_REG_CR1 | \ 591 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 592 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 593 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 594 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 595 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 596 ) 597 598 /* 599 * The PL023 variant has further differences: no loopback mode, no microwire 600 * support, and a new clock feedback delay setting. 601 */ 602 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 603 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 604 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 605 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 606 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 607 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 608 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 609 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 610 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 611 ) 612 613 #define DEFAULT_SSP_REG_CPSR ( \ 614 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 615 ) 616 617 #define DEFAULT_SSP_REG_DMACR (\ 618 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 619 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 620 ) 621 622 /** 623 * load_ssp_default_config - Load default configuration for SSP 624 * @pl022: SSP driver private data structure 625 */ 626 static void load_ssp_default_config(struct pl022 *pl022) 627 { 628 if (pl022->vendor->pl023) { 629 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 630 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 631 } else if (pl022->vendor->extended_cr) { 632 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 633 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 634 } else { 635 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 636 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 637 } 638 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 639 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 640 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 641 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 642 } 643 644 /** 645 * This will write to TX and read from RX according to the parameters 646 * set in pl022. 647 */ 648 static void readwriter(struct pl022 *pl022) 649 { 650 651 /* 652 * The FIFO depth is different between primecell variants. 653 * I believe filling in too much in the FIFO might cause 654 * errons in 8bit wide transfers on ARM variants (just 8 words 655 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 656 * 657 * To prevent this issue, the TX FIFO is only filled to the 658 * unused RX FIFO fill length, regardless of what the TX 659 * FIFO status flag indicates. 660 */ 661 dev_dbg(&pl022->adev->dev, 662 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 663 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 664 665 /* Read as much as you can */ 666 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 667 && (pl022->rx < pl022->rx_end)) { 668 switch (pl022->read) { 669 case READING_NULL: 670 readw(SSP_DR(pl022->virtbase)); 671 break; 672 case READING_U8: 673 *(u8 *) (pl022->rx) = 674 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 675 break; 676 case READING_U16: 677 *(u16 *) (pl022->rx) = 678 (u16) readw(SSP_DR(pl022->virtbase)); 679 break; 680 case READING_U32: 681 *(u32 *) (pl022->rx) = 682 readl(SSP_DR(pl022->virtbase)); 683 break; 684 } 685 pl022->rx += (pl022->cur_chip->n_bytes); 686 pl022->exp_fifo_level--; 687 } 688 /* 689 * Write as much as possible up to the RX FIFO size 690 */ 691 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 692 && (pl022->tx < pl022->tx_end)) { 693 switch (pl022->write) { 694 case WRITING_NULL: 695 writew(0x0, SSP_DR(pl022->virtbase)); 696 break; 697 case WRITING_U8: 698 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 699 break; 700 case WRITING_U16: 701 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 702 break; 703 case WRITING_U32: 704 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 705 break; 706 } 707 pl022->tx += (pl022->cur_chip->n_bytes); 708 pl022->exp_fifo_level++; 709 /* 710 * This inner reader takes care of things appearing in the RX 711 * FIFO as we're transmitting. This will happen a lot since the 712 * clock starts running when you put things into the TX FIFO, 713 * and then things are continuously clocked into the RX FIFO. 714 */ 715 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 716 && (pl022->rx < pl022->rx_end)) { 717 switch (pl022->read) { 718 case READING_NULL: 719 readw(SSP_DR(pl022->virtbase)); 720 break; 721 case READING_U8: 722 *(u8 *) (pl022->rx) = 723 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 724 break; 725 case READING_U16: 726 *(u16 *) (pl022->rx) = 727 (u16) readw(SSP_DR(pl022->virtbase)); 728 break; 729 case READING_U32: 730 *(u32 *) (pl022->rx) = 731 readl(SSP_DR(pl022->virtbase)); 732 break; 733 } 734 pl022->rx += (pl022->cur_chip->n_bytes); 735 pl022->exp_fifo_level--; 736 } 737 } 738 /* 739 * When we exit here the TX FIFO should be full and the RX FIFO 740 * should be empty 741 */ 742 } 743 744 /** 745 * next_transfer - Move to the Next transfer in the current spi message 746 * @pl022: SSP driver private data structure 747 * 748 * This function moves though the linked list of spi transfers in the 749 * current spi message and returns with the state of current spi 750 * message i.e whether its last transfer is done(STATE_DONE) or 751 * Next transfer is ready(STATE_RUNNING) 752 */ 753 static void *next_transfer(struct pl022 *pl022) 754 { 755 struct spi_message *msg = pl022->cur_msg; 756 struct spi_transfer *trans = pl022->cur_transfer; 757 758 /* Move to next transfer */ 759 if (trans->transfer_list.next != &msg->transfers) { 760 pl022->cur_transfer = 761 list_entry(trans->transfer_list.next, 762 struct spi_transfer, transfer_list); 763 return STATE_RUNNING; 764 } 765 return STATE_DONE; 766 } 767 768 /* 769 * This DMA functionality is only compiled in if we have 770 * access to the generic DMA devices/DMA engine. 771 */ 772 #ifdef CONFIG_DMA_ENGINE 773 static void unmap_free_dma_scatter(struct pl022 *pl022) 774 { 775 /* Unmap and free the SG tables */ 776 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 777 pl022->sgt_tx.nents, DMA_TO_DEVICE); 778 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 779 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 780 sg_free_table(&pl022->sgt_rx); 781 sg_free_table(&pl022->sgt_tx); 782 } 783 784 static void dma_callback(void *data) 785 { 786 struct pl022 *pl022 = data; 787 struct spi_message *msg = pl022->cur_msg; 788 789 BUG_ON(!pl022->sgt_rx.sgl); 790 791 #ifdef VERBOSE_DEBUG 792 /* 793 * Optionally dump out buffers to inspect contents, this is 794 * good if you want to convince yourself that the loopback 795 * read/write contents are the same, when adopting to a new 796 * DMA engine. 797 */ 798 { 799 struct scatterlist *sg; 800 unsigned int i; 801 802 dma_sync_sg_for_cpu(&pl022->adev->dev, 803 pl022->sgt_rx.sgl, 804 pl022->sgt_rx.nents, 805 DMA_FROM_DEVICE); 806 807 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 808 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 809 print_hex_dump(KERN_ERR, "SPI RX: ", 810 DUMP_PREFIX_OFFSET, 811 16, 812 1, 813 sg_virt(sg), 814 sg_dma_len(sg), 815 1); 816 } 817 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 818 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 819 print_hex_dump(KERN_ERR, "SPI TX: ", 820 DUMP_PREFIX_OFFSET, 821 16, 822 1, 823 sg_virt(sg), 824 sg_dma_len(sg), 825 1); 826 } 827 } 828 #endif 829 830 unmap_free_dma_scatter(pl022); 831 832 /* Update total bytes transferred */ 833 msg->actual_length += pl022->cur_transfer->len; 834 if (pl022->cur_transfer->cs_change) 835 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 836 837 /* Move to next transfer */ 838 msg->state = next_transfer(pl022); 839 tasklet_schedule(&pl022->pump_transfers); 840 } 841 842 static void setup_dma_scatter(struct pl022 *pl022, 843 void *buffer, 844 unsigned int length, 845 struct sg_table *sgtab) 846 { 847 struct scatterlist *sg; 848 int bytesleft = length; 849 void *bufp = buffer; 850 int mapbytes; 851 int i; 852 853 if (buffer) { 854 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 855 /* 856 * If there are less bytes left than what fits 857 * in the current page (plus page alignment offset) 858 * we just feed in this, else we stuff in as much 859 * as we can. 860 */ 861 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 862 mapbytes = bytesleft; 863 else 864 mapbytes = PAGE_SIZE - offset_in_page(bufp); 865 sg_set_page(sg, virt_to_page(bufp), 866 mapbytes, offset_in_page(bufp)); 867 bufp += mapbytes; 868 bytesleft -= mapbytes; 869 dev_dbg(&pl022->adev->dev, 870 "set RX/TX target page @ %p, %d bytes, %d left\n", 871 bufp, mapbytes, bytesleft); 872 } 873 } else { 874 /* Map the dummy buffer on every page */ 875 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 876 if (bytesleft < PAGE_SIZE) 877 mapbytes = bytesleft; 878 else 879 mapbytes = PAGE_SIZE; 880 sg_set_page(sg, virt_to_page(pl022->dummypage), 881 mapbytes, 0); 882 bytesleft -= mapbytes; 883 dev_dbg(&pl022->adev->dev, 884 "set RX/TX to dummy page %d bytes, %d left\n", 885 mapbytes, bytesleft); 886 887 } 888 } 889 BUG_ON(bytesleft); 890 } 891 892 /** 893 * configure_dma - configures the channels for the next transfer 894 * @pl022: SSP driver's private data structure 895 */ 896 static int configure_dma(struct pl022 *pl022) 897 { 898 struct dma_slave_config rx_conf = { 899 .src_addr = SSP_DR(pl022->phybase), 900 .direction = DMA_DEV_TO_MEM, 901 .device_fc = false, 902 }; 903 struct dma_slave_config tx_conf = { 904 .dst_addr = SSP_DR(pl022->phybase), 905 .direction = DMA_MEM_TO_DEV, 906 .device_fc = false, 907 }; 908 unsigned int pages; 909 int ret; 910 int rx_sglen, tx_sglen; 911 struct dma_chan *rxchan = pl022->dma_rx_channel; 912 struct dma_chan *txchan = pl022->dma_tx_channel; 913 struct dma_async_tx_descriptor *rxdesc; 914 struct dma_async_tx_descriptor *txdesc; 915 916 /* Check that the channels are available */ 917 if (!rxchan || !txchan) 918 return -ENODEV; 919 920 /* 921 * If supplied, the DMA burstsize should equal the FIFO trigger level. 922 * Notice that the DMA engine uses one-to-one mapping. Since we can 923 * not trigger on 2 elements this needs explicit mapping rather than 924 * calculation. 925 */ 926 switch (pl022->rx_lev_trig) { 927 case SSP_RX_1_OR_MORE_ELEM: 928 rx_conf.src_maxburst = 1; 929 break; 930 case SSP_RX_4_OR_MORE_ELEM: 931 rx_conf.src_maxburst = 4; 932 break; 933 case SSP_RX_8_OR_MORE_ELEM: 934 rx_conf.src_maxburst = 8; 935 break; 936 case SSP_RX_16_OR_MORE_ELEM: 937 rx_conf.src_maxburst = 16; 938 break; 939 case SSP_RX_32_OR_MORE_ELEM: 940 rx_conf.src_maxburst = 32; 941 break; 942 default: 943 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 944 break; 945 } 946 947 switch (pl022->tx_lev_trig) { 948 case SSP_TX_1_OR_MORE_EMPTY_LOC: 949 tx_conf.dst_maxburst = 1; 950 break; 951 case SSP_TX_4_OR_MORE_EMPTY_LOC: 952 tx_conf.dst_maxburst = 4; 953 break; 954 case SSP_TX_8_OR_MORE_EMPTY_LOC: 955 tx_conf.dst_maxburst = 8; 956 break; 957 case SSP_TX_16_OR_MORE_EMPTY_LOC: 958 tx_conf.dst_maxburst = 16; 959 break; 960 case SSP_TX_32_OR_MORE_EMPTY_LOC: 961 tx_conf.dst_maxburst = 32; 962 break; 963 default: 964 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 965 break; 966 } 967 968 switch (pl022->read) { 969 case READING_NULL: 970 /* Use the same as for writing */ 971 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 972 break; 973 case READING_U8: 974 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 975 break; 976 case READING_U16: 977 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 978 break; 979 case READING_U32: 980 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 981 break; 982 } 983 984 switch (pl022->write) { 985 case WRITING_NULL: 986 /* Use the same as for reading */ 987 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 988 break; 989 case WRITING_U8: 990 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 991 break; 992 case WRITING_U16: 993 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 994 break; 995 case WRITING_U32: 996 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 997 break; 998 } 999 1000 /* SPI pecularity: we need to read and write the same width */ 1001 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1002 rx_conf.src_addr_width = tx_conf.dst_addr_width; 1003 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1004 tx_conf.dst_addr_width = rx_conf.src_addr_width; 1005 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1006 1007 dmaengine_slave_config(rxchan, &rx_conf); 1008 dmaengine_slave_config(txchan, &tx_conf); 1009 1010 /* Create sglists for the transfers */ 1011 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1012 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1013 1014 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1015 if (ret) 1016 goto err_alloc_rx_sg; 1017 1018 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1019 if (ret) 1020 goto err_alloc_tx_sg; 1021 1022 /* Fill in the scatterlists for the RX+TX buffers */ 1023 setup_dma_scatter(pl022, pl022->rx, 1024 pl022->cur_transfer->len, &pl022->sgt_rx); 1025 setup_dma_scatter(pl022, pl022->tx, 1026 pl022->cur_transfer->len, &pl022->sgt_tx); 1027 1028 /* Map DMA buffers */ 1029 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1030 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1031 if (!rx_sglen) 1032 goto err_rx_sgmap; 1033 1034 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1035 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1036 if (!tx_sglen) 1037 goto err_tx_sgmap; 1038 1039 /* Send both scatterlists */ 1040 rxdesc = dmaengine_prep_slave_sg(rxchan, 1041 pl022->sgt_rx.sgl, 1042 rx_sglen, 1043 DMA_DEV_TO_MEM, 1044 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1045 if (!rxdesc) 1046 goto err_rxdesc; 1047 1048 txdesc = dmaengine_prep_slave_sg(txchan, 1049 pl022->sgt_tx.sgl, 1050 tx_sglen, 1051 DMA_MEM_TO_DEV, 1052 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1053 if (!txdesc) 1054 goto err_txdesc; 1055 1056 /* Put the callback on the RX transfer only, that should finish last */ 1057 rxdesc->callback = dma_callback; 1058 rxdesc->callback_param = pl022; 1059 1060 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1061 dmaengine_submit(rxdesc); 1062 dmaengine_submit(txdesc); 1063 dma_async_issue_pending(rxchan); 1064 dma_async_issue_pending(txchan); 1065 pl022->dma_running = true; 1066 1067 return 0; 1068 1069 err_txdesc: 1070 dmaengine_terminate_all(txchan); 1071 err_rxdesc: 1072 dmaengine_terminate_all(rxchan); 1073 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1074 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1075 err_tx_sgmap: 1076 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1077 pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1078 err_rx_sgmap: 1079 sg_free_table(&pl022->sgt_tx); 1080 err_alloc_tx_sg: 1081 sg_free_table(&pl022->sgt_rx); 1082 err_alloc_rx_sg: 1083 return -ENOMEM; 1084 } 1085 1086 static int __devinit pl022_dma_probe(struct pl022 *pl022) 1087 { 1088 dma_cap_mask_t mask; 1089 1090 /* Try to acquire a generic DMA engine slave channel */ 1091 dma_cap_zero(mask); 1092 dma_cap_set(DMA_SLAVE, mask); 1093 /* 1094 * We need both RX and TX channels to do DMA, else do none 1095 * of them. 1096 */ 1097 pl022->dma_rx_channel = dma_request_channel(mask, 1098 pl022->master_info->dma_filter, 1099 pl022->master_info->dma_rx_param); 1100 if (!pl022->dma_rx_channel) { 1101 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1102 goto err_no_rxchan; 1103 } 1104 1105 pl022->dma_tx_channel = dma_request_channel(mask, 1106 pl022->master_info->dma_filter, 1107 pl022->master_info->dma_tx_param); 1108 if (!pl022->dma_tx_channel) { 1109 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1110 goto err_no_txchan; 1111 } 1112 1113 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1114 if (!pl022->dummypage) { 1115 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1116 goto err_no_dummypage; 1117 } 1118 1119 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1120 dma_chan_name(pl022->dma_rx_channel), 1121 dma_chan_name(pl022->dma_tx_channel)); 1122 1123 return 0; 1124 1125 err_no_dummypage: 1126 dma_release_channel(pl022->dma_tx_channel); 1127 err_no_txchan: 1128 dma_release_channel(pl022->dma_rx_channel); 1129 pl022->dma_rx_channel = NULL; 1130 err_no_rxchan: 1131 dev_err(&pl022->adev->dev, 1132 "Failed to work in dma mode, work without dma!\n"); 1133 return -ENODEV; 1134 } 1135 1136 static void terminate_dma(struct pl022 *pl022) 1137 { 1138 struct dma_chan *rxchan = pl022->dma_rx_channel; 1139 struct dma_chan *txchan = pl022->dma_tx_channel; 1140 1141 dmaengine_terminate_all(rxchan); 1142 dmaengine_terminate_all(txchan); 1143 unmap_free_dma_scatter(pl022); 1144 pl022->dma_running = false; 1145 } 1146 1147 static void pl022_dma_remove(struct pl022 *pl022) 1148 { 1149 if (pl022->dma_running) 1150 terminate_dma(pl022); 1151 if (pl022->dma_tx_channel) 1152 dma_release_channel(pl022->dma_tx_channel); 1153 if (pl022->dma_rx_channel) 1154 dma_release_channel(pl022->dma_rx_channel); 1155 kfree(pl022->dummypage); 1156 } 1157 1158 #else 1159 static inline int configure_dma(struct pl022 *pl022) 1160 { 1161 return -ENODEV; 1162 } 1163 1164 static inline int pl022_dma_probe(struct pl022 *pl022) 1165 { 1166 return 0; 1167 } 1168 1169 static inline void pl022_dma_remove(struct pl022 *pl022) 1170 { 1171 } 1172 #endif 1173 1174 /** 1175 * pl022_interrupt_handler - Interrupt handler for SSP controller 1176 * 1177 * This function handles interrupts generated for an interrupt based transfer. 1178 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1179 * current message's state as STATE_ERROR and schedule the tasklet 1180 * pump_transfers which will do the postprocessing of the current message by 1181 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1182 * more data, and writes data in TX FIFO till it is not full. If we complete 1183 * the transfer we move to the next transfer and schedule the tasklet. 1184 */ 1185 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1186 { 1187 struct pl022 *pl022 = dev_id; 1188 struct spi_message *msg = pl022->cur_msg; 1189 u16 irq_status = 0; 1190 u16 flag = 0; 1191 1192 if (unlikely(!msg)) { 1193 dev_err(&pl022->adev->dev, 1194 "bad message state in interrupt handler"); 1195 /* Never fail */ 1196 return IRQ_HANDLED; 1197 } 1198 1199 /* Read the Interrupt Status Register */ 1200 irq_status = readw(SSP_MIS(pl022->virtbase)); 1201 1202 if (unlikely(!irq_status)) 1203 return IRQ_NONE; 1204 1205 /* 1206 * This handles the FIFO interrupts, the timeout 1207 * interrupts are flatly ignored, they cannot be 1208 * trusted. 1209 */ 1210 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1211 /* 1212 * Overrun interrupt - bail out since our Data has been 1213 * corrupted 1214 */ 1215 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1216 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1217 dev_err(&pl022->adev->dev, 1218 "RXFIFO is full\n"); 1219 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1220 dev_err(&pl022->adev->dev, 1221 "TXFIFO is full\n"); 1222 1223 /* 1224 * Disable and clear interrupts, disable SSP, 1225 * mark message with bad status so it can be 1226 * retried. 1227 */ 1228 writew(DISABLE_ALL_INTERRUPTS, 1229 SSP_IMSC(pl022->virtbase)); 1230 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1231 writew((readw(SSP_CR1(pl022->virtbase)) & 1232 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1233 msg->state = STATE_ERROR; 1234 1235 /* Schedule message queue handler */ 1236 tasklet_schedule(&pl022->pump_transfers); 1237 return IRQ_HANDLED; 1238 } 1239 1240 readwriter(pl022); 1241 1242 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1243 flag = 1; 1244 /* Disable Transmit interrupt, enable receive interrupt */ 1245 writew((readw(SSP_IMSC(pl022->virtbase)) & 1246 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1247 SSP_IMSC(pl022->virtbase)); 1248 } 1249 1250 /* 1251 * Since all transactions must write as much as shall be read, 1252 * we can conclude the entire transaction once RX is complete. 1253 * At this point, all TX will always be finished. 1254 */ 1255 if (pl022->rx >= pl022->rx_end) { 1256 writew(DISABLE_ALL_INTERRUPTS, 1257 SSP_IMSC(pl022->virtbase)); 1258 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1259 if (unlikely(pl022->rx > pl022->rx_end)) { 1260 dev_warn(&pl022->adev->dev, "read %u surplus " 1261 "bytes (did you request an odd " 1262 "number of bytes on a 16bit bus?)\n", 1263 (u32) (pl022->rx - pl022->rx_end)); 1264 } 1265 /* Update total bytes transferred */ 1266 msg->actual_length += pl022->cur_transfer->len; 1267 if (pl022->cur_transfer->cs_change) 1268 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1269 /* Move to next transfer */ 1270 msg->state = next_transfer(pl022); 1271 tasklet_schedule(&pl022->pump_transfers); 1272 return IRQ_HANDLED; 1273 } 1274 1275 return IRQ_HANDLED; 1276 } 1277 1278 /** 1279 * This sets up the pointers to memory for the next message to 1280 * send out on the SPI bus. 1281 */ 1282 static int set_up_next_transfer(struct pl022 *pl022, 1283 struct spi_transfer *transfer) 1284 { 1285 int residue; 1286 1287 /* Sanity check the message for this bus width */ 1288 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1289 if (unlikely(residue != 0)) { 1290 dev_err(&pl022->adev->dev, 1291 "message of %u bytes to transmit but the current " 1292 "chip bus has a data width of %u bytes!\n", 1293 pl022->cur_transfer->len, 1294 pl022->cur_chip->n_bytes); 1295 dev_err(&pl022->adev->dev, "skipping this message\n"); 1296 return -EIO; 1297 } 1298 pl022->tx = (void *)transfer->tx_buf; 1299 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1300 pl022->rx = (void *)transfer->rx_buf; 1301 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1302 pl022->write = 1303 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1304 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1305 return 0; 1306 } 1307 1308 /** 1309 * pump_transfers - Tasklet function which schedules next transfer 1310 * when running in interrupt or DMA transfer mode. 1311 * @data: SSP driver private data structure 1312 * 1313 */ 1314 static void pump_transfers(unsigned long data) 1315 { 1316 struct pl022 *pl022 = (struct pl022 *) data; 1317 struct spi_message *message = NULL; 1318 struct spi_transfer *transfer = NULL; 1319 struct spi_transfer *previous = NULL; 1320 1321 /* Get current state information */ 1322 message = pl022->cur_msg; 1323 transfer = pl022->cur_transfer; 1324 1325 /* Handle for abort */ 1326 if (message->state == STATE_ERROR) { 1327 message->status = -EIO; 1328 giveback(pl022); 1329 return; 1330 } 1331 1332 /* Handle end of message */ 1333 if (message->state == STATE_DONE) { 1334 message->status = 0; 1335 giveback(pl022); 1336 return; 1337 } 1338 1339 /* Delay if requested at end of transfer before CS change */ 1340 if (message->state == STATE_RUNNING) { 1341 previous = list_entry(transfer->transfer_list.prev, 1342 struct spi_transfer, 1343 transfer_list); 1344 if (previous->delay_usecs) 1345 /* 1346 * FIXME: This runs in interrupt context. 1347 * Is this really smart? 1348 */ 1349 udelay(previous->delay_usecs); 1350 1351 /* Reselect chip select only if cs_change was requested */ 1352 if (previous->cs_change) 1353 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1354 } else { 1355 /* STATE_START */ 1356 message->state = STATE_RUNNING; 1357 } 1358 1359 if (set_up_next_transfer(pl022, transfer)) { 1360 message->state = STATE_ERROR; 1361 message->status = -EIO; 1362 giveback(pl022); 1363 return; 1364 } 1365 /* Flush the FIFOs and let's go! */ 1366 flush(pl022); 1367 1368 if (pl022->cur_chip->enable_dma) { 1369 if (configure_dma(pl022)) { 1370 dev_dbg(&pl022->adev->dev, 1371 "configuration of DMA failed, fall back to interrupt mode\n"); 1372 goto err_config_dma; 1373 } 1374 return; 1375 } 1376 1377 err_config_dma: 1378 /* enable all interrupts except RX */ 1379 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1380 } 1381 1382 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1383 { 1384 /* 1385 * Default is to enable all interrupts except RX - 1386 * this will be enabled once TX is complete 1387 */ 1388 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1389 1390 /* Enable target chip, if not already active */ 1391 if (!pl022->next_msg_cs_active) 1392 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1393 1394 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1395 /* Error path */ 1396 pl022->cur_msg->state = STATE_ERROR; 1397 pl022->cur_msg->status = -EIO; 1398 giveback(pl022); 1399 return; 1400 } 1401 /* If we're using DMA, set up DMA here */ 1402 if (pl022->cur_chip->enable_dma) { 1403 /* Configure DMA transfer */ 1404 if (configure_dma(pl022)) { 1405 dev_dbg(&pl022->adev->dev, 1406 "configuration of DMA failed, fall back to interrupt mode\n"); 1407 goto err_config_dma; 1408 } 1409 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1410 irqflags = DISABLE_ALL_INTERRUPTS; 1411 } 1412 err_config_dma: 1413 /* Enable SSP, turn on interrupts */ 1414 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1415 SSP_CR1(pl022->virtbase)); 1416 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1417 } 1418 1419 static void do_polling_transfer(struct pl022 *pl022) 1420 { 1421 struct spi_message *message = NULL; 1422 struct spi_transfer *transfer = NULL; 1423 struct spi_transfer *previous = NULL; 1424 struct chip_data *chip; 1425 unsigned long time, timeout; 1426 1427 chip = pl022->cur_chip; 1428 message = pl022->cur_msg; 1429 1430 while (message->state != STATE_DONE) { 1431 /* Handle for abort */ 1432 if (message->state == STATE_ERROR) 1433 break; 1434 transfer = pl022->cur_transfer; 1435 1436 /* Delay if requested at end of transfer */ 1437 if (message->state == STATE_RUNNING) { 1438 previous = 1439 list_entry(transfer->transfer_list.prev, 1440 struct spi_transfer, transfer_list); 1441 if (previous->delay_usecs) 1442 udelay(previous->delay_usecs); 1443 if (previous->cs_change) 1444 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1445 } else { 1446 /* STATE_START */ 1447 message->state = STATE_RUNNING; 1448 if (!pl022->next_msg_cs_active) 1449 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1450 } 1451 1452 /* Configuration Changing Per Transfer */ 1453 if (set_up_next_transfer(pl022, transfer)) { 1454 /* Error path */ 1455 message->state = STATE_ERROR; 1456 break; 1457 } 1458 /* Flush FIFOs and enable SSP */ 1459 flush(pl022); 1460 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1461 SSP_CR1(pl022->virtbase)); 1462 1463 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1464 1465 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1466 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1467 time = jiffies; 1468 readwriter(pl022); 1469 if (time_after(time, timeout)) { 1470 dev_warn(&pl022->adev->dev, 1471 "%s: timeout!\n", __func__); 1472 message->state = STATE_ERROR; 1473 goto out; 1474 } 1475 cpu_relax(); 1476 } 1477 1478 /* Update total byte transferred */ 1479 message->actual_length += pl022->cur_transfer->len; 1480 if (pl022->cur_transfer->cs_change) 1481 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1482 /* Move to next transfer */ 1483 message->state = next_transfer(pl022); 1484 } 1485 out: 1486 /* Handle end of message */ 1487 if (message->state == STATE_DONE) 1488 message->status = 0; 1489 else 1490 message->status = -EIO; 1491 1492 giveback(pl022); 1493 return; 1494 } 1495 1496 static int pl022_transfer_one_message(struct spi_master *master, 1497 struct spi_message *msg) 1498 { 1499 struct pl022 *pl022 = spi_master_get_devdata(master); 1500 1501 /* Initial message state */ 1502 pl022->cur_msg = msg; 1503 msg->state = STATE_START; 1504 1505 pl022->cur_transfer = list_entry(msg->transfers.next, 1506 struct spi_transfer, transfer_list); 1507 1508 /* Setup the SPI using the per chip configuration */ 1509 pl022->cur_chip = spi_get_ctldata(msg->spi); 1510 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; 1511 1512 restore_state(pl022); 1513 flush(pl022); 1514 1515 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1516 do_polling_transfer(pl022); 1517 else 1518 do_interrupt_dma_transfer(pl022); 1519 1520 return 0; 1521 } 1522 1523 static int pl022_prepare_transfer_hardware(struct spi_master *master) 1524 { 1525 struct pl022 *pl022 = spi_master_get_devdata(master); 1526 1527 /* 1528 * Just make sure we have all we need to run the transfer by syncing 1529 * with the runtime PM framework. 1530 */ 1531 pm_runtime_get_sync(&pl022->adev->dev); 1532 return 0; 1533 } 1534 1535 static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1536 { 1537 struct pl022 *pl022 = spi_master_get_devdata(master); 1538 1539 /* nothing more to do - disable spi/ssp and power off */ 1540 writew((readw(SSP_CR1(pl022->virtbase)) & 1541 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1542 1543 if (pl022->master_info->autosuspend_delay > 0) { 1544 pm_runtime_mark_last_busy(&pl022->adev->dev); 1545 pm_runtime_put_autosuspend(&pl022->adev->dev); 1546 } else { 1547 pm_runtime_put(&pl022->adev->dev); 1548 } 1549 1550 return 0; 1551 } 1552 1553 static int verify_controller_parameters(struct pl022 *pl022, 1554 struct pl022_config_chip const *chip_info) 1555 { 1556 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1557 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1558 dev_err(&pl022->adev->dev, 1559 "interface is configured incorrectly\n"); 1560 return -EINVAL; 1561 } 1562 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1563 (!pl022->vendor->unidir)) { 1564 dev_err(&pl022->adev->dev, 1565 "unidirectional mode not supported in this " 1566 "hardware version\n"); 1567 return -EINVAL; 1568 } 1569 if ((chip_info->hierarchy != SSP_MASTER) 1570 && (chip_info->hierarchy != SSP_SLAVE)) { 1571 dev_err(&pl022->adev->dev, 1572 "hierarchy is configured incorrectly\n"); 1573 return -EINVAL; 1574 } 1575 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1576 && (chip_info->com_mode != DMA_TRANSFER) 1577 && (chip_info->com_mode != POLLING_TRANSFER)) { 1578 dev_err(&pl022->adev->dev, 1579 "Communication mode is configured incorrectly\n"); 1580 return -EINVAL; 1581 } 1582 switch (chip_info->rx_lev_trig) { 1583 case SSP_RX_1_OR_MORE_ELEM: 1584 case SSP_RX_4_OR_MORE_ELEM: 1585 case SSP_RX_8_OR_MORE_ELEM: 1586 /* These are always OK, all variants can handle this */ 1587 break; 1588 case SSP_RX_16_OR_MORE_ELEM: 1589 if (pl022->vendor->fifodepth < 16) { 1590 dev_err(&pl022->adev->dev, 1591 "RX FIFO Trigger Level is configured incorrectly\n"); 1592 return -EINVAL; 1593 } 1594 break; 1595 case SSP_RX_32_OR_MORE_ELEM: 1596 if (pl022->vendor->fifodepth < 32) { 1597 dev_err(&pl022->adev->dev, 1598 "RX FIFO Trigger Level is configured incorrectly\n"); 1599 return -EINVAL; 1600 } 1601 break; 1602 default: 1603 dev_err(&pl022->adev->dev, 1604 "RX FIFO Trigger Level is configured incorrectly\n"); 1605 return -EINVAL; 1606 break; 1607 } 1608 switch (chip_info->tx_lev_trig) { 1609 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1610 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1611 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1612 /* These are always OK, all variants can handle this */ 1613 break; 1614 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1615 if (pl022->vendor->fifodepth < 16) { 1616 dev_err(&pl022->adev->dev, 1617 "TX FIFO Trigger Level is configured incorrectly\n"); 1618 return -EINVAL; 1619 } 1620 break; 1621 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1622 if (pl022->vendor->fifodepth < 32) { 1623 dev_err(&pl022->adev->dev, 1624 "TX FIFO Trigger Level is configured incorrectly\n"); 1625 return -EINVAL; 1626 } 1627 break; 1628 default: 1629 dev_err(&pl022->adev->dev, 1630 "TX FIFO Trigger Level is configured incorrectly\n"); 1631 return -EINVAL; 1632 break; 1633 } 1634 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1635 if ((chip_info->ctrl_len < SSP_BITS_4) 1636 || (chip_info->ctrl_len > SSP_BITS_32)) { 1637 dev_err(&pl022->adev->dev, 1638 "CTRL LEN is configured incorrectly\n"); 1639 return -EINVAL; 1640 } 1641 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1642 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1643 dev_err(&pl022->adev->dev, 1644 "Wait State is configured incorrectly\n"); 1645 return -EINVAL; 1646 } 1647 /* Half duplex is only available in the ST Micro version */ 1648 if (pl022->vendor->extended_cr) { 1649 if ((chip_info->duplex != 1650 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1651 && (chip_info->duplex != 1652 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1653 dev_err(&pl022->adev->dev, 1654 "Microwire duplex mode is configured incorrectly\n"); 1655 return -EINVAL; 1656 } 1657 } else { 1658 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1659 dev_err(&pl022->adev->dev, 1660 "Microwire half duplex mode requested," 1661 " but this is only available in the" 1662 " ST version of PL022\n"); 1663 return -EINVAL; 1664 } 1665 } 1666 return 0; 1667 } 1668 1669 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1670 { 1671 return rate / (cpsdvsr * (1 + scr)); 1672 } 1673 1674 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1675 ssp_clock_params * clk_freq) 1676 { 1677 /* Lets calculate the frequency parameters */ 1678 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1679 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1680 best_scr = 0, tmp, found = 0; 1681 1682 rate = clk_get_rate(pl022->clk); 1683 /* cpsdvscr = 2 & scr 0 */ 1684 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1685 /* cpsdvsr = 254 & scr = 255 */ 1686 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1687 1688 if (freq > max_tclk) 1689 dev_warn(&pl022->adev->dev, 1690 "Max speed that can be programmed is %d Hz, you requested %d\n", 1691 max_tclk, freq); 1692 1693 if (freq < min_tclk) { 1694 dev_err(&pl022->adev->dev, 1695 "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1696 freq, min_tclk); 1697 return -EINVAL; 1698 } 1699 1700 /* 1701 * best_freq will give closest possible available rate (<= requested 1702 * freq) for all values of scr & cpsdvsr. 1703 */ 1704 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1705 while (scr <= SCR_MAX) { 1706 tmp = spi_rate(rate, cpsdvsr, scr); 1707 1708 if (tmp > freq) { 1709 /* we need lower freq */ 1710 scr++; 1711 continue; 1712 } 1713 1714 /* 1715 * If found exact value, mark found and break. 1716 * If found more closer value, update and break. 1717 */ 1718 if (tmp > best_freq) { 1719 best_freq = tmp; 1720 best_cpsdvsr = cpsdvsr; 1721 best_scr = scr; 1722 1723 if (tmp == freq) 1724 found = 1; 1725 } 1726 /* 1727 * increased scr will give lower rates, which are not 1728 * required 1729 */ 1730 break; 1731 } 1732 cpsdvsr += 2; 1733 scr = SCR_MIN; 1734 } 1735 1736 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 1737 freq); 1738 1739 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1740 clk_freq->scr = (u8) (best_scr & 0xFF); 1741 dev_dbg(&pl022->adev->dev, 1742 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1743 freq, best_freq); 1744 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1745 clk_freq->cpsdvsr, clk_freq->scr); 1746 1747 return 0; 1748 } 1749 1750 /* 1751 * A piece of default chip info unless the platform 1752 * supplies it. 1753 */ 1754 static const struct pl022_config_chip pl022_default_chip_info = { 1755 .com_mode = POLLING_TRANSFER, 1756 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1757 .hierarchy = SSP_SLAVE, 1758 .slave_tx_disable = DO_NOT_DRIVE_TX, 1759 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1760 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1761 .ctrl_len = SSP_BITS_8, 1762 .wait_state = SSP_MWIRE_WAIT_ZERO, 1763 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1764 .cs_control = null_cs_control, 1765 }; 1766 1767 /** 1768 * pl022_setup - setup function registered to SPI master framework 1769 * @spi: spi device which is requesting setup 1770 * 1771 * This function is registered to the SPI framework for this SPI master 1772 * controller. If it is the first time when setup is called by this device, 1773 * this function will initialize the runtime state for this chip and save 1774 * the same in the device structure. Else it will update the runtime info 1775 * with the updated chip info. Nothing is really being written to the 1776 * controller hardware here, that is not done until the actual transfer 1777 * commence. 1778 */ 1779 static int pl022_setup(struct spi_device *spi) 1780 { 1781 struct pl022_config_chip const *chip_info; 1782 struct pl022_config_chip chip_info_dt; 1783 struct chip_data *chip; 1784 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1785 int status = 0; 1786 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1787 unsigned int bits = spi->bits_per_word; 1788 u32 tmp; 1789 struct device_node *np = spi->dev.of_node; 1790 1791 if (!spi->max_speed_hz) 1792 return -EINVAL; 1793 1794 /* Get controller_state if one is supplied */ 1795 chip = spi_get_ctldata(spi); 1796 1797 if (chip == NULL) { 1798 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1799 if (!chip) { 1800 dev_err(&spi->dev, 1801 "cannot allocate controller state\n"); 1802 return -ENOMEM; 1803 } 1804 dev_dbg(&spi->dev, 1805 "allocated memory for controller's runtime state\n"); 1806 } 1807 1808 /* Get controller data if one is supplied */ 1809 chip_info = spi->controller_data; 1810 1811 if (chip_info == NULL) { 1812 if (np) { 1813 chip_info_dt = pl022_default_chip_info; 1814 1815 chip_info_dt.hierarchy = SSP_MASTER; 1816 of_property_read_u32(np, "pl022,interface", 1817 &chip_info_dt.iface); 1818 of_property_read_u32(np, "pl022,com-mode", 1819 &chip_info_dt.com_mode); 1820 of_property_read_u32(np, "pl022,rx-level-trig", 1821 &chip_info_dt.rx_lev_trig); 1822 of_property_read_u32(np, "pl022,tx-level-trig", 1823 &chip_info_dt.tx_lev_trig); 1824 of_property_read_u32(np, "pl022,ctrl-len", 1825 &chip_info_dt.ctrl_len); 1826 of_property_read_u32(np, "pl022,wait-state", 1827 &chip_info_dt.wait_state); 1828 of_property_read_u32(np, "pl022,duplex", 1829 &chip_info_dt.duplex); 1830 1831 chip_info = &chip_info_dt; 1832 } else { 1833 chip_info = &pl022_default_chip_info; 1834 /* spi_board_info.controller_data not is supplied */ 1835 dev_dbg(&spi->dev, 1836 "using default controller_data settings\n"); 1837 } 1838 } else 1839 dev_dbg(&spi->dev, 1840 "using user supplied controller_data settings\n"); 1841 1842 /* 1843 * We can override with custom divisors, else we use the board 1844 * frequency setting 1845 */ 1846 if ((0 == chip_info->clk_freq.cpsdvsr) 1847 && (0 == chip_info->clk_freq.scr)) { 1848 status = calculate_effective_freq(pl022, 1849 spi->max_speed_hz, 1850 &clk_freq); 1851 if (status < 0) 1852 goto err_config_params; 1853 } else { 1854 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1855 if ((clk_freq.cpsdvsr % 2) != 0) 1856 clk_freq.cpsdvsr = 1857 clk_freq.cpsdvsr - 1; 1858 } 1859 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1860 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1861 status = -EINVAL; 1862 dev_err(&spi->dev, 1863 "cpsdvsr is configured incorrectly\n"); 1864 goto err_config_params; 1865 } 1866 1867 status = verify_controller_parameters(pl022, chip_info); 1868 if (status) { 1869 dev_err(&spi->dev, "controller data is incorrect"); 1870 goto err_config_params; 1871 } 1872 1873 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1874 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1875 1876 /* Now set controller state based on controller data */ 1877 chip->xfer_type = chip_info->com_mode; 1878 if (!chip_info->cs_control) { 1879 chip->cs_control = null_cs_control; 1880 if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) 1881 dev_warn(&spi->dev, 1882 "invalid chip select\n"); 1883 } else 1884 chip->cs_control = chip_info->cs_control; 1885 1886 /* Check bits per word with vendor specific range */ 1887 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1888 status = -ENOTSUPP; 1889 dev_err(&spi->dev, "illegal data size for this controller!\n"); 1890 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1891 pl022->vendor->max_bpw); 1892 goto err_config_params; 1893 } else if (bits <= 8) { 1894 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1895 chip->n_bytes = 1; 1896 chip->read = READING_U8; 1897 chip->write = WRITING_U8; 1898 } else if (bits <= 16) { 1899 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1900 chip->n_bytes = 2; 1901 chip->read = READING_U16; 1902 chip->write = WRITING_U16; 1903 } else { 1904 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1905 chip->n_bytes = 4; 1906 chip->read = READING_U32; 1907 chip->write = WRITING_U32; 1908 } 1909 1910 /* Now Initialize all register settings required for this chip */ 1911 chip->cr0 = 0; 1912 chip->cr1 = 0; 1913 chip->dmacr = 0; 1914 chip->cpsr = 0; 1915 if ((chip_info->com_mode == DMA_TRANSFER) 1916 && ((pl022->master_info)->enable_dma)) { 1917 chip->enable_dma = true; 1918 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1919 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1920 SSP_DMACR_MASK_RXDMAE, 0); 1921 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1922 SSP_DMACR_MASK_TXDMAE, 1); 1923 } else { 1924 chip->enable_dma = false; 1925 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1926 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1927 SSP_DMACR_MASK_RXDMAE, 0); 1928 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1929 SSP_DMACR_MASK_TXDMAE, 1); 1930 } 1931 1932 chip->cpsr = clk_freq.cpsdvsr; 1933 1934 /* Special setup for the ST micro extended control registers */ 1935 if (pl022->vendor->extended_cr) { 1936 u32 etx; 1937 1938 if (pl022->vendor->pl023) { 1939 /* These bits are only in the PL023 */ 1940 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1941 SSP_CR1_MASK_FBCLKDEL_ST, 13); 1942 } else { 1943 /* These bits are in the PL022 but not PL023 */ 1944 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1945 SSP_CR0_MASK_HALFDUP_ST, 5); 1946 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1947 SSP_CR0_MASK_CSS_ST, 16); 1948 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1949 SSP_CR0_MASK_FRF_ST, 21); 1950 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 1951 SSP_CR1_MASK_MWAIT_ST, 6); 1952 } 1953 SSP_WRITE_BITS(chip->cr0, bits - 1, 1954 SSP_CR0_MASK_DSS_ST, 0); 1955 1956 if (spi->mode & SPI_LSB_FIRST) { 1957 tmp = SSP_RX_LSB; 1958 etx = SSP_TX_LSB; 1959 } else { 1960 tmp = SSP_RX_MSB; 1961 etx = SSP_TX_MSB; 1962 } 1963 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 1964 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 1965 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 1966 SSP_CR1_MASK_RXIFLSEL_ST, 7); 1967 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 1968 SSP_CR1_MASK_TXIFLSEL_ST, 10); 1969 } else { 1970 SSP_WRITE_BITS(chip->cr0, bits - 1, 1971 SSP_CR0_MASK_DSS, 0); 1972 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1973 SSP_CR0_MASK_FRF, 4); 1974 } 1975 1976 /* Stuff that is common for all versions */ 1977 if (spi->mode & SPI_CPOL) 1978 tmp = SSP_CLK_POL_IDLE_HIGH; 1979 else 1980 tmp = SSP_CLK_POL_IDLE_LOW; 1981 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 1982 1983 if (spi->mode & SPI_CPHA) 1984 tmp = SSP_CLK_SECOND_EDGE; 1985 else 1986 tmp = SSP_CLK_FIRST_EDGE; 1987 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 1988 1989 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 1990 /* Loopback is available on all versions except PL023 */ 1991 if (pl022->vendor->loopback) { 1992 if (spi->mode & SPI_LOOP) 1993 tmp = LOOPBACK_ENABLED; 1994 else 1995 tmp = LOOPBACK_DISABLED; 1996 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 1997 } 1998 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 1999 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2000 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2001 3); 2002 2003 /* Save controller_state */ 2004 spi_set_ctldata(spi, chip); 2005 return status; 2006 err_config_params: 2007 spi_set_ctldata(spi, NULL); 2008 kfree(chip); 2009 return status; 2010 } 2011 2012 /** 2013 * pl022_cleanup - cleanup function registered to SPI master framework 2014 * @spi: spi device which is requesting cleanup 2015 * 2016 * This function is registered to the SPI framework for this SPI master 2017 * controller. It will free the runtime state of chip. 2018 */ 2019 static void pl022_cleanup(struct spi_device *spi) 2020 { 2021 struct chip_data *chip = spi_get_ctldata(spi); 2022 2023 spi_set_ctldata(spi, NULL); 2024 kfree(chip); 2025 } 2026 2027 static int __devinit 2028 pl022_probe(struct amba_device *adev, const struct amba_id *id) 2029 { 2030 struct device *dev = &adev->dev; 2031 struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2032 struct spi_master *master; 2033 struct pl022 *pl022 = NULL; /*Data for this driver */ 2034 struct device_node *np = adev->dev.of_node; 2035 int status = 0, i, num_cs; 2036 2037 dev_info(&adev->dev, 2038 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2039 if (platform_info == NULL) { 2040 dev_err(&adev->dev, "probe - no platform data supplied\n"); 2041 status = -ENODEV; 2042 goto err_no_pdata; 2043 } 2044 2045 if (platform_info->num_chipselect) { 2046 num_cs = platform_info->num_chipselect; 2047 } else if (IS_ENABLED(CONFIG_OF)) { 2048 of_property_read_u32(np, "num-cs", &num_cs); 2049 } else { 2050 dev_err(&adev->dev, "probe: no chip select defined\n"); 2051 status = -ENODEV; 2052 goto err_no_pdata; 2053 } 2054 2055 /* Allocate master with space for data */ 2056 master = spi_alloc_master(dev, sizeof(struct pl022)); 2057 if (master == NULL) { 2058 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2059 status = -ENOMEM; 2060 goto err_no_master; 2061 } 2062 2063 pl022 = spi_master_get_devdata(master); 2064 pl022->master = master; 2065 pl022->master_info = platform_info; 2066 pl022->adev = adev; 2067 pl022->vendor = id->data; 2068 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), 2069 GFP_KERNEL); 2070 2071 /* 2072 * Bus Number Which has been Assigned to this SSP controller 2073 * on this board 2074 */ 2075 master->bus_num = platform_info->bus_id; 2076 master->num_chipselect = num_cs; 2077 master->cleanup = pl022_cleanup; 2078 master->setup = pl022_setup; 2079 master->prepare_transfer_hardware = pl022_prepare_transfer_hardware; 2080 master->transfer_one_message = pl022_transfer_one_message; 2081 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2082 master->rt = platform_info->rt; 2083 master->dev.of_node = dev->of_node; 2084 2085 if (platform_info->num_chipselect && platform_info->chipselects) { 2086 for (i = 0; i < num_cs; i++) 2087 pl022->chipselects[i] = platform_info->chipselects[i]; 2088 } else if (IS_ENABLED(CONFIG_OF)) { 2089 for (i = 0; i < num_cs; i++) { 2090 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 2091 2092 if (cs_gpio == -EPROBE_DEFER) { 2093 status = -EPROBE_DEFER; 2094 goto err_no_gpio; 2095 } 2096 2097 pl022->chipselects[i] = cs_gpio; 2098 2099 if (gpio_is_valid(cs_gpio)) { 2100 if (gpio_request(cs_gpio, "ssp-pl022")) 2101 dev_err(&adev->dev, 2102 "could not request %d gpio\n", 2103 cs_gpio); 2104 else if (gpio_direction_output(cs_gpio, 1)) 2105 dev_err(&adev->dev, 2106 "could set gpio %d as output\n", 2107 cs_gpio); 2108 } 2109 } 2110 } 2111 2112 /* 2113 * Supports mode 0-3, loopback, and active low CS. Transfers are 2114 * always MS bit first on the original pl022. 2115 */ 2116 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2117 if (pl022->vendor->extended_cr) 2118 master->mode_bits |= SPI_LSB_FIRST; 2119 2120 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2121 2122 status = amba_request_regions(adev, NULL); 2123 if (status) 2124 goto err_no_ioregion; 2125 2126 pl022->phybase = adev->res.start; 2127 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2128 if (pl022->virtbase == NULL) { 2129 status = -ENOMEM; 2130 goto err_no_ioremap; 2131 } 2132 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2133 adev->res.start, pl022->virtbase); 2134 2135 pm_runtime_enable(dev); 2136 pm_runtime_resume(dev); 2137 2138 pl022->clk = clk_get(&adev->dev, NULL); 2139 if (IS_ERR(pl022->clk)) { 2140 status = PTR_ERR(pl022->clk); 2141 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2142 goto err_no_clk; 2143 } 2144 2145 status = clk_prepare(pl022->clk); 2146 if (status) { 2147 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 2148 goto err_clk_prep; 2149 } 2150 2151 status = clk_enable(pl022->clk); 2152 if (status) { 2153 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2154 goto err_no_clk_en; 2155 } 2156 2157 /* Initialize transfer pump */ 2158 tasklet_init(&pl022->pump_transfers, pump_transfers, 2159 (unsigned long)pl022); 2160 2161 /* Disable SSP */ 2162 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2163 SSP_CR1(pl022->virtbase)); 2164 load_ssp_default_config(pl022); 2165 2166 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2167 pl022); 2168 if (status < 0) { 2169 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2170 goto err_no_irq; 2171 } 2172 2173 /* Get DMA channels */ 2174 if (platform_info->enable_dma) { 2175 status = pl022_dma_probe(pl022); 2176 if (status != 0) 2177 platform_info->enable_dma = 0; 2178 } 2179 2180 /* Register with the SPI framework */ 2181 amba_set_drvdata(adev, pl022); 2182 status = spi_register_master(master); 2183 if (status != 0) { 2184 dev_err(&adev->dev, 2185 "probe - problem registering spi master\n"); 2186 goto err_spi_register; 2187 } 2188 dev_dbg(dev, "probe succeeded\n"); 2189 2190 /* let runtime pm put suspend */ 2191 if (platform_info->autosuspend_delay > 0) { 2192 dev_info(&adev->dev, 2193 "will use autosuspend for runtime pm, delay %dms\n", 2194 platform_info->autosuspend_delay); 2195 pm_runtime_set_autosuspend_delay(dev, 2196 platform_info->autosuspend_delay); 2197 pm_runtime_use_autosuspend(dev); 2198 pm_runtime_put_autosuspend(dev); 2199 } else { 2200 pm_runtime_put(dev); 2201 } 2202 return 0; 2203 2204 err_spi_register: 2205 if (platform_info->enable_dma) 2206 pl022_dma_remove(pl022); 2207 2208 free_irq(adev->irq[0], pl022); 2209 err_no_irq: 2210 clk_disable(pl022->clk); 2211 err_no_clk_en: 2212 clk_unprepare(pl022->clk); 2213 err_clk_prep: 2214 clk_put(pl022->clk); 2215 err_no_clk: 2216 iounmap(pl022->virtbase); 2217 err_no_ioremap: 2218 amba_release_regions(adev); 2219 err_no_ioregion: 2220 err_no_gpio: 2221 spi_master_put(master); 2222 err_no_master: 2223 err_no_pdata: 2224 return status; 2225 } 2226 2227 static int __devexit 2228 pl022_remove(struct amba_device *adev) 2229 { 2230 struct pl022 *pl022 = amba_get_drvdata(adev); 2231 2232 if (!pl022) 2233 return 0; 2234 2235 /* 2236 * undo pm_runtime_put() in probe. I assume that we're not 2237 * accessing the primecell here. 2238 */ 2239 pm_runtime_get_noresume(&adev->dev); 2240 2241 load_ssp_default_config(pl022); 2242 if (pl022->master_info->enable_dma) 2243 pl022_dma_remove(pl022); 2244 2245 free_irq(adev->irq[0], pl022); 2246 clk_disable(pl022->clk); 2247 clk_unprepare(pl022->clk); 2248 clk_put(pl022->clk); 2249 pm_runtime_disable(&adev->dev); 2250 iounmap(pl022->virtbase); 2251 amba_release_regions(adev); 2252 tasklet_disable(&pl022->pump_transfers); 2253 spi_unregister_master(pl022->master); 2254 amba_set_drvdata(adev, NULL); 2255 return 0; 2256 } 2257 2258 #ifdef CONFIG_SUSPEND 2259 static int pl022_suspend(struct device *dev) 2260 { 2261 struct pl022 *pl022 = dev_get_drvdata(dev); 2262 int ret; 2263 2264 ret = spi_master_suspend(pl022->master); 2265 if (ret) { 2266 dev_warn(dev, "cannot suspend master\n"); 2267 return ret; 2268 } 2269 2270 dev_dbg(dev, "suspended\n"); 2271 return 0; 2272 } 2273 2274 static int pl022_resume(struct device *dev) 2275 { 2276 struct pl022 *pl022 = dev_get_drvdata(dev); 2277 int ret; 2278 2279 /* Start the queue running */ 2280 ret = spi_master_resume(pl022->master); 2281 if (ret) 2282 dev_err(dev, "problem starting queue (%d)\n", ret); 2283 else 2284 dev_dbg(dev, "resumed\n"); 2285 2286 return ret; 2287 } 2288 #endif /* CONFIG_PM */ 2289 2290 #ifdef CONFIG_PM_RUNTIME 2291 static int pl022_runtime_suspend(struct device *dev) 2292 { 2293 struct pl022 *pl022 = dev_get_drvdata(dev); 2294 2295 clk_disable(pl022->clk); 2296 2297 return 0; 2298 } 2299 2300 static int pl022_runtime_resume(struct device *dev) 2301 { 2302 struct pl022 *pl022 = dev_get_drvdata(dev); 2303 2304 clk_enable(pl022->clk); 2305 2306 return 0; 2307 } 2308 #endif 2309 2310 static const struct dev_pm_ops pl022_dev_pm_ops = { 2311 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2312 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2313 }; 2314 2315 static struct vendor_data vendor_arm = { 2316 .fifodepth = 8, 2317 .max_bpw = 16, 2318 .unidir = false, 2319 .extended_cr = false, 2320 .pl023 = false, 2321 .loopback = true, 2322 }; 2323 2324 static struct vendor_data vendor_st = { 2325 .fifodepth = 32, 2326 .max_bpw = 32, 2327 .unidir = false, 2328 .extended_cr = true, 2329 .pl023 = false, 2330 .loopback = true, 2331 }; 2332 2333 static struct vendor_data vendor_st_pl023 = { 2334 .fifodepth = 32, 2335 .max_bpw = 32, 2336 .unidir = false, 2337 .extended_cr = true, 2338 .pl023 = true, 2339 .loopback = false, 2340 }; 2341 2342 static struct amba_id pl022_ids[] = { 2343 { 2344 /* 2345 * ARM PL022 variant, this has a 16bit wide 2346 * and 8 locations deep TX/RX FIFO 2347 */ 2348 .id = 0x00041022, 2349 .mask = 0x000fffff, 2350 .data = &vendor_arm, 2351 }, 2352 { 2353 /* 2354 * ST Micro derivative, this has 32bit wide 2355 * and 32 locations deep TX/RX FIFO 2356 */ 2357 .id = 0x01080022, 2358 .mask = 0xffffffff, 2359 .data = &vendor_st, 2360 }, 2361 { 2362 /* 2363 * ST-Ericsson derivative "PL023" (this is not 2364 * an official ARM number), this is a PL022 SSP block 2365 * stripped to SPI mode only, it has 32bit wide 2366 * and 32 locations deep TX/RX FIFO but no extended 2367 * CR0/CR1 register 2368 */ 2369 .id = 0x00080023, 2370 .mask = 0xffffffff, 2371 .data = &vendor_st_pl023, 2372 }, 2373 { 0, 0 }, 2374 }; 2375 2376 MODULE_DEVICE_TABLE(amba, pl022_ids); 2377 2378 static struct amba_driver pl022_driver = { 2379 .drv = { 2380 .name = "ssp-pl022", 2381 .pm = &pl022_dev_pm_ops, 2382 }, 2383 .id_table = pl022_ids, 2384 .probe = pl022_probe, 2385 .remove = __devexit_p(pl022_remove), 2386 }; 2387 2388 static int __init pl022_init(void) 2389 { 2390 return amba_driver_register(&pl022_driver); 2391 } 2392 subsys_initcall(pl022_init); 2393 2394 static void __exit pl022_exit(void) 2395 { 2396 amba_driver_unregister(&pl022_driver); 2397 } 2398 module_exit(pl022_exit); 2399 2400 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2401 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2402 MODULE_LICENSE("GPL"); 2403