1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2009 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/workqueue.h> 33 #include <linux/delay.h> 34 #include <linux/clk.h> 35 #include <linux/err.h> 36 #include <linux/amba/bus.h> 37 #include <linux/amba/pl022.h> 38 #include <linux/io.h> 39 #include <linux/slab.h> 40 #include <linux/dmaengine.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/scatterlist.h> 43 #include <linux/pm_runtime.h> 44 45 /* 46 * This macro is used to define some register default values. 47 * reg is masked with mask, the OR:ed with an (again masked) 48 * val shifted sb steps to the left. 49 */ 50 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 51 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 52 53 /* 54 * This macro is also used to define some default values. 55 * It will just shift val by sb steps to the left and mask 56 * the result with mask. 57 */ 58 #define GEN_MASK_BITS(val, mask, sb) \ 59 (((val)<<(sb)) & (mask)) 60 61 #define DRIVE_TX 0 62 #define DO_NOT_DRIVE_TX 1 63 64 #define DO_NOT_QUEUE_DMA 0 65 #define QUEUE_DMA 1 66 67 #define RX_TRANSFER 1 68 #define TX_TRANSFER 2 69 70 /* 71 * Macros to access SSP Registers with their offsets 72 */ 73 #define SSP_CR0(r) (r + 0x000) 74 #define SSP_CR1(r) (r + 0x004) 75 #define SSP_DR(r) (r + 0x008) 76 #define SSP_SR(r) (r + 0x00C) 77 #define SSP_CPSR(r) (r + 0x010) 78 #define SSP_IMSC(r) (r + 0x014) 79 #define SSP_RIS(r) (r + 0x018) 80 #define SSP_MIS(r) (r + 0x01C) 81 #define SSP_ICR(r) (r + 0x020) 82 #define SSP_DMACR(r) (r + 0x024) 83 #define SSP_ITCR(r) (r + 0x080) 84 #define SSP_ITIP(r) (r + 0x084) 85 #define SSP_ITOP(r) (r + 0x088) 86 #define SSP_TDR(r) (r + 0x08C) 87 88 #define SSP_PID0(r) (r + 0xFE0) 89 #define SSP_PID1(r) (r + 0xFE4) 90 #define SSP_PID2(r) (r + 0xFE8) 91 #define SSP_PID3(r) (r + 0xFEC) 92 93 #define SSP_CID0(r) (r + 0xFF0) 94 #define SSP_CID1(r) (r + 0xFF4) 95 #define SSP_CID2(r) (r + 0xFF8) 96 #define SSP_CID3(r) (r + 0xFFC) 97 98 /* 99 * SSP Control Register 0 - SSP_CR0 100 */ 101 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 102 #define SSP_CR0_MASK_FRF (0x3UL << 4) 103 #define SSP_CR0_MASK_SPO (0x1UL << 6) 104 #define SSP_CR0_MASK_SPH (0x1UL << 7) 105 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 106 107 /* 108 * The ST version of this block moves som bits 109 * in SSP_CR0 and extends it to 32 bits 110 */ 111 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 112 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 113 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 114 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 115 116 117 /* 118 * SSP Control Register 0 - SSP_CR1 119 */ 120 #define SSP_CR1_MASK_LBM (0x1UL << 0) 121 #define SSP_CR1_MASK_SSE (0x1UL << 1) 122 #define SSP_CR1_MASK_MS (0x1UL << 2) 123 #define SSP_CR1_MASK_SOD (0x1UL << 3) 124 125 /* 126 * The ST version of this block adds some bits 127 * in SSP_CR1 128 */ 129 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 130 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 131 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 132 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 133 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 134 /* This one is only in the PL023 variant */ 135 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 136 137 /* 138 * SSP Status Register - SSP_SR 139 */ 140 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 141 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 142 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 143 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 144 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 145 146 /* 147 * SSP Clock Prescale Register - SSP_CPSR 148 */ 149 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 150 151 /* 152 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 153 */ 154 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 155 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 156 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 157 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 158 159 /* 160 * SSP Raw Interrupt Status Register - SSP_RIS 161 */ 162 /* Receive Overrun Raw Interrupt status */ 163 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 164 /* Receive Timeout Raw Interrupt status */ 165 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 166 /* Receive FIFO Raw Interrupt status */ 167 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 168 /* Transmit FIFO Raw Interrupt status */ 169 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 170 171 /* 172 * SSP Masked Interrupt Status Register - SSP_MIS 173 */ 174 /* Receive Overrun Masked Interrupt status */ 175 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 176 /* Receive Timeout Masked Interrupt status */ 177 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 178 /* Receive FIFO Masked Interrupt status */ 179 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 180 /* Transmit FIFO Masked Interrupt status */ 181 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 182 183 /* 184 * SSP Interrupt Clear Register - SSP_ICR 185 */ 186 /* Receive Overrun Raw Clear Interrupt bit */ 187 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 188 /* Receive Timeout Clear Interrupt bit */ 189 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 190 191 /* 192 * SSP DMA Control Register - SSP_DMACR 193 */ 194 /* Receive DMA Enable bit */ 195 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 196 /* Transmit DMA Enable bit */ 197 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 198 199 /* 200 * SSP Integration Test control Register - SSP_ITCR 201 */ 202 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 203 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 204 205 /* 206 * SSP Integration Test Input Register - SSP_ITIP 207 */ 208 #define ITIP_MASK_SSPRXD (0x1UL << 0) 209 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 210 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 211 #define ITIP_MASK_RXDMAC (0x1UL << 3) 212 #define ITIP_MASK_TXDMAC (0x1UL << 4) 213 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 214 215 /* 216 * SSP Integration Test output Register - SSP_ITOP 217 */ 218 #define ITOP_MASK_SSPTXD (0x1UL << 0) 219 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 220 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 221 #define ITOP_MASK_SSPOEn (0x1UL << 3) 222 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 223 #define ITOP_MASK_RORINTR (0x1UL << 5) 224 #define ITOP_MASK_RTINTR (0x1UL << 6) 225 #define ITOP_MASK_RXINTR (0x1UL << 7) 226 #define ITOP_MASK_TXINTR (0x1UL << 8) 227 #define ITOP_MASK_INTR (0x1UL << 9) 228 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 229 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 230 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 231 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 232 233 /* 234 * SSP Test Data Register - SSP_TDR 235 */ 236 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 237 238 /* 239 * Message State 240 * we use the spi_message.state (void *) pointer to 241 * hold a single state value, that's why all this 242 * (void *) casting is done here. 243 */ 244 #define STATE_START ((void *) 0) 245 #define STATE_RUNNING ((void *) 1) 246 #define STATE_DONE ((void *) 2) 247 #define STATE_ERROR ((void *) -1) 248 249 /* 250 * SSP State - Whether Enabled or Disabled 251 */ 252 #define SSP_DISABLED (0) 253 #define SSP_ENABLED (1) 254 255 /* 256 * SSP DMA State - Whether DMA Enabled or Disabled 257 */ 258 #define SSP_DMA_DISABLED (0) 259 #define SSP_DMA_ENABLED (1) 260 261 /* 262 * SSP Clock Defaults 263 */ 264 #define SSP_DEFAULT_CLKRATE 0x2 265 #define SSP_DEFAULT_PRESCALE 0x40 266 267 /* 268 * SSP Clock Parameter ranges 269 */ 270 #define CPSDVR_MIN 0x02 271 #define CPSDVR_MAX 0xFE 272 #define SCR_MIN 0x00 273 #define SCR_MAX 0xFF 274 275 /* 276 * SSP Interrupt related Macros 277 */ 278 #define DEFAULT_SSP_REG_IMSC 0x0UL 279 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 280 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 281 282 #define CLEAR_ALL_INTERRUPTS 0x3 283 284 #define SPI_POLLING_TIMEOUT 1000 285 286 287 /* 288 * The type of reading going on on this chip 289 */ 290 enum ssp_reading { 291 READING_NULL, 292 READING_U8, 293 READING_U16, 294 READING_U32 295 }; 296 297 /** 298 * The type of writing going on on this chip 299 */ 300 enum ssp_writing { 301 WRITING_NULL, 302 WRITING_U8, 303 WRITING_U16, 304 WRITING_U32 305 }; 306 307 /** 308 * struct vendor_data - vendor-specific config parameters 309 * for PL022 derivates 310 * @fifodepth: depth of FIFOs (both) 311 * @max_bpw: maximum number of bits per word 312 * @unidir: supports unidirection transfers 313 * @extended_cr: 32 bit wide control register 0 with extra 314 * features and extra features in CR1 as found in the ST variants 315 * @pl023: supports a subset of the ST extensions called "PL023" 316 */ 317 struct vendor_data { 318 int fifodepth; 319 int max_bpw; 320 bool unidir; 321 bool extended_cr; 322 bool pl023; 323 bool loopback; 324 }; 325 326 /** 327 * struct pl022 - This is the private SSP driver data structure 328 * @adev: AMBA device model hookup 329 * @vendor: vendor data for the IP block 330 * @phybase: the physical memory where the SSP device resides 331 * @virtbase: the virtual memory where the SSP is mapped 332 * @clk: outgoing clock "SPICLK" for the SPI bus 333 * @master: SPI framework hookup 334 * @master_info: controller-specific data from machine setup 335 * @workqueue: a workqueue on which any spi_message request is queued 336 * @pump_messages: work struct for scheduling work to the workqueue 337 * @queue_lock: spinlock to syncronise access to message queue 338 * @queue: message queue 339 * @busy: workqueue is busy 340 * @running: workqueue is running 341 * @pump_transfers: Tasklet used in Interrupt Transfer mode 342 * @cur_msg: Pointer to current spi_message being processed 343 * @cur_transfer: Pointer to current spi_transfer 344 * @cur_chip: pointer to current clients chip(assigned from controller_state) 345 * @tx: current position in TX buffer to be read 346 * @tx_end: end position in TX buffer to be read 347 * @rx: current position in RX buffer to be written 348 * @rx_end: end position in RX buffer to be written 349 * @read: the type of read currently going on 350 * @write: the type of write currently going on 351 * @exp_fifo_level: expected FIFO level 352 * @dma_rx_channel: optional channel for RX DMA 353 * @dma_tx_channel: optional channel for TX DMA 354 * @sgt_rx: scattertable for the RX transfer 355 * @sgt_tx: scattertable for the TX transfer 356 * @dummypage: a dummy page used for driving data on the bus with DMA 357 */ 358 struct pl022 { 359 struct amba_device *adev; 360 struct vendor_data *vendor; 361 resource_size_t phybase; 362 void __iomem *virtbase; 363 struct clk *clk; 364 struct spi_master *master; 365 struct pl022_ssp_controller *master_info; 366 /* Driver message queue */ 367 struct workqueue_struct *workqueue; 368 struct work_struct pump_messages; 369 spinlock_t queue_lock; 370 struct list_head queue; 371 bool busy; 372 bool running; 373 /* Message transfer pump */ 374 struct tasklet_struct pump_transfers; 375 struct spi_message *cur_msg; 376 struct spi_transfer *cur_transfer; 377 struct chip_data *cur_chip; 378 void *tx; 379 void *tx_end; 380 void *rx; 381 void *rx_end; 382 enum ssp_reading read; 383 enum ssp_writing write; 384 u32 exp_fifo_level; 385 enum ssp_rx_level_trig rx_lev_trig; 386 enum ssp_tx_level_trig tx_lev_trig; 387 /* DMA settings */ 388 #ifdef CONFIG_DMA_ENGINE 389 struct dma_chan *dma_rx_channel; 390 struct dma_chan *dma_tx_channel; 391 struct sg_table sgt_rx; 392 struct sg_table sgt_tx; 393 char *dummypage; 394 #endif 395 }; 396 397 /** 398 * struct chip_data - To maintain runtime state of SSP for each client chip 399 * @cr0: Value of control register CR0 of SSP - on later ST variants this 400 * register is 32 bits wide rather than just 16 401 * @cr1: Value of control register CR1 of SSP 402 * @dmacr: Value of DMA control Register of SSP 403 * @cpsr: Value of Clock prescale register 404 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 405 * @enable_dma: Whether to enable DMA or not 406 * @read: function ptr to be used to read when doing xfer for this chip 407 * @write: function ptr to be used to write when doing xfer for this chip 408 * @cs_control: chip select callback provided by chip 409 * @xfer_type: polling/interrupt/DMA 410 * 411 * Runtime state of the SSP controller, maintained per chip, 412 * This would be set according to the current message that would be served 413 */ 414 struct chip_data { 415 u32 cr0; 416 u16 cr1; 417 u16 dmacr; 418 u16 cpsr; 419 u8 n_bytes; 420 bool enable_dma; 421 enum ssp_reading read; 422 enum ssp_writing write; 423 void (*cs_control) (u32 command); 424 int xfer_type; 425 }; 426 427 /** 428 * null_cs_control - Dummy chip select function 429 * @command: select/delect the chip 430 * 431 * If no chip select function is provided by client this is used as dummy 432 * chip select 433 */ 434 static void null_cs_control(u32 command) 435 { 436 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 437 } 438 439 /** 440 * giveback - current spi_message is over, schedule next message and call 441 * callback of this message. Assumes that caller already 442 * set message->status; dma and pio irqs are blocked 443 * @pl022: SSP driver private data structure 444 */ 445 static void giveback(struct pl022 *pl022) 446 { 447 struct spi_transfer *last_transfer; 448 unsigned long flags; 449 struct spi_message *msg; 450 void (*curr_cs_control) (u32 command); 451 452 /* 453 * This local reference to the chip select function 454 * is needed because we set curr_chip to NULL 455 * as a step toward termininating the message. 456 */ 457 curr_cs_control = pl022->cur_chip->cs_control; 458 spin_lock_irqsave(&pl022->queue_lock, flags); 459 msg = pl022->cur_msg; 460 pl022->cur_msg = NULL; 461 pl022->cur_transfer = NULL; 462 pl022->cur_chip = NULL; 463 queue_work(pl022->workqueue, &pl022->pump_messages); 464 spin_unlock_irqrestore(&pl022->queue_lock, flags); 465 466 last_transfer = list_entry(msg->transfers.prev, 467 struct spi_transfer, 468 transfer_list); 469 470 /* Delay if requested before any change in chip select */ 471 if (last_transfer->delay_usecs) 472 /* 473 * FIXME: This runs in interrupt context. 474 * Is this really smart? 475 */ 476 udelay(last_transfer->delay_usecs); 477 478 /* 479 * Drop chip select UNLESS cs_change is true or we are returning 480 * a message with an error, or next message is for another chip 481 */ 482 if (!last_transfer->cs_change) 483 curr_cs_control(SSP_CHIP_DESELECT); 484 else { 485 struct spi_message *next_msg; 486 487 /* Holding of cs was hinted, but we need to make sure 488 * the next message is for the same chip. Don't waste 489 * time with the following tests unless this was hinted. 490 * 491 * We cannot postpone this until pump_messages, because 492 * after calling msg->complete (below) the driver that 493 * sent the current message could be unloaded, which 494 * could invalidate the cs_control() callback... 495 */ 496 497 /* get a pointer to the next message, if any */ 498 spin_lock_irqsave(&pl022->queue_lock, flags); 499 if (list_empty(&pl022->queue)) 500 next_msg = NULL; 501 else 502 next_msg = list_entry(pl022->queue.next, 503 struct spi_message, queue); 504 spin_unlock_irqrestore(&pl022->queue_lock, flags); 505 506 /* see if the next and current messages point 507 * to the same chip 508 */ 509 if (next_msg && next_msg->spi != msg->spi) 510 next_msg = NULL; 511 if (!next_msg || msg->state == STATE_ERROR) 512 curr_cs_control(SSP_CHIP_DESELECT); 513 } 514 msg->state = NULL; 515 if (msg->complete) 516 msg->complete(msg->context); 517 /* This message is completed, so let's turn off the clocks & power */ 518 clk_disable(pl022->clk); 519 amba_pclk_disable(pl022->adev); 520 amba_vcore_disable(pl022->adev); 521 pm_runtime_put(&pl022->adev->dev); 522 } 523 524 /** 525 * flush - flush the FIFO to reach a clean state 526 * @pl022: SSP driver private data structure 527 */ 528 static int flush(struct pl022 *pl022) 529 { 530 unsigned long limit = loops_per_jiffy << 1; 531 532 dev_dbg(&pl022->adev->dev, "flush\n"); 533 do { 534 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 535 readw(SSP_DR(pl022->virtbase)); 536 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 537 538 pl022->exp_fifo_level = 0; 539 540 return limit; 541 } 542 543 /** 544 * restore_state - Load configuration of current chip 545 * @pl022: SSP driver private data structure 546 */ 547 static void restore_state(struct pl022 *pl022) 548 { 549 struct chip_data *chip = pl022->cur_chip; 550 551 if (pl022->vendor->extended_cr) 552 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 553 else 554 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 555 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 556 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 557 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 558 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 559 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 560 } 561 562 /* 563 * Default SSP Register Values 564 */ 565 #define DEFAULT_SSP_REG_CR0 ( \ 566 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 567 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 568 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 569 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 570 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 571 ) 572 573 /* ST versions have slightly different bit layout */ 574 #define DEFAULT_SSP_REG_CR0_ST ( \ 575 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 576 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 577 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 578 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 579 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 580 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 581 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 582 ) 583 584 /* The PL023 version is slightly different again */ 585 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 586 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 587 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 588 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 589 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 590 ) 591 592 #define DEFAULT_SSP_REG_CR1 ( \ 593 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 594 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 595 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 596 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 597 ) 598 599 /* ST versions extend this register to use all 16 bits */ 600 #define DEFAULT_SSP_REG_CR1_ST ( \ 601 DEFAULT_SSP_REG_CR1 | \ 602 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 603 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 604 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 605 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 606 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 607 ) 608 609 /* 610 * The PL023 variant has further differences: no loopback mode, no microwire 611 * support, and a new clock feedback delay setting. 612 */ 613 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 614 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 615 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 616 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 617 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 618 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 619 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 620 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 621 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 622 ) 623 624 #define DEFAULT_SSP_REG_CPSR ( \ 625 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 626 ) 627 628 #define DEFAULT_SSP_REG_DMACR (\ 629 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 630 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 631 ) 632 633 /** 634 * load_ssp_default_config - Load default configuration for SSP 635 * @pl022: SSP driver private data structure 636 */ 637 static void load_ssp_default_config(struct pl022 *pl022) 638 { 639 if (pl022->vendor->pl023) { 640 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 641 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 642 } else if (pl022->vendor->extended_cr) { 643 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 644 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 645 } else { 646 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 647 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 648 } 649 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 650 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 651 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 652 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 653 } 654 655 /** 656 * This will write to TX and read from RX according to the parameters 657 * set in pl022. 658 */ 659 static void readwriter(struct pl022 *pl022) 660 { 661 662 /* 663 * The FIFO depth is different between primecell variants. 664 * I believe filling in too much in the FIFO might cause 665 * errons in 8bit wide transfers on ARM variants (just 8 words 666 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 667 * 668 * To prevent this issue, the TX FIFO is only filled to the 669 * unused RX FIFO fill length, regardless of what the TX 670 * FIFO status flag indicates. 671 */ 672 dev_dbg(&pl022->adev->dev, 673 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 674 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 675 676 /* Read as much as you can */ 677 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 678 && (pl022->rx < pl022->rx_end)) { 679 switch (pl022->read) { 680 case READING_NULL: 681 readw(SSP_DR(pl022->virtbase)); 682 break; 683 case READING_U8: 684 *(u8 *) (pl022->rx) = 685 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 686 break; 687 case READING_U16: 688 *(u16 *) (pl022->rx) = 689 (u16) readw(SSP_DR(pl022->virtbase)); 690 break; 691 case READING_U32: 692 *(u32 *) (pl022->rx) = 693 readl(SSP_DR(pl022->virtbase)); 694 break; 695 } 696 pl022->rx += (pl022->cur_chip->n_bytes); 697 pl022->exp_fifo_level--; 698 } 699 /* 700 * Write as much as possible up to the RX FIFO size 701 */ 702 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 703 && (pl022->tx < pl022->tx_end)) { 704 switch (pl022->write) { 705 case WRITING_NULL: 706 writew(0x0, SSP_DR(pl022->virtbase)); 707 break; 708 case WRITING_U8: 709 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 710 break; 711 case WRITING_U16: 712 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 713 break; 714 case WRITING_U32: 715 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 716 break; 717 } 718 pl022->tx += (pl022->cur_chip->n_bytes); 719 pl022->exp_fifo_level++; 720 /* 721 * This inner reader takes care of things appearing in the RX 722 * FIFO as we're transmitting. This will happen a lot since the 723 * clock starts running when you put things into the TX FIFO, 724 * and then things are continuously clocked into the RX FIFO. 725 */ 726 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 727 && (pl022->rx < pl022->rx_end)) { 728 switch (pl022->read) { 729 case READING_NULL: 730 readw(SSP_DR(pl022->virtbase)); 731 break; 732 case READING_U8: 733 *(u8 *) (pl022->rx) = 734 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 735 break; 736 case READING_U16: 737 *(u16 *) (pl022->rx) = 738 (u16) readw(SSP_DR(pl022->virtbase)); 739 break; 740 case READING_U32: 741 *(u32 *) (pl022->rx) = 742 readl(SSP_DR(pl022->virtbase)); 743 break; 744 } 745 pl022->rx += (pl022->cur_chip->n_bytes); 746 pl022->exp_fifo_level--; 747 } 748 } 749 /* 750 * When we exit here the TX FIFO should be full and the RX FIFO 751 * should be empty 752 */ 753 } 754 755 756 /** 757 * next_transfer - Move to the Next transfer in the current spi message 758 * @pl022: SSP driver private data structure 759 * 760 * This function moves though the linked list of spi transfers in the 761 * current spi message and returns with the state of current spi 762 * message i.e whether its last transfer is done(STATE_DONE) or 763 * Next transfer is ready(STATE_RUNNING) 764 */ 765 static void *next_transfer(struct pl022 *pl022) 766 { 767 struct spi_message *msg = pl022->cur_msg; 768 struct spi_transfer *trans = pl022->cur_transfer; 769 770 /* Move to next transfer */ 771 if (trans->transfer_list.next != &msg->transfers) { 772 pl022->cur_transfer = 773 list_entry(trans->transfer_list.next, 774 struct spi_transfer, transfer_list); 775 return STATE_RUNNING; 776 } 777 return STATE_DONE; 778 } 779 780 /* 781 * This DMA functionality is only compiled in if we have 782 * access to the generic DMA devices/DMA engine. 783 */ 784 #ifdef CONFIG_DMA_ENGINE 785 static void unmap_free_dma_scatter(struct pl022 *pl022) 786 { 787 /* Unmap and free the SG tables */ 788 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 789 pl022->sgt_tx.nents, DMA_TO_DEVICE); 790 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 791 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 792 sg_free_table(&pl022->sgt_rx); 793 sg_free_table(&pl022->sgt_tx); 794 } 795 796 static void dma_callback(void *data) 797 { 798 struct pl022 *pl022 = data; 799 struct spi_message *msg = pl022->cur_msg; 800 801 BUG_ON(!pl022->sgt_rx.sgl); 802 803 #ifdef VERBOSE_DEBUG 804 /* 805 * Optionally dump out buffers to inspect contents, this is 806 * good if you want to convince yourself that the loopback 807 * read/write contents are the same, when adopting to a new 808 * DMA engine. 809 */ 810 { 811 struct scatterlist *sg; 812 unsigned int i; 813 814 dma_sync_sg_for_cpu(&pl022->adev->dev, 815 pl022->sgt_rx.sgl, 816 pl022->sgt_rx.nents, 817 DMA_FROM_DEVICE); 818 819 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 820 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 821 print_hex_dump(KERN_ERR, "SPI RX: ", 822 DUMP_PREFIX_OFFSET, 823 16, 824 1, 825 sg_virt(sg), 826 sg_dma_len(sg), 827 1); 828 } 829 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 830 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 831 print_hex_dump(KERN_ERR, "SPI TX: ", 832 DUMP_PREFIX_OFFSET, 833 16, 834 1, 835 sg_virt(sg), 836 sg_dma_len(sg), 837 1); 838 } 839 } 840 #endif 841 842 unmap_free_dma_scatter(pl022); 843 844 /* Update total bytes transferred */ 845 msg->actual_length += pl022->cur_transfer->len; 846 if (pl022->cur_transfer->cs_change) 847 pl022->cur_chip-> 848 cs_control(SSP_CHIP_DESELECT); 849 850 /* Move to next transfer */ 851 msg->state = next_transfer(pl022); 852 tasklet_schedule(&pl022->pump_transfers); 853 } 854 855 static void setup_dma_scatter(struct pl022 *pl022, 856 void *buffer, 857 unsigned int length, 858 struct sg_table *sgtab) 859 { 860 struct scatterlist *sg; 861 int bytesleft = length; 862 void *bufp = buffer; 863 int mapbytes; 864 int i; 865 866 if (buffer) { 867 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 868 /* 869 * If there are less bytes left than what fits 870 * in the current page (plus page alignment offset) 871 * we just feed in this, else we stuff in as much 872 * as we can. 873 */ 874 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 875 mapbytes = bytesleft; 876 else 877 mapbytes = PAGE_SIZE - offset_in_page(bufp); 878 sg_set_page(sg, virt_to_page(bufp), 879 mapbytes, offset_in_page(bufp)); 880 bufp += mapbytes; 881 bytesleft -= mapbytes; 882 dev_dbg(&pl022->adev->dev, 883 "set RX/TX target page @ %p, %d bytes, %d left\n", 884 bufp, mapbytes, bytesleft); 885 } 886 } else { 887 /* Map the dummy buffer on every page */ 888 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 889 if (bytesleft < PAGE_SIZE) 890 mapbytes = bytesleft; 891 else 892 mapbytes = PAGE_SIZE; 893 sg_set_page(sg, virt_to_page(pl022->dummypage), 894 mapbytes, 0); 895 bytesleft -= mapbytes; 896 dev_dbg(&pl022->adev->dev, 897 "set RX/TX to dummy page %d bytes, %d left\n", 898 mapbytes, bytesleft); 899 900 } 901 } 902 BUG_ON(bytesleft); 903 } 904 905 /** 906 * configure_dma - configures the channels for the next transfer 907 * @pl022: SSP driver's private data structure 908 */ 909 static int configure_dma(struct pl022 *pl022) 910 { 911 struct dma_slave_config rx_conf = { 912 .src_addr = SSP_DR(pl022->phybase), 913 .direction = DMA_DEV_TO_MEM, 914 }; 915 struct dma_slave_config tx_conf = { 916 .dst_addr = SSP_DR(pl022->phybase), 917 .direction = DMA_MEM_TO_DEV, 918 }; 919 unsigned int pages; 920 int ret; 921 int rx_sglen, tx_sglen; 922 struct dma_chan *rxchan = pl022->dma_rx_channel; 923 struct dma_chan *txchan = pl022->dma_tx_channel; 924 struct dma_async_tx_descriptor *rxdesc; 925 struct dma_async_tx_descriptor *txdesc; 926 927 /* Check that the channels are available */ 928 if (!rxchan || !txchan) 929 return -ENODEV; 930 931 /* 932 * If supplied, the DMA burstsize should equal the FIFO trigger level. 933 * Notice that the DMA engine uses one-to-one mapping. Since we can 934 * not trigger on 2 elements this needs explicit mapping rather than 935 * calculation. 936 */ 937 switch (pl022->rx_lev_trig) { 938 case SSP_RX_1_OR_MORE_ELEM: 939 rx_conf.src_maxburst = 1; 940 break; 941 case SSP_RX_4_OR_MORE_ELEM: 942 rx_conf.src_maxburst = 4; 943 break; 944 case SSP_RX_8_OR_MORE_ELEM: 945 rx_conf.src_maxburst = 8; 946 break; 947 case SSP_RX_16_OR_MORE_ELEM: 948 rx_conf.src_maxburst = 16; 949 break; 950 case SSP_RX_32_OR_MORE_ELEM: 951 rx_conf.src_maxburst = 32; 952 break; 953 default: 954 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 955 break; 956 } 957 958 switch (pl022->tx_lev_trig) { 959 case SSP_TX_1_OR_MORE_EMPTY_LOC: 960 tx_conf.dst_maxburst = 1; 961 break; 962 case SSP_TX_4_OR_MORE_EMPTY_LOC: 963 tx_conf.dst_maxburst = 4; 964 break; 965 case SSP_TX_8_OR_MORE_EMPTY_LOC: 966 tx_conf.dst_maxburst = 8; 967 break; 968 case SSP_TX_16_OR_MORE_EMPTY_LOC: 969 tx_conf.dst_maxburst = 16; 970 break; 971 case SSP_TX_32_OR_MORE_EMPTY_LOC: 972 tx_conf.dst_maxburst = 32; 973 break; 974 default: 975 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 976 break; 977 } 978 979 switch (pl022->read) { 980 case READING_NULL: 981 /* Use the same as for writing */ 982 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 983 break; 984 case READING_U8: 985 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 986 break; 987 case READING_U16: 988 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 989 break; 990 case READING_U32: 991 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 992 break; 993 } 994 995 switch (pl022->write) { 996 case WRITING_NULL: 997 /* Use the same as for reading */ 998 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 999 break; 1000 case WRITING_U8: 1001 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1002 break; 1003 case WRITING_U16: 1004 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1005 break; 1006 case WRITING_U32: 1007 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1008 break; 1009 } 1010 1011 /* SPI pecularity: we need to read and write the same width */ 1012 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1013 rx_conf.src_addr_width = tx_conf.dst_addr_width; 1014 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1015 tx_conf.dst_addr_width = rx_conf.src_addr_width; 1016 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1017 1018 dmaengine_slave_config(rxchan, &rx_conf); 1019 dmaengine_slave_config(txchan, &tx_conf); 1020 1021 /* Create sglists for the transfers */ 1022 pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1; 1023 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1024 1025 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL); 1026 if (ret) 1027 goto err_alloc_rx_sg; 1028 1029 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL); 1030 if (ret) 1031 goto err_alloc_tx_sg; 1032 1033 /* Fill in the scatterlists for the RX+TX buffers */ 1034 setup_dma_scatter(pl022, pl022->rx, 1035 pl022->cur_transfer->len, &pl022->sgt_rx); 1036 setup_dma_scatter(pl022, pl022->tx, 1037 pl022->cur_transfer->len, &pl022->sgt_tx); 1038 1039 /* Map DMA buffers */ 1040 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1041 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1042 if (!rx_sglen) 1043 goto err_rx_sgmap; 1044 1045 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1046 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1047 if (!tx_sglen) 1048 goto err_tx_sgmap; 1049 1050 /* Send both scatterlists */ 1051 rxdesc = rxchan->device->device_prep_slave_sg(rxchan, 1052 pl022->sgt_rx.sgl, 1053 rx_sglen, 1054 DMA_DEV_TO_MEM, 1055 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1056 if (!rxdesc) 1057 goto err_rxdesc; 1058 1059 txdesc = txchan->device->device_prep_slave_sg(txchan, 1060 pl022->sgt_tx.sgl, 1061 tx_sglen, 1062 DMA_MEM_TO_DEV, 1063 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1064 if (!txdesc) 1065 goto err_txdesc; 1066 1067 /* Put the callback on the RX transfer only, that should finish last */ 1068 rxdesc->callback = dma_callback; 1069 rxdesc->callback_param = pl022; 1070 1071 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1072 dmaengine_submit(rxdesc); 1073 dmaengine_submit(txdesc); 1074 dma_async_issue_pending(rxchan); 1075 dma_async_issue_pending(txchan); 1076 1077 return 0; 1078 1079 err_txdesc: 1080 dmaengine_terminate_all(txchan); 1081 err_rxdesc: 1082 dmaengine_terminate_all(rxchan); 1083 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1084 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1085 err_tx_sgmap: 1086 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1087 pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1088 err_rx_sgmap: 1089 sg_free_table(&pl022->sgt_tx); 1090 err_alloc_tx_sg: 1091 sg_free_table(&pl022->sgt_rx); 1092 err_alloc_rx_sg: 1093 return -ENOMEM; 1094 } 1095 1096 static int __init pl022_dma_probe(struct pl022 *pl022) 1097 { 1098 dma_cap_mask_t mask; 1099 1100 /* Try to acquire a generic DMA engine slave channel */ 1101 dma_cap_zero(mask); 1102 dma_cap_set(DMA_SLAVE, mask); 1103 /* 1104 * We need both RX and TX channels to do DMA, else do none 1105 * of them. 1106 */ 1107 pl022->dma_rx_channel = dma_request_channel(mask, 1108 pl022->master_info->dma_filter, 1109 pl022->master_info->dma_rx_param); 1110 if (!pl022->dma_rx_channel) { 1111 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1112 goto err_no_rxchan; 1113 } 1114 1115 pl022->dma_tx_channel = dma_request_channel(mask, 1116 pl022->master_info->dma_filter, 1117 pl022->master_info->dma_tx_param); 1118 if (!pl022->dma_tx_channel) { 1119 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1120 goto err_no_txchan; 1121 } 1122 1123 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1124 if (!pl022->dummypage) { 1125 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1126 goto err_no_dummypage; 1127 } 1128 1129 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1130 dma_chan_name(pl022->dma_rx_channel), 1131 dma_chan_name(pl022->dma_tx_channel)); 1132 1133 return 0; 1134 1135 err_no_dummypage: 1136 dma_release_channel(pl022->dma_tx_channel); 1137 err_no_txchan: 1138 dma_release_channel(pl022->dma_rx_channel); 1139 pl022->dma_rx_channel = NULL; 1140 err_no_rxchan: 1141 dev_err(&pl022->adev->dev, 1142 "Failed to work in dma mode, work without dma!\n"); 1143 return -ENODEV; 1144 } 1145 1146 static void terminate_dma(struct pl022 *pl022) 1147 { 1148 struct dma_chan *rxchan = pl022->dma_rx_channel; 1149 struct dma_chan *txchan = pl022->dma_tx_channel; 1150 1151 dmaengine_terminate_all(rxchan); 1152 dmaengine_terminate_all(txchan); 1153 unmap_free_dma_scatter(pl022); 1154 } 1155 1156 static void pl022_dma_remove(struct pl022 *pl022) 1157 { 1158 if (pl022->busy) 1159 terminate_dma(pl022); 1160 if (pl022->dma_tx_channel) 1161 dma_release_channel(pl022->dma_tx_channel); 1162 if (pl022->dma_rx_channel) 1163 dma_release_channel(pl022->dma_rx_channel); 1164 kfree(pl022->dummypage); 1165 } 1166 1167 #else 1168 static inline int configure_dma(struct pl022 *pl022) 1169 { 1170 return -ENODEV; 1171 } 1172 1173 static inline int pl022_dma_probe(struct pl022 *pl022) 1174 { 1175 return 0; 1176 } 1177 1178 static inline void pl022_dma_remove(struct pl022 *pl022) 1179 { 1180 } 1181 #endif 1182 1183 /** 1184 * pl022_interrupt_handler - Interrupt handler for SSP controller 1185 * 1186 * This function handles interrupts generated for an interrupt based transfer. 1187 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1188 * current message's state as STATE_ERROR and schedule the tasklet 1189 * pump_transfers which will do the postprocessing of the current message by 1190 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1191 * more data, and writes data in TX FIFO till it is not full. If we complete 1192 * the transfer we move to the next transfer and schedule the tasklet. 1193 */ 1194 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1195 { 1196 struct pl022 *pl022 = dev_id; 1197 struct spi_message *msg = pl022->cur_msg; 1198 u16 irq_status = 0; 1199 u16 flag = 0; 1200 1201 if (unlikely(!msg)) { 1202 dev_err(&pl022->adev->dev, 1203 "bad message state in interrupt handler"); 1204 /* Never fail */ 1205 return IRQ_HANDLED; 1206 } 1207 1208 /* Read the Interrupt Status Register */ 1209 irq_status = readw(SSP_MIS(pl022->virtbase)); 1210 1211 if (unlikely(!irq_status)) 1212 return IRQ_NONE; 1213 1214 /* 1215 * This handles the FIFO interrupts, the timeout 1216 * interrupts are flatly ignored, they cannot be 1217 * trusted. 1218 */ 1219 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1220 /* 1221 * Overrun interrupt - bail out since our Data has been 1222 * corrupted 1223 */ 1224 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1225 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1226 dev_err(&pl022->adev->dev, 1227 "RXFIFO is full\n"); 1228 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1229 dev_err(&pl022->adev->dev, 1230 "TXFIFO is full\n"); 1231 1232 /* 1233 * Disable and clear interrupts, disable SSP, 1234 * mark message with bad status so it can be 1235 * retried. 1236 */ 1237 writew(DISABLE_ALL_INTERRUPTS, 1238 SSP_IMSC(pl022->virtbase)); 1239 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1240 writew((readw(SSP_CR1(pl022->virtbase)) & 1241 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1242 msg->state = STATE_ERROR; 1243 1244 /* Schedule message queue handler */ 1245 tasklet_schedule(&pl022->pump_transfers); 1246 return IRQ_HANDLED; 1247 } 1248 1249 readwriter(pl022); 1250 1251 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1252 flag = 1; 1253 /* Disable Transmit interrupt */ 1254 writew(readw(SSP_IMSC(pl022->virtbase)) & 1255 (~SSP_IMSC_MASK_TXIM), 1256 SSP_IMSC(pl022->virtbase)); 1257 } 1258 1259 /* 1260 * Since all transactions must write as much as shall be read, 1261 * we can conclude the entire transaction once RX is complete. 1262 * At this point, all TX will always be finished. 1263 */ 1264 if (pl022->rx >= pl022->rx_end) { 1265 writew(DISABLE_ALL_INTERRUPTS, 1266 SSP_IMSC(pl022->virtbase)); 1267 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1268 if (unlikely(pl022->rx > pl022->rx_end)) { 1269 dev_warn(&pl022->adev->dev, "read %u surplus " 1270 "bytes (did you request an odd " 1271 "number of bytes on a 16bit bus?)\n", 1272 (u32) (pl022->rx - pl022->rx_end)); 1273 } 1274 /* Update total bytes transferred */ 1275 msg->actual_length += pl022->cur_transfer->len; 1276 if (pl022->cur_transfer->cs_change) 1277 pl022->cur_chip-> 1278 cs_control(SSP_CHIP_DESELECT); 1279 /* Move to next transfer */ 1280 msg->state = next_transfer(pl022); 1281 tasklet_schedule(&pl022->pump_transfers); 1282 return IRQ_HANDLED; 1283 } 1284 1285 return IRQ_HANDLED; 1286 } 1287 1288 /** 1289 * This sets up the pointers to memory for the next message to 1290 * send out on the SPI bus. 1291 */ 1292 static int set_up_next_transfer(struct pl022 *pl022, 1293 struct spi_transfer *transfer) 1294 { 1295 int residue; 1296 1297 /* Sanity check the message for this bus width */ 1298 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1299 if (unlikely(residue != 0)) { 1300 dev_err(&pl022->adev->dev, 1301 "message of %u bytes to transmit but the current " 1302 "chip bus has a data width of %u bytes!\n", 1303 pl022->cur_transfer->len, 1304 pl022->cur_chip->n_bytes); 1305 dev_err(&pl022->adev->dev, "skipping this message\n"); 1306 return -EIO; 1307 } 1308 pl022->tx = (void *)transfer->tx_buf; 1309 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1310 pl022->rx = (void *)transfer->rx_buf; 1311 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1312 pl022->write = 1313 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1314 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1315 return 0; 1316 } 1317 1318 /** 1319 * pump_transfers - Tasklet function which schedules next transfer 1320 * when running in interrupt or DMA transfer mode. 1321 * @data: SSP driver private data structure 1322 * 1323 */ 1324 static void pump_transfers(unsigned long data) 1325 { 1326 struct pl022 *pl022 = (struct pl022 *) data; 1327 struct spi_message *message = NULL; 1328 struct spi_transfer *transfer = NULL; 1329 struct spi_transfer *previous = NULL; 1330 1331 /* Get current state information */ 1332 message = pl022->cur_msg; 1333 transfer = pl022->cur_transfer; 1334 1335 /* Handle for abort */ 1336 if (message->state == STATE_ERROR) { 1337 message->status = -EIO; 1338 giveback(pl022); 1339 return; 1340 } 1341 1342 /* Handle end of message */ 1343 if (message->state == STATE_DONE) { 1344 message->status = 0; 1345 giveback(pl022); 1346 return; 1347 } 1348 1349 /* Delay if requested at end of transfer before CS change */ 1350 if (message->state == STATE_RUNNING) { 1351 previous = list_entry(transfer->transfer_list.prev, 1352 struct spi_transfer, 1353 transfer_list); 1354 if (previous->delay_usecs) 1355 /* 1356 * FIXME: This runs in interrupt context. 1357 * Is this really smart? 1358 */ 1359 udelay(previous->delay_usecs); 1360 1361 /* Drop chip select only if cs_change is requested */ 1362 if (previous->cs_change) 1363 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1364 } else { 1365 /* STATE_START */ 1366 message->state = STATE_RUNNING; 1367 } 1368 1369 if (set_up_next_transfer(pl022, transfer)) { 1370 message->state = STATE_ERROR; 1371 message->status = -EIO; 1372 giveback(pl022); 1373 return; 1374 } 1375 /* Flush the FIFOs and let's go! */ 1376 flush(pl022); 1377 1378 if (pl022->cur_chip->enable_dma) { 1379 if (configure_dma(pl022)) { 1380 dev_dbg(&pl022->adev->dev, 1381 "configuration of DMA failed, fall back to interrupt mode\n"); 1382 goto err_config_dma; 1383 } 1384 return; 1385 } 1386 1387 err_config_dma: 1388 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 1389 } 1390 1391 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1392 { 1393 u32 irqflags = ENABLE_ALL_INTERRUPTS; 1394 1395 /* Enable target chip */ 1396 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1397 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1398 /* Error path */ 1399 pl022->cur_msg->state = STATE_ERROR; 1400 pl022->cur_msg->status = -EIO; 1401 giveback(pl022); 1402 return; 1403 } 1404 /* If we're using DMA, set up DMA here */ 1405 if (pl022->cur_chip->enable_dma) { 1406 /* Configure DMA transfer */ 1407 if (configure_dma(pl022)) { 1408 dev_dbg(&pl022->adev->dev, 1409 "configuration of DMA failed, fall back to interrupt mode\n"); 1410 goto err_config_dma; 1411 } 1412 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1413 irqflags = DISABLE_ALL_INTERRUPTS; 1414 } 1415 err_config_dma: 1416 /* Enable SSP, turn on interrupts */ 1417 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1418 SSP_CR1(pl022->virtbase)); 1419 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1420 } 1421 1422 static void do_polling_transfer(struct pl022 *pl022) 1423 { 1424 struct spi_message *message = NULL; 1425 struct spi_transfer *transfer = NULL; 1426 struct spi_transfer *previous = NULL; 1427 struct chip_data *chip; 1428 unsigned long time, timeout; 1429 1430 chip = pl022->cur_chip; 1431 message = pl022->cur_msg; 1432 1433 while (message->state != STATE_DONE) { 1434 /* Handle for abort */ 1435 if (message->state == STATE_ERROR) 1436 break; 1437 transfer = pl022->cur_transfer; 1438 1439 /* Delay if requested at end of transfer */ 1440 if (message->state == STATE_RUNNING) { 1441 previous = 1442 list_entry(transfer->transfer_list.prev, 1443 struct spi_transfer, transfer_list); 1444 if (previous->delay_usecs) 1445 udelay(previous->delay_usecs); 1446 if (previous->cs_change) 1447 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1448 } else { 1449 /* STATE_START */ 1450 message->state = STATE_RUNNING; 1451 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1452 } 1453 1454 /* Configuration Changing Per Transfer */ 1455 if (set_up_next_transfer(pl022, transfer)) { 1456 /* Error path */ 1457 message->state = STATE_ERROR; 1458 break; 1459 } 1460 /* Flush FIFOs and enable SSP */ 1461 flush(pl022); 1462 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1463 SSP_CR1(pl022->virtbase)); 1464 1465 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1466 1467 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1468 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1469 time = jiffies; 1470 readwriter(pl022); 1471 if (time_after(time, timeout)) { 1472 dev_warn(&pl022->adev->dev, 1473 "%s: timeout!\n", __func__); 1474 message->state = STATE_ERROR; 1475 goto out; 1476 } 1477 cpu_relax(); 1478 } 1479 1480 /* Update total byte transferred */ 1481 message->actual_length += pl022->cur_transfer->len; 1482 if (pl022->cur_transfer->cs_change) 1483 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 1484 /* Move to next transfer */ 1485 message->state = next_transfer(pl022); 1486 } 1487 out: 1488 /* Handle end of message */ 1489 if (message->state == STATE_DONE) 1490 message->status = 0; 1491 else 1492 message->status = -EIO; 1493 1494 giveback(pl022); 1495 return; 1496 } 1497 1498 /** 1499 * pump_messages - Workqueue function which processes spi message queue 1500 * @data: pointer to private data of SSP driver 1501 * 1502 * This function checks if there is any spi message in the queue that 1503 * needs processing and delegate control to appropriate function 1504 * do_polling_transfer()/do_interrupt_dma_transfer() 1505 * based on the kind of the transfer 1506 * 1507 */ 1508 static void pump_messages(struct work_struct *work) 1509 { 1510 struct pl022 *pl022 = 1511 container_of(work, struct pl022, pump_messages); 1512 unsigned long flags; 1513 1514 /* Lock queue and check for queue work */ 1515 spin_lock_irqsave(&pl022->queue_lock, flags); 1516 if (list_empty(&pl022->queue) || !pl022->running) { 1517 pl022->busy = false; 1518 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1519 return; 1520 } 1521 /* Make sure we are not already running a message */ 1522 if (pl022->cur_msg) { 1523 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1524 return; 1525 } 1526 /* Extract head of queue */ 1527 pl022->cur_msg = 1528 list_entry(pl022->queue.next, struct spi_message, queue); 1529 1530 list_del_init(&pl022->cur_msg->queue); 1531 pl022->busy = true; 1532 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1533 1534 /* Initial message state */ 1535 pl022->cur_msg->state = STATE_START; 1536 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, 1537 struct spi_transfer, 1538 transfer_list); 1539 1540 /* Setup the SPI using the per chip configuration */ 1541 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); 1542 /* 1543 * We enable the core voltage and clocks here, then the clocks 1544 * and core will be disabled when giveback() is called in each method 1545 * (poll/interrupt/DMA) 1546 */ 1547 pm_runtime_get_sync(&pl022->adev->dev); 1548 amba_vcore_enable(pl022->adev); 1549 amba_pclk_enable(pl022->adev); 1550 clk_enable(pl022->clk); 1551 restore_state(pl022); 1552 flush(pl022); 1553 1554 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1555 do_polling_transfer(pl022); 1556 else 1557 do_interrupt_dma_transfer(pl022); 1558 } 1559 1560 1561 static int __init init_queue(struct pl022 *pl022) 1562 { 1563 INIT_LIST_HEAD(&pl022->queue); 1564 spin_lock_init(&pl022->queue_lock); 1565 1566 pl022->running = false; 1567 pl022->busy = false; 1568 1569 tasklet_init(&pl022->pump_transfers, 1570 pump_transfers, (unsigned long)pl022); 1571 1572 INIT_WORK(&pl022->pump_messages, pump_messages); 1573 pl022->workqueue = create_singlethread_workqueue( 1574 dev_name(pl022->master->dev.parent)); 1575 if (pl022->workqueue == NULL) 1576 return -EBUSY; 1577 1578 return 0; 1579 } 1580 1581 1582 static int start_queue(struct pl022 *pl022) 1583 { 1584 unsigned long flags; 1585 1586 spin_lock_irqsave(&pl022->queue_lock, flags); 1587 1588 if (pl022->running || pl022->busy) { 1589 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1590 return -EBUSY; 1591 } 1592 1593 pl022->running = true; 1594 pl022->cur_msg = NULL; 1595 pl022->cur_transfer = NULL; 1596 pl022->cur_chip = NULL; 1597 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1598 1599 queue_work(pl022->workqueue, &pl022->pump_messages); 1600 1601 return 0; 1602 } 1603 1604 1605 static int stop_queue(struct pl022 *pl022) 1606 { 1607 unsigned long flags; 1608 unsigned limit = 500; 1609 int status = 0; 1610 1611 spin_lock_irqsave(&pl022->queue_lock, flags); 1612 1613 /* This is a bit lame, but is optimized for the common execution path. 1614 * A wait_queue on the pl022->busy could be used, but then the common 1615 * execution path (pump_messages) would be required to call wake_up or 1616 * friends on every SPI message. Do this instead */ 1617 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { 1618 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1619 msleep(10); 1620 spin_lock_irqsave(&pl022->queue_lock, flags); 1621 } 1622 1623 if (!list_empty(&pl022->queue) || pl022->busy) 1624 status = -EBUSY; 1625 else 1626 pl022->running = false; 1627 1628 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1629 1630 return status; 1631 } 1632 1633 static int destroy_queue(struct pl022 *pl022) 1634 { 1635 int status; 1636 1637 status = stop_queue(pl022); 1638 /* we are unloading the module or failing to load (only two calls 1639 * to this routine), and neither call can handle a return value. 1640 * However, destroy_workqueue calls flush_workqueue, and that will 1641 * block until all work is done. If the reason that stop_queue 1642 * timed out is that the work will never finish, then it does no 1643 * good to call destroy_workqueue, so return anyway. */ 1644 if (status != 0) 1645 return status; 1646 1647 destroy_workqueue(pl022->workqueue); 1648 1649 return 0; 1650 } 1651 1652 static int verify_controller_parameters(struct pl022 *pl022, 1653 struct pl022_config_chip const *chip_info) 1654 { 1655 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1656 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1657 dev_err(&pl022->adev->dev, 1658 "interface is configured incorrectly\n"); 1659 return -EINVAL; 1660 } 1661 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1662 (!pl022->vendor->unidir)) { 1663 dev_err(&pl022->adev->dev, 1664 "unidirectional mode not supported in this " 1665 "hardware version\n"); 1666 return -EINVAL; 1667 } 1668 if ((chip_info->hierarchy != SSP_MASTER) 1669 && (chip_info->hierarchy != SSP_SLAVE)) { 1670 dev_err(&pl022->adev->dev, 1671 "hierarchy is configured incorrectly\n"); 1672 return -EINVAL; 1673 } 1674 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1675 && (chip_info->com_mode != DMA_TRANSFER) 1676 && (chip_info->com_mode != POLLING_TRANSFER)) { 1677 dev_err(&pl022->adev->dev, 1678 "Communication mode is configured incorrectly\n"); 1679 return -EINVAL; 1680 } 1681 switch (chip_info->rx_lev_trig) { 1682 case SSP_RX_1_OR_MORE_ELEM: 1683 case SSP_RX_4_OR_MORE_ELEM: 1684 case SSP_RX_8_OR_MORE_ELEM: 1685 /* These are always OK, all variants can handle this */ 1686 break; 1687 case SSP_RX_16_OR_MORE_ELEM: 1688 if (pl022->vendor->fifodepth < 16) { 1689 dev_err(&pl022->adev->dev, 1690 "RX FIFO Trigger Level is configured incorrectly\n"); 1691 return -EINVAL; 1692 } 1693 break; 1694 case SSP_RX_32_OR_MORE_ELEM: 1695 if (pl022->vendor->fifodepth < 32) { 1696 dev_err(&pl022->adev->dev, 1697 "RX FIFO Trigger Level is configured incorrectly\n"); 1698 return -EINVAL; 1699 } 1700 break; 1701 default: 1702 dev_err(&pl022->adev->dev, 1703 "RX FIFO Trigger Level is configured incorrectly\n"); 1704 return -EINVAL; 1705 break; 1706 } 1707 switch (chip_info->tx_lev_trig) { 1708 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1709 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1710 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1711 /* These are always OK, all variants can handle this */ 1712 break; 1713 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1714 if (pl022->vendor->fifodepth < 16) { 1715 dev_err(&pl022->adev->dev, 1716 "TX FIFO Trigger Level is configured incorrectly\n"); 1717 return -EINVAL; 1718 } 1719 break; 1720 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1721 if (pl022->vendor->fifodepth < 32) { 1722 dev_err(&pl022->adev->dev, 1723 "TX FIFO Trigger Level is configured incorrectly\n"); 1724 return -EINVAL; 1725 } 1726 break; 1727 default: 1728 dev_err(&pl022->adev->dev, 1729 "TX FIFO Trigger Level is configured incorrectly\n"); 1730 return -EINVAL; 1731 break; 1732 } 1733 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1734 if ((chip_info->ctrl_len < SSP_BITS_4) 1735 || (chip_info->ctrl_len > SSP_BITS_32)) { 1736 dev_err(&pl022->adev->dev, 1737 "CTRL LEN is configured incorrectly\n"); 1738 return -EINVAL; 1739 } 1740 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1741 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1742 dev_err(&pl022->adev->dev, 1743 "Wait State is configured incorrectly\n"); 1744 return -EINVAL; 1745 } 1746 /* Half duplex is only available in the ST Micro version */ 1747 if (pl022->vendor->extended_cr) { 1748 if ((chip_info->duplex != 1749 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1750 && (chip_info->duplex != 1751 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1752 dev_err(&pl022->adev->dev, 1753 "Microwire duplex mode is configured incorrectly\n"); 1754 return -EINVAL; 1755 } 1756 } else { 1757 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1758 dev_err(&pl022->adev->dev, 1759 "Microwire half duplex mode requested," 1760 " but this is only available in the" 1761 " ST version of PL022\n"); 1762 return -EINVAL; 1763 } 1764 } 1765 return 0; 1766 } 1767 1768 /** 1769 * pl022_transfer - transfer function registered to SPI master framework 1770 * @spi: spi device which is requesting transfer 1771 * @msg: spi message which is to handled is queued to driver queue 1772 * 1773 * This function is registered to the SPI framework for this SPI master 1774 * controller. It will queue the spi_message in the queue of driver if 1775 * the queue is not stopped and return. 1776 */ 1777 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) 1778 { 1779 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1780 unsigned long flags; 1781 1782 spin_lock_irqsave(&pl022->queue_lock, flags); 1783 1784 if (!pl022->running) { 1785 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1786 return -ESHUTDOWN; 1787 } 1788 msg->actual_length = 0; 1789 msg->status = -EINPROGRESS; 1790 msg->state = STATE_START; 1791 1792 list_add_tail(&msg->queue, &pl022->queue); 1793 if (pl022->running && !pl022->busy) 1794 queue_work(pl022->workqueue, &pl022->pump_messages); 1795 1796 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1797 return 0; 1798 } 1799 1800 static int calculate_effective_freq(struct pl022 *pl022, 1801 int freq, 1802 struct ssp_clock_params *clk_freq) 1803 { 1804 /* Lets calculate the frequency parameters */ 1805 u16 cpsdvsr = 2; 1806 u16 scr = 0; 1807 bool freq_found = false; 1808 u32 rate; 1809 u32 max_tclk; 1810 u32 min_tclk; 1811 1812 rate = clk_get_rate(pl022->clk); 1813 /* cpsdvscr = 2 & scr 0 */ 1814 max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN))); 1815 /* cpsdvsr = 254 & scr = 255 */ 1816 min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX))); 1817 1818 if ((freq <= max_tclk) && (freq >= min_tclk)) { 1819 while (cpsdvsr <= CPSDVR_MAX && !freq_found) { 1820 while (scr <= SCR_MAX && !freq_found) { 1821 if ((rate / 1822 (cpsdvsr * (1 + scr))) > freq) 1823 scr += 1; 1824 else { 1825 /* 1826 * This bool is made true when 1827 * effective frequency >= 1828 * target frequency is found 1829 */ 1830 freq_found = true; 1831 if ((rate / 1832 (cpsdvsr * (1 + scr))) != freq) { 1833 if (scr == SCR_MIN) { 1834 cpsdvsr -= 2; 1835 scr = SCR_MAX; 1836 } else 1837 scr -= 1; 1838 } 1839 } 1840 } 1841 if (!freq_found) { 1842 cpsdvsr += 2; 1843 scr = SCR_MIN; 1844 } 1845 } 1846 if (cpsdvsr != 0) { 1847 dev_dbg(&pl022->adev->dev, 1848 "SSP Effective Frequency is %u\n", 1849 (rate / (cpsdvsr * (1 + scr)))); 1850 clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF); 1851 clk_freq->scr = (u8) (scr & 0xFF); 1852 dev_dbg(&pl022->adev->dev, 1853 "SSP cpsdvsr = %d, scr = %d\n", 1854 clk_freq->cpsdvsr, clk_freq->scr); 1855 } 1856 } else { 1857 dev_err(&pl022->adev->dev, 1858 "controller data is incorrect: out of range frequency"); 1859 return -EINVAL; 1860 } 1861 return 0; 1862 } 1863 1864 1865 /* 1866 * A piece of default chip info unless the platform 1867 * supplies it. 1868 */ 1869 static const struct pl022_config_chip pl022_default_chip_info = { 1870 .com_mode = POLLING_TRANSFER, 1871 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1872 .hierarchy = SSP_SLAVE, 1873 .slave_tx_disable = DO_NOT_DRIVE_TX, 1874 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1875 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1876 .ctrl_len = SSP_BITS_8, 1877 .wait_state = SSP_MWIRE_WAIT_ZERO, 1878 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1879 .cs_control = null_cs_control, 1880 }; 1881 1882 1883 /** 1884 * pl022_setup - setup function registered to SPI master framework 1885 * @spi: spi device which is requesting setup 1886 * 1887 * This function is registered to the SPI framework for this SPI master 1888 * controller. If it is the first time when setup is called by this device, 1889 * this function will initialize the runtime state for this chip and save 1890 * the same in the device structure. Else it will update the runtime info 1891 * with the updated chip info. Nothing is really being written to the 1892 * controller hardware here, that is not done until the actual transfer 1893 * commence. 1894 */ 1895 static int pl022_setup(struct spi_device *spi) 1896 { 1897 struct pl022_config_chip const *chip_info; 1898 struct chip_data *chip; 1899 struct ssp_clock_params clk_freq = {0, }; 1900 int status = 0; 1901 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1902 unsigned int bits = spi->bits_per_word; 1903 u32 tmp; 1904 1905 if (!spi->max_speed_hz) 1906 return -EINVAL; 1907 1908 /* Get controller_state if one is supplied */ 1909 chip = spi_get_ctldata(spi); 1910 1911 if (chip == NULL) { 1912 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1913 if (!chip) { 1914 dev_err(&spi->dev, 1915 "cannot allocate controller state\n"); 1916 return -ENOMEM; 1917 } 1918 dev_dbg(&spi->dev, 1919 "allocated memory for controller's runtime state\n"); 1920 } 1921 1922 /* Get controller data if one is supplied */ 1923 chip_info = spi->controller_data; 1924 1925 if (chip_info == NULL) { 1926 chip_info = &pl022_default_chip_info; 1927 /* spi_board_info.controller_data not is supplied */ 1928 dev_dbg(&spi->dev, 1929 "using default controller_data settings\n"); 1930 } else 1931 dev_dbg(&spi->dev, 1932 "using user supplied controller_data settings\n"); 1933 1934 /* 1935 * We can override with custom divisors, else we use the board 1936 * frequency setting 1937 */ 1938 if ((0 == chip_info->clk_freq.cpsdvsr) 1939 && (0 == chip_info->clk_freq.scr)) { 1940 status = calculate_effective_freq(pl022, 1941 spi->max_speed_hz, 1942 &clk_freq); 1943 if (status < 0) 1944 goto err_config_params; 1945 } else { 1946 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1947 if ((clk_freq.cpsdvsr % 2) != 0) 1948 clk_freq.cpsdvsr = 1949 clk_freq.cpsdvsr - 1; 1950 } 1951 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1952 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1953 status = -EINVAL; 1954 dev_err(&spi->dev, 1955 "cpsdvsr is configured incorrectly\n"); 1956 goto err_config_params; 1957 } 1958 1959 1960 status = verify_controller_parameters(pl022, chip_info); 1961 if (status) { 1962 dev_err(&spi->dev, "controller data is incorrect"); 1963 goto err_config_params; 1964 } 1965 1966 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1967 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1968 1969 /* Now set controller state based on controller data */ 1970 chip->xfer_type = chip_info->com_mode; 1971 if (!chip_info->cs_control) { 1972 chip->cs_control = null_cs_control; 1973 dev_warn(&spi->dev, 1974 "chip select function is NULL for this chip\n"); 1975 } else 1976 chip->cs_control = chip_info->cs_control; 1977 1978 if (bits <= 3) { 1979 /* PL022 doesn't support less than 4-bits */ 1980 status = -ENOTSUPP; 1981 goto err_config_params; 1982 } else if (bits <= 8) { 1983 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1984 chip->n_bytes = 1; 1985 chip->read = READING_U8; 1986 chip->write = WRITING_U8; 1987 } else if (bits <= 16) { 1988 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1989 chip->n_bytes = 2; 1990 chip->read = READING_U16; 1991 chip->write = WRITING_U16; 1992 } else { 1993 if (pl022->vendor->max_bpw >= 32) { 1994 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1995 chip->n_bytes = 4; 1996 chip->read = READING_U32; 1997 chip->write = WRITING_U32; 1998 } else { 1999 dev_err(&spi->dev, 2000 "illegal data size for this controller!\n"); 2001 dev_err(&spi->dev, 2002 "a standard pl022 can only handle " 2003 "1 <= n <= 16 bit words\n"); 2004 status = -ENOTSUPP; 2005 goto err_config_params; 2006 } 2007 } 2008 2009 /* Now Initialize all register settings required for this chip */ 2010 chip->cr0 = 0; 2011 chip->cr1 = 0; 2012 chip->dmacr = 0; 2013 chip->cpsr = 0; 2014 if ((chip_info->com_mode == DMA_TRANSFER) 2015 && ((pl022->master_info)->enable_dma)) { 2016 chip->enable_dma = true; 2017 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 2018 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2019 SSP_DMACR_MASK_RXDMAE, 0); 2020 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2021 SSP_DMACR_MASK_TXDMAE, 1); 2022 } else { 2023 chip->enable_dma = false; 2024 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 2025 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2026 SSP_DMACR_MASK_RXDMAE, 0); 2027 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2028 SSP_DMACR_MASK_TXDMAE, 1); 2029 } 2030 2031 chip->cpsr = clk_freq.cpsdvsr; 2032 2033 /* Special setup for the ST micro extended control registers */ 2034 if (pl022->vendor->extended_cr) { 2035 u32 etx; 2036 2037 if (pl022->vendor->pl023) { 2038 /* These bits are only in the PL023 */ 2039 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 2040 SSP_CR1_MASK_FBCLKDEL_ST, 13); 2041 } else { 2042 /* These bits are in the PL022 but not PL023 */ 2043 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 2044 SSP_CR0_MASK_HALFDUP_ST, 5); 2045 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 2046 SSP_CR0_MASK_CSS_ST, 16); 2047 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2048 SSP_CR0_MASK_FRF_ST, 21); 2049 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 2050 SSP_CR1_MASK_MWAIT_ST, 6); 2051 } 2052 SSP_WRITE_BITS(chip->cr0, bits - 1, 2053 SSP_CR0_MASK_DSS_ST, 0); 2054 2055 if (spi->mode & SPI_LSB_FIRST) { 2056 tmp = SSP_RX_LSB; 2057 etx = SSP_TX_LSB; 2058 } else { 2059 tmp = SSP_RX_MSB; 2060 etx = SSP_TX_MSB; 2061 } 2062 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2063 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2064 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2065 SSP_CR1_MASK_RXIFLSEL_ST, 7); 2066 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2067 SSP_CR1_MASK_TXIFLSEL_ST, 10); 2068 } else { 2069 SSP_WRITE_BITS(chip->cr0, bits - 1, 2070 SSP_CR0_MASK_DSS, 0); 2071 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2072 SSP_CR0_MASK_FRF, 4); 2073 } 2074 2075 /* Stuff that is common for all versions */ 2076 if (spi->mode & SPI_CPOL) 2077 tmp = SSP_CLK_POL_IDLE_HIGH; 2078 else 2079 tmp = SSP_CLK_POL_IDLE_LOW; 2080 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2081 2082 if (spi->mode & SPI_CPHA) 2083 tmp = SSP_CLK_SECOND_EDGE; 2084 else 2085 tmp = SSP_CLK_FIRST_EDGE; 2086 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2087 2088 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2089 /* Loopback is available on all versions except PL023 */ 2090 if (pl022->vendor->loopback) { 2091 if (spi->mode & SPI_LOOP) 2092 tmp = LOOPBACK_ENABLED; 2093 else 2094 tmp = LOOPBACK_DISABLED; 2095 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2096 } 2097 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2098 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2099 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3); 2100 2101 /* Save controller_state */ 2102 spi_set_ctldata(spi, chip); 2103 return status; 2104 err_config_params: 2105 spi_set_ctldata(spi, NULL); 2106 kfree(chip); 2107 return status; 2108 } 2109 2110 /** 2111 * pl022_cleanup - cleanup function registered to SPI master framework 2112 * @spi: spi device which is requesting cleanup 2113 * 2114 * This function is registered to the SPI framework for this SPI master 2115 * controller. It will free the runtime state of chip. 2116 */ 2117 static void pl022_cleanup(struct spi_device *spi) 2118 { 2119 struct chip_data *chip = spi_get_ctldata(spi); 2120 2121 spi_set_ctldata(spi, NULL); 2122 kfree(chip); 2123 } 2124 2125 2126 static int __devinit 2127 pl022_probe(struct amba_device *adev, const struct amba_id *id) 2128 { 2129 struct device *dev = &adev->dev; 2130 struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2131 struct spi_master *master; 2132 struct pl022 *pl022 = NULL; /*Data for this driver */ 2133 int status = 0; 2134 2135 dev_info(&adev->dev, 2136 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2137 if (platform_info == NULL) { 2138 dev_err(&adev->dev, "probe - no platform data supplied\n"); 2139 status = -ENODEV; 2140 goto err_no_pdata; 2141 } 2142 2143 /* Allocate master with space for data */ 2144 master = spi_alloc_master(dev, sizeof(struct pl022)); 2145 if (master == NULL) { 2146 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2147 status = -ENOMEM; 2148 goto err_no_master; 2149 } 2150 2151 pl022 = spi_master_get_devdata(master); 2152 pl022->master = master; 2153 pl022->master_info = platform_info; 2154 pl022->adev = adev; 2155 pl022->vendor = id->data; 2156 2157 /* 2158 * Bus Number Which has been Assigned to this SSP controller 2159 * on this board 2160 */ 2161 master->bus_num = platform_info->bus_id; 2162 master->num_chipselect = platform_info->num_chipselect; 2163 master->cleanup = pl022_cleanup; 2164 master->setup = pl022_setup; 2165 master->transfer = pl022_transfer; 2166 2167 /* 2168 * Supports mode 0-3, loopback, and active low CS. Transfers are 2169 * always MS bit first on the original pl022. 2170 */ 2171 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2172 if (pl022->vendor->extended_cr) 2173 master->mode_bits |= SPI_LSB_FIRST; 2174 2175 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2176 2177 status = amba_request_regions(adev, NULL); 2178 if (status) 2179 goto err_no_ioregion; 2180 2181 pl022->phybase = adev->res.start; 2182 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2183 if (pl022->virtbase == NULL) { 2184 status = -ENOMEM; 2185 goto err_no_ioremap; 2186 } 2187 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2188 adev->res.start, pl022->virtbase); 2189 pm_runtime_enable(dev); 2190 pm_runtime_resume(dev); 2191 2192 pl022->clk = clk_get(&adev->dev, NULL); 2193 if (IS_ERR(pl022->clk)) { 2194 status = PTR_ERR(pl022->clk); 2195 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2196 goto err_no_clk; 2197 } 2198 2199 /* Disable SSP */ 2200 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2201 SSP_CR1(pl022->virtbase)); 2202 load_ssp_default_config(pl022); 2203 2204 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2205 pl022); 2206 if (status < 0) { 2207 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2208 goto err_no_irq; 2209 } 2210 2211 /* Get DMA channels */ 2212 if (platform_info->enable_dma) { 2213 status = pl022_dma_probe(pl022); 2214 if (status != 0) 2215 platform_info->enable_dma = 0; 2216 } 2217 2218 /* Initialize and start queue */ 2219 status = init_queue(pl022); 2220 if (status != 0) { 2221 dev_err(&adev->dev, "probe - problem initializing queue\n"); 2222 goto err_init_queue; 2223 } 2224 status = start_queue(pl022); 2225 if (status != 0) { 2226 dev_err(&adev->dev, "probe - problem starting queue\n"); 2227 goto err_start_queue; 2228 } 2229 /* Register with the SPI framework */ 2230 amba_set_drvdata(adev, pl022); 2231 status = spi_register_master(master); 2232 if (status != 0) { 2233 dev_err(&adev->dev, 2234 "probe - problem registering spi master\n"); 2235 goto err_spi_register; 2236 } 2237 dev_dbg(dev, "probe succeeded\n"); 2238 /* 2239 * Disable the silicon block pclk and any voltage domain and just 2240 * power it up and clock it when it's needed 2241 */ 2242 amba_pclk_disable(adev); 2243 amba_vcore_disable(adev); 2244 return 0; 2245 2246 err_spi_register: 2247 err_start_queue: 2248 err_init_queue: 2249 destroy_queue(pl022); 2250 pl022_dma_remove(pl022); 2251 free_irq(adev->irq[0], pl022); 2252 pm_runtime_disable(&adev->dev); 2253 err_no_irq: 2254 clk_put(pl022->clk); 2255 err_no_clk: 2256 iounmap(pl022->virtbase); 2257 err_no_ioremap: 2258 amba_release_regions(adev); 2259 err_no_ioregion: 2260 spi_master_put(master); 2261 err_no_master: 2262 err_no_pdata: 2263 return status; 2264 } 2265 2266 static int __devexit 2267 pl022_remove(struct amba_device *adev) 2268 { 2269 struct pl022 *pl022 = amba_get_drvdata(adev); 2270 2271 if (!pl022) 2272 return 0; 2273 2274 /* Remove the queue */ 2275 if (destroy_queue(pl022) != 0) 2276 dev_err(&adev->dev, "queue remove failed\n"); 2277 load_ssp_default_config(pl022); 2278 pl022_dma_remove(pl022); 2279 free_irq(adev->irq[0], pl022); 2280 clk_disable(pl022->clk); 2281 clk_put(pl022->clk); 2282 iounmap(pl022->virtbase); 2283 amba_release_regions(adev); 2284 tasklet_disable(&pl022->pump_transfers); 2285 spi_unregister_master(pl022->master); 2286 spi_master_put(pl022->master); 2287 amba_set_drvdata(adev, NULL); 2288 return 0; 2289 } 2290 2291 #ifdef CONFIG_PM 2292 static int pl022_suspend(struct amba_device *adev, pm_message_t state) 2293 { 2294 struct pl022 *pl022 = amba_get_drvdata(adev); 2295 int status = 0; 2296 2297 status = stop_queue(pl022); 2298 if (status) { 2299 dev_warn(&adev->dev, "suspend cannot stop queue\n"); 2300 return status; 2301 } 2302 2303 amba_vcore_enable(adev); 2304 amba_pclk_enable(adev); 2305 load_ssp_default_config(pl022); 2306 amba_pclk_disable(adev); 2307 amba_vcore_disable(adev); 2308 dev_dbg(&adev->dev, "suspended\n"); 2309 return 0; 2310 } 2311 2312 static int pl022_resume(struct amba_device *adev) 2313 { 2314 struct pl022 *pl022 = amba_get_drvdata(adev); 2315 int status = 0; 2316 2317 /* Start the queue running */ 2318 status = start_queue(pl022); 2319 if (status) 2320 dev_err(&adev->dev, "problem starting queue (%d)\n", status); 2321 else 2322 dev_dbg(&adev->dev, "resumed\n"); 2323 2324 return status; 2325 } 2326 #else 2327 #define pl022_suspend NULL 2328 #define pl022_resume NULL 2329 #endif /* CONFIG_PM */ 2330 2331 static struct vendor_data vendor_arm = { 2332 .fifodepth = 8, 2333 .max_bpw = 16, 2334 .unidir = false, 2335 .extended_cr = false, 2336 .pl023 = false, 2337 .loopback = true, 2338 }; 2339 2340 2341 static struct vendor_data vendor_st = { 2342 .fifodepth = 32, 2343 .max_bpw = 32, 2344 .unidir = false, 2345 .extended_cr = true, 2346 .pl023 = false, 2347 .loopback = true, 2348 }; 2349 2350 static struct vendor_data vendor_st_pl023 = { 2351 .fifodepth = 32, 2352 .max_bpw = 32, 2353 .unidir = false, 2354 .extended_cr = true, 2355 .pl023 = true, 2356 .loopback = false, 2357 }; 2358 2359 static struct vendor_data vendor_db5500_pl023 = { 2360 .fifodepth = 32, 2361 .max_bpw = 32, 2362 .unidir = false, 2363 .extended_cr = true, 2364 .pl023 = true, 2365 .loopback = true, 2366 }; 2367 2368 static struct amba_id pl022_ids[] = { 2369 { 2370 /* 2371 * ARM PL022 variant, this has a 16bit wide 2372 * and 8 locations deep TX/RX FIFO 2373 */ 2374 .id = 0x00041022, 2375 .mask = 0x000fffff, 2376 .data = &vendor_arm, 2377 }, 2378 { 2379 /* 2380 * ST Micro derivative, this has 32bit wide 2381 * and 32 locations deep TX/RX FIFO 2382 */ 2383 .id = 0x01080022, 2384 .mask = 0xffffffff, 2385 .data = &vendor_st, 2386 }, 2387 { 2388 /* 2389 * ST-Ericsson derivative "PL023" (this is not 2390 * an official ARM number), this is a PL022 SSP block 2391 * stripped to SPI mode only, it has 32bit wide 2392 * and 32 locations deep TX/RX FIFO but no extended 2393 * CR0/CR1 register 2394 */ 2395 .id = 0x00080023, 2396 .mask = 0xffffffff, 2397 .data = &vendor_st_pl023, 2398 }, 2399 { 2400 .id = 0x10080023, 2401 .mask = 0xffffffff, 2402 .data = &vendor_db5500_pl023, 2403 }, 2404 { 0, 0 }, 2405 }; 2406 2407 static struct amba_driver pl022_driver = { 2408 .drv = { 2409 .name = "ssp-pl022", 2410 }, 2411 .id_table = pl022_ids, 2412 .probe = pl022_probe, 2413 .remove = __devexit_p(pl022_remove), 2414 .suspend = pl022_suspend, 2415 .resume = pl022_resume, 2416 }; 2417 2418 2419 static int __init pl022_init(void) 2420 { 2421 return amba_driver_register(&pl022_driver); 2422 } 2423 2424 subsys_initcall(pl022_init); 2425 2426 static void __exit pl022_exit(void) 2427 { 2428 amba_driver_unregister(&pl022_driver); 2429 } 2430 2431 module_exit(pl022_exit); 2432 2433 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2434 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2435 MODULE_LICENSE("GPL"); 2436