1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2009 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/workqueue.h> 33 #include <linux/delay.h> 34 #include <linux/clk.h> 35 #include <linux/err.h> 36 #include <linux/amba/bus.h> 37 #include <linux/amba/pl022.h> 38 #include <linux/io.h> 39 #include <linux/slab.h> 40 #include <linux/dmaengine.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/scatterlist.h> 43 #include <linux/pm_runtime.h> 44 45 /* 46 * This macro is used to define some register default values. 47 * reg is masked with mask, the OR:ed with an (again masked) 48 * val shifted sb steps to the left. 49 */ 50 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 51 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 52 53 /* 54 * This macro is also used to define some default values. 55 * It will just shift val by sb steps to the left and mask 56 * the result with mask. 57 */ 58 #define GEN_MASK_BITS(val, mask, sb) \ 59 (((val)<<(sb)) & (mask)) 60 61 #define DRIVE_TX 0 62 #define DO_NOT_DRIVE_TX 1 63 64 #define DO_NOT_QUEUE_DMA 0 65 #define QUEUE_DMA 1 66 67 #define RX_TRANSFER 1 68 #define TX_TRANSFER 2 69 70 /* 71 * Macros to access SSP Registers with their offsets 72 */ 73 #define SSP_CR0(r) (r + 0x000) 74 #define SSP_CR1(r) (r + 0x004) 75 #define SSP_DR(r) (r + 0x008) 76 #define SSP_SR(r) (r + 0x00C) 77 #define SSP_CPSR(r) (r + 0x010) 78 #define SSP_IMSC(r) (r + 0x014) 79 #define SSP_RIS(r) (r + 0x018) 80 #define SSP_MIS(r) (r + 0x01C) 81 #define SSP_ICR(r) (r + 0x020) 82 #define SSP_DMACR(r) (r + 0x024) 83 #define SSP_ITCR(r) (r + 0x080) 84 #define SSP_ITIP(r) (r + 0x084) 85 #define SSP_ITOP(r) (r + 0x088) 86 #define SSP_TDR(r) (r + 0x08C) 87 88 #define SSP_PID0(r) (r + 0xFE0) 89 #define SSP_PID1(r) (r + 0xFE4) 90 #define SSP_PID2(r) (r + 0xFE8) 91 #define SSP_PID3(r) (r + 0xFEC) 92 93 #define SSP_CID0(r) (r + 0xFF0) 94 #define SSP_CID1(r) (r + 0xFF4) 95 #define SSP_CID2(r) (r + 0xFF8) 96 #define SSP_CID3(r) (r + 0xFFC) 97 98 /* 99 * SSP Control Register 0 - SSP_CR0 100 */ 101 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 102 #define SSP_CR0_MASK_FRF (0x3UL << 4) 103 #define SSP_CR0_MASK_SPO (0x1UL << 6) 104 #define SSP_CR0_MASK_SPH (0x1UL << 7) 105 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 106 107 /* 108 * The ST version of this block moves som bits 109 * in SSP_CR0 and extends it to 32 bits 110 */ 111 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 112 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 113 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 114 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 115 116 /* 117 * SSP Control Register 0 - SSP_CR1 118 */ 119 #define SSP_CR1_MASK_LBM (0x1UL << 0) 120 #define SSP_CR1_MASK_SSE (0x1UL << 1) 121 #define SSP_CR1_MASK_MS (0x1UL << 2) 122 #define SSP_CR1_MASK_SOD (0x1UL << 3) 123 124 /* 125 * The ST version of this block adds some bits 126 * in SSP_CR1 127 */ 128 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 129 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 130 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 131 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 132 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 133 /* This one is only in the PL023 variant */ 134 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 135 136 /* 137 * SSP Status Register - SSP_SR 138 */ 139 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 140 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 141 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 142 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 143 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 144 145 /* 146 * SSP Clock Prescale Register - SSP_CPSR 147 */ 148 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 149 150 /* 151 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 152 */ 153 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 154 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 155 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 156 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 157 158 /* 159 * SSP Raw Interrupt Status Register - SSP_RIS 160 */ 161 /* Receive Overrun Raw Interrupt status */ 162 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 163 /* Receive Timeout Raw Interrupt status */ 164 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 165 /* Receive FIFO Raw Interrupt status */ 166 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 167 /* Transmit FIFO Raw Interrupt status */ 168 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 169 170 /* 171 * SSP Masked Interrupt Status Register - SSP_MIS 172 */ 173 /* Receive Overrun Masked Interrupt status */ 174 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 175 /* Receive Timeout Masked Interrupt status */ 176 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 177 /* Receive FIFO Masked Interrupt status */ 178 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 179 /* Transmit FIFO Masked Interrupt status */ 180 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 181 182 /* 183 * SSP Interrupt Clear Register - SSP_ICR 184 */ 185 /* Receive Overrun Raw Clear Interrupt bit */ 186 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 187 /* Receive Timeout Clear Interrupt bit */ 188 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 189 190 /* 191 * SSP DMA Control Register - SSP_DMACR 192 */ 193 /* Receive DMA Enable bit */ 194 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 195 /* Transmit DMA Enable bit */ 196 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 197 198 /* 199 * SSP Integration Test control Register - SSP_ITCR 200 */ 201 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 202 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 203 204 /* 205 * SSP Integration Test Input Register - SSP_ITIP 206 */ 207 #define ITIP_MASK_SSPRXD (0x1UL << 0) 208 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 209 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 210 #define ITIP_MASK_RXDMAC (0x1UL << 3) 211 #define ITIP_MASK_TXDMAC (0x1UL << 4) 212 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 213 214 /* 215 * SSP Integration Test output Register - SSP_ITOP 216 */ 217 #define ITOP_MASK_SSPTXD (0x1UL << 0) 218 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 219 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 220 #define ITOP_MASK_SSPOEn (0x1UL << 3) 221 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 222 #define ITOP_MASK_RORINTR (0x1UL << 5) 223 #define ITOP_MASK_RTINTR (0x1UL << 6) 224 #define ITOP_MASK_RXINTR (0x1UL << 7) 225 #define ITOP_MASK_TXINTR (0x1UL << 8) 226 #define ITOP_MASK_INTR (0x1UL << 9) 227 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 228 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 229 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 230 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 231 232 /* 233 * SSP Test Data Register - SSP_TDR 234 */ 235 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 236 237 /* 238 * Message State 239 * we use the spi_message.state (void *) pointer to 240 * hold a single state value, that's why all this 241 * (void *) casting is done here. 242 */ 243 #define STATE_START ((void *) 0) 244 #define STATE_RUNNING ((void *) 1) 245 #define STATE_DONE ((void *) 2) 246 #define STATE_ERROR ((void *) -1) 247 248 /* 249 * SSP State - Whether Enabled or Disabled 250 */ 251 #define SSP_DISABLED (0) 252 #define SSP_ENABLED (1) 253 254 /* 255 * SSP DMA State - Whether DMA Enabled or Disabled 256 */ 257 #define SSP_DMA_DISABLED (0) 258 #define SSP_DMA_ENABLED (1) 259 260 /* 261 * SSP Clock Defaults 262 */ 263 #define SSP_DEFAULT_CLKRATE 0x2 264 #define SSP_DEFAULT_PRESCALE 0x40 265 266 /* 267 * SSP Clock Parameter ranges 268 */ 269 #define CPSDVR_MIN 0x02 270 #define CPSDVR_MAX 0xFE 271 #define SCR_MIN 0x00 272 #define SCR_MAX 0xFF 273 274 /* 275 * SSP Interrupt related Macros 276 */ 277 #define DEFAULT_SSP_REG_IMSC 0x0UL 278 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 279 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 280 281 #define CLEAR_ALL_INTERRUPTS 0x3 282 283 #define SPI_POLLING_TIMEOUT 1000 284 285 /* 286 * The type of reading going on on this chip 287 */ 288 enum ssp_reading { 289 READING_NULL, 290 READING_U8, 291 READING_U16, 292 READING_U32 293 }; 294 295 /** 296 * The type of writing going on on this chip 297 */ 298 enum ssp_writing { 299 WRITING_NULL, 300 WRITING_U8, 301 WRITING_U16, 302 WRITING_U32 303 }; 304 305 /** 306 * struct vendor_data - vendor-specific config parameters 307 * for PL022 derivates 308 * @fifodepth: depth of FIFOs (both) 309 * @max_bpw: maximum number of bits per word 310 * @unidir: supports unidirection transfers 311 * @extended_cr: 32 bit wide control register 0 with extra 312 * features and extra features in CR1 as found in the ST variants 313 * @pl023: supports a subset of the ST extensions called "PL023" 314 */ 315 struct vendor_data { 316 int fifodepth; 317 int max_bpw; 318 bool unidir; 319 bool extended_cr; 320 bool pl023; 321 bool loopback; 322 }; 323 324 /** 325 * struct pl022 - This is the private SSP driver data structure 326 * @adev: AMBA device model hookup 327 * @vendor: vendor data for the IP block 328 * @phybase: the physical memory where the SSP device resides 329 * @virtbase: the virtual memory where the SSP is mapped 330 * @clk: outgoing clock "SPICLK" for the SPI bus 331 * @master: SPI framework hookup 332 * @master_info: controller-specific data from machine setup 333 * @workqueue: a workqueue on which any spi_message request is queued 334 * @pump_messages: work struct for scheduling work to the workqueue 335 * @queue_lock: spinlock to syncronise access to message queue 336 * @queue: message queue 337 * @busy: workqueue is busy 338 * @running: workqueue is running 339 * @pump_transfers: Tasklet used in Interrupt Transfer mode 340 * @cur_msg: Pointer to current spi_message being processed 341 * @cur_transfer: Pointer to current spi_transfer 342 * @cur_chip: pointer to current clients chip(assigned from controller_state) 343 * @next_msg_cs_active: the next message in the queue has been examined 344 * and it was found that it uses the same chip select as the previous 345 * message, so we left it active after the previous transfer, and it's 346 * active already. 347 * @tx: current position in TX buffer to be read 348 * @tx_end: end position in TX buffer to be read 349 * @rx: current position in RX buffer to be written 350 * @rx_end: end position in RX buffer to be written 351 * @read: the type of read currently going on 352 * @write: the type of write currently going on 353 * @exp_fifo_level: expected FIFO level 354 * @dma_rx_channel: optional channel for RX DMA 355 * @dma_tx_channel: optional channel for TX DMA 356 * @sgt_rx: scattertable for the RX transfer 357 * @sgt_tx: scattertable for the TX transfer 358 * @dummypage: a dummy page used for driving data on the bus with DMA 359 */ 360 struct pl022 { 361 struct amba_device *adev; 362 struct vendor_data *vendor; 363 resource_size_t phybase; 364 void __iomem *virtbase; 365 struct clk *clk; 366 struct spi_master *master; 367 struct pl022_ssp_controller *master_info; 368 /* Driver message queue */ 369 struct workqueue_struct *workqueue; 370 struct work_struct pump_messages; 371 spinlock_t queue_lock; 372 struct list_head queue; 373 bool busy; 374 bool running; 375 /* Message transfer pump */ 376 struct tasklet_struct pump_transfers; 377 struct spi_message *cur_msg; 378 struct spi_transfer *cur_transfer; 379 struct chip_data *cur_chip; 380 bool next_msg_cs_active; 381 void *tx; 382 void *tx_end; 383 void *rx; 384 void *rx_end; 385 enum ssp_reading read; 386 enum ssp_writing write; 387 u32 exp_fifo_level; 388 enum ssp_rx_level_trig rx_lev_trig; 389 enum ssp_tx_level_trig tx_lev_trig; 390 /* DMA settings */ 391 #ifdef CONFIG_DMA_ENGINE 392 struct dma_chan *dma_rx_channel; 393 struct dma_chan *dma_tx_channel; 394 struct sg_table sgt_rx; 395 struct sg_table sgt_tx; 396 char *dummypage; 397 #endif 398 }; 399 400 /** 401 * struct chip_data - To maintain runtime state of SSP for each client chip 402 * @cr0: Value of control register CR0 of SSP - on later ST variants this 403 * register is 32 bits wide rather than just 16 404 * @cr1: Value of control register CR1 of SSP 405 * @dmacr: Value of DMA control Register of SSP 406 * @cpsr: Value of Clock prescale register 407 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 408 * @enable_dma: Whether to enable DMA or not 409 * @read: function ptr to be used to read when doing xfer for this chip 410 * @write: function ptr to be used to write when doing xfer for this chip 411 * @cs_control: chip select callback provided by chip 412 * @xfer_type: polling/interrupt/DMA 413 * 414 * Runtime state of the SSP controller, maintained per chip, 415 * This would be set according to the current message that would be served 416 */ 417 struct chip_data { 418 u32 cr0; 419 u16 cr1; 420 u16 dmacr; 421 u16 cpsr; 422 u8 n_bytes; 423 bool enable_dma; 424 enum ssp_reading read; 425 enum ssp_writing write; 426 void (*cs_control) (u32 command); 427 int xfer_type; 428 }; 429 430 /** 431 * null_cs_control - Dummy chip select function 432 * @command: select/delect the chip 433 * 434 * If no chip select function is provided by client this is used as dummy 435 * chip select 436 */ 437 static void null_cs_control(u32 command) 438 { 439 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 440 } 441 442 /** 443 * giveback - current spi_message is over, schedule next message and call 444 * callback of this message. Assumes that caller already 445 * set message->status; dma and pio irqs are blocked 446 * @pl022: SSP driver private data structure 447 */ 448 static void giveback(struct pl022 *pl022) 449 { 450 struct spi_transfer *last_transfer; 451 unsigned long flags; 452 struct spi_message *msg; 453 pl022->next_msg_cs_active = false; 454 455 last_transfer = list_entry(pl022->cur_msg->transfers.prev, 456 struct spi_transfer, 457 transfer_list); 458 459 /* Delay if requested before any change in chip select */ 460 if (last_transfer->delay_usecs) 461 /* 462 * FIXME: This runs in interrupt context. 463 * Is this really smart? 464 */ 465 udelay(last_transfer->delay_usecs); 466 467 if (!last_transfer->cs_change) { 468 struct spi_message *next_msg; 469 470 /* 471 * cs_change was not set. We can keep the chip select 472 * enabled if there is message in the queue and it is 473 * for the same spi device. 474 * 475 * We cannot postpone this until pump_messages, because 476 * after calling msg->complete (below) the driver that 477 * sent the current message could be unloaded, which 478 * could invalidate the cs_control() callback... 479 */ 480 481 /* get a pointer to the next message, if any */ 482 spin_lock_irqsave(&pl022->queue_lock, flags); 483 if (list_empty(&pl022->queue)) 484 next_msg = NULL; 485 else 486 next_msg = list_entry(pl022->queue.next, 487 struct spi_message, queue); 488 spin_unlock_irqrestore(&pl022->queue_lock, flags); 489 490 /* 491 * see if the next and current messages point 492 * to the same spi device. 493 */ 494 if (next_msg && next_msg->spi != pl022->cur_msg->spi) 495 next_msg = NULL; 496 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 497 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 498 else 499 pl022->next_msg_cs_active = true; 500 } 501 502 spin_lock_irqsave(&pl022->queue_lock, flags); 503 msg = pl022->cur_msg; 504 pl022->cur_msg = NULL; 505 pl022->cur_transfer = NULL; 506 pl022->cur_chip = NULL; 507 queue_work(pl022->workqueue, &pl022->pump_messages); 508 spin_unlock_irqrestore(&pl022->queue_lock, flags); 509 510 msg->state = NULL; 511 if (msg->complete) 512 msg->complete(msg->context); 513 } 514 515 /** 516 * flush - flush the FIFO to reach a clean state 517 * @pl022: SSP driver private data structure 518 */ 519 static int flush(struct pl022 *pl022) 520 { 521 unsigned long limit = loops_per_jiffy << 1; 522 523 dev_dbg(&pl022->adev->dev, "flush\n"); 524 do { 525 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 526 readw(SSP_DR(pl022->virtbase)); 527 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 528 529 pl022->exp_fifo_level = 0; 530 531 return limit; 532 } 533 534 /** 535 * restore_state - Load configuration of current chip 536 * @pl022: SSP driver private data structure 537 */ 538 static void restore_state(struct pl022 *pl022) 539 { 540 struct chip_data *chip = pl022->cur_chip; 541 542 if (pl022->vendor->extended_cr) 543 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 544 else 545 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 546 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 547 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 548 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 549 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 550 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 551 } 552 553 /* 554 * Default SSP Register Values 555 */ 556 #define DEFAULT_SSP_REG_CR0 ( \ 557 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 558 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 559 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 560 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 561 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 562 ) 563 564 /* ST versions have slightly different bit layout */ 565 #define DEFAULT_SSP_REG_CR0_ST ( \ 566 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 567 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 568 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 569 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 570 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 571 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 572 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 573 ) 574 575 /* The PL023 version is slightly different again */ 576 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 577 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 578 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 579 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 580 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 581 ) 582 583 #define DEFAULT_SSP_REG_CR1 ( \ 584 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 585 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 586 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 587 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 588 ) 589 590 /* ST versions extend this register to use all 16 bits */ 591 #define DEFAULT_SSP_REG_CR1_ST ( \ 592 DEFAULT_SSP_REG_CR1 | \ 593 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 594 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 595 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 596 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 597 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 598 ) 599 600 /* 601 * The PL023 variant has further differences: no loopback mode, no microwire 602 * support, and a new clock feedback delay setting. 603 */ 604 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 605 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 606 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 607 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 608 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 609 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 610 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 611 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 612 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 613 ) 614 615 #define DEFAULT_SSP_REG_CPSR ( \ 616 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 617 ) 618 619 #define DEFAULT_SSP_REG_DMACR (\ 620 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 621 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 622 ) 623 624 /** 625 * load_ssp_default_config - Load default configuration for SSP 626 * @pl022: SSP driver private data structure 627 */ 628 static void load_ssp_default_config(struct pl022 *pl022) 629 { 630 if (pl022->vendor->pl023) { 631 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 632 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 633 } else if (pl022->vendor->extended_cr) { 634 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 635 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 636 } else { 637 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 638 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 639 } 640 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 641 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 642 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 643 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 644 } 645 646 /** 647 * This will write to TX and read from RX according to the parameters 648 * set in pl022. 649 */ 650 static void readwriter(struct pl022 *pl022) 651 { 652 653 /* 654 * The FIFO depth is different between primecell variants. 655 * I believe filling in too much in the FIFO might cause 656 * errons in 8bit wide transfers on ARM variants (just 8 words 657 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 658 * 659 * To prevent this issue, the TX FIFO is only filled to the 660 * unused RX FIFO fill length, regardless of what the TX 661 * FIFO status flag indicates. 662 */ 663 dev_dbg(&pl022->adev->dev, 664 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 665 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 666 667 /* Read as much as you can */ 668 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 669 && (pl022->rx < pl022->rx_end)) { 670 switch (pl022->read) { 671 case READING_NULL: 672 readw(SSP_DR(pl022->virtbase)); 673 break; 674 case READING_U8: 675 *(u8 *) (pl022->rx) = 676 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 677 break; 678 case READING_U16: 679 *(u16 *) (pl022->rx) = 680 (u16) readw(SSP_DR(pl022->virtbase)); 681 break; 682 case READING_U32: 683 *(u32 *) (pl022->rx) = 684 readl(SSP_DR(pl022->virtbase)); 685 break; 686 } 687 pl022->rx += (pl022->cur_chip->n_bytes); 688 pl022->exp_fifo_level--; 689 } 690 /* 691 * Write as much as possible up to the RX FIFO size 692 */ 693 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 694 && (pl022->tx < pl022->tx_end)) { 695 switch (pl022->write) { 696 case WRITING_NULL: 697 writew(0x0, SSP_DR(pl022->virtbase)); 698 break; 699 case WRITING_U8: 700 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 701 break; 702 case WRITING_U16: 703 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 704 break; 705 case WRITING_U32: 706 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 707 break; 708 } 709 pl022->tx += (pl022->cur_chip->n_bytes); 710 pl022->exp_fifo_level++; 711 /* 712 * This inner reader takes care of things appearing in the RX 713 * FIFO as we're transmitting. This will happen a lot since the 714 * clock starts running when you put things into the TX FIFO, 715 * and then things are continuously clocked into the RX FIFO. 716 */ 717 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 718 && (pl022->rx < pl022->rx_end)) { 719 switch (pl022->read) { 720 case READING_NULL: 721 readw(SSP_DR(pl022->virtbase)); 722 break; 723 case READING_U8: 724 *(u8 *) (pl022->rx) = 725 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 726 break; 727 case READING_U16: 728 *(u16 *) (pl022->rx) = 729 (u16) readw(SSP_DR(pl022->virtbase)); 730 break; 731 case READING_U32: 732 *(u32 *) (pl022->rx) = 733 readl(SSP_DR(pl022->virtbase)); 734 break; 735 } 736 pl022->rx += (pl022->cur_chip->n_bytes); 737 pl022->exp_fifo_level--; 738 } 739 } 740 /* 741 * When we exit here the TX FIFO should be full and the RX FIFO 742 * should be empty 743 */ 744 } 745 746 /** 747 * next_transfer - Move to the Next transfer in the current spi message 748 * @pl022: SSP driver private data structure 749 * 750 * This function moves though the linked list of spi transfers in the 751 * current spi message and returns with the state of current spi 752 * message i.e whether its last transfer is done(STATE_DONE) or 753 * Next transfer is ready(STATE_RUNNING) 754 */ 755 static void *next_transfer(struct pl022 *pl022) 756 { 757 struct spi_message *msg = pl022->cur_msg; 758 struct spi_transfer *trans = pl022->cur_transfer; 759 760 /* Move to next transfer */ 761 if (trans->transfer_list.next != &msg->transfers) { 762 pl022->cur_transfer = 763 list_entry(trans->transfer_list.next, 764 struct spi_transfer, transfer_list); 765 return STATE_RUNNING; 766 } 767 return STATE_DONE; 768 } 769 770 /* 771 * This DMA functionality is only compiled in if we have 772 * access to the generic DMA devices/DMA engine. 773 */ 774 #ifdef CONFIG_DMA_ENGINE 775 static void unmap_free_dma_scatter(struct pl022 *pl022) 776 { 777 /* Unmap and free the SG tables */ 778 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 779 pl022->sgt_tx.nents, DMA_TO_DEVICE); 780 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 781 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 782 sg_free_table(&pl022->sgt_rx); 783 sg_free_table(&pl022->sgt_tx); 784 } 785 786 static void dma_callback(void *data) 787 { 788 struct pl022 *pl022 = data; 789 struct spi_message *msg = pl022->cur_msg; 790 791 BUG_ON(!pl022->sgt_rx.sgl); 792 793 #ifdef VERBOSE_DEBUG 794 /* 795 * Optionally dump out buffers to inspect contents, this is 796 * good if you want to convince yourself that the loopback 797 * read/write contents are the same, when adopting to a new 798 * DMA engine. 799 */ 800 { 801 struct scatterlist *sg; 802 unsigned int i; 803 804 dma_sync_sg_for_cpu(&pl022->adev->dev, 805 pl022->sgt_rx.sgl, 806 pl022->sgt_rx.nents, 807 DMA_FROM_DEVICE); 808 809 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 810 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 811 print_hex_dump(KERN_ERR, "SPI RX: ", 812 DUMP_PREFIX_OFFSET, 813 16, 814 1, 815 sg_virt(sg), 816 sg_dma_len(sg), 817 1); 818 } 819 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 820 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 821 print_hex_dump(KERN_ERR, "SPI TX: ", 822 DUMP_PREFIX_OFFSET, 823 16, 824 1, 825 sg_virt(sg), 826 sg_dma_len(sg), 827 1); 828 } 829 } 830 #endif 831 832 unmap_free_dma_scatter(pl022); 833 834 /* Update total bytes transferred */ 835 msg->actual_length += pl022->cur_transfer->len; 836 if (pl022->cur_transfer->cs_change) 837 pl022->cur_chip-> 838 cs_control(SSP_CHIP_DESELECT); 839 840 /* Move to next transfer */ 841 msg->state = next_transfer(pl022); 842 tasklet_schedule(&pl022->pump_transfers); 843 } 844 845 static void setup_dma_scatter(struct pl022 *pl022, 846 void *buffer, 847 unsigned int length, 848 struct sg_table *sgtab) 849 { 850 struct scatterlist *sg; 851 int bytesleft = length; 852 void *bufp = buffer; 853 int mapbytes; 854 int i; 855 856 if (buffer) { 857 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 858 /* 859 * If there are less bytes left than what fits 860 * in the current page (plus page alignment offset) 861 * we just feed in this, else we stuff in as much 862 * as we can. 863 */ 864 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 865 mapbytes = bytesleft; 866 else 867 mapbytes = PAGE_SIZE - offset_in_page(bufp); 868 sg_set_page(sg, virt_to_page(bufp), 869 mapbytes, offset_in_page(bufp)); 870 bufp += mapbytes; 871 bytesleft -= mapbytes; 872 dev_dbg(&pl022->adev->dev, 873 "set RX/TX target page @ %p, %d bytes, %d left\n", 874 bufp, mapbytes, bytesleft); 875 } 876 } else { 877 /* Map the dummy buffer on every page */ 878 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 879 if (bytesleft < PAGE_SIZE) 880 mapbytes = bytesleft; 881 else 882 mapbytes = PAGE_SIZE; 883 sg_set_page(sg, virt_to_page(pl022->dummypage), 884 mapbytes, 0); 885 bytesleft -= mapbytes; 886 dev_dbg(&pl022->adev->dev, 887 "set RX/TX to dummy page %d bytes, %d left\n", 888 mapbytes, bytesleft); 889 890 } 891 } 892 BUG_ON(bytesleft); 893 } 894 895 /** 896 * configure_dma - configures the channels for the next transfer 897 * @pl022: SSP driver's private data structure 898 */ 899 static int configure_dma(struct pl022 *pl022) 900 { 901 struct dma_slave_config rx_conf = { 902 .src_addr = SSP_DR(pl022->phybase), 903 .direction = DMA_DEV_TO_MEM, 904 }; 905 struct dma_slave_config tx_conf = { 906 .dst_addr = SSP_DR(pl022->phybase), 907 .direction = DMA_MEM_TO_DEV, 908 }; 909 unsigned int pages; 910 int ret; 911 int rx_sglen, tx_sglen; 912 struct dma_chan *rxchan = pl022->dma_rx_channel; 913 struct dma_chan *txchan = pl022->dma_tx_channel; 914 struct dma_async_tx_descriptor *rxdesc; 915 struct dma_async_tx_descriptor *txdesc; 916 917 /* Check that the channels are available */ 918 if (!rxchan || !txchan) 919 return -ENODEV; 920 921 /* 922 * If supplied, the DMA burstsize should equal the FIFO trigger level. 923 * Notice that the DMA engine uses one-to-one mapping. Since we can 924 * not trigger on 2 elements this needs explicit mapping rather than 925 * calculation. 926 */ 927 switch (pl022->rx_lev_trig) { 928 case SSP_RX_1_OR_MORE_ELEM: 929 rx_conf.src_maxburst = 1; 930 break; 931 case SSP_RX_4_OR_MORE_ELEM: 932 rx_conf.src_maxburst = 4; 933 break; 934 case SSP_RX_8_OR_MORE_ELEM: 935 rx_conf.src_maxburst = 8; 936 break; 937 case SSP_RX_16_OR_MORE_ELEM: 938 rx_conf.src_maxburst = 16; 939 break; 940 case SSP_RX_32_OR_MORE_ELEM: 941 rx_conf.src_maxburst = 32; 942 break; 943 default: 944 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 945 break; 946 } 947 948 switch (pl022->tx_lev_trig) { 949 case SSP_TX_1_OR_MORE_EMPTY_LOC: 950 tx_conf.dst_maxburst = 1; 951 break; 952 case SSP_TX_4_OR_MORE_EMPTY_LOC: 953 tx_conf.dst_maxburst = 4; 954 break; 955 case SSP_TX_8_OR_MORE_EMPTY_LOC: 956 tx_conf.dst_maxburst = 8; 957 break; 958 case SSP_TX_16_OR_MORE_EMPTY_LOC: 959 tx_conf.dst_maxburst = 16; 960 break; 961 case SSP_TX_32_OR_MORE_EMPTY_LOC: 962 tx_conf.dst_maxburst = 32; 963 break; 964 default: 965 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 966 break; 967 } 968 969 switch (pl022->read) { 970 case READING_NULL: 971 /* Use the same as for writing */ 972 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 973 break; 974 case READING_U8: 975 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 976 break; 977 case READING_U16: 978 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 979 break; 980 case READING_U32: 981 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 982 break; 983 } 984 985 switch (pl022->write) { 986 case WRITING_NULL: 987 /* Use the same as for reading */ 988 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 989 break; 990 case WRITING_U8: 991 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 992 break; 993 case WRITING_U16: 994 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 995 break; 996 case WRITING_U32: 997 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 998 break; 999 } 1000 1001 /* SPI pecularity: we need to read and write the same width */ 1002 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1003 rx_conf.src_addr_width = tx_conf.dst_addr_width; 1004 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1005 tx_conf.dst_addr_width = rx_conf.src_addr_width; 1006 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1007 1008 dmaengine_slave_config(rxchan, &rx_conf); 1009 dmaengine_slave_config(txchan, &tx_conf); 1010 1011 /* Create sglists for the transfers */ 1012 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1013 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1014 1015 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1016 if (ret) 1017 goto err_alloc_rx_sg; 1018 1019 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1020 if (ret) 1021 goto err_alloc_tx_sg; 1022 1023 /* Fill in the scatterlists for the RX+TX buffers */ 1024 setup_dma_scatter(pl022, pl022->rx, 1025 pl022->cur_transfer->len, &pl022->sgt_rx); 1026 setup_dma_scatter(pl022, pl022->tx, 1027 pl022->cur_transfer->len, &pl022->sgt_tx); 1028 1029 /* Map DMA buffers */ 1030 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1031 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1032 if (!rx_sglen) 1033 goto err_rx_sgmap; 1034 1035 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1036 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1037 if (!tx_sglen) 1038 goto err_tx_sgmap; 1039 1040 /* Send both scatterlists */ 1041 rxdesc = rxchan->device->device_prep_slave_sg(rxchan, 1042 pl022->sgt_rx.sgl, 1043 rx_sglen, 1044 DMA_DEV_TO_MEM, 1045 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1046 if (!rxdesc) 1047 goto err_rxdesc; 1048 1049 txdesc = txchan->device->device_prep_slave_sg(txchan, 1050 pl022->sgt_tx.sgl, 1051 tx_sglen, 1052 DMA_MEM_TO_DEV, 1053 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1054 if (!txdesc) 1055 goto err_txdesc; 1056 1057 /* Put the callback on the RX transfer only, that should finish last */ 1058 rxdesc->callback = dma_callback; 1059 rxdesc->callback_param = pl022; 1060 1061 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1062 dmaengine_submit(rxdesc); 1063 dmaengine_submit(txdesc); 1064 dma_async_issue_pending(rxchan); 1065 dma_async_issue_pending(txchan); 1066 1067 return 0; 1068 1069 err_txdesc: 1070 dmaengine_terminate_all(txchan); 1071 err_rxdesc: 1072 dmaengine_terminate_all(rxchan); 1073 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1074 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1075 err_tx_sgmap: 1076 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1077 pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1078 err_rx_sgmap: 1079 sg_free_table(&pl022->sgt_tx); 1080 err_alloc_tx_sg: 1081 sg_free_table(&pl022->sgt_rx); 1082 err_alloc_rx_sg: 1083 return -ENOMEM; 1084 } 1085 1086 static int __init pl022_dma_probe(struct pl022 *pl022) 1087 { 1088 dma_cap_mask_t mask; 1089 1090 /* Try to acquire a generic DMA engine slave channel */ 1091 dma_cap_zero(mask); 1092 dma_cap_set(DMA_SLAVE, mask); 1093 /* 1094 * We need both RX and TX channels to do DMA, else do none 1095 * of them. 1096 */ 1097 pl022->dma_rx_channel = dma_request_channel(mask, 1098 pl022->master_info->dma_filter, 1099 pl022->master_info->dma_rx_param); 1100 if (!pl022->dma_rx_channel) { 1101 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1102 goto err_no_rxchan; 1103 } 1104 1105 pl022->dma_tx_channel = dma_request_channel(mask, 1106 pl022->master_info->dma_filter, 1107 pl022->master_info->dma_tx_param); 1108 if (!pl022->dma_tx_channel) { 1109 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1110 goto err_no_txchan; 1111 } 1112 1113 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1114 if (!pl022->dummypage) { 1115 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1116 goto err_no_dummypage; 1117 } 1118 1119 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1120 dma_chan_name(pl022->dma_rx_channel), 1121 dma_chan_name(pl022->dma_tx_channel)); 1122 1123 return 0; 1124 1125 err_no_dummypage: 1126 dma_release_channel(pl022->dma_tx_channel); 1127 err_no_txchan: 1128 dma_release_channel(pl022->dma_rx_channel); 1129 pl022->dma_rx_channel = NULL; 1130 err_no_rxchan: 1131 dev_err(&pl022->adev->dev, 1132 "Failed to work in dma mode, work without dma!\n"); 1133 return -ENODEV; 1134 } 1135 1136 static void terminate_dma(struct pl022 *pl022) 1137 { 1138 struct dma_chan *rxchan = pl022->dma_rx_channel; 1139 struct dma_chan *txchan = pl022->dma_tx_channel; 1140 1141 dmaengine_terminate_all(rxchan); 1142 dmaengine_terminate_all(txchan); 1143 unmap_free_dma_scatter(pl022); 1144 } 1145 1146 static void pl022_dma_remove(struct pl022 *pl022) 1147 { 1148 if (pl022->busy) 1149 terminate_dma(pl022); 1150 if (pl022->dma_tx_channel) 1151 dma_release_channel(pl022->dma_tx_channel); 1152 if (pl022->dma_rx_channel) 1153 dma_release_channel(pl022->dma_rx_channel); 1154 kfree(pl022->dummypage); 1155 } 1156 1157 #else 1158 static inline int configure_dma(struct pl022 *pl022) 1159 { 1160 return -ENODEV; 1161 } 1162 1163 static inline int pl022_dma_probe(struct pl022 *pl022) 1164 { 1165 return 0; 1166 } 1167 1168 static inline void pl022_dma_remove(struct pl022 *pl022) 1169 { 1170 } 1171 #endif 1172 1173 /** 1174 * pl022_interrupt_handler - Interrupt handler for SSP controller 1175 * 1176 * This function handles interrupts generated for an interrupt based transfer. 1177 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1178 * current message's state as STATE_ERROR and schedule the tasklet 1179 * pump_transfers which will do the postprocessing of the current message by 1180 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1181 * more data, and writes data in TX FIFO till it is not full. If we complete 1182 * the transfer we move to the next transfer and schedule the tasklet. 1183 */ 1184 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1185 { 1186 struct pl022 *pl022 = dev_id; 1187 struct spi_message *msg = pl022->cur_msg; 1188 u16 irq_status = 0; 1189 u16 flag = 0; 1190 1191 if (unlikely(!msg)) { 1192 dev_err(&pl022->adev->dev, 1193 "bad message state in interrupt handler"); 1194 /* Never fail */ 1195 return IRQ_HANDLED; 1196 } 1197 1198 /* Read the Interrupt Status Register */ 1199 irq_status = readw(SSP_MIS(pl022->virtbase)); 1200 1201 if (unlikely(!irq_status)) 1202 return IRQ_NONE; 1203 1204 /* 1205 * This handles the FIFO interrupts, the timeout 1206 * interrupts are flatly ignored, they cannot be 1207 * trusted. 1208 */ 1209 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1210 /* 1211 * Overrun interrupt - bail out since our Data has been 1212 * corrupted 1213 */ 1214 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1215 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1216 dev_err(&pl022->adev->dev, 1217 "RXFIFO is full\n"); 1218 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1219 dev_err(&pl022->adev->dev, 1220 "TXFIFO is full\n"); 1221 1222 /* 1223 * Disable and clear interrupts, disable SSP, 1224 * mark message with bad status so it can be 1225 * retried. 1226 */ 1227 writew(DISABLE_ALL_INTERRUPTS, 1228 SSP_IMSC(pl022->virtbase)); 1229 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1230 writew((readw(SSP_CR1(pl022->virtbase)) & 1231 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1232 msg->state = STATE_ERROR; 1233 1234 /* Schedule message queue handler */ 1235 tasklet_schedule(&pl022->pump_transfers); 1236 return IRQ_HANDLED; 1237 } 1238 1239 readwriter(pl022); 1240 1241 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1242 flag = 1; 1243 /* Disable Transmit interrupt, enable receive interrupt */ 1244 writew((readw(SSP_IMSC(pl022->virtbase)) & 1245 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1246 SSP_IMSC(pl022->virtbase)); 1247 } 1248 1249 /* 1250 * Since all transactions must write as much as shall be read, 1251 * we can conclude the entire transaction once RX is complete. 1252 * At this point, all TX will always be finished. 1253 */ 1254 if (pl022->rx >= pl022->rx_end) { 1255 writew(DISABLE_ALL_INTERRUPTS, 1256 SSP_IMSC(pl022->virtbase)); 1257 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1258 if (unlikely(pl022->rx > pl022->rx_end)) { 1259 dev_warn(&pl022->adev->dev, "read %u surplus " 1260 "bytes (did you request an odd " 1261 "number of bytes on a 16bit bus?)\n", 1262 (u32) (pl022->rx - pl022->rx_end)); 1263 } 1264 /* Update total bytes transferred */ 1265 msg->actual_length += pl022->cur_transfer->len; 1266 if (pl022->cur_transfer->cs_change) 1267 pl022->cur_chip-> 1268 cs_control(SSP_CHIP_DESELECT); 1269 /* Move to next transfer */ 1270 msg->state = next_transfer(pl022); 1271 tasklet_schedule(&pl022->pump_transfers); 1272 return IRQ_HANDLED; 1273 } 1274 1275 return IRQ_HANDLED; 1276 } 1277 1278 /** 1279 * This sets up the pointers to memory for the next message to 1280 * send out on the SPI bus. 1281 */ 1282 static int set_up_next_transfer(struct pl022 *pl022, 1283 struct spi_transfer *transfer) 1284 { 1285 int residue; 1286 1287 /* Sanity check the message for this bus width */ 1288 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1289 if (unlikely(residue != 0)) { 1290 dev_err(&pl022->adev->dev, 1291 "message of %u bytes to transmit but the current " 1292 "chip bus has a data width of %u bytes!\n", 1293 pl022->cur_transfer->len, 1294 pl022->cur_chip->n_bytes); 1295 dev_err(&pl022->adev->dev, "skipping this message\n"); 1296 return -EIO; 1297 } 1298 pl022->tx = (void *)transfer->tx_buf; 1299 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1300 pl022->rx = (void *)transfer->rx_buf; 1301 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1302 pl022->write = 1303 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1304 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1305 return 0; 1306 } 1307 1308 /** 1309 * pump_transfers - Tasklet function which schedules next transfer 1310 * when running in interrupt or DMA transfer mode. 1311 * @data: SSP driver private data structure 1312 * 1313 */ 1314 static void pump_transfers(unsigned long data) 1315 { 1316 struct pl022 *pl022 = (struct pl022 *) data; 1317 struct spi_message *message = NULL; 1318 struct spi_transfer *transfer = NULL; 1319 struct spi_transfer *previous = NULL; 1320 1321 /* Get current state information */ 1322 message = pl022->cur_msg; 1323 transfer = pl022->cur_transfer; 1324 1325 /* Handle for abort */ 1326 if (message->state == STATE_ERROR) { 1327 message->status = -EIO; 1328 giveback(pl022); 1329 return; 1330 } 1331 1332 /* Handle end of message */ 1333 if (message->state == STATE_DONE) { 1334 message->status = 0; 1335 giveback(pl022); 1336 return; 1337 } 1338 1339 /* Delay if requested at end of transfer before CS change */ 1340 if (message->state == STATE_RUNNING) { 1341 previous = list_entry(transfer->transfer_list.prev, 1342 struct spi_transfer, 1343 transfer_list); 1344 if (previous->delay_usecs) 1345 /* 1346 * FIXME: This runs in interrupt context. 1347 * Is this really smart? 1348 */ 1349 udelay(previous->delay_usecs); 1350 1351 /* Reselect chip select only if cs_change was requested */ 1352 if (previous->cs_change) 1353 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1354 } else { 1355 /* STATE_START */ 1356 message->state = STATE_RUNNING; 1357 } 1358 1359 if (set_up_next_transfer(pl022, transfer)) { 1360 message->state = STATE_ERROR; 1361 message->status = -EIO; 1362 giveback(pl022); 1363 return; 1364 } 1365 /* Flush the FIFOs and let's go! */ 1366 flush(pl022); 1367 1368 if (pl022->cur_chip->enable_dma) { 1369 if (configure_dma(pl022)) { 1370 dev_dbg(&pl022->adev->dev, 1371 "configuration of DMA failed, fall back to interrupt mode\n"); 1372 goto err_config_dma; 1373 } 1374 return; 1375 } 1376 1377 err_config_dma: 1378 /* enable all interrupts except RX */ 1379 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1380 } 1381 1382 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1383 { 1384 /* 1385 * Default is to enable all interrupts except RX - 1386 * this will be enabled once TX is complete 1387 */ 1388 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1389 1390 /* Enable target chip, if not already active */ 1391 if (!pl022->next_msg_cs_active) 1392 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1393 1394 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1395 /* Error path */ 1396 pl022->cur_msg->state = STATE_ERROR; 1397 pl022->cur_msg->status = -EIO; 1398 giveback(pl022); 1399 return; 1400 } 1401 /* If we're using DMA, set up DMA here */ 1402 if (pl022->cur_chip->enable_dma) { 1403 /* Configure DMA transfer */ 1404 if (configure_dma(pl022)) { 1405 dev_dbg(&pl022->adev->dev, 1406 "configuration of DMA failed, fall back to interrupt mode\n"); 1407 goto err_config_dma; 1408 } 1409 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1410 irqflags = DISABLE_ALL_INTERRUPTS; 1411 } 1412 err_config_dma: 1413 /* Enable SSP, turn on interrupts */ 1414 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1415 SSP_CR1(pl022->virtbase)); 1416 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1417 } 1418 1419 static void do_polling_transfer(struct pl022 *pl022) 1420 { 1421 struct spi_message *message = NULL; 1422 struct spi_transfer *transfer = NULL; 1423 struct spi_transfer *previous = NULL; 1424 struct chip_data *chip; 1425 unsigned long time, timeout; 1426 1427 chip = pl022->cur_chip; 1428 message = pl022->cur_msg; 1429 1430 while (message->state != STATE_DONE) { 1431 /* Handle for abort */ 1432 if (message->state == STATE_ERROR) 1433 break; 1434 transfer = pl022->cur_transfer; 1435 1436 /* Delay if requested at end of transfer */ 1437 if (message->state == STATE_RUNNING) { 1438 previous = 1439 list_entry(transfer->transfer_list.prev, 1440 struct spi_transfer, transfer_list); 1441 if (previous->delay_usecs) 1442 udelay(previous->delay_usecs); 1443 if (previous->cs_change) 1444 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1445 } else { 1446 /* STATE_START */ 1447 message->state = STATE_RUNNING; 1448 if (!pl022->next_msg_cs_active) 1449 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1450 } 1451 1452 /* Configuration Changing Per Transfer */ 1453 if (set_up_next_transfer(pl022, transfer)) { 1454 /* Error path */ 1455 message->state = STATE_ERROR; 1456 break; 1457 } 1458 /* Flush FIFOs and enable SSP */ 1459 flush(pl022); 1460 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1461 SSP_CR1(pl022->virtbase)); 1462 1463 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1464 1465 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1466 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1467 time = jiffies; 1468 readwriter(pl022); 1469 if (time_after(time, timeout)) { 1470 dev_warn(&pl022->adev->dev, 1471 "%s: timeout!\n", __func__); 1472 message->state = STATE_ERROR; 1473 goto out; 1474 } 1475 cpu_relax(); 1476 } 1477 1478 /* Update total byte transferred */ 1479 message->actual_length += pl022->cur_transfer->len; 1480 if (pl022->cur_transfer->cs_change) 1481 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 1482 /* Move to next transfer */ 1483 message->state = next_transfer(pl022); 1484 } 1485 out: 1486 /* Handle end of message */ 1487 if (message->state == STATE_DONE) 1488 message->status = 0; 1489 else 1490 message->status = -EIO; 1491 1492 giveback(pl022); 1493 return; 1494 } 1495 1496 /** 1497 * pump_messages - Workqueue function which processes spi message queue 1498 * @data: pointer to private data of SSP driver 1499 * 1500 * This function checks if there is any spi message in the queue that 1501 * needs processing and delegate control to appropriate function 1502 * do_polling_transfer()/do_interrupt_dma_transfer() 1503 * based on the kind of the transfer 1504 * 1505 */ 1506 static void pump_messages(struct work_struct *work) 1507 { 1508 struct pl022 *pl022 = 1509 container_of(work, struct pl022, pump_messages); 1510 unsigned long flags; 1511 bool was_busy = false; 1512 1513 /* Lock queue and check for queue work */ 1514 spin_lock_irqsave(&pl022->queue_lock, flags); 1515 if (list_empty(&pl022->queue) || !pl022->running) { 1516 if (pl022->busy) { 1517 /* nothing more to do - disable spi/ssp and power off */ 1518 writew((readw(SSP_CR1(pl022->virtbase)) & 1519 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1520 1521 if (pl022->master_info->autosuspend_delay > 0) { 1522 pm_runtime_mark_last_busy(&pl022->adev->dev); 1523 pm_runtime_put_autosuspend(&pl022->adev->dev); 1524 } else { 1525 pm_runtime_put(&pl022->adev->dev); 1526 } 1527 } 1528 pl022->busy = false; 1529 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1530 return; 1531 } 1532 1533 /* Make sure we are not already running a message */ 1534 if (pl022->cur_msg) { 1535 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1536 return; 1537 } 1538 /* Extract head of queue */ 1539 pl022->cur_msg = 1540 list_entry(pl022->queue.next, struct spi_message, queue); 1541 1542 list_del_init(&pl022->cur_msg->queue); 1543 if (pl022->busy) 1544 was_busy = true; 1545 else 1546 pl022->busy = true; 1547 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1548 1549 /* Initial message state */ 1550 pl022->cur_msg->state = STATE_START; 1551 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, 1552 struct spi_transfer, transfer_list); 1553 1554 /* Setup the SPI using the per chip configuration */ 1555 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); 1556 if (!was_busy) 1557 /* 1558 * We enable the core voltage and clocks here, then the clocks 1559 * and core will be disabled when this workqueue is run again 1560 * and there is no more work to be done. 1561 */ 1562 pm_runtime_get_sync(&pl022->adev->dev); 1563 1564 restore_state(pl022); 1565 flush(pl022); 1566 1567 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1568 do_polling_transfer(pl022); 1569 else 1570 do_interrupt_dma_transfer(pl022); 1571 } 1572 1573 static int __init init_queue(struct pl022 *pl022) 1574 { 1575 INIT_LIST_HEAD(&pl022->queue); 1576 spin_lock_init(&pl022->queue_lock); 1577 1578 pl022->running = false; 1579 pl022->busy = false; 1580 1581 tasklet_init(&pl022->pump_transfers, pump_transfers, 1582 (unsigned long)pl022); 1583 1584 INIT_WORK(&pl022->pump_messages, pump_messages); 1585 pl022->workqueue = create_singlethread_workqueue( 1586 dev_name(pl022->master->dev.parent)); 1587 if (pl022->workqueue == NULL) 1588 return -EBUSY; 1589 1590 return 0; 1591 } 1592 1593 static int start_queue(struct pl022 *pl022) 1594 { 1595 unsigned long flags; 1596 1597 spin_lock_irqsave(&pl022->queue_lock, flags); 1598 1599 if (pl022->running || pl022->busy) { 1600 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1601 return -EBUSY; 1602 } 1603 1604 pl022->running = true; 1605 pl022->cur_msg = NULL; 1606 pl022->cur_transfer = NULL; 1607 pl022->cur_chip = NULL; 1608 pl022->next_msg_cs_active = false; 1609 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1610 1611 queue_work(pl022->workqueue, &pl022->pump_messages); 1612 1613 return 0; 1614 } 1615 1616 static int stop_queue(struct pl022 *pl022) 1617 { 1618 unsigned long flags; 1619 unsigned limit = 500; 1620 int status = 0; 1621 1622 spin_lock_irqsave(&pl022->queue_lock, flags); 1623 1624 /* This is a bit lame, but is optimized for the common execution path. 1625 * A wait_queue on the pl022->busy could be used, but then the common 1626 * execution path (pump_messages) would be required to call wake_up or 1627 * friends on every SPI message. Do this instead */ 1628 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { 1629 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1630 msleep(10); 1631 spin_lock_irqsave(&pl022->queue_lock, flags); 1632 } 1633 1634 if (!list_empty(&pl022->queue) || pl022->busy) 1635 status = -EBUSY; 1636 else 1637 pl022->running = false; 1638 1639 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1640 1641 return status; 1642 } 1643 1644 static int destroy_queue(struct pl022 *pl022) 1645 { 1646 int status; 1647 1648 status = stop_queue(pl022); 1649 /* we are unloading the module or failing to load (only two calls 1650 * to this routine), and neither call can handle a return value. 1651 * However, destroy_workqueue calls flush_workqueue, and that will 1652 * block until all work is done. If the reason that stop_queue 1653 * timed out is that the work will never finish, then it does no 1654 * good to call destroy_workqueue, so return anyway. */ 1655 if (status != 0) 1656 return status; 1657 1658 destroy_workqueue(pl022->workqueue); 1659 1660 return 0; 1661 } 1662 1663 static int verify_controller_parameters(struct pl022 *pl022, 1664 struct pl022_config_chip const *chip_info) 1665 { 1666 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1667 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1668 dev_err(&pl022->adev->dev, 1669 "interface is configured incorrectly\n"); 1670 return -EINVAL; 1671 } 1672 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1673 (!pl022->vendor->unidir)) { 1674 dev_err(&pl022->adev->dev, 1675 "unidirectional mode not supported in this " 1676 "hardware version\n"); 1677 return -EINVAL; 1678 } 1679 if ((chip_info->hierarchy != SSP_MASTER) 1680 && (chip_info->hierarchy != SSP_SLAVE)) { 1681 dev_err(&pl022->adev->dev, 1682 "hierarchy is configured incorrectly\n"); 1683 return -EINVAL; 1684 } 1685 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1686 && (chip_info->com_mode != DMA_TRANSFER) 1687 && (chip_info->com_mode != POLLING_TRANSFER)) { 1688 dev_err(&pl022->adev->dev, 1689 "Communication mode is configured incorrectly\n"); 1690 return -EINVAL; 1691 } 1692 switch (chip_info->rx_lev_trig) { 1693 case SSP_RX_1_OR_MORE_ELEM: 1694 case SSP_RX_4_OR_MORE_ELEM: 1695 case SSP_RX_8_OR_MORE_ELEM: 1696 /* These are always OK, all variants can handle this */ 1697 break; 1698 case SSP_RX_16_OR_MORE_ELEM: 1699 if (pl022->vendor->fifodepth < 16) { 1700 dev_err(&pl022->adev->dev, 1701 "RX FIFO Trigger Level is configured incorrectly\n"); 1702 return -EINVAL; 1703 } 1704 break; 1705 case SSP_RX_32_OR_MORE_ELEM: 1706 if (pl022->vendor->fifodepth < 32) { 1707 dev_err(&pl022->adev->dev, 1708 "RX FIFO Trigger Level is configured incorrectly\n"); 1709 return -EINVAL; 1710 } 1711 break; 1712 default: 1713 dev_err(&pl022->adev->dev, 1714 "RX FIFO Trigger Level is configured incorrectly\n"); 1715 return -EINVAL; 1716 break; 1717 } 1718 switch (chip_info->tx_lev_trig) { 1719 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1720 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1721 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1722 /* These are always OK, all variants can handle this */ 1723 break; 1724 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1725 if (pl022->vendor->fifodepth < 16) { 1726 dev_err(&pl022->adev->dev, 1727 "TX FIFO Trigger Level is configured incorrectly\n"); 1728 return -EINVAL; 1729 } 1730 break; 1731 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1732 if (pl022->vendor->fifodepth < 32) { 1733 dev_err(&pl022->adev->dev, 1734 "TX FIFO Trigger Level is configured incorrectly\n"); 1735 return -EINVAL; 1736 } 1737 break; 1738 default: 1739 dev_err(&pl022->adev->dev, 1740 "TX FIFO Trigger Level is configured incorrectly\n"); 1741 return -EINVAL; 1742 break; 1743 } 1744 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1745 if ((chip_info->ctrl_len < SSP_BITS_4) 1746 || (chip_info->ctrl_len > SSP_BITS_32)) { 1747 dev_err(&pl022->adev->dev, 1748 "CTRL LEN is configured incorrectly\n"); 1749 return -EINVAL; 1750 } 1751 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1752 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1753 dev_err(&pl022->adev->dev, 1754 "Wait State is configured incorrectly\n"); 1755 return -EINVAL; 1756 } 1757 /* Half duplex is only available in the ST Micro version */ 1758 if (pl022->vendor->extended_cr) { 1759 if ((chip_info->duplex != 1760 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1761 && (chip_info->duplex != 1762 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1763 dev_err(&pl022->adev->dev, 1764 "Microwire duplex mode is configured incorrectly\n"); 1765 return -EINVAL; 1766 } 1767 } else { 1768 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1769 dev_err(&pl022->adev->dev, 1770 "Microwire half duplex mode requested," 1771 " but this is only available in the" 1772 " ST version of PL022\n"); 1773 return -EINVAL; 1774 } 1775 } 1776 return 0; 1777 } 1778 1779 /** 1780 * pl022_transfer - transfer function registered to SPI master framework 1781 * @spi: spi device which is requesting transfer 1782 * @msg: spi message which is to handled is queued to driver queue 1783 * 1784 * This function is registered to the SPI framework for this SPI master 1785 * controller. It will queue the spi_message in the queue of driver if 1786 * the queue is not stopped and return. 1787 */ 1788 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) 1789 { 1790 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1791 unsigned long flags; 1792 1793 spin_lock_irqsave(&pl022->queue_lock, flags); 1794 1795 if (!pl022->running) { 1796 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1797 return -ESHUTDOWN; 1798 } 1799 msg->actual_length = 0; 1800 msg->status = -EINPROGRESS; 1801 msg->state = STATE_START; 1802 1803 list_add_tail(&msg->queue, &pl022->queue); 1804 if (pl022->running && !pl022->busy) 1805 queue_work(pl022->workqueue, &pl022->pump_messages); 1806 1807 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1808 return 0; 1809 } 1810 1811 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1812 { 1813 return rate / (cpsdvsr * (1 + scr)); 1814 } 1815 1816 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1817 ssp_clock_params * clk_freq) 1818 { 1819 /* Lets calculate the frequency parameters */ 1820 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1821 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1822 best_scr = 0, tmp, found = 0; 1823 1824 rate = clk_get_rate(pl022->clk); 1825 /* cpsdvscr = 2 & scr 0 */ 1826 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1827 /* cpsdvsr = 254 & scr = 255 */ 1828 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1829 1830 if (!((freq <= max_tclk) && (freq >= min_tclk))) { 1831 dev_err(&pl022->adev->dev, 1832 "controller data is incorrect: out of range frequency"); 1833 return -EINVAL; 1834 } 1835 1836 /* 1837 * best_freq will give closest possible available rate (<= requested 1838 * freq) for all values of scr & cpsdvsr. 1839 */ 1840 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1841 while (scr <= SCR_MAX) { 1842 tmp = spi_rate(rate, cpsdvsr, scr); 1843 1844 if (tmp > freq) 1845 scr++; 1846 /* 1847 * If found exact value, update and break. 1848 * If found more closer value, update and continue. 1849 */ 1850 else if ((tmp == freq) || (tmp > best_freq)) { 1851 best_freq = tmp; 1852 best_cpsdvsr = cpsdvsr; 1853 best_scr = scr; 1854 1855 if (tmp == freq) 1856 break; 1857 } 1858 scr++; 1859 } 1860 cpsdvsr += 2; 1861 scr = SCR_MIN; 1862 } 1863 1864 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1865 clk_freq->scr = (u8) (best_scr & 0xFF); 1866 dev_dbg(&pl022->adev->dev, 1867 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1868 freq, best_freq); 1869 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1870 clk_freq->cpsdvsr, clk_freq->scr); 1871 1872 return 0; 1873 } 1874 1875 /* 1876 * A piece of default chip info unless the platform 1877 * supplies it. 1878 */ 1879 static const struct pl022_config_chip pl022_default_chip_info = { 1880 .com_mode = POLLING_TRANSFER, 1881 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1882 .hierarchy = SSP_SLAVE, 1883 .slave_tx_disable = DO_NOT_DRIVE_TX, 1884 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1885 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1886 .ctrl_len = SSP_BITS_8, 1887 .wait_state = SSP_MWIRE_WAIT_ZERO, 1888 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1889 .cs_control = null_cs_control, 1890 }; 1891 1892 /** 1893 * pl022_setup - setup function registered to SPI master framework 1894 * @spi: spi device which is requesting setup 1895 * 1896 * This function is registered to the SPI framework for this SPI master 1897 * controller. If it is the first time when setup is called by this device, 1898 * this function will initialize the runtime state for this chip and save 1899 * the same in the device structure. Else it will update the runtime info 1900 * with the updated chip info. Nothing is really being written to the 1901 * controller hardware here, that is not done until the actual transfer 1902 * commence. 1903 */ 1904 static int pl022_setup(struct spi_device *spi) 1905 { 1906 struct pl022_config_chip const *chip_info; 1907 struct chip_data *chip; 1908 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1909 int status = 0; 1910 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1911 unsigned int bits = spi->bits_per_word; 1912 u32 tmp; 1913 1914 if (!spi->max_speed_hz) 1915 return -EINVAL; 1916 1917 /* Get controller_state if one is supplied */ 1918 chip = spi_get_ctldata(spi); 1919 1920 if (chip == NULL) { 1921 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1922 if (!chip) { 1923 dev_err(&spi->dev, 1924 "cannot allocate controller state\n"); 1925 return -ENOMEM; 1926 } 1927 dev_dbg(&spi->dev, 1928 "allocated memory for controller's runtime state\n"); 1929 } 1930 1931 /* Get controller data if one is supplied */ 1932 chip_info = spi->controller_data; 1933 1934 if (chip_info == NULL) { 1935 chip_info = &pl022_default_chip_info; 1936 /* spi_board_info.controller_data not is supplied */ 1937 dev_dbg(&spi->dev, 1938 "using default controller_data settings\n"); 1939 } else 1940 dev_dbg(&spi->dev, 1941 "using user supplied controller_data settings\n"); 1942 1943 /* 1944 * We can override with custom divisors, else we use the board 1945 * frequency setting 1946 */ 1947 if ((0 == chip_info->clk_freq.cpsdvsr) 1948 && (0 == chip_info->clk_freq.scr)) { 1949 status = calculate_effective_freq(pl022, 1950 spi->max_speed_hz, 1951 &clk_freq); 1952 if (status < 0) 1953 goto err_config_params; 1954 } else { 1955 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1956 if ((clk_freq.cpsdvsr % 2) != 0) 1957 clk_freq.cpsdvsr = 1958 clk_freq.cpsdvsr - 1; 1959 } 1960 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1961 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1962 status = -EINVAL; 1963 dev_err(&spi->dev, 1964 "cpsdvsr is configured incorrectly\n"); 1965 goto err_config_params; 1966 } 1967 1968 status = verify_controller_parameters(pl022, chip_info); 1969 if (status) { 1970 dev_err(&spi->dev, "controller data is incorrect"); 1971 goto err_config_params; 1972 } 1973 1974 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1975 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1976 1977 /* Now set controller state based on controller data */ 1978 chip->xfer_type = chip_info->com_mode; 1979 if (!chip_info->cs_control) { 1980 chip->cs_control = null_cs_control; 1981 dev_warn(&spi->dev, 1982 "chip select function is NULL for this chip\n"); 1983 } else 1984 chip->cs_control = chip_info->cs_control; 1985 1986 if (bits <= 3) { 1987 /* PL022 doesn't support less than 4-bits */ 1988 status = -ENOTSUPP; 1989 goto err_config_params; 1990 } else if (bits <= 8) { 1991 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1992 chip->n_bytes = 1; 1993 chip->read = READING_U8; 1994 chip->write = WRITING_U8; 1995 } else if (bits <= 16) { 1996 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1997 chip->n_bytes = 2; 1998 chip->read = READING_U16; 1999 chip->write = WRITING_U16; 2000 } else { 2001 if (pl022->vendor->max_bpw >= 32) { 2002 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 2003 chip->n_bytes = 4; 2004 chip->read = READING_U32; 2005 chip->write = WRITING_U32; 2006 } else { 2007 dev_err(&spi->dev, 2008 "illegal data size for this controller!\n"); 2009 dev_err(&spi->dev, 2010 "a standard pl022 can only handle " 2011 "1 <= n <= 16 bit words\n"); 2012 status = -ENOTSUPP; 2013 goto err_config_params; 2014 } 2015 } 2016 2017 /* Now Initialize all register settings required for this chip */ 2018 chip->cr0 = 0; 2019 chip->cr1 = 0; 2020 chip->dmacr = 0; 2021 chip->cpsr = 0; 2022 if ((chip_info->com_mode == DMA_TRANSFER) 2023 && ((pl022->master_info)->enable_dma)) { 2024 chip->enable_dma = true; 2025 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 2026 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2027 SSP_DMACR_MASK_RXDMAE, 0); 2028 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2029 SSP_DMACR_MASK_TXDMAE, 1); 2030 } else { 2031 chip->enable_dma = false; 2032 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 2033 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2034 SSP_DMACR_MASK_RXDMAE, 0); 2035 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2036 SSP_DMACR_MASK_TXDMAE, 1); 2037 } 2038 2039 chip->cpsr = clk_freq.cpsdvsr; 2040 2041 /* Special setup for the ST micro extended control registers */ 2042 if (pl022->vendor->extended_cr) { 2043 u32 etx; 2044 2045 if (pl022->vendor->pl023) { 2046 /* These bits are only in the PL023 */ 2047 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 2048 SSP_CR1_MASK_FBCLKDEL_ST, 13); 2049 } else { 2050 /* These bits are in the PL022 but not PL023 */ 2051 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 2052 SSP_CR0_MASK_HALFDUP_ST, 5); 2053 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 2054 SSP_CR0_MASK_CSS_ST, 16); 2055 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2056 SSP_CR0_MASK_FRF_ST, 21); 2057 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 2058 SSP_CR1_MASK_MWAIT_ST, 6); 2059 } 2060 SSP_WRITE_BITS(chip->cr0, bits - 1, 2061 SSP_CR0_MASK_DSS_ST, 0); 2062 2063 if (spi->mode & SPI_LSB_FIRST) { 2064 tmp = SSP_RX_LSB; 2065 etx = SSP_TX_LSB; 2066 } else { 2067 tmp = SSP_RX_MSB; 2068 etx = SSP_TX_MSB; 2069 } 2070 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2071 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2072 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2073 SSP_CR1_MASK_RXIFLSEL_ST, 7); 2074 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2075 SSP_CR1_MASK_TXIFLSEL_ST, 10); 2076 } else { 2077 SSP_WRITE_BITS(chip->cr0, bits - 1, 2078 SSP_CR0_MASK_DSS, 0); 2079 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2080 SSP_CR0_MASK_FRF, 4); 2081 } 2082 2083 /* Stuff that is common for all versions */ 2084 if (spi->mode & SPI_CPOL) 2085 tmp = SSP_CLK_POL_IDLE_HIGH; 2086 else 2087 tmp = SSP_CLK_POL_IDLE_LOW; 2088 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2089 2090 if (spi->mode & SPI_CPHA) 2091 tmp = SSP_CLK_SECOND_EDGE; 2092 else 2093 tmp = SSP_CLK_FIRST_EDGE; 2094 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2095 2096 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2097 /* Loopback is available on all versions except PL023 */ 2098 if (pl022->vendor->loopback) { 2099 if (spi->mode & SPI_LOOP) 2100 tmp = LOOPBACK_ENABLED; 2101 else 2102 tmp = LOOPBACK_DISABLED; 2103 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2104 } 2105 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2106 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2107 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2108 3); 2109 2110 /* Save controller_state */ 2111 spi_set_ctldata(spi, chip); 2112 return status; 2113 err_config_params: 2114 spi_set_ctldata(spi, NULL); 2115 kfree(chip); 2116 return status; 2117 } 2118 2119 /** 2120 * pl022_cleanup - cleanup function registered to SPI master framework 2121 * @spi: spi device which is requesting cleanup 2122 * 2123 * This function is registered to the SPI framework for this SPI master 2124 * controller. It will free the runtime state of chip. 2125 */ 2126 static void pl022_cleanup(struct spi_device *spi) 2127 { 2128 struct chip_data *chip = spi_get_ctldata(spi); 2129 2130 spi_set_ctldata(spi, NULL); 2131 kfree(chip); 2132 } 2133 2134 static int __devinit 2135 pl022_probe(struct amba_device *adev, const struct amba_id *id) 2136 { 2137 struct device *dev = &adev->dev; 2138 struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2139 struct spi_master *master; 2140 struct pl022 *pl022 = NULL; /*Data for this driver */ 2141 int status = 0; 2142 2143 dev_info(&adev->dev, 2144 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2145 if (platform_info == NULL) { 2146 dev_err(&adev->dev, "probe - no platform data supplied\n"); 2147 status = -ENODEV; 2148 goto err_no_pdata; 2149 } 2150 2151 /* Allocate master with space for data */ 2152 master = spi_alloc_master(dev, sizeof(struct pl022)); 2153 if (master == NULL) { 2154 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2155 status = -ENOMEM; 2156 goto err_no_master; 2157 } 2158 2159 pl022 = spi_master_get_devdata(master); 2160 pl022->master = master; 2161 pl022->master_info = platform_info; 2162 pl022->adev = adev; 2163 pl022->vendor = id->data; 2164 2165 /* 2166 * Bus Number Which has been Assigned to this SSP controller 2167 * on this board 2168 */ 2169 master->bus_num = platform_info->bus_id; 2170 master->num_chipselect = platform_info->num_chipselect; 2171 master->cleanup = pl022_cleanup; 2172 master->setup = pl022_setup; 2173 master->transfer = pl022_transfer; 2174 2175 /* 2176 * Supports mode 0-3, loopback, and active low CS. Transfers are 2177 * always MS bit first on the original pl022. 2178 */ 2179 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2180 if (pl022->vendor->extended_cr) 2181 master->mode_bits |= SPI_LSB_FIRST; 2182 2183 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2184 2185 status = amba_request_regions(adev, NULL); 2186 if (status) 2187 goto err_no_ioregion; 2188 2189 pl022->phybase = adev->res.start; 2190 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2191 if (pl022->virtbase == NULL) { 2192 status = -ENOMEM; 2193 goto err_no_ioremap; 2194 } 2195 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2196 adev->res.start, pl022->virtbase); 2197 2198 pl022->clk = clk_get(&adev->dev, NULL); 2199 if (IS_ERR(pl022->clk)) { 2200 status = PTR_ERR(pl022->clk); 2201 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2202 goto err_no_clk; 2203 } 2204 2205 status = clk_prepare(pl022->clk); 2206 if (status) { 2207 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 2208 goto err_clk_prep; 2209 } 2210 2211 status = clk_enable(pl022->clk); 2212 if (status) { 2213 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2214 goto err_no_clk_en; 2215 } 2216 2217 /* Disable SSP */ 2218 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2219 SSP_CR1(pl022->virtbase)); 2220 load_ssp_default_config(pl022); 2221 2222 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2223 pl022); 2224 if (status < 0) { 2225 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2226 goto err_no_irq; 2227 } 2228 2229 /* Get DMA channels */ 2230 if (platform_info->enable_dma) { 2231 status = pl022_dma_probe(pl022); 2232 if (status != 0) 2233 platform_info->enable_dma = 0; 2234 } 2235 2236 /* Initialize and start queue */ 2237 status = init_queue(pl022); 2238 if (status != 0) { 2239 dev_err(&adev->dev, "probe - problem initializing queue\n"); 2240 goto err_init_queue; 2241 } 2242 status = start_queue(pl022); 2243 if (status != 0) { 2244 dev_err(&adev->dev, "probe - problem starting queue\n"); 2245 goto err_start_queue; 2246 } 2247 /* Register with the SPI framework */ 2248 amba_set_drvdata(adev, pl022); 2249 status = spi_register_master(master); 2250 if (status != 0) { 2251 dev_err(&adev->dev, 2252 "probe - problem registering spi master\n"); 2253 goto err_spi_register; 2254 } 2255 dev_dbg(dev, "probe succeeded\n"); 2256 2257 /* let runtime pm put suspend */ 2258 if (platform_info->autosuspend_delay > 0) { 2259 dev_info(&adev->dev, 2260 "will use autosuspend for runtime pm, delay %dms\n", 2261 platform_info->autosuspend_delay); 2262 pm_runtime_set_autosuspend_delay(dev, 2263 platform_info->autosuspend_delay); 2264 pm_runtime_use_autosuspend(dev); 2265 pm_runtime_put_autosuspend(dev); 2266 } else { 2267 pm_runtime_put(dev); 2268 } 2269 return 0; 2270 2271 err_spi_register: 2272 err_start_queue: 2273 err_init_queue: 2274 destroy_queue(pl022); 2275 if (platform_info->enable_dma) 2276 pl022_dma_remove(pl022); 2277 2278 free_irq(adev->irq[0], pl022); 2279 err_no_irq: 2280 clk_disable(pl022->clk); 2281 err_no_clk_en: 2282 clk_unprepare(pl022->clk); 2283 err_clk_prep: 2284 clk_put(pl022->clk); 2285 err_no_clk: 2286 iounmap(pl022->virtbase); 2287 err_no_ioremap: 2288 amba_release_regions(adev); 2289 err_no_ioregion: 2290 spi_master_put(master); 2291 err_no_master: 2292 err_no_pdata: 2293 return status; 2294 } 2295 2296 static int __devexit 2297 pl022_remove(struct amba_device *adev) 2298 { 2299 struct pl022 *pl022 = amba_get_drvdata(adev); 2300 2301 if (!pl022) 2302 return 0; 2303 2304 /* 2305 * undo pm_runtime_put() in probe. I assume that we're not 2306 * accessing the primecell here. 2307 */ 2308 pm_runtime_get_noresume(&adev->dev); 2309 2310 /* Remove the queue */ 2311 if (destroy_queue(pl022) != 0) 2312 dev_err(&adev->dev, "queue remove failed\n"); 2313 load_ssp_default_config(pl022); 2314 if (pl022->master_info->enable_dma) 2315 pl022_dma_remove(pl022); 2316 2317 free_irq(adev->irq[0], pl022); 2318 clk_disable(pl022->clk); 2319 clk_unprepare(pl022->clk); 2320 clk_put(pl022->clk); 2321 iounmap(pl022->virtbase); 2322 amba_release_regions(adev); 2323 tasklet_disable(&pl022->pump_transfers); 2324 spi_unregister_master(pl022->master); 2325 spi_master_put(pl022->master); 2326 amba_set_drvdata(adev, NULL); 2327 return 0; 2328 } 2329 2330 #ifdef CONFIG_SUSPEND 2331 static int pl022_suspend(struct device *dev) 2332 { 2333 struct pl022 *pl022 = dev_get_drvdata(dev); 2334 int status = 0; 2335 2336 status = stop_queue(pl022); 2337 if (status) { 2338 dev_warn(dev, "suspend cannot stop queue\n"); 2339 return status; 2340 } 2341 2342 dev_dbg(dev, "suspended\n"); 2343 return 0; 2344 } 2345 2346 static int pl022_resume(struct device *dev) 2347 { 2348 struct pl022 *pl022 = dev_get_drvdata(dev); 2349 int status = 0; 2350 2351 /* Start the queue running */ 2352 status = start_queue(pl022); 2353 if (status) 2354 dev_err(dev, "problem starting queue (%d)\n", status); 2355 else 2356 dev_dbg(dev, "resumed\n"); 2357 2358 return status; 2359 } 2360 #endif /* CONFIG_PM */ 2361 2362 #ifdef CONFIG_PM_RUNTIME 2363 static int pl022_runtime_suspend(struct device *dev) 2364 { 2365 struct pl022 *pl022 = dev_get_drvdata(dev); 2366 2367 clk_disable(pl022->clk); 2368 amba_vcore_disable(pl022->adev); 2369 2370 return 0; 2371 } 2372 2373 static int pl022_runtime_resume(struct device *dev) 2374 { 2375 struct pl022 *pl022 = dev_get_drvdata(dev); 2376 2377 amba_vcore_enable(pl022->adev); 2378 clk_enable(pl022->clk); 2379 2380 return 0; 2381 } 2382 #endif 2383 2384 static const struct dev_pm_ops pl022_dev_pm_ops = { 2385 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2386 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2387 }; 2388 2389 static struct vendor_data vendor_arm = { 2390 .fifodepth = 8, 2391 .max_bpw = 16, 2392 .unidir = false, 2393 .extended_cr = false, 2394 .pl023 = false, 2395 .loopback = true, 2396 }; 2397 2398 static struct vendor_data vendor_st = { 2399 .fifodepth = 32, 2400 .max_bpw = 32, 2401 .unidir = false, 2402 .extended_cr = true, 2403 .pl023 = false, 2404 .loopback = true, 2405 }; 2406 2407 static struct vendor_data vendor_st_pl023 = { 2408 .fifodepth = 32, 2409 .max_bpw = 32, 2410 .unidir = false, 2411 .extended_cr = true, 2412 .pl023 = true, 2413 .loopback = false, 2414 }; 2415 2416 static struct vendor_data vendor_db5500_pl023 = { 2417 .fifodepth = 32, 2418 .max_bpw = 32, 2419 .unidir = false, 2420 .extended_cr = true, 2421 .pl023 = true, 2422 .loopback = true, 2423 }; 2424 2425 static struct amba_id pl022_ids[] = { 2426 { 2427 /* 2428 * ARM PL022 variant, this has a 16bit wide 2429 * and 8 locations deep TX/RX FIFO 2430 */ 2431 .id = 0x00041022, 2432 .mask = 0x000fffff, 2433 .data = &vendor_arm, 2434 }, 2435 { 2436 /* 2437 * ST Micro derivative, this has 32bit wide 2438 * and 32 locations deep TX/RX FIFO 2439 */ 2440 .id = 0x01080022, 2441 .mask = 0xffffffff, 2442 .data = &vendor_st, 2443 }, 2444 { 2445 /* 2446 * ST-Ericsson derivative "PL023" (this is not 2447 * an official ARM number), this is a PL022 SSP block 2448 * stripped to SPI mode only, it has 32bit wide 2449 * and 32 locations deep TX/RX FIFO but no extended 2450 * CR0/CR1 register 2451 */ 2452 .id = 0x00080023, 2453 .mask = 0xffffffff, 2454 .data = &vendor_st_pl023, 2455 }, 2456 { 2457 .id = 0x10080023, 2458 .mask = 0xffffffff, 2459 .data = &vendor_db5500_pl023, 2460 }, 2461 { 0, 0 }, 2462 }; 2463 2464 MODULE_DEVICE_TABLE(amba, pl022_ids); 2465 2466 static struct amba_driver pl022_driver = { 2467 .drv = { 2468 .name = "ssp-pl022", 2469 .pm = &pl022_dev_pm_ops, 2470 }, 2471 .id_table = pl022_ids, 2472 .probe = pl022_probe, 2473 .remove = __devexit_p(pl022_remove), 2474 }; 2475 2476 static int __init pl022_init(void) 2477 { 2478 return amba_driver_register(&pl022_driver); 2479 } 2480 subsys_initcall(pl022_init); 2481 2482 static void __exit pl022_exit(void) 2483 { 2484 amba_driver_unregister(&pl022_driver); 2485 } 2486 module_exit(pl022_exit); 2487 2488 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2489 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2490 MODULE_LICENSE("GPL"); 2491