1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2009 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/workqueue.h> 33 #include <linux/delay.h> 34 #include <linux/clk.h> 35 #include <linux/err.h> 36 #include <linux/amba/bus.h> 37 #include <linux/amba/pl022.h> 38 #include <linux/io.h> 39 #include <linux/slab.h> 40 #include <linux/dmaengine.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/scatterlist.h> 43 #include <linux/pm_runtime.h> 44 45 /* 46 * This macro is used to define some register default values. 47 * reg is masked with mask, the OR:ed with an (again masked) 48 * val shifted sb steps to the left. 49 */ 50 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 51 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 52 53 /* 54 * This macro is also used to define some default values. 55 * It will just shift val by sb steps to the left and mask 56 * the result with mask. 57 */ 58 #define GEN_MASK_BITS(val, mask, sb) \ 59 (((val)<<(sb)) & (mask)) 60 61 #define DRIVE_TX 0 62 #define DO_NOT_DRIVE_TX 1 63 64 #define DO_NOT_QUEUE_DMA 0 65 #define QUEUE_DMA 1 66 67 #define RX_TRANSFER 1 68 #define TX_TRANSFER 2 69 70 /* 71 * Macros to access SSP Registers with their offsets 72 */ 73 #define SSP_CR0(r) (r + 0x000) 74 #define SSP_CR1(r) (r + 0x004) 75 #define SSP_DR(r) (r + 0x008) 76 #define SSP_SR(r) (r + 0x00C) 77 #define SSP_CPSR(r) (r + 0x010) 78 #define SSP_IMSC(r) (r + 0x014) 79 #define SSP_RIS(r) (r + 0x018) 80 #define SSP_MIS(r) (r + 0x01C) 81 #define SSP_ICR(r) (r + 0x020) 82 #define SSP_DMACR(r) (r + 0x024) 83 #define SSP_ITCR(r) (r + 0x080) 84 #define SSP_ITIP(r) (r + 0x084) 85 #define SSP_ITOP(r) (r + 0x088) 86 #define SSP_TDR(r) (r + 0x08C) 87 88 #define SSP_PID0(r) (r + 0xFE0) 89 #define SSP_PID1(r) (r + 0xFE4) 90 #define SSP_PID2(r) (r + 0xFE8) 91 #define SSP_PID3(r) (r + 0xFEC) 92 93 #define SSP_CID0(r) (r + 0xFF0) 94 #define SSP_CID1(r) (r + 0xFF4) 95 #define SSP_CID2(r) (r + 0xFF8) 96 #define SSP_CID3(r) (r + 0xFFC) 97 98 /* 99 * SSP Control Register 0 - SSP_CR0 100 */ 101 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 102 #define SSP_CR0_MASK_FRF (0x3UL << 4) 103 #define SSP_CR0_MASK_SPO (0x1UL << 6) 104 #define SSP_CR0_MASK_SPH (0x1UL << 7) 105 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 106 107 /* 108 * The ST version of this block moves som bits 109 * in SSP_CR0 and extends it to 32 bits 110 */ 111 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 112 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 113 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 114 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 115 116 /* 117 * SSP Control Register 0 - SSP_CR1 118 */ 119 #define SSP_CR1_MASK_LBM (0x1UL << 0) 120 #define SSP_CR1_MASK_SSE (0x1UL << 1) 121 #define SSP_CR1_MASK_MS (0x1UL << 2) 122 #define SSP_CR1_MASK_SOD (0x1UL << 3) 123 124 /* 125 * The ST version of this block adds some bits 126 * in SSP_CR1 127 */ 128 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 129 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 130 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 131 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 132 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 133 /* This one is only in the PL023 variant */ 134 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 135 136 /* 137 * SSP Status Register - SSP_SR 138 */ 139 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 140 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 141 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 142 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 143 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 144 145 /* 146 * SSP Clock Prescale Register - SSP_CPSR 147 */ 148 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 149 150 /* 151 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 152 */ 153 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 154 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 155 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 156 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 157 158 /* 159 * SSP Raw Interrupt Status Register - SSP_RIS 160 */ 161 /* Receive Overrun Raw Interrupt status */ 162 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 163 /* Receive Timeout Raw Interrupt status */ 164 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 165 /* Receive FIFO Raw Interrupt status */ 166 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 167 /* Transmit FIFO Raw Interrupt status */ 168 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 169 170 /* 171 * SSP Masked Interrupt Status Register - SSP_MIS 172 */ 173 /* Receive Overrun Masked Interrupt status */ 174 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 175 /* Receive Timeout Masked Interrupt status */ 176 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 177 /* Receive FIFO Masked Interrupt status */ 178 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 179 /* Transmit FIFO Masked Interrupt status */ 180 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 181 182 /* 183 * SSP Interrupt Clear Register - SSP_ICR 184 */ 185 /* Receive Overrun Raw Clear Interrupt bit */ 186 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 187 /* Receive Timeout Clear Interrupt bit */ 188 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 189 190 /* 191 * SSP DMA Control Register - SSP_DMACR 192 */ 193 /* Receive DMA Enable bit */ 194 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 195 /* Transmit DMA Enable bit */ 196 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 197 198 /* 199 * SSP Integration Test control Register - SSP_ITCR 200 */ 201 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 202 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 203 204 /* 205 * SSP Integration Test Input Register - SSP_ITIP 206 */ 207 #define ITIP_MASK_SSPRXD (0x1UL << 0) 208 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 209 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 210 #define ITIP_MASK_RXDMAC (0x1UL << 3) 211 #define ITIP_MASK_TXDMAC (0x1UL << 4) 212 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 213 214 /* 215 * SSP Integration Test output Register - SSP_ITOP 216 */ 217 #define ITOP_MASK_SSPTXD (0x1UL << 0) 218 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 219 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 220 #define ITOP_MASK_SSPOEn (0x1UL << 3) 221 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 222 #define ITOP_MASK_RORINTR (0x1UL << 5) 223 #define ITOP_MASK_RTINTR (0x1UL << 6) 224 #define ITOP_MASK_RXINTR (0x1UL << 7) 225 #define ITOP_MASK_TXINTR (0x1UL << 8) 226 #define ITOP_MASK_INTR (0x1UL << 9) 227 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 228 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 229 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 230 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 231 232 /* 233 * SSP Test Data Register - SSP_TDR 234 */ 235 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 236 237 /* 238 * Message State 239 * we use the spi_message.state (void *) pointer to 240 * hold a single state value, that's why all this 241 * (void *) casting is done here. 242 */ 243 #define STATE_START ((void *) 0) 244 #define STATE_RUNNING ((void *) 1) 245 #define STATE_DONE ((void *) 2) 246 #define STATE_ERROR ((void *) -1) 247 248 /* 249 * SSP State - Whether Enabled or Disabled 250 */ 251 #define SSP_DISABLED (0) 252 #define SSP_ENABLED (1) 253 254 /* 255 * SSP DMA State - Whether DMA Enabled or Disabled 256 */ 257 #define SSP_DMA_DISABLED (0) 258 #define SSP_DMA_ENABLED (1) 259 260 /* 261 * SSP Clock Defaults 262 */ 263 #define SSP_DEFAULT_CLKRATE 0x2 264 #define SSP_DEFAULT_PRESCALE 0x40 265 266 /* 267 * SSP Clock Parameter ranges 268 */ 269 #define CPSDVR_MIN 0x02 270 #define CPSDVR_MAX 0xFE 271 #define SCR_MIN 0x00 272 #define SCR_MAX 0xFF 273 274 /* 275 * SSP Interrupt related Macros 276 */ 277 #define DEFAULT_SSP_REG_IMSC 0x0UL 278 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 279 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 280 281 #define CLEAR_ALL_INTERRUPTS 0x3 282 283 #define SPI_POLLING_TIMEOUT 1000 284 285 /* 286 * The type of reading going on on this chip 287 */ 288 enum ssp_reading { 289 READING_NULL, 290 READING_U8, 291 READING_U16, 292 READING_U32 293 }; 294 295 /** 296 * The type of writing going on on this chip 297 */ 298 enum ssp_writing { 299 WRITING_NULL, 300 WRITING_U8, 301 WRITING_U16, 302 WRITING_U32 303 }; 304 305 /** 306 * struct vendor_data - vendor-specific config parameters 307 * for PL022 derivates 308 * @fifodepth: depth of FIFOs (both) 309 * @max_bpw: maximum number of bits per word 310 * @unidir: supports unidirection transfers 311 * @extended_cr: 32 bit wide control register 0 with extra 312 * features and extra features in CR1 as found in the ST variants 313 * @pl023: supports a subset of the ST extensions called "PL023" 314 */ 315 struct vendor_data { 316 int fifodepth; 317 int max_bpw; 318 bool unidir; 319 bool extended_cr; 320 bool pl023; 321 bool loopback; 322 }; 323 324 /** 325 * struct pl022 - This is the private SSP driver data structure 326 * @adev: AMBA device model hookup 327 * @vendor: vendor data for the IP block 328 * @phybase: the physical memory where the SSP device resides 329 * @virtbase: the virtual memory where the SSP is mapped 330 * @clk: outgoing clock "SPICLK" for the SPI bus 331 * @master: SPI framework hookup 332 * @master_info: controller-specific data from machine setup 333 * @workqueue: a workqueue on which any spi_message request is queued 334 * @pump_messages: work struct for scheduling work to the workqueue 335 * @queue_lock: spinlock to syncronise access to message queue 336 * @queue: message queue 337 * @busy: workqueue is busy 338 * @running: workqueue is running 339 * @pump_transfers: Tasklet used in Interrupt Transfer mode 340 * @cur_msg: Pointer to current spi_message being processed 341 * @cur_transfer: Pointer to current spi_transfer 342 * @cur_chip: pointer to current clients chip(assigned from controller_state) 343 * @tx: current position in TX buffer to be read 344 * @tx_end: end position in TX buffer to be read 345 * @rx: current position in RX buffer to be written 346 * @rx_end: end position in RX buffer to be written 347 * @read: the type of read currently going on 348 * @write: the type of write currently going on 349 * @exp_fifo_level: expected FIFO level 350 * @dma_rx_channel: optional channel for RX DMA 351 * @dma_tx_channel: optional channel for TX DMA 352 * @sgt_rx: scattertable for the RX transfer 353 * @sgt_tx: scattertable for the TX transfer 354 * @dummypage: a dummy page used for driving data on the bus with DMA 355 */ 356 struct pl022 { 357 struct amba_device *adev; 358 struct vendor_data *vendor; 359 resource_size_t phybase; 360 void __iomem *virtbase; 361 struct clk *clk; 362 struct spi_master *master; 363 struct pl022_ssp_controller *master_info; 364 /* Driver message queue */ 365 struct workqueue_struct *workqueue; 366 struct work_struct pump_messages; 367 spinlock_t queue_lock; 368 struct list_head queue; 369 bool busy; 370 bool running; 371 /* Message transfer pump */ 372 struct tasklet_struct pump_transfers; 373 struct spi_message *cur_msg; 374 struct spi_transfer *cur_transfer; 375 struct chip_data *cur_chip; 376 void *tx; 377 void *tx_end; 378 void *rx; 379 void *rx_end; 380 enum ssp_reading read; 381 enum ssp_writing write; 382 u32 exp_fifo_level; 383 enum ssp_rx_level_trig rx_lev_trig; 384 enum ssp_tx_level_trig tx_lev_trig; 385 /* DMA settings */ 386 #ifdef CONFIG_DMA_ENGINE 387 struct dma_chan *dma_rx_channel; 388 struct dma_chan *dma_tx_channel; 389 struct sg_table sgt_rx; 390 struct sg_table sgt_tx; 391 char *dummypage; 392 #endif 393 }; 394 395 /** 396 * struct chip_data - To maintain runtime state of SSP for each client chip 397 * @cr0: Value of control register CR0 of SSP - on later ST variants this 398 * register is 32 bits wide rather than just 16 399 * @cr1: Value of control register CR1 of SSP 400 * @dmacr: Value of DMA control Register of SSP 401 * @cpsr: Value of Clock prescale register 402 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 403 * @enable_dma: Whether to enable DMA or not 404 * @read: function ptr to be used to read when doing xfer for this chip 405 * @write: function ptr to be used to write when doing xfer for this chip 406 * @cs_control: chip select callback provided by chip 407 * @xfer_type: polling/interrupt/DMA 408 * 409 * Runtime state of the SSP controller, maintained per chip, 410 * This would be set according to the current message that would be served 411 */ 412 struct chip_data { 413 u32 cr0; 414 u16 cr1; 415 u16 dmacr; 416 u16 cpsr; 417 u8 n_bytes; 418 bool enable_dma; 419 enum ssp_reading read; 420 enum ssp_writing write; 421 void (*cs_control) (u32 command); 422 int xfer_type; 423 }; 424 425 /** 426 * null_cs_control - Dummy chip select function 427 * @command: select/delect the chip 428 * 429 * If no chip select function is provided by client this is used as dummy 430 * chip select 431 */ 432 static void null_cs_control(u32 command) 433 { 434 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 435 } 436 437 /** 438 * giveback - current spi_message is over, schedule next message and call 439 * callback of this message. Assumes that caller already 440 * set message->status; dma and pio irqs are blocked 441 * @pl022: SSP driver private data structure 442 */ 443 static void giveback(struct pl022 *pl022) 444 { 445 struct spi_transfer *last_transfer; 446 unsigned long flags; 447 struct spi_message *msg; 448 void (*curr_cs_control) (u32 command); 449 450 /* 451 * This local reference to the chip select function 452 * is needed because we set curr_chip to NULL 453 * as a step toward termininating the message. 454 */ 455 curr_cs_control = pl022->cur_chip->cs_control; 456 spin_lock_irqsave(&pl022->queue_lock, flags); 457 msg = pl022->cur_msg; 458 pl022->cur_msg = NULL; 459 pl022->cur_transfer = NULL; 460 pl022->cur_chip = NULL; 461 queue_work(pl022->workqueue, &pl022->pump_messages); 462 spin_unlock_irqrestore(&pl022->queue_lock, flags); 463 464 last_transfer = list_entry(msg->transfers.prev, 465 struct spi_transfer, 466 transfer_list); 467 468 /* Delay if requested before any change in chip select */ 469 if (last_transfer->delay_usecs) 470 /* 471 * FIXME: This runs in interrupt context. 472 * Is this really smart? 473 */ 474 udelay(last_transfer->delay_usecs); 475 476 /* 477 * Drop chip select UNLESS cs_change is true or we are returning 478 * a message with an error, or next message is for another chip 479 */ 480 if (!last_transfer->cs_change) 481 curr_cs_control(SSP_CHIP_DESELECT); 482 else { 483 struct spi_message *next_msg; 484 485 /* Holding of cs was hinted, but we need to make sure 486 * the next message is for the same chip. Don't waste 487 * time with the following tests unless this was hinted. 488 * 489 * We cannot postpone this until pump_messages, because 490 * after calling msg->complete (below) the driver that 491 * sent the current message could be unloaded, which 492 * could invalidate the cs_control() callback... 493 */ 494 495 /* get a pointer to the next message, if any */ 496 spin_lock_irqsave(&pl022->queue_lock, flags); 497 if (list_empty(&pl022->queue)) 498 next_msg = NULL; 499 else 500 next_msg = list_entry(pl022->queue.next, 501 struct spi_message, queue); 502 spin_unlock_irqrestore(&pl022->queue_lock, flags); 503 504 /* see if the next and current messages point 505 * to the same chip 506 */ 507 if (next_msg && next_msg->spi != msg->spi) 508 next_msg = NULL; 509 if (!next_msg || msg->state == STATE_ERROR) 510 curr_cs_control(SSP_CHIP_DESELECT); 511 } 512 msg->state = NULL; 513 if (msg->complete) 514 msg->complete(msg->context); 515 } 516 517 /** 518 * flush - flush the FIFO to reach a clean state 519 * @pl022: SSP driver private data structure 520 */ 521 static int flush(struct pl022 *pl022) 522 { 523 unsigned long limit = loops_per_jiffy << 1; 524 525 dev_dbg(&pl022->adev->dev, "flush\n"); 526 do { 527 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 528 readw(SSP_DR(pl022->virtbase)); 529 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 530 531 pl022->exp_fifo_level = 0; 532 533 return limit; 534 } 535 536 /** 537 * restore_state - Load configuration of current chip 538 * @pl022: SSP driver private data structure 539 */ 540 static void restore_state(struct pl022 *pl022) 541 { 542 struct chip_data *chip = pl022->cur_chip; 543 544 if (pl022->vendor->extended_cr) 545 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 546 else 547 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 548 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 549 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 550 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 551 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 552 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 553 } 554 555 /* 556 * Default SSP Register Values 557 */ 558 #define DEFAULT_SSP_REG_CR0 ( \ 559 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 560 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 561 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 562 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 563 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 564 ) 565 566 /* ST versions have slightly different bit layout */ 567 #define DEFAULT_SSP_REG_CR0_ST ( \ 568 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 569 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 570 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 571 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 572 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 573 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 574 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 575 ) 576 577 /* The PL023 version is slightly different again */ 578 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 579 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 580 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 581 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 582 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 583 ) 584 585 #define DEFAULT_SSP_REG_CR1 ( \ 586 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 587 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 588 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 589 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 590 ) 591 592 /* ST versions extend this register to use all 16 bits */ 593 #define DEFAULT_SSP_REG_CR1_ST ( \ 594 DEFAULT_SSP_REG_CR1 | \ 595 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 596 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 597 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 598 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 599 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 600 ) 601 602 /* 603 * The PL023 variant has further differences: no loopback mode, no microwire 604 * support, and a new clock feedback delay setting. 605 */ 606 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 607 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 608 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 609 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 610 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 611 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 612 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 613 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 614 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 615 ) 616 617 #define DEFAULT_SSP_REG_CPSR ( \ 618 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 619 ) 620 621 #define DEFAULT_SSP_REG_DMACR (\ 622 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 623 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 624 ) 625 626 /** 627 * load_ssp_default_config - Load default configuration for SSP 628 * @pl022: SSP driver private data structure 629 */ 630 static void load_ssp_default_config(struct pl022 *pl022) 631 { 632 if (pl022->vendor->pl023) { 633 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 634 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 635 } else if (pl022->vendor->extended_cr) { 636 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 637 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 638 } else { 639 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 640 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 641 } 642 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 643 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 644 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 645 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 646 } 647 648 /** 649 * This will write to TX and read from RX according to the parameters 650 * set in pl022. 651 */ 652 static void readwriter(struct pl022 *pl022) 653 { 654 655 /* 656 * The FIFO depth is different between primecell variants. 657 * I believe filling in too much in the FIFO might cause 658 * errons in 8bit wide transfers on ARM variants (just 8 words 659 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 660 * 661 * To prevent this issue, the TX FIFO is only filled to the 662 * unused RX FIFO fill length, regardless of what the TX 663 * FIFO status flag indicates. 664 */ 665 dev_dbg(&pl022->adev->dev, 666 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 667 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 668 669 /* Read as much as you can */ 670 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 671 && (pl022->rx < pl022->rx_end)) { 672 switch (pl022->read) { 673 case READING_NULL: 674 readw(SSP_DR(pl022->virtbase)); 675 break; 676 case READING_U8: 677 *(u8 *) (pl022->rx) = 678 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 679 break; 680 case READING_U16: 681 *(u16 *) (pl022->rx) = 682 (u16) readw(SSP_DR(pl022->virtbase)); 683 break; 684 case READING_U32: 685 *(u32 *) (pl022->rx) = 686 readl(SSP_DR(pl022->virtbase)); 687 break; 688 } 689 pl022->rx += (pl022->cur_chip->n_bytes); 690 pl022->exp_fifo_level--; 691 } 692 /* 693 * Write as much as possible up to the RX FIFO size 694 */ 695 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 696 && (pl022->tx < pl022->tx_end)) { 697 switch (pl022->write) { 698 case WRITING_NULL: 699 writew(0x0, SSP_DR(pl022->virtbase)); 700 break; 701 case WRITING_U8: 702 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 703 break; 704 case WRITING_U16: 705 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 706 break; 707 case WRITING_U32: 708 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 709 break; 710 } 711 pl022->tx += (pl022->cur_chip->n_bytes); 712 pl022->exp_fifo_level++; 713 /* 714 * This inner reader takes care of things appearing in the RX 715 * FIFO as we're transmitting. This will happen a lot since the 716 * clock starts running when you put things into the TX FIFO, 717 * and then things are continuously clocked into the RX FIFO. 718 */ 719 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 720 && (pl022->rx < pl022->rx_end)) { 721 switch (pl022->read) { 722 case READING_NULL: 723 readw(SSP_DR(pl022->virtbase)); 724 break; 725 case READING_U8: 726 *(u8 *) (pl022->rx) = 727 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 728 break; 729 case READING_U16: 730 *(u16 *) (pl022->rx) = 731 (u16) readw(SSP_DR(pl022->virtbase)); 732 break; 733 case READING_U32: 734 *(u32 *) (pl022->rx) = 735 readl(SSP_DR(pl022->virtbase)); 736 break; 737 } 738 pl022->rx += (pl022->cur_chip->n_bytes); 739 pl022->exp_fifo_level--; 740 } 741 } 742 /* 743 * When we exit here the TX FIFO should be full and the RX FIFO 744 * should be empty 745 */ 746 } 747 748 /** 749 * next_transfer - Move to the Next transfer in the current spi message 750 * @pl022: SSP driver private data structure 751 * 752 * This function moves though the linked list of spi transfers in the 753 * current spi message and returns with the state of current spi 754 * message i.e whether its last transfer is done(STATE_DONE) or 755 * Next transfer is ready(STATE_RUNNING) 756 */ 757 static void *next_transfer(struct pl022 *pl022) 758 { 759 struct spi_message *msg = pl022->cur_msg; 760 struct spi_transfer *trans = pl022->cur_transfer; 761 762 /* Move to next transfer */ 763 if (trans->transfer_list.next != &msg->transfers) { 764 pl022->cur_transfer = 765 list_entry(trans->transfer_list.next, 766 struct spi_transfer, transfer_list); 767 return STATE_RUNNING; 768 } 769 return STATE_DONE; 770 } 771 772 /* 773 * This DMA functionality is only compiled in if we have 774 * access to the generic DMA devices/DMA engine. 775 */ 776 #ifdef CONFIG_DMA_ENGINE 777 static void unmap_free_dma_scatter(struct pl022 *pl022) 778 { 779 /* Unmap and free the SG tables */ 780 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 781 pl022->sgt_tx.nents, DMA_TO_DEVICE); 782 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 783 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 784 sg_free_table(&pl022->sgt_rx); 785 sg_free_table(&pl022->sgt_tx); 786 } 787 788 static void dma_callback(void *data) 789 { 790 struct pl022 *pl022 = data; 791 struct spi_message *msg = pl022->cur_msg; 792 793 BUG_ON(!pl022->sgt_rx.sgl); 794 795 #ifdef VERBOSE_DEBUG 796 /* 797 * Optionally dump out buffers to inspect contents, this is 798 * good if you want to convince yourself that the loopback 799 * read/write contents are the same, when adopting to a new 800 * DMA engine. 801 */ 802 { 803 struct scatterlist *sg; 804 unsigned int i; 805 806 dma_sync_sg_for_cpu(&pl022->adev->dev, 807 pl022->sgt_rx.sgl, 808 pl022->sgt_rx.nents, 809 DMA_FROM_DEVICE); 810 811 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 812 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 813 print_hex_dump(KERN_ERR, "SPI RX: ", 814 DUMP_PREFIX_OFFSET, 815 16, 816 1, 817 sg_virt(sg), 818 sg_dma_len(sg), 819 1); 820 } 821 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 822 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 823 print_hex_dump(KERN_ERR, "SPI TX: ", 824 DUMP_PREFIX_OFFSET, 825 16, 826 1, 827 sg_virt(sg), 828 sg_dma_len(sg), 829 1); 830 } 831 } 832 #endif 833 834 unmap_free_dma_scatter(pl022); 835 836 /* Update total bytes transferred */ 837 msg->actual_length += pl022->cur_transfer->len; 838 if (pl022->cur_transfer->cs_change) 839 pl022->cur_chip-> 840 cs_control(SSP_CHIP_DESELECT); 841 842 /* Move to next transfer */ 843 msg->state = next_transfer(pl022); 844 tasklet_schedule(&pl022->pump_transfers); 845 } 846 847 static void setup_dma_scatter(struct pl022 *pl022, 848 void *buffer, 849 unsigned int length, 850 struct sg_table *sgtab) 851 { 852 struct scatterlist *sg; 853 int bytesleft = length; 854 void *bufp = buffer; 855 int mapbytes; 856 int i; 857 858 if (buffer) { 859 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 860 /* 861 * If there are less bytes left than what fits 862 * in the current page (plus page alignment offset) 863 * we just feed in this, else we stuff in as much 864 * as we can. 865 */ 866 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 867 mapbytes = bytesleft; 868 else 869 mapbytes = PAGE_SIZE - offset_in_page(bufp); 870 sg_set_page(sg, virt_to_page(bufp), 871 mapbytes, offset_in_page(bufp)); 872 bufp += mapbytes; 873 bytesleft -= mapbytes; 874 dev_dbg(&pl022->adev->dev, 875 "set RX/TX target page @ %p, %d bytes, %d left\n", 876 bufp, mapbytes, bytesleft); 877 } 878 } else { 879 /* Map the dummy buffer on every page */ 880 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 881 if (bytesleft < PAGE_SIZE) 882 mapbytes = bytesleft; 883 else 884 mapbytes = PAGE_SIZE; 885 sg_set_page(sg, virt_to_page(pl022->dummypage), 886 mapbytes, 0); 887 bytesleft -= mapbytes; 888 dev_dbg(&pl022->adev->dev, 889 "set RX/TX to dummy page %d bytes, %d left\n", 890 mapbytes, bytesleft); 891 892 } 893 } 894 BUG_ON(bytesleft); 895 } 896 897 /** 898 * configure_dma - configures the channels for the next transfer 899 * @pl022: SSP driver's private data structure 900 */ 901 static int configure_dma(struct pl022 *pl022) 902 { 903 struct dma_slave_config rx_conf = { 904 .src_addr = SSP_DR(pl022->phybase), 905 .direction = DMA_FROM_DEVICE, 906 }; 907 struct dma_slave_config tx_conf = { 908 .dst_addr = SSP_DR(pl022->phybase), 909 .direction = DMA_TO_DEVICE, 910 }; 911 unsigned int pages; 912 int ret; 913 int rx_sglen, tx_sglen; 914 struct dma_chan *rxchan = pl022->dma_rx_channel; 915 struct dma_chan *txchan = pl022->dma_tx_channel; 916 struct dma_async_tx_descriptor *rxdesc; 917 struct dma_async_tx_descriptor *txdesc; 918 919 /* Check that the channels are available */ 920 if (!rxchan || !txchan) 921 return -ENODEV; 922 923 /* 924 * If supplied, the DMA burstsize should equal the FIFO trigger level. 925 * Notice that the DMA engine uses one-to-one mapping. Since we can 926 * not trigger on 2 elements this needs explicit mapping rather than 927 * calculation. 928 */ 929 switch (pl022->rx_lev_trig) { 930 case SSP_RX_1_OR_MORE_ELEM: 931 rx_conf.src_maxburst = 1; 932 break; 933 case SSP_RX_4_OR_MORE_ELEM: 934 rx_conf.src_maxburst = 4; 935 break; 936 case SSP_RX_8_OR_MORE_ELEM: 937 rx_conf.src_maxburst = 8; 938 break; 939 case SSP_RX_16_OR_MORE_ELEM: 940 rx_conf.src_maxburst = 16; 941 break; 942 case SSP_RX_32_OR_MORE_ELEM: 943 rx_conf.src_maxburst = 32; 944 break; 945 default: 946 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 947 break; 948 } 949 950 switch (pl022->tx_lev_trig) { 951 case SSP_TX_1_OR_MORE_EMPTY_LOC: 952 tx_conf.dst_maxburst = 1; 953 break; 954 case SSP_TX_4_OR_MORE_EMPTY_LOC: 955 tx_conf.dst_maxburst = 4; 956 break; 957 case SSP_TX_8_OR_MORE_EMPTY_LOC: 958 tx_conf.dst_maxburst = 8; 959 break; 960 case SSP_TX_16_OR_MORE_EMPTY_LOC: 961 tx_conf.dst_maxburst = 16; 962 break; 963 case SSP_TX_32_OR_MORE_EMPTY_LOC: 964 tx_conf.dst_maxburst = 32; 965 break; 966 default: 967 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 968 break; 969 } 970 971 switch (pl022->read) { 972 case READING_NULL: 973 /* Use the same as for writing */ 974 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 975 break; 976 case READING_U8: 977 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 978 break; 979 case READING_U16: 980 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 981 break; 982 case READING_U32: 983 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 984 break; 985 } 986 987 switch (pl022->write) { 988 case WRITING_NULL: 989 /* Use the same as for reading */ 990 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 991 break; 992 case WRITING_U8: 993 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 994 break; 995 case WRITING_U16: 996 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 997 break; 998 case WRITING_U32: 999 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1000 break; 1001 } 1002 1003 /* SPI pecularity: we need to read and write the same width */ 1004 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1005 rx_conf.src_addr_width = tx_conf.dst_addr_width; 1006 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1007 tx_conf.dst_addr_width = rx_conf.src_addr_width; 1008 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1009 1010 dmaengine_slave_config(rxchan, &rx_conf); 1011 dmaengine_slave_config(txchan, &tx_conf); 1012 1013 /* Create sglists for the transfers */ 1014 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1015 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1016 1017 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1018 if (ret) 1019 goto err_alloc_rx_sg; 1020 1021 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1022 if (ret) 1023 goto err_alloc_tx_sg; 1024 1025 /* Fill in the scatterlists for the RX+TX buffers */ 1026 setup_dma_scatter(pl022, pl022->rx, 1027 pl022->cur_transfer->len, &pl022->sgt_rx); 1028 setup_dma_scatter(pl022, pl022->tx, 1029 pl022->cur_transfer->len, &pl022->sgt_tx); 1030 1031 /* Map DMA buffers */ 1032 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1033 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1034 if (!rx_sglen) 1035 goto err_rx_sgmap; 1036 1037 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1038 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1039 if (!tx_sglen) 1040 goto err_tx_sgmap; 1041 1042 /* Send both scatterlists */ 1043 rxdesc = rxchan->device->device_prep_slave_sg(rxchan, 1044 pl022->sgt_rx.sgl, 1045 rx_sglen, 1046 DMA_FROM_DEVICE, 1047 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1048 if (!rxdesc) 1049 goto err_rxdesc; 1050 1051 txdesc = txchan->device->device_prep_slave_sg(txchan, 1052 pl022->sgt_tx.sgl, 1053 tx_sglen, 1054 DMA_TO_DEVICE, 1055 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1056 if (!txdesc) 1057 goto err_txdesc; 1058 1059 /* Put the callback on the RX transfer only, that should finish last */ 1060 rxdesc->callback = dma_callback; 1061 rxdesc->callback_param = pl022; 1062 1063 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1064 dmaengine_submit(rxdesc); 1065 dmaengine_submit(txdesc); 1066 dma_async_issue_pending(rxchan); 1067 dma_async_issue_pending(txchan); 1068 1069 return 0; 1070 1071 err_txdesc: 1072 dmaengine_terminate_all(txchan); 1073 err_rxdesc: 1074 dmaengine_terminate_all(rxchan); 1075 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1076 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1077 err_tx_sgmap: 1078 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1079 pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1080 err_rx_sgmap: 1081 sg_free_table(&pl022->sgt_tx); 1082 err_alloc_tx_sg: 1083 sg_free_table(&pl022->sgt_rx); 1084 err_alloc_rx_sg: 1085 return -ENOMEM; 1086 } 1087 1088 static int __init pl022_dma_probe(struct pl022 *pl022) 1089 { 1090 dma_cap_mask_t mask; 1091 1092 /* Try to acquire a generic DMA engine slave channel */ 1093 dma_cap_zero(mask); 1094 dma_cap_set(DMA_SLAVE, mask); 1095 /* 1096 * We need both RX and TX channels to do DMA, else do none 1097 * of them. 1098 */ 1099 pl022->dma_rx_channel = dma_request_channel(mask, 1100 pl022->master_info->dma_filter, 1101 pl022->master_info->dma_rx_param); 1102 if (!pl022->dma_rx_channel) { 1103 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1104 goto err_no_rxchan; 1105 } 1106 1107 pl022->dma_tx_channel = dma_request_channel(mask, 1108 pl022->master_info->dma_filter, 1109 pl022->master_info->dma_tx_param); 1110 if (!pl022->dma_tx_channel) { 1111 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1112 goto err_no_txchan; 1113 } 1114 1115 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1116 if (!pl022->dummypage) { 1117 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1118 goto err_no_dummypage; 1119 } 1120 1121 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1122 dma_chan_name(pl022->dma_rx_channel), 1123 dma_chan_name(pl022->dma_tx_channel)); 1124 1125 return 0; 1126 1127 err_no_dummypage: 1128 dma_release_channel(pl022->dma_tx_channel); 1129 err_no_txchan: 1130 dma_release_channel(pl022->dma_rx_channel); 1131 pl022->dma_rx_channel = NULL; 1132 err_no_rxchan: 1133 dev_err(&pl022->adev->dev, 1134 "Failed to work in dma mode, work without dma!\n"); 1135 return -ENODEV; 1136 } 1137 1138 static void terminate_dma(struct pl022 *pl022) 1139 { 1140 struct dma_chan *rxchan = pl022->dma_rx_channel; 1141 struct dma_chan *txchan = pl022->dma_tx_channel; 1142 1143 dmaengine_terminate_all(rxchan); 1144 dmaengine_terminate_all(txchan); 1145 unmap_free_dma_scatter(pl022); 1146 } 1147 1148 static void pl022_dma_remove(struct pl022 *pl022) 1149 { 1150 if (pl022->busy) 1151 terminate_dma(pl022); 1152 if (pl022->dma_tx_channel) 1153 dma_release_channel(pl022->dma_tx_channel); 1154 if (pl022->dma_rx_channel) 1155 dma_release_channel(pl022->dma_rx_channel); 1156 kfree(pl022->dummypage); 1157 } 1158 1159 #else 1160 static inline int configure_dma(struct pl022 *pl022) 1161 { 1162 return -ENODEV; 1163 } 1164 1165 static inline int pl022_dma_probe(struct pl022 *pl022) 1166 { 1167 return 0; 1168 } 1169 1170 static inline void pl022_dma_remove(struct pl022 *pl022) 1171 { 1172 } 1173 #endif 1174 1175 /** 1176 * pl022_interrupt_handler - Interrupt handler for SSP controller 1177 * 1178 * This function handles interrupts generated for an interrupt based transfer. 1179 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1180 * current message's state as STATE_ERROR and schedule the tasklet 1181 * pump_transfers which will do the postprocessing of the current message by 1182 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1183 * more data, and writes data in TX FIFO till it is not full. If we complete 1184 * the transfer we move to the next transfer and schedule the tasklet. 1185 */ 1186 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1187 { 1188 struct pl022 *pl022 = dev_id; 1189 struct spi_message *msg = pl022->cur_msg; 1190 u16 irq_status = 0; 1191 u16 flag = 0; 1192 1193 if (unlikely(!msg)) { 1194 dev_err(&pl022->adev->dev, 1195 "bad message state in interrupt handler"); 1196 /* Never fail */ 1197 return IRQ_HANDLED; 1198 } 1199 1200 /* Read the Interrupt Status Register */ 1201 irq_status = readw(SSP_MIS(pl022->virtbase)); 1202 1203 if (unlikely(!irq_status)) 1204 return IRQ_NONE; 1205 1206 /* 1207 * This handles the FIFO interrupts, the timeout 1208 * interrupts are flatly ignored, they cannot be 1209 * trusted. 1210 */ 1211 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1212 /* 1213 * Overrun interrupt - bail out since our Data has been 1214 * corrupted 1215 */ 1216 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1217 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1218 dev_err(&pl022->adev->dev, 1219 "RXFIFO is full\n"); 1220 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1221 dev_err(&pl022->adev->dev, 1222 "TXFIFO is full\n"); 1223 1224 /* 1225 * Disable and clear interrupts, disable SSP, 1226 * mark message with bad status so it can be 1227 * retried. 1228 */ 1229 writew(DISABLE_ALL_INTERRUPTS, 1230 SSP_IMSC(pl022->virtbase)); 1231 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1232 writew((readw(SSP_CR1(pl022->virtbase)) & 1233 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1234 msg->state = STATE_ERROR; 1235 1236 /* Schedule message queue handler */ 1237 tasklet_schedule(&pl022->pump_transfers); 1238 return IRQ_HANDLED; 1239 } 1240 1241 readwriter(pl022); 1242 1243 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1244 flag = 1; 1245 /* Disable Transmit interrupt, enable receive interrupt */ 1246 writew((readw(SSP_IMSC(pl022->virtbase)) & 1247 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1248 SSP_IMSC(pl022->virtbase)); 1249 } 1250 1251 /* 1252 * Since all transactions must write as much as shall be read, 1253 * we can conclude the entire transaction once RX is complete. 1254 * At this point, all TX will always be finished. 1255 */ 1256 if (pl022->rx >= pl022->rx_end) { 1257 writew(DISABLE_ALL_INTERRUPTS, 1258 SSP_IMSC(pl022->virtbase)); 1259 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1260 if (unlikely(pl022->rx > pl022->rx_end)) { 1261 dev_warn(&pl022->adev->dev, "read %u surplus " 1262 "bytes (did you request an odd " 1263 "number of bytes on a 16bit bus?)\n", 1264 (u32) (pl022->rx - pl022->rx_end)); 1265 } 1266 /* Update total bytes transferred */ 1267 msg->actual_length += pl022->cur_transfer->len; 1268 if (pl022->cur_transfer->cs_change) 1269 pl022->cur_chip-> 1270 cs_control(SSP_CHIP_DESELECT); 1271 /* Move to next transfer */ 1272 msg->state = next_transfer(pl022); 1273 tasklet_schedule(&pl022->pump_transfers); 1274 return IRQ_HANDLED; 1275 } 1276 1277 return IRQ_HANDLED; 1278 } 1279 1280 /** 1281 * This sets up the pointers to memory for the next message to 1282 * send out on the SPI bus. 1283 */ 1284 static int set_up_next_transfer(struct pl022 *pl022, 1285 struct spi_transfer *transfer) 1286 { 1287 int residue; 1288 1289 /* Sanity check the message for this bus width */ 1290 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1291 if (unlikely(residue != 0)) { 1292 dev_err(&pl022->adev->dev, 1293 "message of %u bytes to transmit but the current " 1294 "chip bus has a data width of %u bytes!\n", 1295 pl022->cur_transfer->len, 1296 pl022->cur_chip->n_bytes); 1297 dev_err(&pl022->adev->dev, "skipping this message\n"); 1298 return -EIO; 1299 } 1300 pl022->tx = (void *)transfer->tx_buf; 1301 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1302 pl022->rx = (void *)transfer->rx_buf; 1303 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1304 pl022->write = 1305 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1306 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1307 return 0; 1308 } 1309 1310 /** 1311 * pump_transfers - Tasklet function which schedules next transfer 1312 * when running in interrupt or DMA transfer mode. 1313 * @data: SSP driver private data structure 1314 * 1315 */ 1316 static void pump_transfers(unsigned long data) 1317 { 1318 struct pl022 *pl022 = (struct pl022 *) data; 1319 struct spi_message *message = NULL; 1320 struct spi_transfer *transfer = NULL; 1321 struct spi_transfer *previous = NULL; 1322 1323 /* Get current state information */ 1324 message = pl022->cur_msg; 1325 transfer = pl022->cur_transfer; 1326 1327 /* Handle for abort */ 1328 if (message->state == STATE_ERROR) { 1329 message->status = -EIO; 1330 giveback(pl022); 1331 return; 1332 } 1333 1334 /* Handle end of message */ 1335 if (message->state == STATE_DONE) { 1336 message->status = 0; 1337 giveback(pl022); 1338 return; 1339 } 1340 1341 /* Delay if requested at end of transfer before CS change */ 1342 if (message->state == STATE_RUNNING) { 1343 previous = list_entry(transfer->transfer_list.prev, 1344 struct spi_transfer, 1345 transfer_list); 1346 if (previous->delay_usecs) 1347 /* 1348 * FIXME: This runs in interrupt context. 1349 * Is this really smart? 1350 */ 1351 udelay(previous->delay_usecs); 1352 1353 /* Drop chip select only if cs_change is requested */ 1354 if (previous->cs_change) 1355 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1356 } else { 1357 /* STATE_START */ 1358 message->state = STATE_RUNNING; 1359 } 1360 1361 if (set_up_next_transfer(pl022, transfer)) { 1362 message->state = STATE_ERROR; 1363 message->status = -EIO; 1364 giveback(pl022); 1365 return; 1366 } 1367 /* Flush the FIFOs and let's go! */ 1368 flush(pl022); 1369 1370 if (pl022->cur_chip->enable_dma) { 1371 if (configure_dma(pl022)) { 1372 dev_dbg(&pl022->adev->dev, 1373 "configuration of DMA failed, fall back to interrupt mode\n"); 1374 goto err_config_dma; 1375 } 1376 return; 1377 } 1378 1379 err_config_dma: 1380 /* enable all interrupts except RX */ 1381 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1382 } 1383 1384 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1385 { 1386 /* 1387 * Default is to enable all interrupts except RX - 1388 * this will be enabled once TX is complete 1389 */ 1390 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1391 1392 /* Enable target chip */ 1393 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1394 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1395 /* Error path */ 1396 pl022->cur_msg->state = STATE_ERROR; 1397 pl022->cur_msg->status = -EIO; 1398 giveback(pl022); 1399 return; 1400 } 1401 /* If we're using DMA, set up DMA here */ 1402 if (pl022->cur_chip->enable_dma) { 1403 /* Configure DMA transfer */ 1404 if (configure_dma(pl022)) { 1405 dev_dbg(&pl022->adev->dev, 1406 "configuration of DMA failed, fall back to interrupt mode\n"); 1407 goto err_config_dma; 1408 } 1409 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1410 irqflags = DISABLE_ALL_INTERRUPTS; 1411 } 1412 err_config_dma: 1413 /* Enable SSP, turn on interrupts */ 1414 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1415 SSP_CR1(pl022->virtbase)); 1416 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1417 } 1418 1419 static void do_polling_transfer(struct pl022 *pl022) 1420 { 1421 struct spi_message *message = NULL; 1422 struct spi_transfer *transfer = NULL; 1423 struct spi_transfer *previous = NULL; 1424 struct chip_data *chip; 1425 unsigned long time, timeout; 1426 1427 chip = pl022->cur_chip; 1428 message = pl022->cur_msg; 1429 1430 while (message->state != STATE_DONE) { 1431 /* Handle for abort */ 1432 if (message->state == STATE_ERROR) 1433 break; 1434 transfer = pl022->cur_transfer; 1435 1436 /* Delay if requested at end of transfer */ 1437 if (message->state == STATE_RUNNING) { 1438 previous = 1439 list_entry(transfer->transfer_list.prev, 1440 struct spi_transfer, transfer_list); 1441 if (previous->delay_usecs) 1442 udelay(previous->delay_usecs); 1443 if (previous->cs_change) 1444 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1445 } else { 1446 /* STATE_START */ 1447 message->state = STATE_RUNNING; 1448 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1449 } 1450 1451 /* Configuration Changing Per Transfer */ 1452 if (set_up_next_transfer(pl022, transfer)) { 1453 /* Error path */ 1454 message->state = STATE_ERROR; 1455 break; 1456 } 1457 /* Flush FIFOs and enable SSP */ 1458 flush(pl022); 1459 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1460 SSP_CR1(pl022->virtbase)); 1461 1462 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1463 1464 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1465 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1466 time = jiffies; 1467 readwriter(pl022); 1468 if (time_after(time, timeout)) { 1469 dev_warn(&pl022->adev->dev, 1470 "%s: timeout!\n", __func__); 1471 message->state = STATE_ERROR; 1472 goto out; 1473 } 1474 cpu_relax(); 1475 } 1476 1477 /* Update total byte transferred */ 1478 message->actual_length += pl022->cur_transfer->len; 1479 if (pl022->cur_transfer->cs_change) 1480 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 1481 /* Move to next transfer */ 1482 message->state = next_transfer(pl022); 1483 } 1484 out: 1485 /* Handle end of message */ 1486 if (message->state == STATE_DONE) 1487 message->status = 0; 1488 else 1489 message->status = -EIO; 1490 1491 giveback(pl022); 1492 return; 1493 } 1494 1495 /** 1496 * pump_messages - Workqueue function which processes spi message queue 1497 * @data: pointer to private data of SSP driver 1498 * 1499 * This function checks if there is any spi message in the queue that 1500 * needs processing and delegate control to appropriate function 1501 * do_polling_transfer()/do_interrupt_dma_transfer() 1502 * based on the kind of the transfer 1503 * 1504 */ 1505 static void pump_messages(struct work_struct *work) 1506 { 1507 struct pl022 *pl022 = 1508 container_of(work, struct pl022, pump_messages); 1509 unsigned long flags; 1510 bool was_busy = false; 1511 1512 /* Lock queue and check for queue work */ 1513 spin_lock_irqsave(&pl022->queue_lock, flags); 1514 if (list_empty(&pl022->queue) || !pl022->running) { 1515 if (pl022->busy) { 1516 /* nothing more to do - disable spi/ssp and power off */ 1517 writew((readw(SSP_CR1(pl022->virtbase)) & 1518 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1519 1520 if (pl022->master_info->autosuspend_delay > 0) { 1521 pm_runtime_mark_last_busy(&pl022->adev->dev); 1522 pm_runtime_put_autosuspend(&pl022->adev->dev); 1523 } else { 1524 pm_runtime_put(&pl022->adev->dev); 1525 } 1526 } 1527 pl022->busy = false; 1528 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1529 return; 1530 } 1531 1532 /* Make sure we are not already running a message */ 1533 if (pl022->cur_msg) { 1534 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1535 return; 1536 } 1537 /* Extract head of queue */ 1538 pl022->cur_msg = 1539 list_entry(pl022->queue.next, struct spi_message, queue); 1540 1541 list_del_init(&pl022->cur_msg->queue); 1542 if (pl022->busy) 1543 was_busy = true; 1544 else 1545 pl022->busy = true; 1546 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1547 1548 /* Initial message state */ 1549 pl022->cur_msg->state = STATE_START; 1550 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, 1551 struct spi_transfer, transfer_list); 1552 1553 /* Setup the SPI using the per chip configuration */ 1554 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); 1555 if (!was_busy) 1556 /* 1557 * We enable the core voltage and clocks here, then the clocks 1558 * and core will be disabled when this workqueue is run again 1559 * and there is no more work to be done. 1560 */ 1561 pm_runtime_get_sync(&pl022->adev->dev); 1562 1563 restore_state(pl022); 1564 flush(pl022); 1565 1566 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1567 do_polling_transfer(pl022); 1568 else 1569 do_interrupt_dma_transfer(pl022); 1570 } 1571 1572 static int __init init_queue(struct pl022 *pl022) 1573 { 1574 INIT_LIST_HEAD(&pl022->queue); 1575 spin_lock_init(&pl022->queue_lock); 1576 1577 pl022->running = false; 1578 pl022->busy = false; 1579 1580 tasklet_init(&pl022->pump_transfers, pump_transfers, 1581 (unsigned long)pl022); 1582 1583 INIT_WORK(&pl022->pump_messages, pump_messages); 1584 pl022->workqueue = create_singlethread_workqueue( 1585 dev_name(pl022->master->dev.parent)); 1586 if (pl022->workqueue == NULL) 1587 return -EBUSY; 1588 1589 return 0; 1590 } 1591 1592 static int start_queue(struct pl022 *pl022) 1593 { 1594 unsigned long flags; 1595 1596 spin_lock_irqsave(&pl022->queue_lock, flags); 1597 1598 if (pl022->running || pl022->busy) { 1599 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1600 return -EBUSY; 1601 } 1602 1603 pl022->running = true; 1604 pl022->cur_msg = NULL; 1605 pl022->cur_transfer = NULL; 1606 pl022->cur_chip = NULL; 1607 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1608 1609 queue_work(pl022->workqueue, &pl022->pump_messages); 1610 1611 return 0; 1612 } 1613 1614 static int stop_queue(struct pl022 *pl022) 1615 { 1616 unsigned long flags; 1617 unsigned limit = 500; 1618 int status = 0; 1619 1620 spin_lock_irqsave(&pl022->queue_lock, flags); 1621 1622 /* This is a bit lame, but is optimized for the common execution path. 1623 * A wait_queue on the pl022->busy could be used, but then the common 1624 * execution path (pump_messages) would be required to call wake_up or 1625 * friends on every SPI message. Do this instead */ 1626 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { 1627 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1628 msleep(10); 1629 spin_lock_irqsave(&pl022->queue_lock, flags); 1630 } 1631 1632 if (!list_empty(&pl022->queue) || pl022->busy) 1633 status = -EBUSY; 1634 else 1635 pl022->running = false; 1636 1637 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1638 1639 return status; 1640 } 1641 1642 static int destroy_queue(struct pl022 *pl022) 1643 { 1644 int status; 1645 1646 status = stop_queue(pl022); 1647 /* we are unloading the module or failing to load (only two calls 1648 * to this routine), and neither call can handle a return value. 1649 * However, destroy_workqueue calls flush_workqueue, and that will 1650 * block until all work is done. If the reason that stop_queue 1651 * timed out is that the work will never finish, then it does no 1652 * good to call destroy_workqueue, so return anyway. */ 1653 if (status != 0) 1654 return status; 1655 1656 destroy_workqueue(pl022->workqueue); 1657 1658 return 0; 1659 } 1660 1661 static int verify_controller_parameters(struct pl022 *pl022, 1662 struct pl022_config_chip const *chip_info) 1663 { 1664 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1665 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1666 dev_err(&pl022->adev->dev, 1667 "interface is configured incorrectly\n"); 1668 return -EINVAL; 1669 } 1670 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1671 (!pl022->vendor->unidir)) { 1672 dev_err(&pl022->adev->dev, 1673 "unidirectional mode not supported in this " 1674 "hardware version\n"); 1675 return -EINVAL; 1676 } 1677 if ((chip_info->hierarchy != SSP_MASTER) 1678 && (chip_info->hierarchy != SSP_SLAVE)) { 1679 dev_err(&pl022->adev->dev, 1680 "hierarchy is configured incorrectly\n"); 1681 return -EINVAL; 1682 } 1683 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1684 && (chip_info->com_mode != DMA_TRANSFER) 1685 && (chip_info->com_mode != POLLING_TRANSFER)) { 1686 dev_err(&pl022->adev->dev, 1687 "Communication mode is configured incorrectly\n"); 1688 return -EINVAL; 1689 } 1690 switch (chip_info->rx_lev_trig) { 1691 case SSP_RX_1_OR_MORE_ELEM: 1692 case SSP_RX_4_OR_MORE_ELEM: 1693 case SSP_RX_8_OR_MORE_ELEM: 1694 /* These are always OK, all variants can handle this */ 1695 break; 1696 case SSP_RX_16_OR_MORE_ELEM: 1697 if (pl022->vendor->fifodepth < 16) { 1698 dev_err(&pl022->adev->dev, 1699 "RX FIFO Trigger Level is configured incorrectly\n"); 1700 return -EINVAL; 1701 } 1702 break; 1703 case SSP_RX_32_OR_MORE_ELEM: 1704 if (pl022->vendor->fifodepth < 32) { 1705 dev_err(&pl022->adev->dev, 1706 "RX FIFO Trigger Level is configured incorrectly\n"); 1707 return -EINVAL; 1708 } 1709 break; 1710 default: 1711 dev_err(&pl022->adev->dev, 1712 "RX FIFO Trigger Level is configured incorrectly\n"); 1713 return -EINVAL; 1714 break; 1715 } 1716 switch (chip_info->tx_lev_trig) { 1717 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1718 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1719 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1720 /* These are always OK, all variants can handle this */ 1721 break; 1722 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1723 if (pl022->vendor->fifodepth < 16) { 1724 dev_err(&pl022->adev->dev, 1725 "TX FIFO Trigger Level is configured incorrectly\n"); 1726 return -EINVAL; 1727 } 1728 break; 1729 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1730 if (pl022->vendor->fifodepth < 32) { 1731 dev_err(&pl022->adev->dev, 1732 "TX FIFO Trigger Level is configured incorrectly\n"); 1733 return -EINVAL; 1734 } 1735 break; 1736 default: 1737 dev_err(&pl022->adev->dev, 1738 "TX FIFO Trigger Level is configured incorrectly\n"); 1739 return -EINVAL; 1740 break; 1741 } 1742 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1743 if ((chip_info->ctrl_len < SSP_BITS_4) 1744 || (chip_info->ctrl_len > SSP_BITS_32)) { 1745 dev_err(&pl022->adev->dev, 1746 "CTRL LEN is configured incorrectly\n"); 1747 return -EINVAL; 1748 } 1749 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1750 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1751 dev_err(&pl022->adev->dev, 1752 "Wait State is configured incorrectly\n"); 1753 return -EINVAL; 1754 } 1755 /* Half duplex is only available in the ST Micro version */ 1756 if (pl022->vendor->extended_cr) { 1757 if ((chip_info->duplex != 1758 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1759 && (chip_info->duplex != 1760 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1761 dev_err(&pl022->adev->dev, 1762 "Microwire duplex mode is configured incorrectly\n"); 1763 return -EINVAL; 1764 } 1765 } else { 1766 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1767 dev_err(&pl022->adev->dev, 1768 "Microwire half duplex mode requested," 1769 " but this is only available in the" 1770 " ST version of PL022\n"); 1771 return -EINVAL; 1772 } 1773 } 1774 return 0; 1775 } 1776 1777 /** 1778 * pl022_transfer - transfer function registered to SPI master framework 1779 * @spi: spi device which is requesting transfer 1780 * @msg: spi message which is to handled is queued to driver queue 1781 * 1782 * This function is registered to the SPI framework for this SPI master 1783 * controller. It will queue the spi_message in the queue of driver if 1784 * the queue is not stopped and return. 1785 */ 1786 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) 1787 { 1788 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1789 unsigned long flags; 1790 1791 spin_lock_irqsave(&pl022->queue_lock, flags); 1792 1793 if (!pl022->running) { 1794 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1795 return -ESHUTDOWN; 1796 } 1797 msg->actual_length = 0; 1798 msg->status = -EINPROGRESS; 1799 msg->state = STATE_START; 1800 1801 list_add_tail(&msg->queue, &pl022->queue); 1802 if (pl022->running && !pl022->busy) 1803 queue_work(pl022->workqueue, &pl022->pump_messages); 1804 1805 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1806 return 0; 1807 } 1808 1809 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1810 { 1811 return rate / (cpsdvsr * (1 + scr)); 1812 } 1813 1814 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1815 ssp_clock_params * clk_freq) 1816 { 1817 /* Lets calculate the frequency parameters */ 1818 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1819 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1820 best_scr = 0, tmp, found = 0; 1821 1822 rate = clk_get_rate(pl022->clk); 1823 /* cpsdvscr = 2 & scr 0 */ 1824 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1825 /* cpsdvsr = 254 & scr = 255 */ 1826 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1827 1828 if (!((freq <= max_tclk) && (freq >= min_tclk))) { 1829 dev_err(&pl022->adev->dev, 1830 "controller data is incorrect: out of range frequency"); 1831 return -EINVAL; 1832 } 1833 1834 /* 1835 * best_freq will give closest possible available rate (<= requested 1836 * freq) for all values of scr & cpsdvsr. 1837 */ 1838 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1839 while (scr <= SCR_MAX) { 1840 tmp = spi_rate(rate, cpsdvsr, scr); 1841 1842 if (tmp > freq) 1843 scr++; 1844 /* 1845 * If found exact value, update and break. 1846 * If found more closer value, update and continue. 1847 */ 1848 else if ((tmp == freq) || (tmp > best_freq)) { 1849 best_freq = tmp; 1850 best_cpsdvsr = cpsdvsr; 1851 best_scr = scr; 1852 1853 if (tmp == freq) 1854 break; 1855 } 1856 scr++; 1857 } 1858 cpsdvsr += 2; 1859 scr = SCR_MIN; 1860 } 1861 1862 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1863 clk_freq->scr = (u8) (best_scr & 0xFF); 1864 dev_dbg(&pl022->adev->dev, 1865 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1866 freq, best_freq); 1867 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1868 clk_freq->cpsdvsr, clk_freq->scr); 1869 1870 return 0; 1871 } 1872 1873 /* 1874 * A piece of default chip info unless the platform 1875 * supplies it. 1876 */ 1877 static const struct pl022_config_chip pl022_default_chip_info = { 1878 .com_mode = POLLING_TRANSFER, 1879 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1880 .hierarchy = SSP_SLAVE, 1881 .slave_tx_disable = DO_NOT_DRIVE_TX, 1882 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1883 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1884 .ctrl_len = SSP_BITS_8, 1885 .wait_state = SSP_MWIRE_WAIT_ZERO, 1886 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1887 .cs_control = null_cs_control, 1888 }; 1889 1890 /** 1891 * pl022_setup - setup function registered to SPI master framework 1892 * @spi: spi device which is requesting setup 1893 * 1894 * This function is registered to the SPI framework for this SPI master 1895 * controller. If it is the first time when setup is called by this device, 1896 * this function will initialize the runtime state for this chip and save 1897 * the same in the device structure. Else it will update the runtime info 1898 * with the updated chip info. Nothing is really being written to the 1899 * controller hardware here, that is not done until the actual transfer 1900 * commence. 1901 */ 1902 static int pl022_setup(struct spi_device *spi) 1903 { 1904 struct pl022_config_chip const *chip_info; 1905 struct chip_data *chip; 1906 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1907 int status = 0; 1908 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1909 unsigned int bits = spi->bits_per_word; 1910 u32 tmp; 1911 1912 if (!spi->max_speed_hz) 1913 return -EINVAL; 1914 1915 /* Get controller_state if one is supplied */ 1916 chip = spi_get_ctldata(spi); 1917 1918 if (chip == NULL) { 1919 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1920 if (!chip) { 1921 dev_err(&spi->dev, 1922 "cannot allocate controller state\n"); 1923 return -ENOMEM; 1924 } 1925 dev_dbg(&spi->dev, 1926 "allocated memory for controller's runtime state\n"); 1927 } 1928 1929 /* Get controller data if one is supplied */ 1930 chip_info = spi->controller_data; 1931 1932 if (chip_info == NULL) { 1933 chip_info = &pl022_default_chip_info; 1934 /* spi_board_info.controller_data not is supplied */ 1935 dev_dbg(&spi->dev, 1936 "using default controller_data settings\n"); 1937 } else 1938 dev_dbg(&spi->dev, 1939 "using user supplied controller_data settings\n"); 1940 1941 /* 1942 * We can override with custom divisors, else we use the board 1943 * frequency setting 1944 */ 1945 if ((0 == chip_info->clk_freq.cpsdvsr) 1946 && (0 == chip_info->clk_freq.scr)) { 1947 status = calculate_effective_freq(pl022, 1948 spi->max_speed_hz, 1949 &clk_freq); 1950 if (status < 0) 1951 goto err_config_params; 1952 } else { 1953 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1954 if ((clk_freq.cpsdvsr % 2) != 0) 1955 clk_freq.cpsdvsr = 1956 clk_freq.cpsdvsr - 1; 1957 } 1958 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1959 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1960 status = -EINVAL; 1961 dev_err(&spi->dev, 1962 "cpsdvsr is configured incorrectly\n"); 1963 goto err_config_params; 1964 } 1965 1966 status = verify_controller_parameters(pl022, chip_info); 1967 if (status) { 1968 dev_err(&spi->dev, "controller data is incorrect"); 1969 goto err_config_params; 1970 } 1971 1972 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1973 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1974 1975 /* Now set controller state based on controller data */ 1976 chip->xfer_type = chip_info->com_mode; 1977 if (!chip_info->cs_control) { 1978 chip->cs_control = null_cs_control; 1979 dev_warn(&spi->dev, 1980 "chip select function is NULL for this chip\n"); 1981 } else 1982 chip->cs_control = chip_info->cs_control; 1983 1984 if (bits <= 3) { 1985 /* PL022 doesn't support less than 4-bits */ 1986 status = -ENOTSUPP; 1987 goto err_config_params; 1988 } else if (bits <= 8) { 1989 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1990 chip->n_bytes = 1; 1991 chip->read = READING_U8; 1992 chip->write = WRITING_U8; 1993 } else if (bits <= 16) { 1994 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1995 chip->n_bytes = 2; 1996 chip->read = READING_U16; 1997 chip->write = WRITING_U16; 1998 } else { 1999 if (pl022->vendor->max_bpw >= 32) { 2000 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 2001 chip->n_bytes = 4; 2002 chip->read = READING_U32; 2003 chip->write = WRITING_U32; 2004 } else { 2005 dev_err(&spi->dev, 2006 "illegal data size for this controller!\n"); 2007 dev_err(&spi->dev, 2008 "a standard pl022 can only handle " 2009 "1 <= n <= 16 bit words\n"); 2010 status = -ENOTSUPP; 2011 goto err_config_params; 2012 } 2013 } 2014 2015 /* Now Initialize all register settings required for this chip */ 2016 chip->cr0 = 0; 2017 chip->cr1 = 0; 2018 chip->dmacr = 0; 2019 chip->cpsr = 0; 2020 if ((chip_info->com_mode == DMA_TRANSFER) 2021 && ((pl022->master_info)->enable_dma)) { 2022 chip->enable_dma = true; 2023 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 2024 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2025 SSP_DMACR_MASK_RXDMAE, 0); 2026 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2027 SSP_DMACR_MASK_TXDMAE, 1); 2028 } else { 2029 chip->enable_dma = false; 2030 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 2031 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2032 SSP_DMACR_MASK_RXDMAE, 0); 2033 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2034 SSP_DMACR_MASK_TXDMAE, 1); 2035 } 2036 2037 chip->cpsr = clk_freq.cpsdvsr; 2038 2039 /* Special setup for the ST micro extended control registers */ 2040 if (pl022->vendor->extended_cr) { 2041 u32 etx; 2042 2043 if (pl022->vendor->pl023) { 2044 /* These bits are only in the PL023 */ 2045 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 2046 SSP_CR1_MASK_FBCLKDEL_ST, 13); 2047 } else { 2048 /* These bits are in the PL022 but not PL023 */ 2049 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 2050 SSP_CR0_MASK_HALFDUP_ST, 5); 2051 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 2052 SSP_CR0_MASK_CSS_ST, 16); 2053 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2054 SSP_CR0_MASK_FRF_ST, 21); 2055 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 2056 SSP_CR1_MASK_MWAIT_ST, 6); 2057 } 2058 SSP_WRITE_BITS(chip->cr0, bits - 1, 2059 SSP_CR0_MASK_DSS_ST, 0); 2060 2061 if (spi->mode & SPI_LSB_FIRST) { 2062 tmp = SSP_RX_LSB; 2063 etx = SSP_TX_LSB; 2064 } else { 2065 tmp = SSP_RX_MSB; 2066 etx = SSP_TX_MSB; 2067 } 2068 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2069 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2070 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2071 SSP_CR1_MASK_RXIFLSEL_ST, 7); 2072 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2073 SSP_CR1_MASK_TXIFLSEL_ST, 10); 2074 } else { 2075 SSP_WRITE_BITS(chip->cr0, bits - 1, 2076 SSP_CR0_MASK_DSS, 0); 2077 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2078 SSP_CR0_MASK_FRF, 4); 2079 } 2080 2081 /* Stuff that is common for all versions */ 2082 if (spi->mode & SPI_CPOL) 2083 tmp = SSP_CLK_POL_IDLE_HIGH; 2084 else 2085 tmp = SSP_CLK_POL_IDLE_LOW; 2086 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2087 2088 if (spi->mode & SPI_CPHA) 2089 tmp = SSP_CLK_SECOND_EDGE; 2090 else 2091 tmp = SSP_CLK_FIRST_EDGE; 2092 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2093 2094 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2095 /* Loopback is available on all versions except PL023 */ 2096 if (pl022->vendor->loopback) { 2097 if (spi->mode & SPI_LOOP) 2098 tmp = LOOPBACK_ENABLED; 2099 else 2100 tmp = LOOPBACK_DISABLED; 2101 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2102 } 2103 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2104 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2105 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2106 3); 2107 2108 /* Save controller_state */ 2109 spi_set_ctldata(spi, chip); 2110 return status; 2111 err_config_params: 2112 spi_set_ctldata(spi, NULL); 2113 kfree(chip); 2114 return status; 2115 } 2116 2117 /** 2118 * pl022_cleanup - cleanup function registered to SPI master framework 2119 * @spi: spi device which is requesting cleanup 2120 * 2121 * This function is registered to the SPI framework for this SPI master 2122 * controller. It will free the runtime state of chip. 2123 */ 2124 static void pl022_cleanup(struct spi_device *spi) 2125 { 2126 struct chip_data *chip = spi_get_ctldata(spi); 2127 2128 spi_set_ctldata(spi, NULL); 2129 kfree(chip); 2130 } 2131 2132 static int __devinit 2133 pl022_probe(struct amba_device *adev, const struct amba_id *id) 2134 { 2135 struct device *dev = &adev->dev; 2136 struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2137 struct spi_master *master; 2138 struct pl022 *pl022 = NULL; /*Data for this driver */ 2139 int status = 0; 2140 2141 dev_info(&adev->dev, 2142 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2143 if (platform_info == NULL) { 2144 dev_err(&adev->dev, "probe - no platform data supplied\n"); 2145 status = -ENODEV; 2146 goto err_no_pdata; 2147 } 2148 2149 /* Allocate master with space for data */ 2150 master = spi_alloc_master(dev, sizeof(struct pl022)); 2151 if (master == NULL) { 2152 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2153 status = -ENOMEM; 2154 goto err_no_master; 2155 } 2156 2157 pl022 = spi_master_get_devdata(master); 2158 pl022->master = master; 2159 pl022->master_info = platform_info; 2160 pl022->adev = adev; 2161 pl022->vendor = id->data; 2162 2163 /* 2164 * Bus Number Which has been Assigned to this SSP controller 2165 * on this board 2166 */ 2167 master->bus_num = platform_info->bus_id; 2168 master->num_chipselect = platform_info->num_chipselect; 2169 master->cleanup = pl022_cleanup; 2170 master->setup = pl022_setup; 2171 master->transfer = pl022_transfer; 2172 2173 /* 2174 * Supports mode 0-3, loopback, and active low CS. Transfers are 2175 * always MS bit first on the original pl022. 2176 */ 2177 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2178 if (pl022->vendor->extended_cr) 2179 master->mode_bits |= SPI_LSB_FIRST; 2180 2181 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2182 2183 status = amba_request_regions(adev, NULL); 2184 if (status) 2185 goto err_no_ioregion; 2186 2187 pl022->phybase = adev->res.start; 2188 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2189 if (pl022->virtbase == NULL) { 2190 status = -ENOMEM; 2191 goto err_no_ioremap; 2192 } 2193 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2194 adev->res.start, pl022->virtbase); 2195 2196 pl022->clk = clk_get(&adev->dev, NULL); 2197 if (IS_ERR(pl022->clk)) { 2198 status = PTR_ERR(pl022->clk); 2199 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2200 goto err_no_clk; 2201 } 2202 2203 status = clk_prepare(pl022->clk); 2204 if (status) { 2205 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 2206 goto err_clk_prep; 2207 } 2208 2209 status = clk_enable(pl022->clk); 2210 if (status) { 2211 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2212 goto err_no_clk_en; 2213 } 2214 2215 /* Disable SSP */ 2216 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2217 SSP_CR1(pl022->virtbase)); 2218 load_ssp_default_config(pl022); 2219 2220 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2221 pl022); 2222 if (status < 0) { 2223 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2224 goto err_no_irq; 2225 } 2226 2227 /* Get DMA channels */ 2228 if (platform_info->enable_dma) { 2229 status = pl022_dma_probe(pl022); 2230 if (status != 0) 2231 platform_info->enable_dma = 0; 2232 } 2233 2234 /* Initialize and start queue */ 2235 status = init_queue(pl022); 2236 if (status != 0) { 2237 dev_err(&adev->dev, "probe - problem initializing queue\n"); 2238 goto err_init_queue; 2239 } 2240 status = start_queue(pl022); 2241 if (status != 0) { 2242 dev_err(&adev->dev, "probe - problem starting queue\n"); 2243 goto err_start_queue; 2244 } 2245 /* Register with the SPI framework */ 2246 amba_set_drvdata(adev, pl022); 2247 status = spi_register_master(master); 2248 if (status != 0) { 2249 dev_err(&adev->dev, 2250 "probe - problem registering spi master\n"); 2251 goto err_spi_register; 2252 } 2253 dev_dbg(dev, "probe succeeded\n"); 2254 2255 /* let runtime pm put suspend */ 2256 if (platform_info->autosuspend_delay > 0) { 2257 dev_info(&adev->dev, 2258 "will use autosuspend for runtime pm, delay %dms\n", 2259 platform_info->autosuspend_delay); 2260 pm_runtime_set_autosuspend_delay(dev, 2261 platform_info->autosuspend_delay); 2262 pm_runtime_use_autosuspend(dev); 2263 pm_runtime_put_autosuspend(dev); 2264 } else { 2265 pm_runtime_put(dev); 2266 } 2267 return 0; 2268 2269 err_spi_register: 2270 err_start_queue: 2271 err_init_queue: 2272 destroy_queue(pl022); 2273 if (platform_info->enable_dma) 2274 pl022_dma_remove(pl022); 2275 2276 free_irq(adev->irq[0], pl022); 2277 err_no_irq: 2278 clk_disable(pl022->clk); 2279 err_no_clk_en: 2280 clk_unprepare(pl022->clk); 2281 err_clk_prep: 2282 clk_put(pl022->clk); 2283 err_no_clk: 2284 iounmap(pl022->virtbase); 2285 err_no_ioremap: 2286 amba_release_regions(adev); 2287 err_no_ioregion: 2288 spi_master_put(master); 2289 err_no_master: 2290 err_no_pdata: 2291 return status; 2292 } 2293 2294 static int __devexit 2295 pl022_remove(struct amba_device *adev) 2296 { 2297 struct pl022 *pl022 = amba_get_drvdata(adev); 2298 2299 if (!pl022) 2300 return 0; 2301 2302 /* 2303 * undo pm_runtime_put() in probe. I assume that we're not 2304 * accessing the primecell here. 2305 */ 2306 pm_runtime_get_noresume(&adev->dev); 2307 2308 /* Remove the queue */ 2309 if (destroy_queue(pl022) != 0) 2310 dev_err(&adev->dev, "queue remove failed\n"); 2311 load_ssp_default_config(pl022); 2312 if (pl022->master_info->enable_dma) 2313 pl022_dma_remove(pl022); 2314 2315 free_irq(adev->irq[0], pl022); 2316 clk_disable(pl022->clk); 2317 clk_unprepare(pl022->clk); 2318 clk_put(pl022->clk); 2319 iounmap(pl022->virtbase); 2320 amba_release_regions(adev); 2321 tasklet_disable(&pl022->pump_transfers); 2322 spi_unregister_master(pl022->master); 2323 spi_master_put(pl022->master); 2324 amba_set_drvdata(adev, NULL); 2325 return 0; 2326 } 2327 2328 #ifdef CONFIG_SUSPEND 2329 static int pl022_suspend(struct device *dev) 2330 { 2331 struct pl022 *pl022 = dev_get_drvdata(dev); 2332 int status = 0; 2333 2334 status = stop_queue(pl022); 2335 if (status) { 2336 dev_warn(dev, "suspend cannot stop queue\n"); 2337 return status; 2338 } 2339 2340 dev_dbg(dev, "suspended\n"); 2341 return 0; 2342 } 2343 2344 static int pl022_resume(struct device *dev) 2345 { 2346 struct pl022 *pl022 = dev_get_drvdata(dev); 2347 int status = 0; 2348 2349 /* Start the queue running */ 2350 status = start_queue(pl022); 2351 if (status) 2352 dev_err(dev, "problem starting queue (%d)\n", status); 2353 else 2354 dev_dbg(dev, "resumed\n"); 2355 2356 return status; 2357 } 2358 #endif /* CONFIG_PM */ 2359 2360 #ifdef CONFIG_PM_RUNTIME 2361 static int pl022_runtime_suspend(struct device *dev) 2362 { 2363 struct pl022 *pl022 = dev_get_drvdata(dev); 2364 2365 clk_disable(pl022->clk); 2366 amba_vcore_disable(pl022->adev); 2367 2368 return 0; 2369 } 2370 2371 static int pl022_runtime_resume(struct device *dev) 2372 { 2373 struct pl022 *pl022 = dev_get_drvdata(dev); 2374 2375 amba_vcore_enable(pl022->adev); 2376 clk_enable(pl022->clk); 2377 2378 return 0; 2379 } 2380 #endif 2381 2382 static const struct dev_pm_ops pl022_dev_pm_ops = { 2383 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2384 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2385 }; 2386 2387 static struct vendor_data vendor_arm = { 2388 .fifodepth = 8, 2389 .max_bpw = 16, 2390 .unidir = false, 2391 .extended_cr = false, 2392 .pl023 = false, 2393 .loopback = true, 2394 }; 2395 2396 static struct vendor_data vendor_st = { 2397 .fifodepth = 32, 2398 .max_bpw = 32, 2399 .unidir = false, 2400 .extended_cr = true, 2401 .pl023 = false, 2402 .loopback = true, 2403 }; 2404 2405 static struct vendor_data vendor_st_pl023 = { 2406 .fifodepth = 32, 2407 .max_bpw = 32, 2408 .unidir = false, 2409 .extended_cr = true, 2410 .pl023 = true, 2411 .loopback = false, 2412 }; 2413 2414 static struct vendor_data vendor_db5500_pl023 = { 2415 .fifodepth = 32, 2416 .max_bpw = 32, 2417 .unidir = false, 2418 .extended_cr = true, 2419 .pl023 = true, 2420 .loopback = true, 2421 }; 2422 2423 static struct amba_id pl022_ids[] = { 2424 { 2425 /* 2426 * ARM PL022 variant, this has a 16bit wide 2427 * and 8 locations deep TX/RX FIFO 2428 */ 2429 .id = 0x00041022, 2430 .mask = 0x000fffff, 2431 .data = &vendor_arm, 2432 }, 2433 { 2434 /* 2435 * ST Micro derivative, this has 32bit wide 2436 * and 32 locations deep TX/RX FIFO 2437 */ 2438 .id = 0x01080022, 2439 .mask = 0xffffffff, 2440 .data = &vendor_st, 2441 }, 2442 { 2443 /* 2444 * ST-Ericsson derivative "PL023" (this is not 2445 * an official ARM number), this is a PL022 SSP block 2446 * stripped to SPI mode only, it has 32bit wide 2447 * and 32 locations deep TX/RX FIFO but no extended 2448 * CR0/CR1 register 2449 */ 2450 .id = 0x00080023, 2451 .mask = 0xffffffff, 2452 .data = &vendor_st_pl023, 2453 }, 2454 { 2455 .id = 0x10080023, 2456 .mask = 0xffffffff, 2457 .data = &vendor_db5500_pl023, 2458 }, 2459 { 0, 0 }, 2460 }; 2461 2462 static struct amba_driver pl022_driver = { 2463 .drv = { 2464 .name = "ssp-pl022", 2465 .pm = &pl022_dev_pm_ops, 2466 }, 2467 .id_table = pl022_ids, 2468 .probe = pl022_probe, 2469 .remove = __devexit_p(pl022_remove), 2470 }; 2471 2472 static int __init pl022_init(void) 2473 { 2474 return amba_driver_register(&pl022_driver); 2475 } 2476 subsys_initcall(pl022_init); 2477 2478 static void __exit pl022_exit(void) 2479 { 2480 amba_driver_unregister(&pl022_driver); 2481 } 2482 module_exit(pl022_exit); 2483 2484 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2485 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2486 MODULE_LICENSE("GPL"); 2487