1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2012 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/delay.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/amba/bus.h> 36 #include <linux/amba/pl022.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 #include <linux/dmaengine.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/scatterlist.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/gpio.h> 44 #include <linux/of_gpio.h> 45 #include <linux/pinctrl/consumer.h> 46 47 /* 48 * This macro is used to define some register default values. 49 * reg is masked with mask, the OR:ed with an (again masked) 50 * val shifted sb steps to the left. 51 */ 52 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 54 55 /* 56 * This macro is also used to define some default values. 57 * It will just shift val by sb steps to the left and mask 58 * the result with mask. 59 */ 60 #define GEN_MASK_BITS(val, mask, sb) \ 61 (((val)<<(sb)) & (mask)) 62 63 #define DRIVE_TX 0 64 #define DO_NOT_DRIVE_TX 1 65 66 #define DO_NOT_QUEUE_DMA 0 67 #define QUEUE_DMA 1 68 69 #define RX_TRANSFER 1 70 #define TX_TRANSFER 2 71 72 /* 73 * Macros to access SSP Registers with their offsets 74 */ 75 #define SSP_CR0(r) (r + 0x000) 76 #define SSP_CR1(r) (r + 0x004) 77 #define SSP_DR(r) (r + 0x008) 78 #define SSP_SR(r) (r + 0x00C) 79 #define SSP_CPSR(r) (r + 0x010) 80 #define SSP_IMSC(r) (r + 0x014) 81 #define SSP_RIS(r) (r + 0x018) 82 #define SSP_MIS(r) (r + 0x01C) 83 #define SSP_ICR(r) (r + 0x020) 84 #define SSP_DMACR(r) (r + 0x024) 85 #define SSP_ITCR(r) (r + 0x080) 86 #define SSP_ITIP(r) (r + 0x084) 87 #define SSP_ITOP(r) (r + 0x088) 88 #define SSP_TDR(r) (r + 0x08C) 89 90 #define SSP_PID0(r) (r + 0xFE0) 91 #define SSP_PID1(r) (r + 0xFE4) 92 #define SSP_PID2(r) (r + 0xFE8) 93 #define SSP_PID3(r) (r + 0xFEC) 94 95 #define SSP_CID0(r) (r + 0xFF0) 96 #define SSP_CID1(r) (r + 0xFF4) 97 #define SSP_CID2(r) (r + 0xFF8) 98 #define SSP_CID3(r) (r + 0xFFC) 99 100 /* 101 * SSP Control Register 0 - SSP_CR0 102 */ 103 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 104 #define SSP_CR0_MASK_FRF (0x3UL << 4) 105 #define SSP_CR0_MASK_SPO (0x1UL << 6) 106 #define SSP_CR0_MASK_SPH (0x1UL << 7) 107 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 108 109 /* 110 * The ST version of this block moves som bits 111 * in SSP_CR0 and extends it to 32 bits 112 */ 113 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 114 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 115 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 116 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 117 118 /* 119 * SSP Control Register 0 - SSP_CR1 120 */ 121 #define SSP_CR1_MASK_LBM (0x1UL << 0) 122 #define SSP_CR1_MASK_SSE (0x1UL << 1) 123 #define SSP_CR1_MASK_MS (0x1UL << 2) 124 #define SSP_CR1_MASK_SOD (0x1UL << 3) 125 126 /* 127 * The ST version of this block adds some bits 128 * in SSP_CR1 129 */ 130 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 131 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 132 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 133 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 134 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 135 /* This one is only in the PL023 variant */ 136 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 137 138 /* 139 * SSP Status Register - SSP_SR 140 */ 141 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 142 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 143 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 144 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 145 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 146 147 /* 148 * SSP Clock Prescale Register - SSP_CPSR 149 */ 150 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 151 152 /* 153 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 154 */ 155 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 156 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 157 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 158 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 159 160 /* 161 * SSP Raw Interrupt Status Register - SSP_RIS 162 */ 163 /* Receive Overrun Raw Interrupt status */ 164 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 165 /* Receive Timeout Raw Interrupt status */ 166 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 167 /* Receive FIFO Raw Interrupt status */ 168 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 169 /* Transmit FIFO Raw Interrupt status */ 170 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 171 172 /* 173 * SSP Masked Interrupt Status Register - SSP_MIS 174 */ 175 /* Receive Overrun Masked Interrupt status */ 176 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 177 /* Receive Timeout Masked Interrupt status */ 178 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 179 /* Receive FIFO Masked Interrupt status */ 180 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 181 /* Transmit FIFO Masked Interrupt status */ 182 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 183 184 /* 185 * SSP Interrupt Clear Register - SSP_ICR 186 */ 187 /* Receive Overrun Raw Clear Interrupt bit */ 188 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 189 /* Receive Timeout Clear Interrupt bit */ 190 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 191 192 /* 193 * SSP DMA Control Register - SSP_DMACR 194 */ 195 /* Receive DMA Enable bit */ 196 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 197 /* Transmit DMA Enable bit */ 198 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 199 200 /* 201 * SSP Integration Test control Register - SSP_ITCR 202 */ 203 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 204 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 205 206 /* 207 * SSP Integration Test Input Register - SSP_ITIP 208 */ 209 #define ITIP_MASK_SSPRXD (0x1UL << 0) 210 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 211 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 212 #define ITIP_MASK_RXDMAC (0x1UL << 3) 213 #define ITIP_MASK_TXDMAC (0x1UL << 4) 214 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 215 216 /* 217 * SSP Integration Test output Register - SSP_ITOP 218 */ 219 #define ITOP_MASK_SSPTXD (0x1UL << 0) 220 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 221 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 222 #define ITOP_MASK_SSPOEn (0x1UL << 3) 223 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 224 #define ITOP_MASK_RORINTR (0x1UL << 5) 225 #define ITOP_MASK_RTINTR (0x1UL << 6) 226 #define ITOP_MASK_RXINTR (0x1UL << 7) 227 #define ITOP_MASK_TXINTR (0x1UL << 8) 228 #define ITOP_MASK_INTR (0x1UL << 9) 229 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 230 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 231 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 232 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 233 234 /* 235 * SSP Test Data Register - SSP_TDR 236 */ 237 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 238 239 /* 240 * Message State 241 * we use the spi_message.state (void *) pointer to 242 * hold a single state value, that's why all this 243 * (void *) casting is done here. 244 */ 245 #define STATE_START ((void *) 0) 246 #define STATE_RUNNING ((void *) 1) 247 #define STATE_DONE ((void *) 2) 248 #define STATE_ERROR ((void *) -1) 249 250 /* 251 * SSP State - Whether Enabled or Disabled 252 */ 253 #define SSP_DISABLED (0) 254 #define SSP_ENABLED (1) 255 256 /* 257 * SSP DMA State - Whether DMA Enabled or Disabled 258 */ 259 #define SSP_DMA_DISABLED (0) 260 #define SSP_DMA_ENABLED (1) 261 262 /* 263 * SSP Clock Defaults 264 */ 265 #define SSP_DEFAULT_CLKRATE 0x2 266 #define SSP_DEFAULT_PRESCALE 0x40 267 268 /* 269 * SSP Clock Parameter ranges 270 */ 271 #define CPSDVR_MIN 0x02 272 #define CPSDVR_MAX 0xFE 273 #define SCR_MIN 0x00 274 #define SCR_MAX 0xFF 275 276 /* 277 * SSP Interrupt related Macros 278 */ 279 #define DEFAULT_SSP_REG_IMSC 0x0UL 280 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 281 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 282 283 #define CLEAR_ALL_INTERRUPTS 0x3 284 285 #define SPI_POLLING_TIMEOUT 1000 286 287 /* 288 * The type of reading going on on this chip 289 */ 290 enum ssp_reading { 291 READING_NULL, 292 READING_U8, 293 READING_U16, 294 READING_U32 295 }; 296 297 /** 298 * The type of writing going on on this chip 299 */ 300 enum ssp_writing { 301 WRITING_NULL, 302 WRITING_U8, 303 WRITING_U16, 304 WRITING_U32 305 }; 306 307 /** 308 * struct vendor_data - vendor-specific config parameters 309 * for PL022 derivates 310 * @fifodepth: depth of FIFOs (both) 311 * @max_bpw: maximum number of bits per word 312 * @unidir: supports unidirection transfers 313 * @extended_cr: 32 bit wide control register 0 with extra 314 * features and extra features in CR1 as found in the ST variants 315 * @pl023: supports a subset of the ST extensions called "PL023" 316 */ 317 struct vendor_data { 318 int fifodepth; 319 int max_bpw; 320 bool unidir; 321 bool extended_cr; 322 bool pl023; 323 bool loopback; 324 }; 325 326 /** 327 * struct pl022 - This is the private SSP driver data structure 328 * @adev: AMBA device model hookup 329 * @vendor: vendor data for the IP block 330 * @phybase: the physical memory where the SSP device resides 331 * @virtbase: the virtual memory where the SSP is mapped 332 * @clk: outgoing clock "SPICLK" for the SPI bus 333 * @master: SPI framework hookup 334 * @master_info: controller-specific data from machine setup 335 * @kworker: thread struct for message pump 336 * @kworker_task: pointer to task for message pump kworker thread 337 * @pump_messages: work struct for scheduling work to the message pump 338 * @queue_lock: spinlock to syncronise access to message queue 339 * @queue: message queue 340 * @busy: message pump is busy 341 * @running: message pump is running 342 * @pump_transfers: Tasklet used in Interrupt Transfer mode 343 * @cur_msg: Pointer to current spi_message being processed 344 * @cur_transfer: Pointer to current spi_transfer 345 * @cur_chip: pointer to current clients chip(assigned from controller_state) 346 * @next_msg_cs_active: the next message in the queue has been examined 347 * and it was found that it uses the same chip select as the previous 348 * message, so we left it active after the previous transfer, and it's 349 * active already. 350 * @tx: current position in TX buffer to be read 351 * @tx_end: end position in TX buffer to be read 352 * @rx: current position in RX buffer to be written 353 * @rx_end: end position in RX buffer to be written 354 * @read: the type of read currently going on 355 * @write: the type of write currently going on 356 * @exp_fifo_level: expected FIFO level 357 * @dma_rx_channel: optional channel for RX DMA 358 * @dma_tx_channel: optional channel for TX DMA 359 * @sgt_rx: scattertable for the RX transfer 360 * @sgt_tx: scattertable for the TX transfer 361 * @dummypage: a dummy page used for driving data on the bus with DMA 362 * @cur_cs: current chip select (gpio) 363 * @chipselects: list of chipselects (gpios) 364 */ 365 struct pl022 { 366 struct amba_device *adev; 367 struct vendor_data *vendor; 368 resource_size_t phybase; 369 void __iomem *virtbase; 370 struct clk *clk; 371 struct spi_master *master; 372 struct pl022_ssp_controller *master_info; 373 /* Message per-transfer pump */ 374 struct tasklet_struct pump_transfers; 375 struct spi_message *cur_msg; 376 struct spi_transfer *cur_transfer; 377 struct chip_data *cur_chip; 378 bool next_msg_cs_active; 379 void *tx; 380 void *tx_end; 381 void *rx; 382 void *rx_end; 383 enum ssp_reading read; 384 enum ssp_writing write; 385 u32 exp_fifo_level; 386 enum ssp_rx_level_trig rx_lev_trig; 387 enum ssp_tx_level_trig tx_lev_trig; 388 /* DMA settings */ 389 #ifdef CONFIG_DMA_ENGINE 390 struct dma_chan *dma_rx_channel; 391 struct dma_chan *dma_tx_channel; 392 struct sg_table sgt_rx; 393 struct sg_table sgt_tx; 394 char *dummypage; 395 bool dma_running; 396 #endif 397 int cur_cs; 398 int *chipselects; 399 }; 400 401 /** 402 * struct chip_data - To maintain runtime state of SSP for each client chip 403 * @cr0: Value of control register CR0 of SSP - on later ST variants this 404 * register is 32 bits wide rather than just 16 405 * @cr1: Value of control register CR1 of SSP 406 * @dmacr: Value of DMA control Register of SSP 407 * @cpsr: Value of Clock prescale register 408 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 409 * @enable_dma: Whether to enable DMA or not 410 * @read: function ptr to be used to read when doing xfer for this chip 411 * @write: function ptr to be used to write when doing xfer for this chip 412 * @cs_control: chip select callback provided by chip 413 * @xfer_type: polling/interrupt/DMA 414 * 415 * Runtime state of the SSP controller, maintained per chip, 416 * This would be set according to the current message that would be served 417 */ 418 struct chip_data { 419 u32 cr0; 420 u16 cr1; 421 u16 dmacr; 422 u16 cpsr; 423 u8 n_bytes; 424 bool enable_dma; 425 enum ssp_reading read; 426 enum ssp_writing write; 427 void (*cs_control) (u32 command); 428 int xfer_type; 429 }; 430 431 /** 432 * null_cs_control - Dummy chip select function 433 * @command: select/delect the chip 434 * 435 * If no chip select function is provided by client this is used as dummy 436 * chip select 437 */ 438 static void null_cs_control(u32 command) 439 { 440 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 441 } 442 443 static void pl022_cs_control(struct pl022 *pl022, u32 command) 444 { 445 if (gpio_is_valid(pl022->cur_cs)) 446 gpio_set_value(pl022->cur_cs, command); 447 else 448 pl022->cur_chip->cs_control(command); 449 } 450 451 /** 452 * giveback - current spi_message is over, schedule next message and call 453 * callback of this message. Assumes that caller already 454 * set message->status; dma and pio irqs are blocked 455 * @pl022: SSP driver private data structure 456 */ 457 static void giveback(struct pl022 *pl022) 458 { 459 struct spi_transfer *last_transfer; 460 pl022->next_msg_cs_active = false; 461 462 last_transfer = list_entry(pl022->cur_msg->transfers.prev, 463 struct spi_transfer, 464 transfer_list); 465 466 /* Delay if requested before any change in chip select */ 467 if (last_transfer->delay_usecs) 468 /* 469 * FIXME: This runs in interrupt context. 470 * Is this really smart? 471 */ 472 udelay(last_transfer->delay_usecs); 473 474 if (!last_transfer->cs_change) { 475 struct spi_message *next_msg; 476 477 /* 478 * cs_change was not set. We can keep the chip select 479 * enabled if there is message in the queue and it is 480 * for the same spi device. 481 * 482 * We cannot postpone this until pump_messages, because 483 * after calling msg->complete (below) the driver that 484 * sent the current message could be unloaded, which 485 * could invalidate the cs_control() callback... 486 */ 487 /* get a pointer to the next message, if any */ 488 next_msg = spi_get_next_queued_message(pl022->master); 489 490 /* 491 * see if the next and current messages point 492 * to the same spi device. 493 */ 494 if (next_msg && next_msg->spi != pl022->cur_msg->spi) 495 next_msg = NULL; 496 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 497 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 498 else 499 pl022->next_msg_cs_active = true; 500 501 } 502 503 pl022->cur_msg = NULL; 504 pl022->cur_transfer = NULL; 505 pl022->cur_chip = NULL; 506 spi_finalize_current_message(pl022->master); 507 508 /* disable the SPI/SSP operation */ 509 writew((readw(SSP_CR1(pl022->virtbase)) & 510 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 511 512 } 513 514 /** 515 * flush - flush the FIFO to reach a clean state 516 * @pl022: SSP driver private data structure 517 */ 518 static int flush(struct pl022 *pl022) 519 { 520 unsigned long limit = loops_per_jiffy << 1; 521 522 dev_dbg(&pl022->adev->dev, "flush\n"); 523 do { 524 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 525 readw(SSP_DR(pl022->virtbase)); 526 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 527 528 pl022->exp_fifo_level = 0; 529 530 return limit; 531 } 532 533 /** 534 * restore_state - Load configuration of current chip 535 * @pl022: SSP driver private data structure 536 */ 537 static void restore_state(struct pl022 *pl022) 538 { 539 struct chip_data *chip = pl022->cur_chip; 540 541 if (pl022->vendor->extended_cr) 542 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 543 else 544 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 545 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 546 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 547 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 548 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 549 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 550 } 551 552 /* 553 * Default SSP Register Values 554 */ 555 #define DEFAULT_SSP_REG_CR0 ( \ 556 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 557 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 558 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 559 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 560 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 561 ) 562 563 /* ST versions have slightly different bit layout */ 564 #define DEFAULT_SSP_REG_CR0_ST ( \ 565 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 566 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 567 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 568 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 569 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 570 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 571 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 572 ) 573 574 /* The PL023 version is slightly different again */ 575 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 576 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 577 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 578 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 579 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 580 ) 581 582 #define DEFAULT_SSP_REG_CR1 ( \ 583 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 584 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 585 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 586 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 587 ) 588 589 /* ST versions extend this register to use all 16 bits */ 590 #define DEFAULT_SSP_REG_CR1_ST ( \ 591 DEFAULT_SSP_REG_CR1 | \ 592 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 593 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 594 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 595 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 596 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 597 ) 598 599 /* 600 * The PL023 variant has further differences: no loopback mode, no microwire 601 * support, and a new clock feedback delay setting. 602 */ 603 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 604 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 605 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 606 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 607 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 608 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 609 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 610 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 611 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 612 ) 613 614 #define DEFAULT_SSP_REG_CPSR ( \ 615 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 616 ) 617 618 #define DEFAULT_SSP_REG_DMACR (\ 619 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 620 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 621 ) 622 623 /** 624 * load_ssp_default_config - Load default configuration for SSP 625 * @pl022: SSP driver private data structure 626 */ 627 static void load_ssp_default_config(struct pl022 *pl022) 628 { 629 if (pl022->vendor->pl023) { 630 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 631 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 632 } else if (pl022->vendor->extended_cr) { 633 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 634 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 635 } else { 636 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 637 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 638 } 639 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 640 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 641 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 642 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 643 } 644 645 /** 646 * This will write to TX and read from RX according to the parameters 647 * set in pl022. 648 */ 649 static void readwriter(struct pl022 *pl022) 650 { 651 652 /* 653 * The FIFO depth is different between primecell variants. 654 * I believe filling in too much in the FIFO might cause 655 * errons in 8bit wide transfers on ARM variants (just 8 words 656 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 657 * 658 * To prevent this issue, the TX FIFO is only filled to the 659 * unused RX FIFO fill length, regardless of what the TX 660 * FIFO status flag indicates. 661 */ 662 dev_dbg(&pl022->adev->dev, 663 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 664 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 665 666 /* Read as much as you can */ 667 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 668 && (pl022->rx < pl022->rx_end)) { 669 switch (pl022->read) { 670 case READING_NULL: 671 readw(SSP_DR(pl022->virtbase)); 672 break; 673 case READING_U8: 674 *(u8 *) (pl022->rx) = 675 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 676 break; 677 case READING_U16: 678 *(u16 *) (pl022->rx) = 679 (u16) readw(SSP_DR(pl022->virtbase)); 680 break; 681 case READING_U32: 682 *(u32 *) (pl022->rx) = 683 readl(SSP_DR(pl022->virtbase)); 684 break; 685 } 686 pl022->rx += (pl022->cur_chip->n_bytes); 687 pl022->exp_fifo_level--; 688 } 689 /* 690 * Write as much as possible up to the RX FIFO size 691 */ 692 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 693 && (pl022->tx < pl022->tx_end)) { 694 switch (pl022->write) { 695 case WRITING_NULL: 696 writew(0x0, SSP_DR(pl022->virtbase)); 697 break; 698 case WRITING_U8: 699 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 700 break; 701 case WRITING_U16: 702 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 703 break; 704 case WRITING_U32: 705 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 706 break; 707 } 708 pl022->tx += (pl022->cur_chip->n_bytes); 709 pl022->exp_fifo_level++; 710 /* 711 * This inner reader takes care of things appearing in the RX 712 * FIFO as we're transmitting. This will happen a lot since the 713 * clock starts running when you put things into the TX FIFO, 714 * and then things are continuously clocked into the RX FIFO. 715 */ 716 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 717 && (pl022->rx < pl022->rx_end)) { 718 switch (pl022->read) { 719 case READING_NULL: 720 readw(SSP_DR(pl022->virtbase)); 721 break; 722 case READING_U8: 723 *(u8 *) (pl022->rx) = 724 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 725 break; 726 case READING_U16: 727 *(u16 *) (pl022->rx) = 728 (u16) readw(SSP_DR(pl022->virtbase)); 729 break; 730 case READING_U32: 731 *(u32 *) (pl022->rx) = 732 readl(SSP_DR(pl022->virtbase)); 733 break; 734 } 735 pl022->rx += (pl022->cur_chip->n_bytes); 736 pl022->exp_fifo_level--; 737 } 738 } 739 /* 740 * When we exit here the TX FIFO should be full and the RX FIFO 741 * should be empty 742 */ 743 } 744 745 /** 746 * next_transfer - Move to the Next transfer in the current spi message 747 * @pl022: SSP driver private data structure 748 * 749 * This function moves though the linked list of spi transfers in the 750 * current spi message and returns with the state of current spi 751 * message i.e whether its last transfer is done(STATE_DONE) or 752 * Next transfer is ready(STATE_RUNNING) 753 */ 754 static void *next_transfer(struct pl022 *pl022) 755 { 756 struct spi_message *msg = pl022->cur_msg; 757 struct spi_transfer *trans = pl022->cur_transfer; 758 759 /* Move to next transfer */ 760 if (trans->transfer_list.next != &msg->transfers) { 761 pl022->cur_transfer = 762 list_entry(trans->transfer_list.next, 763 struct spi_transfer, transfer_list); 764 return STATE_RUNNING; 765 } 766 return STATE_DONE; 767 } 768 769 /* 770 * This DMA functionality is only compiled in if we have 771 * access to the generic DMA devices/DMA engine. 772 */ 773 #ifdef CONFIG_DMA_ENGINE 774 static void unmap_free_dma_scatter(struct pl022 *pl022) 775 { 776 /* Unmap and free the SG tables */ 777 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 778 pl022->sgt_tx.nents, DMA_TO_DEVICE); 779 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 780 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 781 sg_free_table(&pl022->sgt_rx); 782 sg_free_table(&pl022->sgt_tx); 783 } 784 785 static void dma_callback(void *data) 786 { 787 struct pl022 *pl022 = data; 788 struct spi_message *msg = pl022->cur_msg; 789 790 BUG_ON(!pl022->sgt_rx.sgl); 791 792 #ifdef VERBOSE_DEBUG 793 /* 794 * Optionally dump out buffers to inspect contents, this is 795 * good if you want to convince yourself that the loopback 796 * read/write contents are the same, when adopting to a new 797 * DMA engine. 798 */ 799 { 800 struct scatterlist *sg; 801 unsigned int i; 802 803 dma_sync_sg_for_cpu(&pl022->adev->dev, 804 pl022->sgt_rx.sgl, 805 pl022->sgt_rx.nents, 806 DMA_FROM_DEVICE); 807 808 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 809 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 810 print_hex_dump(KERN_ERR, "SPI RX: ", 811 DUMP_PREFIX_OFFSET, 812 16, 813 1, 814 sg_virt(sg), 815 sg_dma_len(sg), 816 1); 817 } 818 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 819 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 820 print_hex_dump(KERN_ERR, "SPI TX: ", 821 DUMP_PREFIX_OFFSET, 822 16, 823 1, 824 sg_virt(sg), 825 sg_dma_len(sg), 826 1); 827 } 828 } 829 #endif 830 831 unmap_free_dma_scatter(pl022); 832 833 /* Update total bytes transferred */ 834 msg->actual_length += pl022->cur_transfer->len; 835 if (pl022->cur_transfer->cs_change) 836 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 837 838 /* Move to next transfer */ 839 msg->state = next_transfer(pl022); 840 tasklet_schedule(&pl022->pump_transfers); 841 } 842 843 static void setup_dma_scatter(struct pl022 *pl022, 844 void *buffer, 845 unsigned int length, 846 struct sg_table *sgtab) 847 { 848 struct scatterlist *sg; 849 int bytesleft = length; 850 void *bufp = buffer; 851 int mapbytes; 852 int i; 853 854 if (buffer) { 855 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 856 /* 857 * If there are less bytes left than what fits 858 * in the current page (plus page alignment offset) 859 * we just feed in this, else we stuff in as much 860 * as we can. 861 */ 862 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 863 mapbytes = bytesleft; 864 else 865 mapbytes = PAGE_SIZE - offset_in_page(bufp); 866 sg_set_page(sg, virt_to_page(bufp), 867 mapbytes, offset_in_page(bufp)); 868 bufp += mapbytes; 869 bytesleft -= mapbytes; 870 dev_dbg(&pl022->adev->dev, 871 "set RX/TX target page @ %p, %d bytes, %d left\n", 872 bufp, mapbytes, bytesleft); 873 } 874 } else { 875 /* Map the dummy buffer on every page */ 876 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 877 if (bytesleft < PAGE_SIZE) 878 mapbytes = bytesleft; 879 else 880 mapbytes = PAGE_SIZE; 881 sg_set_page(sg, virt_to_page(pl022->dummypage), 882 mapbytes, 0); 883 bytesleft -= mapbytes; 884 dev_dbg(&pl022->adev->dev, 885 "set RX/TX to dummy page %d bytes, %d left\n", 886 mapbytes, bytesleft); 887 888 } 889 } 890 BUG_ON(bytesleft); 891 } 892 893 /** 894 * configure_dma - configures the channels for the next transfer 895 * @pl022: SSP driver's private data structure 896 */ 897 static int configure_dma(struct pl022 *pl022) 898 { 899 struct dma_slave_config rx_conf = { 900 .src_addr = SSP_DR(pl022->phybase), 901 .direction = DMA_DEV_TO_MEM, 902 .device_fc = false, 903 }; 904 struct dma_slave_config tx_conf = { 905 .dst_addr = SSP_DR(pl022->phybase), 906 .direction = DMA_MEM_TO_DEV, 907 .device_fc = false, 908 }; 909 unsigned int pages; 910 int ret; 911 int rx_sglen, tx_sglen; 912 struct dma_chan *rxchan = pl022->dma_rx_channel; 913 struct dma_chan *txchan = pl022->dma_tx_channel; 914 struct dma_async_tx_descriptor *rxdesc; 915 struct dma_async_tx_descriptor *txdesc; 916 917 /* Check that the channels are available */ 918 if (!rxchan || !txchan) 919 return -ENODEV; 920 921 /* 922 * If supplied, the DMA burstsize should equal the FIFO trigger level. 923 * Notice that the DMA engine uses one-to-one mapping. Since we can 924 * not trigger on 2 elements this needs explicit mapping rather than 925 * calculation. 926 */ 927 switch (pl022->rx_lev_trig) { 928 case SSP_RX_1_OR_MORE_ELEM: 929 rx_conf.src_maxburst = 1; 930 break; 931 case SSP_RX_4_OR_MORE_ELEM: 932 rx_conf.src_maxburst = 4; 933 break; 934 case SSP_RX_8_OR_MORE_ELEM: 935 rx_conf.src_maxburst = 8; 936 break; 937 case SSP_RX_16_OR_MORE_ELEM: 938 rx_conf.src_maxburst = 16; 939 break; 940 case SSP_RX_32_OR_MORE_ELEM: 941 rx_conf.src_maxburst = 32; 942 break; 943 default: 944 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 945 break; 946 } 947 948 switch (pl022->tx_lev_trig) { 949 case SSP_TX_1_OR_MORE_EMPTY_LOC: 950 tx_conf.dst_maxburst = 1; 951 break; 952 case SSP_TX_4_OR_MORE_EMPTY_LOC: 953 tx_conf.dst_maxburst = 4; 954 break; 955 case SSP_TX_8_OR_MORE_EMPTY_LOC: 956 tx_conf.dst_maxburst = 8; 957 break; 958 case SSP_TX_16_OR_MORE_EMPTY_LOC: 959 tx_conf.dst_maxburst = 16; 960 break; 961 case SSP_TX_32_OR_MORE_EMPTY_LOC: 962 tx_conf.dst_maxburst = 32; 963 break; 964 default: 965 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 966 break; 967 } 968 969 switch (pl022->read) { 970 case READING_NULL: 971 /* Use the same as for writing */ 972 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 973 break; 974 case READING_U8: 975 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 976 break; 977 case READING_U16: 978 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 979 break; 980 case READING_U32: 981 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 982 break; 983 } 984 985 switch (pl022->write) { 986 case WRITING_NULL: 987 /* Use the same as for reading */ 988 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 989 break; 990 case WRITING_U8: 991 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 992 break; 993 case WRITING_U16: 994 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 995 break; 996 case WRITING_U32: 997 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 998 break; 999 } 1000 1001 /* SPI pecularity: we need to read and write the same width */ 1002 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1003 rx_conf.src_addr_width = tx_conf.dst_addr_width; 1004 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1005 tx_conf.dst_addr_width = rx_conf.src_addr_width; 1006 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1007 1008 dmaengine_slave_config(rxchan, &rx_conf); 1009 dmaengine_slave_config(txchan, &tx_conf); 1010 1011 /* Create sglists for the transfers */ 1012 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1013 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1014 1015 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1016 if (ret) 1017 goto err_alloc_rx_sg; 1018 1019 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1020 if (ret) 1021 goto err_alloc_tx_sg; 1022 1023 /* Fill in the scatterlists for the RX+TX buffers */ 1024 setup_dma_scatter(pl022, pl022->rx, 1025 pl022->cur_transfer->len, &pl022->sgt_rx); 1026 setup_dma_scatter(pl022, pl022->tx, 1027 pl022->cur_transfer->len, &pl022->sgt_tx); 1028 1029 /* Map DMA buffers */ 1030 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1031 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1032 if (!rx_sglen) 1033 goto err_rx_sgmap; 1034 1035 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1036 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1037 if (!tx_sglen) 1038 goto err_tx_sgmap; 1039 1040 /* Send both scatterlists */ 1041 rxdesc = dmaengine_prep_slave_sg(rxchan, 1042 pl022->sgt_rx.sgl, 1043 rx_sglen, 1044 DMA_DEV_TO_MEM, 1045 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1046 if (!rxdesc) 1047 goto err_rxdesc; 1048 1049 txdesc = dmaengine_prep_slave_sg(txchan, 1050 pl022->sgt_tx.sgl, 1051 tx_sglen, 1052 DMA_MEM_TO_DEV, 1053 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1054 if (!txdesc) 1055 goto err_txdesc; 1056 1057 /* Put the callback on the RX transfer only, that should finish last */ 1058 rxdesc->callback = dma_callback; 1059 rxdesc->callback_param = pl022; 1060 1061 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1062 dmaengine_submit(rxdesc); 1063 dmaengine_submit(txdesc); 1064 dma_async_issue_pending(rxchan); 1065 dma_async_issue_pending(txchan); 1066 pl022->dma_running = true; 1067 1068 return 0; 1069 1070 err_txdesc: 1071 dmaengine_terminate_all(txchan); 1072 err_rxdesc: 1073 dmaengine_terminate_all(rxchan); 1074 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1075 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1076 err_tx_sgmap: 1077 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1078 pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1079 err_rx_sgmap: 1080 sg_free_table(&pl022->sgt_tx); 1081 err_alloc_tx_sg: 1082 sg_free_table(&pl022->sgt_rx); 1083 err_alloc_rx_sg: 1084 return -ENOMEM; 1085 } 1086 1087 static int pl022_dma_probe(struct pl022 *pl022) 1088 { 1089 dma_cap_mask_t mask; 1090 1091 /* Try to acquire a generic DMA engine slave channel */ 1092 dma_cap_zero(mask); 1093 dma_cap_set(DMA_SLAVE, mask); 1094 /* 1095 * We need both RX and TX channels to do DMA, else do none 1096 * of them. 1097 */ 1098 pl022->dma_rx_channel = dma_request_channel(mask, 1099 pl022->master_info->dma_filter, 1100 pl022->master_info->dma_rx_param); 1101 if (!pl022->dma_rx_channel) { 1102 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1103 goto err_no_rxchan; 1104 } 1105 1106 pl022->dma_tx_channel = dma_request_channel(mask, 1107 pl022->master_info->dma_filter, 1108 pl022->master_info->dma_tx_param); 1109 if (!pl022->dma_tx_channel) { 1110 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1111 goto err_no_txchan; 1112 } 1113 1114 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1115 if (!pl022->dummypage) { 1116 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1117 goto err_no_dummypage; 1118 } 1119 1120 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1121 dma_chan_name(pl022->dma_rx_channel), 1122 dma_chan_name(pl022->dma_tx_channel)); 1123 1124 return 0; 1125 1126 err_no_dummypage: 1127 dma_release_channel(pl022->dma_tx_channel); 1128 err_no_txchan: 1129 dma_release_channel(pl022->dma_rx_channel); 1130 pl022->dma_rx_channel = NULL; 1131 err_no_rxchan: 1132 dev_err(&pl022->adev->dev, 1133 "Failed to work in dma mode, work without dma!\n"); 1134 return -ENODEV; 1135 } 1136 1137 static int pl022_dma_autoprobe(struct pl022 *pl022) 1138 { 1139 struct device *dev = &pl022->adev->dev; 1140 1141 /* automatically configure DMA channels from platform, normally using DT */ 1142 pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx"); 1143 if (!pl022->dma_rx_channel) 1144 goto err_no_rxchan; 1145 1146 pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx"); 1147 if (!pl022->dma_tx_channel) 1148 goto err_no_txchan; 1149 1150 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1151 if (!pl022->dummypage) 1152 goto err_no_dummypage; 1153 1154 return 0; 1155 1156 err_no_dummypage: 1157 dma_release_channel(pl022->dma_tx_channel); 1158 pl022->dma_tx_channel = NULL; 1159 err_no_txchan: 1160 dma_release_channel(pl022->dma_rx_channel); 1161 pl022->dma_rx_channel = NULL; 1162 err_no_rxchan: 1163 return -ENODEV; 1164 } 1165 1166 static void terminate_dma(struct pl022 *pl022) 1167 { 1168 struct dma_chan *rxchan = pl022->dma_rx_channel; 1169 struct dma_chan *txchan = pl022->dma_tx_channel; 1170 1171 dmaengine_terminate_all(rxchan); 1172 dmaengine_terminate_all(txchan); 1173 unmap_free_dma_scatter(pl022); 1174 pl022->dma_running = false; 1175 } 1176 1177 static void pl022_dma_remove(struct pl022 *pl022) 1178 { 1179 if (pl022->dma_running) 1180 terminate_dma(pl022); 1181 if (pl022->dma_tx_channel) 1182 dma_release_channel(pl022->dma_tx_channel); 1183 if (pl022->dma_rx_channel) 1184 dma_release_channel(pl022->dma_rx_channel); 1185 kfree(pl022->dummypage); 1186 } 1187 1188 #else 1189 static inline int configure_dma(struct pl022 *pl022) 1190 { 1191 return -ENODEV; 1192 } 1193 1194 static inline int pl022_dma_autoprobe(struct pl022 *pl022) 1195 { 1196 return 0; 1197 } 1198 1199 static inline int pl022_dma_probe(struct pl022 *pl022) 1200 { 1201 return 0; 1202 } 1203 1204 static inline void pl022_dma_remove(struct pl022 *pl022) 1205 { 1206 } 1207 #endif 1208 1209 /** 1210 * pl022_interrupt_handler - Interrupt handler for SSP controller 1211 * 1212 * This function handles interrupts generated for an interrupt based transfer. 1213 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1214 * current message's state as STATE_ERROR and schedule the tasklet 1215 * pump_transfers which will do the postprocessing of the current message by 1216 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1217 * more data, and writes data in TX FIFO till it is not full. If we complete 1218 * the transfer we move to the next transfer and schedule the tasklet. 1219 */ 1220 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1221 { 1222 struct pl022 *pl022 = dev_id; 1223 struct spi_message *msg = pl022->cur_msg; 1224 u16 irq_status = 0; 1225 u16 flag = 0; 1226 1227 if (unlikely(!msg)) { 1228 dev_err(&pl022->adev->dev, 1229 "bad message state in interrupt handler"); 1230 /* Never fail */ 1231 return IRQ_HANDLED; 1232 } 1233 1234 /* Read the Interrupt Status Register */ 1235 irq_status = readw(SSP_MIS(pl022->virtbase)); 1236 1237 if (unlikely(!irq_status)) 1238 return IRQ_NONE; 1239 1240 /* 1241 * This handles the FIFO interrupts, the timeout 1242 * interrupts are flatly ignored, they cannot be 1243 * trusted. 1244 */ 1245 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1246 /* 1247 * Overrun interrupt - bail out since our Data has been 1248 * corrupted 1249 */ 1250 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1251 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1252 dev_err(&pl022->adev->dev, 1253 "RXFIFO is full\n"); 1254 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1255 dev_err(&pl022->adev->dev, 1256 "TXFIFO is full\n"); 1257 1258 /* 1259 * Disable and clear interrupts, disable SSP, 1260 * mark message with bad status so it can be 1261 * retried. 1262 */ 1263 writew(DISABLE_ALL_INTERRUPTS, 1264 SSP_IMSC(pl022->virtbase)); 1265 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1266 writew((readw(SSP_CR1(pl022->virtbase)) & 1267 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1268 msg->state = STATE_ERROR; 1269 1270 /* Schedule message queue handler */ 1271 tasklet_schedule(&pl022->pump_transfers); 1272 return IRQ_HANDLED; 1273 } 1274 1275 readwriter(pl022); 1276 1277 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1278 flag = 1; 1279 /* Disable Transmit interrupt, enable receive interrupt */ 1280 writew((readw(SSP_IMSC(pl022->virtbase)) & 1281 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1282 SSP_IMSC(pl022->virtbase)); 1283 } 1284 1285 /* 1286 * Since all transactions must write as much as shall be read, 1287 * we can conclude the entire transaction once RX is complete. 1288 * At this point, all TX will always be finished. 1289 */ 1290 if (pl022->rx >= pl022->rx_end) { 1291 writew(DISABLE_ALL_INTERRUPTS, 1292 SSP_IMSC(pl022->virtbase)); 1293 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1294 if (unlikely(pl022->rx > pl022->rx_end)) { 1295 dev_warn(&pl022->adev->dev, "read %u surplus " 1296 "bytes (did you request an odd " 1297 "number of bytes on a 16bit bus?)\n", 1298 (u32) (pl022->rx - pl022->rx_end)); 1299 } 1300 /* Update total bytes transferred */ 1301 msg->actual_length += pl022->cur_transfer->len; 1302 if (pl022->cur_transfer->cs_change) 1303 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1304 /* Move to next transfer */ 1305 msg->state = next_transfer(pl022); 1306 tasklet_schedule(&pl022->pump_transfers); 1307 return IRQ_HANDLED; 1308 } 1309 1310 return IRQ_HANDLED; 1311 } 1312 1313 /** 1314 * This sets up the pointers to memory for the next message to 1315 * send out on the SPI bus. 1316 */ 1317 static int set_up_next_transfer(struct pl022 *pl022, 1318 struct spi_transfer *transfer) 1319 { 1320 int residue; 1321 1322 /* Sanity check the message for this bus width */ 1323 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1324 if (unlikely(residue != 0)) { 1325 dev_err(&pl022->adev->dev, 1326 "message of %u bytes to transmit but the current " 1327 "chip bus has a data width of %u bytes!\n", 1328 pl022->cur_transfer->len, 1329 pl022->cur_chip->n_bytes); 1330 dev_err(&pl022->adev->dev, "skipping this message\n"); 1331 return -EIO; 1332 } 1333 pl022->tx = (void *)transfer->tx_buf; 1334 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1335 pl022->rx = (void *)transfer->rx_buf; 1336 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1337 pl022->write = 1338 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1339 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1340 return 0; 1341 } 1342 1343 /** 1344 * pump_transfers - Tasklet function which schedules next transfer 1345 * when running in interrupt or DMA transfer mode. 1346 * @data: SSP driver private data structure 1347 * 1348 */ 1349 static void pump_transfers(unsigned long data) 1350 { 1351 struct pl022 *pl022 = (struct pl022 *) data; 1352 struct spi_message *message = NULL; 1353 struct spi_transfer *transfer = NULL; 1354 struct spi_transfer *previous = NULL; 1355 1356 /* Get current state information */ 1357 message = pl022->cur_msg; 1358 transfer = pl022->cur_transfer; 1359 1360 /* Handle for abort */ 1361 if (message->state == STATE_ERROR) { 1362 message->status = -EIO; 1363 giveback(pl022); 1364 return; 1365 } 1366 1367 /* Handle end of message */ 1368 if (message->state == STATE_DONE) { 1369 message->status = 0; 1370 giveback(pl022); 1371 return; 1372 } 1373 1374 /* Delay if requested at end of transfer before CS change */ 1375 if (message->state == STATE_RUNNING) { 1376 previous = list_entry(transfer->transfer_list.prev, 1377 struct spi_transfer, 1378 transfer_list); 1379 if (previous->delay_usecs) 1380 /* 1381 * FIXME: This runs in interrupt context. 1382 * Is this really smart? 1383 */ 1384 udelay(previous->delay_usecs); 1385 1386 /* Reselect chip select only if cs_change was requested */ 1387 if (previous->cs_change) 1388 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1389 } else { 1390 /* STATE_START */ 1391 message->state = STATE_RUNNING; 1392 } 1393 1394 if (set_up_next_transfer(pl022, transfer)) { 1395 message->state = STATE_ERROR; 1396 message->status = -EIO; 1397 giveback(pl022); 1398 return; 1399 } 1400 /* Flush the FIFOs and let's go! */ 1401 flush(pl022); 1402 1403 if (pl022->cur_chip->enable_dma) { 1404 if (configure_dma(pl022)) { 1405 dev_dbg(&pl022->adev->dev, 1406 "configuration of DMA failed, fall back to interrupt mode\n"); 1407 goto err_config_dma; 1408 } 1409 return; 1410 } 1411 1412 err_config_dma: 1413 /* enable all interrupts except RX */ 1414 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1415 } 1416 1417 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1418 { 1419 /* 1420 * Default is to enable all interrupts except RX - 1421 * this will be enabled once TX is complete 1422 */ 1423 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1424 1425 /* Enable target chip, if not already active */ 1426 if (!pl022->next_msg_cs_active) 1427 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1428 1429 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1430 /* Error path */ 1431 pl022->cur_msg->state = STATE_ERROR; 1432 pl022->cur_msg->status = -EIO; 1433 giveback(pl022); 1434 return; 1435 } 1436 /* If we're using DMA, set up DMA here */ 1437 if (pl022->cur_chip->enable_dma) { 1438 /* Configure DMA transfer */ 1439 if (configure_dma(pl022)) { 1440 dev_dbg(&pl022->adev->dev, 1441 "configuration of DMA failed, fall back to interrupt mode\n"); 1442 goto err_config_dma; 1443 } 1444 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1445 irqflags = DISABLE_ALL_INTERRUPTS; 1446 } 1447 err_config_dma: 1448 /* Enable SSP, turn on interrupts */ 1449 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1450 SSP_CR1(pl022->virtbase)); 1451 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1452 } 1453 1454 static void do_polling_transfer(struct pl022 *pl022) 1455 { 1456 struct spi_message *message = NULL; 1457 struct spi_transfer *transfer = NULL; 1458 struct spi_transfer *previous = NULL; 1459 struct chip_data *chip; 1460 unsigned long time, timeout; 1461 1462 chip = pl022->cur_chip; 1463 message = pl022->cur_msg; 1464 1465 while (message->state != STATE_DONE) { 1466 /* Handle for abort */ 1467 if (message->state == STATE_ERROR) 1468 break; 1469 transfer = pl022->cur_transfer; 1470 1471 /* Delay if requested at end of transfer */ 1472 if (message->state == STATE_RUNNING) { 1473 previous = 1474 list_entry(transfer->transfer_list.prev, 1475 struct spi_transfer, transfer_list); 1476 if (previous->delay_usecs) 1477 udelay(previous->delay_usecs); 1478 if (previous->cs_change) 1479 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1480 } else { 1481 /* STATE_START */ 1482 message->state = STATE_RUNNING; 1483 if (!pl022->next_msg_cs_active) 1484 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1485 } 1486 1487 /* Configuration Changing Per Transfer */ 1488 if (set_up_next_transfer(pl022, transfer)) { 1489 /* Error path */ 1490 message->state = STATE_ERROR; 1491 break; 1492 } 1493 /* Flush FIFOs and enable SSP */ 1494 flush(pl022); 1495 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1496 SSP_CR1(pl022->virtbase)); 1497 1498 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1499 1500 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1501 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1502 time = jiffies; 1503 readwriter(pl022); 1504 if (time_after(time, timeout)) { 1505 dev_warn(&pl022->adev->dev, 1506 "%s: timeout!\n", __func__); 1507 message->state = STATE_ERROR; 1508 goto out; 1509 } 1510 cpu_relax(); 1511 } 1512 1513 /* Update total byte transferred */ 1514 message->actual_length += pl022->cur_transfer->len; 1515 if (pl022->cur_transfer->cs_change) 1516 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1517 /* Move to next transfer */ 1518 message->state = next_transfer(pl022); 1519 } 1520 out: 1521 /* Handle end of message */ 1522 if (message->state == STATE_DONE) 1523 message->status = 0; 1524 else 1525 message->status = -EIO; 1526 1527 giveback(pl022); 1528 return; 1529 } 1530 1531 static int pl022_transfer_one_message(struct spi_master *master, 1532 struct spi_message *msg) 1533 { 1534 struct pl022 *pl022 = spi_master_get_devdata(master); 1535 1536 /* Initial message state */ 1537 pl022->cur_msg = msg; 1538 msg->state = STATE_START; 1539 1540 pl022->cur_transfer = list_entry(msg->transfers.next, 1541 struct spi_transfer, transfer_list); 1542 1543 /* Setup the SPI using the per chip configuration */ 1544 pl022->cur_chip = spi_get_ctldata(msg->spi); 1545 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; 1546 1547 restore_state(pl022); 1548 flush(pl022); 1549 1550 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1551 do_polling_transfer(pl022); 1552 else 1553 do_interrupt_dma_transfer(pl022); 1554 1555 return 0; 1556 } 1557 1558 static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1559 { 1560 struct pl022 *pl022 = spi_master_get_devdata(master); 1561 1562 /* nothing more to do - disable spi/ssp and power off */ 1563 writew((readw(SSP_CR1(pl022->virtbase)) & 1564 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1565 1566 return 0; 1567 } 1568 1569 static int verify_controller_parameters(struct pl022 *pl022, 1570 struct pl022_config_chip const *chip_info) 1571 { 1572 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1573 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1574 dev_err(&pl022->adev->dev, 1575 "interface is configured incorrectly\n"); 1576 return -EINVAL; 1577 } 1578 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1579 (!pl022->vendor->unidir)) { 1580 dev_err(&pl022->adev->dev, 1581 "unidirectional mode not supported in this " 1582 "hardware version\n"); 1583 return -EINVAL; 1584 } 1585 if ((chip_info->hierarchy != SSP_MASTER) 1586 && (chip_info->hierarchy != SSP_SLAVE)) { 1587 dev_err(&pl022->adev->dev, 1588 "hierarchy is configured incorrectly\n"); 1589 return -EINVAL; 1590 } 1591 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1592 && (chip_info->com_mode != DMA_TRANSFER) 1593 && (chip_info->com_mode != POLLING_TRANSFER)) { 1594 dev_err(&pl022->adev->dev, 1595 "Communication mode is configured incorrectly\n"); 1596 return -EINVAL; 1597 } 1598 switch (chip_info->rx_lev_trig) { 1599 case SSP_RX_1_OR_MORE_ELEM: 1600 case SSP_RX_4_OR_MORE_ELEM: 1601 case SSP_RX_8_OR_MORE_ELEM: 1602 /* These are always OK, all variants can handle this */ 1603 break; 1604 case SSP_RX_16_OR_MORE_ELEM: 1605 if (pl022->vendor->fifodepth < 16) { 1606 dev_err(&pl022->adev->dev, 1607 "RX FIFO Trigger Level is configured incorrectly\n"); 1608 return -EINVAL; 1609 } 1610 break; 1611 case SSP_RX_32_OR_MORE_ELEM: 1612 if (pl022->vendor->fifodepth < 32) { 1613 dev_err(&pl022->adev->dev, 1614 "RX FIFO Trigger Level is configured incorrectly\n"); 1615 return -EINVAL; 1616 } 1617 break; 1618 default: 1619 dev_err(&pl022->adev->dev, 1620 "RX FIFO Trigger Level is configured incorrectly\n"); 1621 return -EINVAL; 1622 } 1623 switch (chip_info->tx_lev_trig) { 1624 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1625 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1626 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1627 /* These are always OK, all variants can handle this */ 1628 break; 1629 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1630 if (pl022->vendor->fifodepth < 16) { 1631 dev_err(&pl022->adev->dev, 1632 "TX FIFO Trigger Level is configured incorrectly\n"); 1633 return -EINVAL; 1634 } 1635 break; 1636 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1637 if (pl022->vendor->fifodepth < 32) { 1638 dev_err(&pl022->adev->dev, 1639 "TX FIFO Trigger Level is configured incorrectly\n"); 1640 return -EINVAL; 1641 } 1642 break; 1643 default: 1644 dev_err(&pl022->adev->dev, 1645 "TX FIFO Trigger Level is configured incorrectly\n"); 1646 return -EINVAL; 1647 } 1648 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1649 if ((chip_info->ctrl_len < SSP_BITS_4) 1650 || (chip_info->ctrl_len > SSP_BITS_32)) { 1651 dev_err(&pl022->adev->dev, 1652 "CTRL LEN is configured incorrectly\n"); 1653 return -EINVAL; 1654 } 1655 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1656 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1657 dev_err(&pl022->adev->dev, 1658 "Wait State is configured incorrectly\n"); 1659 return -EINVAL; 1660 } 1661 /* Half duplex is only available in the ST Micro version */ 1662 if (pl022->vendor->extended_cr) { 1663 if ((chip_info->duplex != 1664 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1665 && (chip_info->duplex != 1666 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1667 dev_err(&pl022->adev->dev, 1668 "Microwire duplex mode is configured incorrectly\n"); 1669 return -EINVAL; 1670 } 1671 } else { 1672 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1673 dev_err(&pl022->adev->dev, 1674 "Microwire half duplex mode requested," 1675 " but this is only available in the" 1676 " ST version of PL022\n"); 1677 return -EINVAL; 1678 } 1679 } 1680 return 0; 1681 } 1682 1683 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1684 { 1685 return rate / (cpsdvsr * (1 + scr)); 1686 } 1687 1688 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1689 ssp_clock_params * clk_freq) 1690 { 1691 /* Lets calculate the frequency parameters */ 1692 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1693 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1694 best_scr = 0, tmp, found = 0; 1695 1696 rate = clk_get_rate(pl022->clk); 1697 /* cpsdvscr = 2 & scr 0 */ 1698 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1699 /* cpsdvsr = 254 & scr = 255 */ 1700 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1701 1702 if (freq > max_tclk) 1703 dev_warn(&pl022->adev->dev, 1704 "Max speed that can be programmed is %d Hz, you requested %d\n", 1705 max_tclk, freq); 1706 1707 if (freq < min_tclk) { 1708 dev_err(&pl022->adev->dev, 1709 "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1710 freq, min_tclk); 1711 return -EINVAL; 1712 } 1713 1714 /* 1715 * best_freq will give closest possible available rate (<= requested 1716 * freq) for all values of scr & cpsdvsr. 1717 */ 1718 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1719 while (scr <= SCR_MAX) { 1720 tmp = spi_rate(rate, cpsdvsr, scr); 1721 1722 if (tmp > freq) { 1723 /* we need lower freq */ 1724 scr++; 1725 continue; 1726 } 1727 1728 /* 1729 * If found exact value, mark found and break. 1730 * If found more closer value, update and break. 1731 */ 1732 if (tmp > best_freq) { 1733 best_freq = tmp; 1734 best_cpsdvsr = cpsdvsr; 1735 best_scr = scr; 1736 1737 if (tmp == freq) 1738 found = 1; 1739 } 1740 /* 1741 * increased scr will give lower rates, which are not 1742 * required 1743 */ 1744 break; 1745 } 1746 cpsdvsr += 2; 1747 scr = SCR_MIN; 1748 } 1749 1750 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 1751 freq); 1752 1753 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1754 clk_freq->scr = (u8) (best_scr & 0xFF); 1755 dev_dbg(&pl022->adev->dev, 1756 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1757 freq, best_freq); 1758 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1759 clk_freq->cpsdvsr, clk_freq->scr); 1760 1761 return 0; 1762 } 1763 1764 /* 1765 * A piece of default chip info unless the platform 1766 * supplies it. 1767 */ 1768 static const struct pl022_config_chip pl022_default_chip_info = { 1769 .com_mode = POLLING_TRANSFER, 1770 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1771 .hierarchy = SSP_SLAVE, 1772 .slave_tx_disable = DO_NOT_DRIVE_TX, 1773 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1774 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1775 .ctrl_len = SSP_BITS_8, 1776 .wait_state = SSP_MWIRE_WAIT_ZERO, 1777 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1778 .cs_control = null_cs_control, 1779 }; 1780 1781 /** 1782 * pl022_setup - setup function registered to SPI master framework 1783 * @spi: spi device which is requesting setup 1784 * 1785 * This function is registered to the SPI framework for this SPI master 1786 * controller. If it is the first time when setup is called by this device, 1787 * this function will initialize the runtime state for this chip and save 1788 * the same in the device structure. Else it will update the runtime info 1789 * with the updated chip info. Nothing is really being written to the 1790 * controller hardware here, that is not done until the actual transfer 1791 * commence. 1792 */ 1793 static int pl022_setup(struct spi_device *spi) 1794 { 1795 struct pl022_config_chip const *chip_info; 1796 struct pl022_config_chip chip_info_dt; 1797 struct chip_data *chip; 1798 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1799 int status = 0; 1800 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1801 unsigned int bits = spi->bits_per_word; 1802 u32 tmp; 1803 struct device_node *np = spi->dev.of_node; 1804 1805 if (!spi->max_speed_hz) 1806 return -EINVAL; 1807 1808 /* Get controller_state if one is supplied */ 1809 chip = spi_get_ctldata(spi); 1810 1811 if (chip == NULL) { 1812 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1813 if (!chip) { 1814 dev_err(&spi->dev, 1815 "cannot allocate controller state\n"); 1816 return -ENOMEM; 1817 } 1818 dev_dbg(&spi->dev, 1819 "allocated memory for controller's runtime state\n"); 1820 } 1821 1822 /* Get controller data if one is supplied */ 1823 chip_info = spi->controller_data; 1824 1825 if (chip_info == NULL) { 1826 if (np) { 1827 chip_info_dt = pl022_default_chip_info; 1828 1829 chip_info_dt.hierarchy = SSP_MASTER; 1830 of_property_read_u32(np, "pl022,interface", 1831 &chip_info_dt.iface); 1832 of_property_read_u32(np, "pl022,com-mode", 1833 &chip_info_dt.com_mode); 1834 of_property_read_u32(np, "pl022,rx-level-trig", 1835 &chip_info_dt.rx_lev_trig); 1836 of_property_read_u32(np, "pl022,tx-level-trig", 1837 &chip_info_dt.tx_lev_trig); 1838 of_property_read_u32(np, "pl022,ctrl-len", 1839 &chip_info_dt.ctrl_len); 1840 of_property_read_u32(np, "pl022,wait-state", 1841 &chip_info_dt.wait_state); 1842 of_property_read_u32(np, "pl022,duplex", 1843 &chip_info_dt.duplex); 1844 1845 chip_info = &chip_info_dt; 1846 } else { 1847 chip_info = &pl022_default_chip_info; 1848 /* spi_board_info.controller_data not is supplied */ 1849 dev_dbg(&spi->dev, 1850 "using default controller_data settings\n"); 1851 } 1852 } else 1853 dev_dbg(&spi->dev, 1854 "using user supplied controller_data settings\n"); 1855 1856 /* 1857 * We can override with custom divisors, else we use the board 1858 * frequency setting 1859 */ 1860 if ((0 == chip_info->clk_freq.cpsdvsr) 1861 && (0 == chip_info->clk_freq.scr)) { 1862 status = calculate_effective_freq(pl022, 1863 spi->max_speed_hz, 1864 &clk_freq); 1865 if (status < 0) 1866 goto err_config_params; 1867 } else { 1868 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1869 if ((clk_freq.cpsdvsr % 2) != 0) 1870 clk_freq.cpsdvsr = 1871 clk_freq.cpsdvsr - 1; 1872 } 1873 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1874 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1875 status = -EINVAL; 1876 dev_err(&spi->dev, 1877 "cpsdvsr is configured incorrectly\n"); 1878 goto err_config_params; 1879 } 1880 1881 status = verify_controller_parameters(pl022, chip_info); 1882 if (status) { 1883 dev_err(&spi->dev, "controller data is incorrect"); 1884 goto err_config_params; 1885 } 1886 1887 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1888 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1889 1890 /* Now set controller state based on controller data */ 1891 chip->xfer_type = chip_info->com_mode; 1892 if (!chip_info->cs_control) { 1893 chip->cs_control = null_cs_control; 1894 if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) 1895 dev_warn(&spi->dev, 1896 "invalid chip select\n"); 1897 } else 1898 chip->cs_control = chip_info->cs_control; 1899 1900 /* Check bits per word with vendor specific range */ 1901 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1902 status = -ENOTSUPP; 1903 dev_err(&spi->dev, "illegal data size for this controller!\n"); 1904 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1905 pl022->vendor->max_bpw); 1906 goto err_config_params; 1907 } else if (bits <= 8) { 1908 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1909 chip->n_bytes = 1; 1910 chip->read = READING_U8; 1911 chip->write = WRITING_U8; 1912 } else if (bits <= 16) { 1913 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1914 chip->n_bytes = 2; 1915 chip->read = READING_U16; 1916 chip->write = WRITING_U16; 1917 } else { 1918 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1919 chip->n_bytes = 4; 1920 chip->read = READING_U32; 1921 chip->write = WRITING_U32; 1922 } 1923 1924 /* Now Initialize all register settings required for this chip */ 1925 chip->cr0 = 0; 1926 chip->cr1 = 0; 1927 chip->dmacr = 0; 1928 chip->cpsr = 0; 1929 if ((chip_info->com_mode == DMA_TRANSFER) 1930 && ((pl022->master_info)->enable_dma)) { 1931 chip->enable_dma = true; 1932 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1933 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1934 SSP_DMACR_MASK_RXDMAE, 0); 1935 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1936 SSP_DMACR_MASK_TXDMAE, 1); 1937 } else { 1938 chip->enable_dma = false; 1939 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1940 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1941 SSP_DMACR_MASK_RXDMAE, 0); 1942 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1943 SSP_DMACR_MASK_TXDMAE, 1); 1944 } 1945 1946 chip->cpsr = clk_freq.cpsdvsr; 1947 1948 /* Special setup for the ST micro extended control registers */ 1949 if (pl022->vendor->extended_cr) { 1950 u32 etx; 1951 1952 if (pl022->vendor->pl023) { 1953 /* These bits are only in the PL023 */ 1954 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1955 SSP_CR1_MASK_FBCLKDEL_ST, 13); 1956 } else { 1957 /* These bits are in the PL022 but not PL023 */ 1958 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1959 SSP_CR0_MASK_HALFDUP_ST, 5); 1960 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1961 SSP_CR0_MASK_CSS_ST, 16); 1962 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1963 SSP_CR0_MASK_FRF_ST, 21); 1964 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 1965 SSP_CR1_MASK_MWAIT_ST, 6); 1966 } 1967 SSP_WRITE_BITS(chip->cr0, bits - 1, 1968 SSP_CR0_MASK_DSS_ST, 0); 1969 1970 if (spi->mode & SPI_LSB_FIRST) { 1971 tmp = SSP_RX_LSB; 1972 etx = SSP_TX_LSB; 1973 } else { 1974 tmp = SSP_RX_MSB; 1975 etx = SSP_TX_MSB; 1976 } 1977 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 1978 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 1979 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 1980 SSP_CR1_MASK_RXIFLSEL_ST, 7); 1981 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 1982 SSP_CR1_MASK_TXIFLSEL_ST, 10); 1983 } else { 1984 SSP_WRITE_BITS(chip->cr0, bits - 1, 1985 SSP_CR0_MASK_DSS, 0); 1986 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1987 SSP_CR0_MASK_FRF, 4); 1988 } 1989 1990 /* Stuff that is common for all versions */ 1991 if (spi->mode & SPI_CPOL) 1992 tmp = SSP_CLK_POL_IDLE_HIGH; 1993 else 1994 tmp = SSP_CLK_POL_IDLE_LOW; 1995 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 1996 1997 if (spi->mode & SPI_CPHA) 1998 tmp = SSP_CLK_SECOND_EDGE; 1999 else 2000 tmp = SSP_CLK_FIRST_EDGE; 2001 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2002 2003 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2004 /* Loopback is available on all versions except PL023 */ 2005 if (pl022->vendor->loopback) { 2006 if (spi->mode & SPI_LOOP) 2007 tmp = LOOPBACK_ENABLED; 2008 else 2009 tmp = LOOPBACK_DISABLED; 2010 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2011 } 2012 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2013 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2014 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2015 3); 2016 2017 /* Save controller_state */ 2018 spi_set_ctldata(spi, chip); 2019 return status; 2020 err_config_params: 2021 spi_set_ctldata(spi, NULL); 2022 kfree(chip); 2023 return status; 2024 } 2025 2026 /** 2027 * pl022_cleanup - cleanup function registered to SPI master framework 2028 * @spi: spi device which is requesting cleanup 2029 * 2030 * This function is registered to the SPI framework for this SPI master 2031 * controller. It will free the runtime state of chip. 2032 */ 2033 static void pl022_cleanup(struct spi_device *spi) 2034 { 2035 struct chip_data *chip = spi_get_ctldata(spi); 2036 2037 spi_set_ctldata(spi, NULL); 2038 kfree(chip); 2039 } 2040 2041 static struct pl022_ssp_controller * 2042 pl022_platform_data_dt_get(struct device *dev) 2043 { 2044 struct device_node *np = dev->of_node; 2045 struct pl022_ssp_controller *pd; 2046 u32 tmp; 2047 2048 if (!np) { 2049 dev_err(dev, "no dt node defined\n"); 2050 return NULL; 2051 } 2052 2053 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); 2054 if (!pd) { 2055 dev_err(dev, "cannot allocate platform data memory\n"); 2056 return NULL; 2057 } 2058 2059 pd->bus_id = -1; 2060 pd->enable_dma = 1; 2061 of_property_read_u32(np, "num-cs", &tmp); 2062 pd->num_chipselect = tmp; 2063 of_property_read_u32(np, "pl022,autosuspend-delay", 2064 &pd->autosuspend_delay); 2065 pd->rt = of_property_read_bool(np, "pl022,rt"); 2066 2067 return pd; 2068 } 2069 2070 static int pl022_probe(struct amba_device *adev, const struct amba_id *id) 2071 { 2072 struct device *dev = &adev->dev; 2073 struct pl022_ssp_controller *platform_info = 2074 dev_get_platdata(&adev->dev); 2075 struct spi_master *master; 2076 struct pl022 *pl022 = NULL; /*Data for this driver */ 2077 struct device_node *np = adev->dev.of_node; 2078 int status = 0, i, num_cs; 2079 2080 dev_info(&adev->dev, 2081 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2082 if (!platform_info && IS_ENABLED(CONFIG_OF)) 2083 platform_info = pl022_platform_data_dt_get(dev); 2084 2085 if (!platform_info) { 2086 dev_err(dev, "probe: no platform data defined\n"); 2087 return -ENODEV; 2088 } 2089 2090 if (platform_info->num_chipselect) { 2091 num_cs = platform_info->num_chipselect; 2092 } else { 2093 dev_err(dev, "probe: no chip select defined\n"); 2094 return -ENODEV; 2095 } 2096 2097 /* Allocate master with space for data */ 2098 master = spi_alloc_master(dev, sizeof(struct pl022)); 2099 if (master == NULL) { 2100 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2101 return -ENOMEM; 2102 } 2103 2104 pl022 = spi_master_get_devdata(master); 2105 pl022->master = master; 2106 pl022->master_info = platform_info; 2107 pl022->adev = adev; 2108 pl022->vendor = id->data; 2109 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), 2110 GFP_KERNEL); 2111 2112 pinctrl_pm_select_default_state(dev); 2113 2114 /* 2115 * Bus Number Which has been Assigned to this SSP controller 2116 * on this board 2117 */ 2118 master->bus_num = platform_info->bus_id; 2119 master->num_chipselect = num_cs; 2120 master->cleanup = pl022_cleanup; 2121 master->setup = pl022_setup; 2122 master->auto_runtime_pm = true; 2123 master->transfer_one_message = pl022_transfer_one_message; 2124 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2125 master->rt = platform_info->rt; 2126 master->dev.of_node = dev->of_node; 2127 2128 if (platform_info->num_chipselect && platform_info->chipselects) { 2129 for (i = 0; i < num_cs; i++) 2130 pl022->chipselects[i] = platform_info->chipselects[i]; 2131 } else if (IS_ENABLED(CONFIG_OF)) { 2132 for (i = 0; i < num_cs; i++) { 2133 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 2134 2135 if (cs_gpio == -EPROBE_DEFER) { 2136 status = -EPROBE_DEFER; 2137 goto err_no_gpio; 2138 } 2139 2140 pl022->chipselects[i] = cs_gpio; 2141 2142 if (gpio_is_valid(cs_gpio)) { 2143 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) 2144 dev_err(&adev->dev, 2145 "could not request %d gpio\n", 2146 cs_gpio); 2147 else if (gpio_direction_output(cs_gpio, 1)) 2148 dev_err(&adev->dev, 2149 "could set gpio %d as output\n", 2150 cs_gpio); 2151 } 2152 } 2153 } 2154 2155 /* 2156 * Supports mode 0-3, loopback, and active low CS. Transfers are 2157 * always MS bit first on the original pl022. 2158 */ 2159 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2160 if (pl022->vendor->extended_cr) 2161 master->mode_bits |= SPI_LSB_FIRST; 2162 2163 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2164 2165 status = amba_request_regions(adev, NULL); 2166 if (status) 2167 goto err_no_ioregion; 2168 2169 pl022->phybase = adev->res.start; 2170 pl022->virtbase = devm_ioremap(dev, adev->res.start, 2171 resource_size(&adev->res)); 2172 if (pl022->virtbase == NULL) { 2173 status = -ENOMEM; 2174 goto err_no_ioremap; 2175 } 2176 dev_info(&adev->dev, "mapped registers from %pa to %p\n", 2177 &adev->res.start, pl022->virtbase); 2178 2179 pl022->clk = devm_clk_get(&adev->dev, NULL); 2180 if (IS_ERR(pl022->clk)) { 2181 status = PTR_ERR(pl022->clk); 2182 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2183 goto err_no_clk; 2184 } 2185 2186 status = clk_prepare(pl022->clk); 2187 if (status) { 2188 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 2189 goto err_clk_prep; 2190 } 2191 2192 status = clk_enable(pl022->clk); 2193 if (status) { 2194 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2195 goto err_no_clk_en; 2196 } 2197 2198 /* Initialize transfer pump */ 2199 tasklet_init(&pl022->pump_transfers, pump_transfers, 2200 (unsigned long)pl022); 2201 2202 /* Disable SSP */ 2203 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2204 SSP_CR1(pl022->virtbase)); 2205 load_ssp_default_config(pl022); 2206 2207 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, 2208 0, "pl022", pl022); 2209 if (status < 0) { 2210 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2211 goto err_no_irq; 2212 } 2213 2214 /* Get DMA channels, try autoconfiguration first */ 2215 status = pl022_dma_autoprobe(pl022); 2216 2217 /* If that failed, use channels from platform_info */ 2218 if (status == 0) 2219 platform_info->enable_dma = 1; 2220 else if (platform_info->enable_dma) { 2221 status = pl022_dma_probe(pl022); 2222 if (status != 0) 2223 platform_info->enable_dma = 0; 2224 } 2225 2226 /* Register with the SPI framework */ 2227 amba_set_drvdata(adev, pl022); 2228 status = spi_register_master(master); 2229 if (status != 0) { 2230 dev_err(&adev->dev, 2231 "probe - problem registering spi master\n"); 2232 goto err_spi_register; 2233 } 2234 dev_dbg(dev, "probe succeeded\n"); 2235 2236 /* let runtime pm put suspend */ 2237 if (platform_info->autosuspend_delay > 0) { 2238 dev_info(&adev->dev, 2239 "will use autosuspend for runtime pm, delay %dms\n", 2240 platform_info->autosuspend_delay); 2241 pm_runtime_set_autosuspend_delay(dev, 2242 platform_info->autosuspend_delay); 2243 pm_runtime_use_autosuspend(dev); 2244 } 2245 pm_runtime_put(dev); 2246 2247 return 0; 2248 2249 err_spi_register: 2250 if (platform_info->enable_dma) 2251 pl022_dma_remove(pl022); 2252 err_no_irq: 2253 clk_disable(pl022->clk); 2254 err_no_clk_en: 2255 clk_unprepare(pl022->clk); 2256 err_clk_prep: 2257 err_no_clk: 2258 err_no_ioremap: 2259 amba_release_regions(adev); 2260 err_no_ioregion: 2261 err_no_gpio: 2262 spi_master_put(master); 2263 return status; 2264 } 2265 2266 static int 2267 pl022_remove(struct amba_device *adev) 2268 { 2269 struct pl022 *pl022 = amba_get_drvdata(adev); 2270 2271 if (!pl022) 2272 return 0; 2273 2274 /* 2275 * undo pm_runtime_put() in probe. I assume that we're not 2276 * accessing the primecell here. 2277 */ 2278 pm_runtime_get_noresume(&adev->dev); 2279 2280 load_ssp_default_config(pl022); 2281 if (pl022->master_info->enable_dma) 2282 pl022_dma_remove(pl022); 2283 2284 clk_disable(pl022->clk); 2285 clk_unprepare(pl022->clk); 2286 amba_release_regions(adev); 2287 tasklet_disable(&pl022->pump_transfers); 2288 spi_unregister_master(pl022->master); 2289 return 0; 2290 } 2291 2292 #if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME) 2293 /* 2294 * These two functions are used from both suspend/resume and 2295 * the runtime counterparts to handle external resources like 2296 * clocks, pins and regulators when going to sleep. 2297 */ 2298 static void pl022_suspend_resources(struct pl022 *pl022, bool runtime) 2299 { 2300 clk_disable(pl022->clk); 2301 2302 if (runtime) 2303 pinctrl_pm_select_idle_state(&pl022->adev->dev); 2304 else 2305 pinctrl_pm_select_sleep_state(&pl022->adev->dev); 2306 } 2307 2308 static void pl022_resume_resources(struct pl022 *pl022, bool runtime) 2309 { 2310 /* First go to the default state */ 2311 pinctrl_pm_select_default_state(&pl022->adev->dev); 2312 if (!runtime) 2313 /* Then let's idle the pins until the next transfer happens */ 2314 pinctrl_pm_select_idle_state(&pl022->adev->dev); 2315 2316 clk_enable(pl022->clk); 2317 } 2318 #endif 2319 2320 #ifdef CONFIG_SUSPEND 2321 static int pl022_suspend(struct device *dev) 2322 { 2323 struct pl022 *pl022 = dev_get_drvdata(dev); 2324 int ret; 2325 2326 ret = spi_master_suspend(pl022->master); 2327 if (ret) { 2328 dev_warn(dev, "cannot suspend master\n"); 2329 return ret; 2330 } 2331 2332 pm_runtime_get_sync(dev); 2333 pl022_suspend_resources(pl022, false); 2334 2335 dev_dbg(dev, "suspended\n"); 2336 return 0; 2337 } 2338 2339 static int pl022_resume(struct device *dev) 2340 { 2341 struct pl022 *pl022 = dev_get_drvdata(dev); 2342 int ret; 2343 2344 pl022_resume_resources(pl022, false); 2345 pm_runtime_put(dev); 2346 2347 /* Start the queue running */ 2348 ret = spi_master_resume(pl022->master); 2349 if (ret) 2350 dev_err(dev, "problem starting queue (%d)\n", ret); 2351 else 2352 dev_dbg(dev, "resumed\n"); 2353 2354 return ret; 2355 } 2356 #endif /* CONFIG_PM */ 2357 2358 #ifdef CONFIG_PM_RUNTIME 2359 static int pl022_runtime_suspend(struct device *dev) 2360 { 2361 struct pl022 *pl022 = dev_get_drvdata(dev); 2362 2363 pl022_suspend_resources(pl022, true); 2364 return 0; 2365 } 2366 2367 static int pl022_runtime_resume(struct device *dev) 2368 { 2369 struct pl022 *pl022 = dev_get_drvdata(dev); 2370 2371 pl022_resume_resources(pl022, true); 2372 return 0; 2373 } 2374 #endif 2375 2376 static const struct dev_pm_ops pl022_dev_pm_ops = { 2377 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2378 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2379 }; 2380 2381 static struct vendor_data vendor_arm = { 2382 .fifodepth = 8, 2383 .max_bpw = 16, 2384 .unidir = false, 2385 .extended_cr = false, 2386 .pl023 = false, 2387 .loopback = true, 2388 }; 2389 2390 static struct vendor_data vendor_st = { 2391 .fifodepth = 32, 2392 .max_bpw = 32, 2393 .unidir = false, 2394 .extended_cr = true, 2395 .pl023 = false, 2396 .loopback = true, 2397 }; 2398 2399 static struct vendor_data vendor_st_pl023 = { 2400 .fifodepth = 32, 2401 .max_bpw = 32, 2402 .unidir = false, 2403 .extended_cr = true, 2404 .pl023 = true, 2405 .loopback = false, 2406 }; 2407 2408 static struct amba_id pl022_ids[] = { 2409 { 2410 /* 2411 * ARM PL022 variant, this has a 16bit wide 2412 * and 8 locations deep TX/RX FIFO 2413 */ 2414 .id = 0x00041022, 2415 .mask = 0x000fffff, 2416 .data = &vendor_arm, 2417 }, 2418 { 2419 /* 2420 * ST Micro derivative, this has 32bit wide 2421 * and 32 locations deep TX/RX FIFO 2422 */ 2423 .id = 0x01080022, 2424 .mask = 0xffffffff, 2425 .data = &vendor_st, 2426 }, 2427 { 2428 /* 2429 * ST-Ericsson derivative "PL023" (this is not 2430 * an official ARM number), this is a PL022 SSP block 2431 * stripped to SPI mode only, it has 32bit wide 2432 * and 32 locations deep TX/RX FIFO but no extended 2433 * CR0/CR1 register 2434 */ 2435 .id = 0x00080023, 2436 .mask = 0xffffffff, 2437 .data = &vendor_st_pl023, 2438 }, 2439 { 0, 0 }, 2440 }; 2441 2442 MODULE_DEVICE_TABLE(amba, pl022_ids); 2443 2444 static struct amba_driver pl022_driver = { 2445 .drv = { 2446 .name = "ssp-pl022", 2447 .pm = &pl022_dev_pm_ops, 2448 }, 2449 .id_table = pl022_ids, 2450 .probe = pl022_probe, 2451 .remove = pl022_remove, 2452 }; 2453 2454 static int __init pl022_init(void) 2455 { 2456 return amba_driver_register(&pl022_driver); 2457 } 2458 subsys_initcall(pl022_init); 2459 2460 static void __exit pl022_exit(void) 2461 { 2462 amba_driver_unregister(&pl022_driver); 2463 } 2464 module_exit(pl022_exit); 2465 2466 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2467 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2468 MODULE_LICENSE("GPL"); 2469