1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2009 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/workqueue.h> 33 #include <linux/delay.h> 34 #include <linux/clk.h> 35 #include <linux/err.h> 36 #include <linux/amba/bus.h> 37 #include <linux/amba/pl022.h> 38 #include <linux/io.h> 39 #include <linux/slab.h> 40 #include <linux/dmaengine.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/scatterlist.h> 43 #include <linux/pm_runtime.h> 44 45 /* 46 * This macro is used to define some register default values. 47 * reg is masked with mask, the OR:ed with an (again masked) 48 * val shifted sb steps to the left. 49 */ 50 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 51 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 52 53 /* 54 * This macro is also used to define some default values. 55 * It will just shift val by sb steps to the left and mask 56 * the result with mask. 57 */ 58 #define GEN_MASK_BITS(val, mask, sb) \ 59 (((val)<<(sb)) & (mask)) 60 61 #define DRIVE_TX 0 62 #define DO_NOT_DRIVE_TX 1 63 64 #define DO_NOT_QUEUE_DMA 0 65 #define QUEUE_DMA 1 66 67 #define RX_TRANSFER 1 68 #define TX_TRANSFER 2 69 70 /* 71 * Macros to access SSP Registers with their offsets 72 */ 73 #define SSP_CR0(r) (r + 0x000) 74 #define SSP_CR1(r) (r + 0x004) 75 #define SSP_DR(r) (r + 0x008) 76 #define SSP_SR(r) (r + 0x00C) 77 #define SSP_CPSR(r) (r + 0x010) 78 #define SSP_IMSC(r) (r + 0x014) 79 #define SSP_RIS(r) (r + 0x018) 80 #define SSP_MIS(r) (r + 0x01C) 81 #define SSP_ICR(r) (r + 0x020) 82 #define SSP_DMACR(r) (r + 0x024) 83 #define SSP_ITCR(r) (r + 0x080) 84 #define SSP_ITIP(r) (r + 0x084) 85 #define SSP_ITOP(r) (r + 0x088) 86 #define SSP_TDR(r) (r + 0x08C) 87 88 #define SSP_PID0(r) (r + 0xFE0) 89 #define SSP_PID1(r) (r + 0xFE4) 90 #define SSP_PID2(r) (r + 0xFE8) 91 #define SSP_PID3(r) (r + 0xFEC) 92 93 #define SSP_CID0(r) (r + 0xFF0) 94 #define SSP_CID1(r) (r + 0xFF4) 95 #define SSP_CID2(r) (r + 0xFF8) 96 #define SSP_CID3(r) (r + 0xFFC) 97 98 /* 99 * SSP Control Register 0 - SSP_CR0 100 */ 101 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 102 #define SSP_CR0_MASK_FRF (0x3UL << 4) 103 #define SSP_CR0_MASK_SPO (0x1UL << 6) 104 #define SSP_CR0_MASK_SPH (0x1UL << 7) 105 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 106 107 /* 108 * The ST version of this block moves som bits 109 * in SSP_CR0 and extends it to 32 bits 110 */ 111 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 112 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 113 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 114 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 115 116 /* 117 * SSP Control Register 0 - SSP_CR1 118 */ 119 #define SSP_CR1_MASK_LBM (0x1UL << 0) 120 #define SSP_CR1_MASK_SSE (0x1UL << 1) 121 #define SSP_CR1_MASK_MS (0x1UL << 2) 122 #define SSP_CR1_MASK_SOD (0x1UL << 3) 123 124 /* 125 * The ST version of this block adds some bits 126 * in SSP_CR1 127 */ 128 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 129 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 130 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 131 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 132 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 133 /* This one is only in the PL023 variant */ 134 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 135 136 /* 137 * SSP Status Register - SSP_SR 138 */ 139 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 140 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 141 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 142 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 143 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 144 145 /* 146 * SSP Clock Prescale Register - SSP_CPSR 147 */ 148 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 149 150 /* 151 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 152 */ 153 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 154 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 155 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 156 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 157 158 /* 159 * SSP Raw Interrupt Status Register - SSP_RIS 160 */ 161 /* Receive Overrun Raw Interrupt status */ 162 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 163 /* Receive Timeout Raw Interrupt status */ 164 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 165 /* Receive FIFO Raw Interrupt status */ 166 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 167 /* Transmit FIFO Raw Interrupt status */ 168 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 169 170 /* 171 * SSP Masked Interrupt Status Register - SSP_MIS 172 */ 173 /* Receive Overrun Masked Interrupt status */ 174 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 175 /* Receive Timeout Masked Interrupt status */ 176 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 177 /* Receive FIFO Masked Interrupt status */ 178 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 179 /* Transmit FIFO Masked Interrupt status */ 180 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 181 182 /* 183 * SSP Interrupt Clear Register - SSP_ICR 184 */ 185 /* Receive Overrun Raw Clear Interrupt bit */ 186 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 187 /* Receive Timeout Clear Interrupt bit */ 188 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 189 190 /* 191 * SSP DMA Control Register - SSP_DMACR 192 */ 193 /* Receive DMA Enable bit */ 194 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 195 /* Transmit DMA Enable bit */ 196 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 197 198 /* 199 * SSP Integration Test control Register - SSP_ITCR 200 */ 201 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 202 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 203 204 /* 205 * SSP Integration Test Input Register - SSP_ITIP 206 */ 207 #define ITIP_MASK_SSPRXD (0x1UL << 0) 208 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 209 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 210 #define ITIP_MASK_RXDMAC (0x1UL << 3) 211 #define ITIP_MASK_TXDMAC (0x1UL << 4) 212 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 213 214 /* 215 * SSP Integration Test output Register - SSP_ITOP 216 */ 217 #define ITOP_MASK_SSPTXD (0x1UL << 0) 218 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 219 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 220 #define ITOP_MASK_SSPOEn (0x1UL << 3) 221 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 222 #define ITOP_MASK_RORINTR (0x1UL << 5) 223 #define ITOP_MASK_RTINTR (0x1UL << 6) 224 #define ITOP_MASK_RXINTR (0x1UL << 7) 225 #define ITOP_MASK_TXINTR (0x1UL << 8) 226 #define ITOP_MASK_INTR (0x1UL << 9) 227 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 228 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 229 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 230 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 231 232 /* 233 * SSP Test Data Register - SSP_TDR 234 */ 235 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 236 237 /* 238 * Message State 239 * we use the spi_message.state (void *) pointer to 240 * hold a single state value, that's why all this 241 * (void *) casting is done here. 242 */ 243 #define STATE_START ((void *) 0) 244 #define STATE_RUNNING ((void *) 1) 245 #define STATE_DONE ((void *) 2) 246 #define STATE_ERROR ((void *) -1) 247 248 /* 249 * SSP State - Whether Enabled or Disabled 250 */ 251 #define SSP_DISABLED (0) 252 #define SSP_ENABLED (1) 253 254 /* 255 * SSP DMA State - Whether DMA Enabled or Disabled 256 */ 257 #define SSP_DMA_DISABLED (0) 258 #define SSP_DMA_ENABLED (1) 259 260 /* 261 * SSP Clock Defaults 262 */ 263 #define SSP_DEFAULT_CLKRATE 0x2 264 #define SSP_DEFAULT_PRESCALE 0x40 265 266 /* 267 * SSP Clock Parameter ranges 268 */ 269 #define CPSDVR_MIN 0x02 270 #define CPSDVR_MAX 0xFE 271 #define SCR_MIN 0x00 272 #define SCR_MAX 0xFF 273 274 /* 275 * SSP Interrupt related Macros 276 */ 277 #define DEFAULT_SSP_REG_IMSC 0x0UL 278 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 279 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) 280 281 #define CLEAR_ALL_INTERRUPTS 0x3 282 283 #define SPI_POLLING_TIMEOUT 1000 284 285 /* 286 * The type of reading going on on this chip 287 */ 288 enum ssp_reading { 289 READING_NULL, 290 READING_U8, 291 READING_U16, 292 READING_U32 293 }; 294 295 /** 296 * The type of writing going on on this chip 297 */ 298 enum ssp_writing { 299 WRITING_NULL, 300 WRITING_U8, 301 WRITING_U16, 302 WRITING_U32 303 }; 304 305 /** 306 * struct vendor_data - vendor-specific config parameters 307 * for PL022 derivates 308 * @fifodepth: depth of FIFOs (both) 309 * @max_bpw: maximum number of bits per word 310 * @unidir: supports unidirection transfers 311 * @extended_cr: 32 bit wide control register 0 with extra 312 * features and extra features in CR1 as found in the ST variants 313 * @pl023: supports a subset of the ST extensions called "PL023" 314 */ 315 struct vendor_data { 316 int fifodepth; 317 int max_bpw; 318 bool unidir; 319 bool extended_cr; 320 bool pl023; 321 bool loopback; 322 }; 323 324 /** 325 * struct pl022 - This is the private SSP driver data structure 326 * @adev: AMBA device model hookup 327 * @vendor: vendor data for the IP block 328 * @phybase: the physical memory where the SSP device resides 329 * @virtbase: the virtual memory where the SSP is mapped 330 * @clk: outgoing clock "SPICLK" for the SPI bus 331 * @master: SPI framework hookup 332 * @master_info: controller-specific data from machine setup 333 * @workqueue: a workqueue on which any spi_message request is queued 334 * @pump_messages: work struct for scheduling work to the workqueue 335 * @queue_lock: spinlock to syncronise access to message queue 336 * @queue: message queue 337 * @busy: workqueue is busy 338 * @running: workqueue is running 339 * @pump_transfers: Tasklet used in Interrupt Transfer mode 340 * @cur_msg: Pointer to current spi_message being processed 341 * @cur_transfer: Pointer to current spi_transfer 342 * @cur_chip: pointer to current clients chip(assigned from controller_state) 343 * @tx: current position in TX buffer to be read 344 * @tx_end: end position in TX buffer to be read 345 * @rx: current position in RX buffer to be written 346 * @rx_end: end position in RX buffer to be written 347 * @read: the type of read currently going on 348 * @write: the type of write currently going on 349 * @exp_fifo_level: expected FIFO level 350 * @dma_rx_channel: optional channel for RX DMA 351 * @dma_tx_channel: optional channel for TX DMA 352 * @sgt_rx: scattertable for the RX transfer 353 * @sgt_tx: scattertable for the TX transfer 354 * @dummypage: a dummy page used for driving data on the bus with DMA 355 */ 356 struct pl022 { 357 struct amba_device *adev; 358 struct vendor_data *vendor; 359 resource_size_t phybase; 360 void __iomem *virtbase; 361 struct clk *clk; 362 struct spi_master *master; 363 struct pl022_ssp_controller *master_info; 364 /* Driver message queue */ 365 struct workqueue_struct *workqueue; 366 struct work_struct pump_messages; 367 spinlock_t queue_lock; 368 struct list_head queue; 369 bool busy; 370 bool running; 371 /* Message transfer pump */ 372 struct tasklet_struct pump_transfers; 373 struct spi_message *cur_msg; 374 struct spi_transfer *cur_transfer; 375 struct chip_data *cur_chip; 376 void *tx; 377 void *tx_end; 378 void *rx; 379 void *rx_end; 380 enum ssp_reading read; 381 enum ssp_writing write; 382 u32 exp_fifo_level; 383 enum ssp_rx_level_trig rx_lev_trig; 384 enum ssp_tx_level_trig tx_lev_trig; 385 /* DMA settings */ 386 #ifdef CONFIG_DMA_ENGINE 387 struct dma_chan *dma_rx_channel; 388 struct dma_chan *dma_tx_channel; 389 struct sg_table sgt_rx; 390 struct sg_table sgt_tx; 391 char *dummypage; 392 #endif 393 }; 394 395 /** 396 * struct chip_data - To maintain runtime state of SSP for each client chip 397 * @cr0: Value of control register CR0 of SSP - on later ST variants this 398 * register is 32 bits wide rather than just 16 399 * @cr1: Value of control register CR1 of SSP 400 * @dmacr: Value of DMA control Register of SSP 401 * @cpsr: Value of Clock prescale register 402 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 403 * @enable_dma: Whether to enable DMA or not 404 * @read: function ptr to be used to read when doing xfer for this chip 405 * @write: function ptr to be used to write when doing xfer for this chip 406 * @cs_control: chip select callback provided by chip 407 * @xfer_type: polling/interrupt/DMA 408 * 409 * Runtime state of the SSP controller, maintained per chip, 410 * This would be set according to the current message that would be served 411 */ 412 struct chip_data { 413 u32 cr0; 414 u16 cr1; 415 u16 dmacr; 416 u16 cpsr; 417 u8 n_bytes; 418 bool enable_dma; 419 enum ssp_reading read; 420 enum ssp_writing write; 421 void (*cs_control) (u32 command); 422 int xfer_type; 423 }; 424 425 /** 426 * null_cs_control - Dummy chip select function 427 * @command: select/delect the chip 428 * 429 * If no chip select function is provided by client this is used as dummy 430 * chip select 431 */ 432 static void null_cs_control(u32 command) 433 { 434 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 435 } 436 437 /** 438 * giveback - current spi_message is over, schedule next message and call 439 * callback of this message. Assumes that caller already 440 * set message->status; dma and pio irqs are blocked 441 * @pl022: SSP driver private data structure 442 */ 443 static void giveback(struct pl022 *pl022) 444 { 445 struct spi_transfer *last_transfer; 446 unsigned long flags; 447 struct spi_message *msg; 448 void (*curr_cs_control) (u32 command); 449 450 /* 451 * This local reference to the chip select function 452 * is needed because we set curr_chip to NULL 453 * as a step toward termininating the message. 454 */ 455 curr_cs_control = pl022->cur_chip->cs_control; 456 spin_lock_irqsave(&pl022->queue_lock, flags); 457 msg = pl022->cur_msg; 458 pl022->cur_msg = NULL; 459 pl022->cur_transfer = NULL; 460 pl022->cur_chip = NULL; 461 queue_work(pl022->workqueue, &pl022->pump_messages); 462 spin_unlock_irqrestore(&pl022->queue_lock, flags); 463 464 last_transfer = list_entry(msg->transfers.prev, 465 struct spi_transfer, 466 transfer_list); 467 468 /* Delay if requested before any change in chip select */ 469 if (last_transfer->delay_usecs) 470 /* 471 * FIXME: This runs in interrupt context. 472 * Is this really smart? 473 */ 474 udelay(last_transfer->delay_usecs); 475 476 /* 477 * Drop chip select UNLESS cs_change is true or we are returning 478 * a message with an error, or next message is for another chip 479 */ 480 if (!last_transfer->cs_change) 481 curr_cs_control(SSP_CHIP_DESELECT); 482 else { 483 struct spi_message *next_msg; 484 485 /* Holding of cs was hinted, but we need to make sure 486 * the next message is for the same chip. Don't waste 487 * time with the following tests unless this was hinted. 488 * 489 * We cannot postpone this until pump_messages, because 490 * after calling msg->complete (below) the driver that 491 * sent the current message could be unloaded, which 492 * could invalidate the cs_control() callback... 493 */ 494 495 /* get a pointer to the next message, if any */ 496 spin_lock_irqsave(&pl022->queue_lock, flags); 497 if (list_empty(&pl022->queue)) 498 next_msg = NULL; 499 else 500 next_msg = list_entry(pl022->queue.next, 501 struct spi_message, queue); 502 spin_unlock_irqrestore(&pl022->queue_lock, flags); 503 504 /* see if the next and current messages point 505 * to the same chip 506 */ 507 if (next_msg && next_msg->spi != msg->spi) 508 next_msg = NULL; 509 if (!next_msg || msg->state == STATE_ERROR) 510 curr_cs_control(SSP_CHIP_DESELECT); 511 } 512 msg->state = NULL; 513 if (msg->complete) 514 msg->complete(msg->context); 515 /* This message is completed, so let's turn off the clocks & power */ 516 pm_runtime_put(&pl022->adev->dev); 517 } 518 519 /** 520 * flush - flush the FIFO to reach a clean state 521 * @pl022: SSP driver private data structure 522 */ 523 static int flush(struct pl022 *pl022) 524 { 525 unsigned long limit = loops_per_jiffy << 1; 526 527 dev_dbg(&pl022->adev->dev, "flush\n"); 528 do { 529 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 530 readw(SSP_DR(pl022->virtbase)); 531 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 532 533 pl022->exp_fifo_level = 0; 534 535 return limit; 536 } 537 538 /** 539 * restore_state - Load configuration of current chip 540 * @pl022: SSP driver private data structure 541 */ 542 static void restore_state(struct pl022 *pl022) 543 { 544 struct chip_data *chip = pl022->cur_chip; 545 546 if (pl022->vendor->extended_cr) 547 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 548 else 549 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 550 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 551 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 552 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 553 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 554 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 555 } 556 557 /* 558 * Default SSP Register Values 559 */ 560 #define DEFAULT_SSP_REG_CR0 ( \ 561 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 562 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 563 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 564 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 565 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 566 ) 567 568 /* ST versions have slightly different bit layout */ 569 #define DEFAULT_SSP_REG_CR0_ST ( \ 570 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 571 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 572 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 573 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 574 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 575 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 576 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 577 ) 578 579 /* The PL023 version is slightly different again */ 580 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 581 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 582 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 583 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 584 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 585 ) 586 587 #define DEFAULT_SSP_REG_CR1 ( \ 588 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 589 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 590 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 591 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 592 ) 593 594 /* ST versions extend this register to use all 16 bits */ 595 #define DEFAULT_SSP_REG_CR1_ST ( \ 596 DEFAULT_SSP_REG_CR1 | \ 597 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 598 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 599 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 600 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 601 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 602 ) 603 604 /* 605 * The PL023 variant has further differences: no loopback mode, no microwire 606 * support, and a new clock feedback delay setting. 607 */ 608 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 609 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 610 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 611 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 612 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 613 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 614 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 615 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 616 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 617 ) 618 619 #define DEFAULT_SSP_REG_CPSR ( \ 620 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 621 ) 622 623 #define DEFAULT_SSP_REG_DMACR (\ 624 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 625 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 626 ) 627 628 /** 629 * load_ssp_default_config - Load default configuration for SSP 630 * @pl022: SSP driver private data structure 631 */ 632 static void load_ssp_default_config(struct pl022 *pl022) 633 { 634 if (pl022->vendor->pl023) { 635 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 636 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 637 } else if (pl022->vendor->extended_cr) { 638 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 639 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 640 } else { 641 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 642 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 643 } 644 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 645 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 646 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 647 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 648 } 649 650 /** 651 * This will write to TX and read from RX according to the parameters 652 * set in pl022. 653 */ 654 static void readwriter(struct pl022 *pl022) 655 { 656 657 /* 658 * The FIFO depth is different between primecell variants. 659 * I believe filling in too much in the FIFO might cause 660 * errons in 8bit wide transfers on ARM variants (just 8 words 661 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 662 * 663 * To prevent this issue, the TX FIFO is only filled to the 664 * unused RX FIFO fill length, regardless of what the TX 665 * FIFO status flag indicates. 666 */ 667 dev_dbg(&pl022->adev->dev, 668 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 669 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 670 671 /* Read as much as you can */ 672 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 673 && (pl022->rx < pl022->rx_end)) { 674 switch (pl022->read) { 675 case READING_NULL: 676 readw(SSP_DR(pl022->virtbase)); 677 break; 678 case READING_U8: 679 *(u8 *) (pl022->rx) = 680 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 681 break; 682 case READING_U16: 683 *(u16 *) (pl022->rx) = 684 (u16) readw(SSP_DR(pl022->virtbase)); 685 break; 686 case READING_U32: 687 *(u32 *) (pl022->rx) = 688 readl(SSP_DR(pl022->virtbase)); 689 break; 690 } 691 pl022->rx += (pl022->cur_chip->n_bytes); 692 pl022->exp_fifo_level--; 693 } 694 /* 695 * Write as much as possible up to the RX FIFO size 696 */ 697 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 698 && (pl022->tx < pl022->tx_end)) { 699 switch (pl022->write) { 700 case WRITING_NULL: 701 writew(0x0, SSP_DR(pl022->virtbase)); 702 break; 703 case WRITING_U8: 704 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 705 break; 706 case WRITING_U16: 707 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 708 break; 709 case WRITING_U32: 710 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 711 break; 712 } 713 pl022->tx += (pl022->cur_chip->n_bytes); 714 pl022->exp_fifo_level++; 715 /* 716 * This inner reader takes care of things appearing in the RX 717 * FIFO as we're transmitting. This will happen a lot since the 718 * clock starts running when you put things into the TX FIFO, 719 * and then things are continuously clocked into the RX FIFO. 720 */ 721 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 722 && (pl022->rx < pl022->rx_end)) { 723 switch (pl022->read) { 724 case READING_NULL: 725 readw(SSP_DR(pl022->virtbase)); 726 break; 727 case READING_U8: 728 *(u8 *) (pl022->rx) = 729 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 730 break; 731 case READING_U16: 732 *(u16 *) (pl022->rx) = 733 (u16) readw(SSP_DR(pl022->virtbase)); 734 break; 735 case READING_U32: 736 *(u32 *) (pl022->rx) = 737 readl(SSP_DR(pl022->virtbase)); 738 break; 739 } 740 pl022->rx += (pl022->cur_chip->n_bytes); 741 pl022->exp_fifo_level--; 742 } 743 } 744 /* 745 * When we exit here the TX FIFO should be full and the RX FIFO 746 * should be empty 747 */ 748 } 749 750 /** 751 * next_transfer - Move to the Next transfer in the current spi message 752 * @pl022: SSP driver private data structure 753 * 754 * This function moves though the linked list of spi transfers in the 755 * current spi message and returns with the state of current spi 756 * message i.e whether its last transfer is done(STATE_DONE) or 757 * Next transfer is ready(STATE_RUNNING) 758 */ 759 static void *next_transfer(struct pl022 *pl022) 760 { 761 struct spi_message *msg = pl022->cur_msg; 762 struct spi_transfer *trans = pl022->cur_transfer; 763 764 /* Move to next transfer */ 765 if (trans->transfer_list.next != &msg->transfers) { 766 pl022->cur_transfer = 767 list_entry(trans->transfer_list.next, 768 struct spi_transfer, transfer_list); 769 return STATE_RUNNING; 770 } 771 return STATE_DONE; 772 } 773 774 /* 775 * This DMA functionality is only compiled in if we have 776 * access to the generic DMA devices/DMA engine. 777 */ 778 #ifdef CONFIG_DMA_ENGINE 779 static void unmap_free_dma_scatter(struct pl022 *pl022) 780 { 781 /* Unmap and free the SG tables */ 782 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 783 pl022->sgt_tx.nents, DMA_TO_DEVICE); 784 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 785 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 786 sg_free_table(&pl022->sgt_rx); 787 sg_free_table(&pl022->sgt_tx); 788 } 789 790 static void dma_callback(void *data) 791 { 792 struct pl022 *pl022 = data; 793 struct spi_message *msg = pl022->cur_msg; 794 795 BUG_ON(!pl022->sgt_rx.sgl); 796 797 #ifdef VERBOSE_DEBUG 798 /* 799 * Optionally dump out buffers to inspect contents, this is 800 * good if you want to convince yourself that the loopback 801 * read/write contents are the same, when adopting to a new 802 * DMA engine. 803 */ 804 { 805 struct scatterlist *sg; 806 unsigned int i; 807 808 dma_sync_sg_for_cpu(&pl022->adev->dev, 809 pl022->sgt_rx.sgl, 810 pl022->sgt_rx.nents, 811 DMA_FROM_DEVICE); 812 813 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 814 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 815 print_hex_dump(KERN_ERR, "SPI RX: ", 816 DUMP_PREFIX_OFFSET, 817 16, 818 1, 819 sg_virt(sg), 820 sg_dma_len(sg), 821 1); 822 } 823 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 824 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 825 print_hex_dump(KERN_ERR, "SPI TX: ", 826 DUMP_PREFIX_OFFSET, 827 16, 828 1, 829 sg_virt(sg), 830 sg_dma_len(sg), 831 1); 832 } 833 } 834 #endif 835 836 unmap_free_dma_scatter(pl022); 837 838 /* Update total bytes transferred */ 839 msg->actual_length += pl022->cur_transfer->len; 840 if (pl022->cur_transfer->cs_change) 841 pl022->cur_chip-> 842 cs_control(SSP_CHIP_DESELECT); 843 844 /* Move to next transfer */ 845 msg->state = next_transfer(pl022); 846 tasklet_schedule(&pl022->pump_transfers); 847 } 848 849 static void setup_dma_scatter(struct pl022 *pl022, 850 void *buffer, 851 unsigned int length, 852 struct sg_table *sgtab) 853 { 854 struct scatterlist *sg; 855 int bytesleft = length; 856 void *bufp = buffer; 857 int mapbytes; 858 int i; 859 860 if (buffer) { 861 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 862 /* 863 * If there are less bytes left than what fits 864 * in the current page (plus page alignment offset) 865 * we just feed in this, else we stuff in as much 866 * as we can. 867 */ 868 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 869 mapbytes = bytesleft; 870 else 871 mapbytes = PAGE_SIZE - offset_in_page(bufp); 872 sg_set_page(sg, virt_to_page(bufp), 873 mapbytes, offset_in_page(bufp)); 874 bufp += mapbytes; 875 bytesleft -= mapbytes; 876 dev_dbg(&pl022->adev->dev, 877 "set RX/TX target page @ %p, %d bytes, %d left\n", 878 bufp, mapbytes, bytesleft); 879 } 880 } else { 881 /* Map the dummy buffer on every page */ 882 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 883 if (bytesleft < PAGE_SIZE) 884 mapbytes = bytesleft; 885 else 886 mapbytes = PAGE_SIZE; 887 sg_set_page(sg, virt_to_page(pl022->dummypage), 888 mapbytes, 0); 889 bytesleft -= mapbytes; 890 dev_dbg(&pl022->adev->dev, 891 "set RX/TX to dummy page %d bytes, %d left\n", 892 mapbytes, bytesleft); 893 894 } 895 } 896 BUG_ON(bytesleft); 897 } 898 899 /** 900 * configure_dma - configures the channels for the next transfer 901 * @pl022: SSP driver's private data structure 902 */ 903 static int configure_dma(struct pl022 *pl022) 904 { 905 struct dma_slave_config rx_conf = { 906 .src_addr = SSP_DR(pl022->phybase), 907 .direction = DMA_FROM_DEVICE, 908 }; 909 struct dma_slave_config tx_conf = { 910 .dst_addr = SSP_DR(pl022->phybase), 911 .direction = DMA_TO_DEVICE, 912 }; 913 unsigned int pages; 914 int ret; 915 int rx_sglen, tx_sglen; 916 struct dma_chan *rxchan = pl022->dma_rx_channel; 917 struct dma_chan *txchan = pl022->dma_tx_channel; 918 struct dma_async_tx_descriptor *rxdesc; 919 struct dma_async_tx_descriptor *txdesc; 920 921 /* Check that the channels are available */ 922 if (!rxchan || !txchan) 923 return -ENODEV; 924 925 /* 926 * If supplied, the DMA burstsize should equal the FIFO trigger level. 927 * Notice that the DMA engine uses one-to-one mapping. Since we can 928 * not trigger on 2 elements this needs explicit mapping rather than 929 * calculation. 930 */ 931 switch (pl022->rx_lev_trig) { 932 case SSP_RX_1_OR_MORE_ELEM: 933 rx_conf.src_maxburst = 1; 934 break; 935 case SSP_RX_4_OR_MORE_ELEM: 936 rx_conf.src_maxburst = 4; 937 break; 938 case SSP_RX_8_OR_MORE_ELEM: 939 rx_conf.src_maxburst = 8; 940 break; 941 case SSP_RX_16_OR_MORE_ELEM: 942 rx_conf.src_maxburst = 16; 943 break; 944 case SSP_RX_32_OR_MORE_ELEM: 945 rx_conf.src_maxburst = 32; 946 break; 947 default: 948 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 949 break; 950 } 951 952 switch (pl022->tx_lev_trig) { 953 case SSP_TX_1_OR_MORE_EMPTY_LOC: 954 tx_conf.dst_maxburst = 1; 955 break; 956 case SSP_TX_4_OR_MORE_EMPTY_LOC: 957 tx_conf.dst_maxburst = 4; 958 break; 959 case SSP_TX_8_OR_MORE_EMPTY_LOC: 960 tx_conf.dst_maxburst = 8; 961 break; 962 case SSP_TX_16_OR_MORE_EMPTY_LOC: 963 tx_conf.dst_maxburst = 16; 964 break; 965 case SSP_TX_32_OR_MORE_EMPTY_LOC: 966 tx_conf.dst_maxburst = 32; 967 break; 968 default: 969 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 970 break; 971 } 972 973 switch (pl022->read) { 974 case READING_NULL: 975 /* Use the same as for writing */ 976 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 977 break; 978 case READING_U8: 979 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 980 break; 981 case READING_U16: 982 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 983 break; 984 case READING_U32: 985 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 986 break; 987 } 988 989 switch (pl022->write) { 990 case WRITING_NULL: 991 /* Use the same as for reading */ 992 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 993 break; 994 case WRITING_U8: 995 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 996 break; 997 case WRITING_U16: 998 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 999 break; 1000 case WRITING_U32: 1001 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1002 break; 1003 } 1004 1005 /* SPI pecularity: we need to read and write the same width */ 1006 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1007 rx_conf.src_addr_width = tx_conf.dst_addr_width; 1008 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1009 tx_conf.dst_addr_width = rx_conf.src_addr_width; 1010 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1011 1012 dmaengine_slave_config(rxchan, &rx_conf); 1013 dmaengine_slave_config(txchan, &tx_conf); 1014 1015 /* Create sglists for the transfers */ 1016 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1017 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1018 1019 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1020 if (ret) 1021 goto err_alloc_rx_sg; 1022 1023 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1024 if (ret) 1025 goto err_alloc_tx_sg; 1026 1027 /* Fill in the scatterlists for the RX+TX buffers */ 1028 setup_dma_scatter(pl022, pl022->rx, 1029 pl022->cur_transfer->len, &pl022->sgt_rx); 1030 setup_dma_scatter(pl022, pl022->tx, 1031 pl022->cur_transfer->len, &pl022->sgt_tx); 1032 1033 /* Map DMA buffers */ 1034 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1035 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1036 if (!rx_sglen) 1037 goto err_rx_sgmap; 1038 1039 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1040 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1041 if (!tx_sglen) 1042 goto err_tx_sgmap; 1043 1044 /* Send both scatterlists */ 1045 rxdesc = rxchan->device->device_prep_slave_sg(rxchan, 1046 pl022->sgt_rx.sgl, 1047 rx_sglen, 1048 DMA_FROM_DEVICE, 1049 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1050 if (!rxdesc) 1051 goto err_rxdesc; 1052 1053 txdesc = txchan->device->device_prep_slave_sg(txchan, 1054 pl022->sgt_tx.sgl, 1055 tx_sglen, 1056 DMA_TO_DEVICE, 1057 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1058 if (!txdesc) 1059 goto err_txdesc; 1060 1061 /* Put the callback on the RX transfer only, that should finish last */ 1062 rxdesc->callback = dma_callback; 1063 rxdesc->callback_param = pl022; 1064 1065 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1066 dmaengine_submit(rxdesc); 1067 dmaengine_submit(txdesc); 1068 dma_async_issue_pending(rxchan); 1069 dma_async_issue_pending(txchan); 1070 1071 return 0; 1072 1073 err_txdesc: 1074 dmaengine_terminate_all(txchan); 1075 err_rxdesc: 1076 dmaengine_terminate_all(rxchan); 1077 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1078 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1079 err_tx_sgmap: 1080 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1081 pl022->sgt_tx.nents, DMA_FROM_DEVICE); 1082 err_rx_sgmap: 1083 sg_free_table(&pl022->sgt_tx); 1084 err_alloc_tx_sg: 1085 sg_free_table(&pl022->sgt_rx); 1086 err_alloc_rx_sg: 1087 return -ENOMEM; 1088 } 1089 1090 static int __init pl022_dma_probe(struct pl022 *pl022) 1091 { 1092 dma_cap_mask_t mask; 1093 1094 /* Try to acquire a generic DMA engine slave channel */ 1095 dma_cap_zero(mask); 1096 dma_cap_set(DMA_SLAVE, mask); 1097 /* 1098 * We need both RX and TX channels to do DMA, else do none 1099 * of them. 1100 */ 1101 pl022->dma_rx_channel = dma_request_channel(mask, 1102 pl022->master_info->dma_filter, 1103 pl022->master_info->dma_rx_param); 1104 if (!pl022->dma_rx_channel) { 1105 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1106 goto err_no_rxchan; 1107 } 1108 1109 pl022->dma_tx_channel = dma_request_channel(mask, 1110 pl022->master_info->dma_filter, 1111 pl022->master_info->dma_tx_param); 1112 if (!pl022->dma_tx_channel) { 1113 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1114 goto err_no_txchan; 1115 } 1116 1117 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1118 if (!pl022->dummypage) { 1119 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); 1120 goto err_no_dummypage; 1121 } 1122 1123 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1124 dma_chan_name(pl022->dma_rx_channel), 1125 dma_chan_name(pl022->dma_tx_channel)); 1126 1127 return 0; 1128 1129 err_no_dummypage: 1130 dma_release_channel(pl022->dma_tx_channel); 1131 err_no_txchan: 1132 dma_release_channel(pl022->dma_rx_channel); 1133 pl022->dma_rx_channel = NULL; 1134 err_no_rxchan: 1135 dev_err(&pl022->adev->dev, 1136 "Failed to work in dma mode, work without dma!\n"); 1137 return -ENODEV; 1138 } 1139 1140 static void terminate_dma(struct pl022 *pl022) 1141 { 1142 struct dma_chan *rxchan = pl022->dma_rx_channel; 1143 struct dma_chan *txchan = pl022->dma_tx_channel; 1144 1145 dmaengine_terminate_all(rxchan); 1146 dmaengine_terminate_all(txchan); 1147 unmap_free_dma_scatter(pl022); 1148 } 1149 1150 static void pl022_dma_remove(struct pl022 *pl022) 1151 { 1152 if (pl022->busy) 1153 terminate_dma(pl022); 1154 if (pl022->dma_tx_channel) 1155 dma_release_channel(pl022->dma_tx_channel); 1156 if (pl022->dma_rx_channel) 1157 dma_release_channel(pl022->dma_rx_channel); 1158 kfree(pl022->dummypage); 1159 } 1160 1161 #else 1162 static inline int configure_dma(struct pl022 *pl022) 1163 { 1164 return -ENODEV; 1165 } 1166 1167 static inline int pl022_dma_probe(struct pl022 *pl022) 1168 { 1169 return 0; 1170 } 1171 1172 static inline void pl022_dma_remove(struct pl022 *pl022) 1173 { 1174 } 1175 #endif 1176 1177 /** 1178 * pl022_interrupt_handler - Interrupt handler for SSP controller 1179 * 1180 * This function handles interrupts generated for an interrupt based transfer. 1181 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1182 * current message's state as STATE_ERROR and schedule the tasklet 1183 * pump_transfers which will do the postprocessing of the current message by 1184 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1185 * more data, and writes data in TX FIFO till it is not full. If we complete 1186 * the transfer we move to the next transfer and schedule the tasklet. 1187 */ 1188 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1189 { 1190 struct pl022 *pl022 = dev_id; 1191 struct spi_message *msg = pl022->cur_msg; 1192 u16 irq_status = 0; 1193 u16 flag = 0; 1194 1195 if (unlikely(!msg)) { 1196 dev_err(&pl022->adev->dev, 1197 "bad message state in interrupt handler"); 1198 /* Never fail */ 1199 return IRQ_HANDLED; 1200 } 1201 1202 /* Read the Interrupt Status Register */ 1203 irq_status = readw(SSP_MIS(pl022->virtbase)); 1204 1205 if (unlikely(!irq_status)) 1206 return IRQ_NONE; 1207 1208 /* 1209 * This handles the FIFO interrupts, the timeout 1210 * interrupts are flatly ignored, they cannot be 1211 * trusted. 1212 */ 1213 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1214 /* 1215 * Overrun interrupt - bail out since our Data has been 1216 * corrupted 1217 */ 1218 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1219 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1220 dev_err(&pl022->adev->dev, 1221 "RXFIFO is full\n"); 1222 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) 1223 dev_err(&pl022->adev->dev, 1224 "TXFIFO is full\n"); 1225 1226 /* 1227 * Disable and clear interrupts, disable SSP, 1228 * mark message with bad status so it can be 1229 * retried. 1230 */ 1231 writew(DISABLE_ALL_INTERRUPTS, 1232 SSP_IMSC(pl022->virtbase)); 1233 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1234 writew((readw(SSP_CR1(pl022->virtbase)) & 1235 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1236 msg->state = STATE_ERROR; 1237 1238 /* Schedule message queue handler */ 1239 tasklet_schedule(&pl022->pump_transfers); 1240 return IRQ_HANDLED; 1241 } 1242 1243 readwriter(pl022); 1244 1245 if ((pl022->tx == pl022->tx_end) && (flag == 0)) { 1246 flag = 1; 1247 /* Disable Transmit interrupt, enable receive interrupt */ 1248 writew((readw(SSP_IMSC(pl022->virtbase)) & 1249 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1250 SSP_IMSC(pl022->virtbase)); 1251 } 1252 1253 /* 1254 * Since all transactions must write as much as shall be read, 1255 * we can conclude the entire transaction once RX is complete. 1256 * At this point, all TX will always be finished. 1257 */ 1258 if (pl022->rx >= pl022->rx_end) { 1259 writew(DISABLE_ALL_INTERRUPTS, 1260 SSP_IMSC(pl022->virtbase)); 1261 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1262 if (unlikely(pl022->rx > pl022->rx_end)) { 1263 dev_warn(&pl022->adev->dev, "read %u surplus " 1264 "bytes (did you request an odd " 1265 "number of bytes on a 16bit bus?)\n", 1266 (u32) (pl022->rx - pl022->rx_end)); 1267 } 1268 /* Update total bytes transferred */ 1269 msg->actual_length += pl022->cur_transfer->len; 1270 if (pl022->cur_transfer->cs_change) 1271 pl022->cur_chip-> 1272 cs_control(SSP_CHIP_DESELECT); 1273 /* Move to next transfer */ 1274 msg->state = next_transfer(pl022); 1275 tasklet_schedule(&pl022->pump_transfers); 1276 return IRQ_HANDLED; 1277 } 1278 1279 return IRQ_HANDLED; 1280 } 1281 1282 /** 1283 * This sets up the pointers to memory for the next message to 1284 * send out on the SPI bus. 1285 */ 1286 static int set_up_next_transfer(struct pl022 *pl022, 1287 struct spi_transfer *transfer) 1288 { 1289 int residue; 1290 1291 /* Sanity check the message for this bus width */ 1292 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1293 if (unlikely(residue != 0)) { 1294 dev_err(&pl022->adev->dev, 1295 "message of %u bytes to transmit but the current " 1296 "chip bus has a data width of %u bytes!\n", 1297 pl022->cur_transfer->len, 1298 pl022->cur_chip->n_bytes); 1299 dev_err(&pl022->adev->dev, "skipping this message\n"); 1300 return -EIO; 1301 } 1302 pl022->tx = (void *)transfer->tx_buf; 1303 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1304 pl022->rx = (void *)transfer->rx_buf; 1305 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1306 pl022->write = 1307 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1308 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1309 return 0; 1310 } 1311 1312 /** 1313 * pump_transfers - Tasklet function which schedules next transfer 1314 * when running in interrupt or DMA transfer mode. 1315 * @data: SSP driver private data structure 1316 * 1317 */ 1318 static void pump_transfers(unsigned long data) 1319 { 1320 struct pl022 *pl022 = (struct pl022 *) data; 1321 struct spi_message *message = NULL; 1322 struct spi_transfer *transfer = NULL; 1323 struct spi_transfer *previous = NULL; 1324 1325 /* Get current state information */ 1326 message = pl022->cur_msg; 1327 transfer = pl022->cur_transfer; 1328 1329 /* Handle for abort */ 1330 if (message->state == STATE_ERROR) { 1331 message->status = -EIO; 1332 giveback(pl022); 1333 return; 1334 } 1335 1336 /* Handle end of message */ 1337 if (message->state == STATE_DONE) { 1338 message->status = 0; 1339 giveback(pl022); 1340 return; 1341 } 1342 1343 /* Delay if requested at end of transfer before CS change */ 1344 if (message->state == STATE_RUNNING) { 1345 previous = list_entry(transfer->transfer_list.prev, 1346 struct spi_transfer, 1347 transfer_list); 1348 if (previous->delay_usecs) 1349 /* 1350 * FIXME: This runs in interrupt context. 1351 * Is this really smart? 1352 */ 1353 udelay(previous->delay_usecs); 1354 1355 /* Drop chip select only if cs_change is requested */ 1356 if (previous->cs_change) 1357 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1358 } else { 1359 /* STATE_START */ 1360 message->state = STATE_RUNNING; 1361 } 1362 1363 if (set_up_next_transfer(pl022, transfer)) { 1364 message->state = STATE_ERROR; 1365 message->status = -EIO; 1366 giveback(pl022); 1367 return; 1368 } 1369 /* Flush the FIFOs and let's go! */ 1370 flush(pl022); 1371 1372 if (pl022->cur_chip->enable_dma) { 1373 if (configure_dma(pl022)) { 1374 dev_dbg(&pl022->adev->dev, 1375 "configuration of DMA failed, fall back to interrupt mode\n"); 1376 goto err_config_dma; 1377 } 1378 return; 1379 } 1380 1381 err_config_dma: 1382 /* enable all interrupts except RX */ 1383 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1384 } 1385 1386 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1387 { 1388 /* 1389 * Default is to enable all interrupts except RX - 1390 * this will be enabled once TX is complete 1391 */ 1392 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; 1393 1394 /* Enable target chip */ 1395 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1396 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1397 /* Error path */ 1398 pl022->cur_msg->state = STATE_ERROR; 1399 pl022->cur_msg->status = -EIO; 1400 giveback(pl022); 1401 return; 1402 } 1403 /* If we're using DMA, set up DMA here */ 1404 if (pl022->cur_chip->enable_dma) { 1405 /* Configure DMA transfer */ 1406 if (configure_dma(pl022)) { 1407 dev_dbg(&pl022->adev->dev, 1408 "configuration of DMA failed, fall back to interrupt mode\n"); 1409 goto err_config_dma; 1410 } 1411 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1412 irqflags = DISABLE_ALL_INTERRUPTS; 1413 } 1414 err_config_dma: 1415 /* Enable SSP, turn on interrupts */ 1416 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1417 SSP_CR1(pl022->virtbase)); 1418 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1419 } 1420 1421 static void do_polling_transfer(struct pl022 *pl022) 1422 { 1423 struct spi_message *message = NULL; 1424 struct spi_transfer *transfer = NULL; 1425 struct spi_transfer *previous = NULL; 1426 struct chip_data *chip; 1427 unsigned long time, timeout; 1428 1429 chip = pl022->cur_chip; 1430 message = pl022->cur_msg; 1431 1432 while (message->state != STATE_DONE) { 1433 /* Handle for abort */ 1434 if (message->state == STATE_ERROR) 1435 break; 1436 transfer = pl022->cur_transfer; 1437 1438 /* Delay if requested at end of transfer */ 1439 if (message->state == STATE_RUNNING) { 1440 previous = 1441 list_entry(transfer->transfer_list.prev, 1442 struct spi_transfer, transfer_list); 1443 if (previous->delay_usecs) 1444 udelay(previous->delay_usecs); 1445 if (previous->cs_change) 1446 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1447 } else { 1448 /* STATE_START */ 1449 message->state = STATE_RUNNING; 1450 pl022->cur_chip->cs_control(SSP_CHIP_SELECT); 1451 } 1452 1453 /* Configuration Changing Per Transfer */ 1454 if (set_up_next_transfer(pl022, transfer)) { 1455 /* Error path */ 1456 message->state = STATE_ERROR; 1457 break; 1458 } 1459 /* Flush FIFOs and enable SSP */ 1460 flush(pl022); 1461 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1462 SSP_CR1(pl022->virtbase)); 1463 1464 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1465 1466 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1467 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1468 time = jiffies; 1469 readwriter(pl022); 1470 if (time_after(time, timeout)) { 1471 dev_warn(&pl022->adev->dev, 1472 "%s: timeout!\n", __func__); 1473 message->state = STATE_ERROR; 1474 goto out; 1475 } 1476 cpu_relax(); 1477 } 1478 1479 /* Update total byte transferred */ 1480 message->actual_length += pl022->cur_transfer->len; 1481 if (pl022->cur_transfer->cs_change) 1482 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); 1483 /* Move to next transfer */ 1484 message->state = next_transfer(pl022); 1485 } 1486 out: 1487 /* Handle end of message */ 1488 if (message->state == STATE_DONE) 1489 message->status = 0; 1490 else 1491 message->status = -EIO; 1492 1493 giveback(pl022); 1494 return; 1495 } 1496 1497 /** 1498 * pump_messages - Workqueue function which processes spi message queue 1499 * @data: pointer to private data of SSP driver 1500 * 1501 * This function checks if there is any spi message in the queue that 1502 * needs processing and delegate control to appropriate function 1503 * do_polling_transfer()/do_interrupt_dma_transfer() 1504 * based on the kind of the transfer 1505 * 1506 */ 1507 static void pump_messages(struct work_struct *work) 1508 { 1509 struct pl022 *pl022 = 1510 container_of(work, struct pl022, pump_messages); 1511 unsigned long flags; 1512 1513 /* Lock queue and check for queue work */ 1514 spin_lock_irqsave(&pl022->queue_lock, flags); 1515 if (list_empty(&pl022->queue) || !pl022->running) { 1516 pl022->busy = false; 1517 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1518 return; 1519 } 1520 /* Make sure we are not already running a message */ 1521 if (pl022->cur_msg) { 1522 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1523 return; 1524 } 1525 /* Extract head of queue */ 1526 pl022->cur_msg = 1527 list_entry(pl022->queue.next, struct spi_message, queue); 1528 1529 list_del_init(&pl022->cur_msg->queue); 1530 pl022->busy = true; 1531 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1532 1533 /* Initial message state */ 1534 pl022->cur_msg->state = STATE_START; 1535 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, 1536 struct spi_transfer, transfer_list); 1537 1538 /* Setup the SPI using the per chip configuration */ 1539 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); 1540 /* 1541 * We enable the core voltage and clocks here, then the clocks 1542 * and core will be disabled when giveback() is called in each method 1543 * (poll/interrupt/DMA) 1544 */ 1545 pm_runtime_get_sync(&pl022->adev->dev); 1546 restore_state(pl022); 1547 flush(pl022); 1548 1549 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1550 do_polling_transfer(pl022); 1551 else 1552 do_interrupt_dma_transfer(pl022); 1553 } 1554 1555 static int __init init_queue(struct pl022 *pl022) 1556 { 1557 INIT_LIST_HEAD(&pl022->queue); 1558 spin_lock_init(&pl022->queue_lock); 1559 1560 pl022->running = false; 1561 pl022->busy = false; 1562 1563 tasklet_init(&pl022->pump_transfers, pump_transfers, 1564 (unsigned long)pl022); 1565 1566 INIT_WORK(&pl022->pump_messages, pump_messages); 1567 pl022->workqueue = create_singlethread_workqueue( 1568 dev_name(pl022->master->dev.parent)); 1569 if (pl022->workqueue == NULL) 1570 return -EBUSY; 1571 1572 return 0; 1573 } 1574 1575 static int start_queue(struct pl022 *pl022) 1576 { 1577 unsigned long flags; 1578 1579 spin_lock_irqsave(&pl022->queue_lock, flags); 1580 1581 if (pl022->running || pl022->busy) { 1582 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1583 return -EBUSY; 1584 } 1585 1586 pl022->running = true; 1587 pl022->cur_msg = NULL; 1588 pl022->cur_transfer = NULL; 1589 pl022->cur_chip = NULL; 1590 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1591 1592 queue_work(pl022->workqueue, &pl022->pump_messages); 1593 1594 return 0; 1595 } 1596 1597 static int stop_queue(struct pl022 *pl022) 1598 { 1599 unsigned long flags; 1600 unsigned limit = 500; 1601 int status = 0; 1602 1603 spin_lock_irqsave(&pl022->queue_lock, flags); 1604 1605 /* This is a bit lame, but is optimized for the common execution path. 1606 * A wait_queue on the pl022->busy could be used, but then the common 1607 * execution path (pump_messages) would be required to call wake_up or 1608 * friends on every SPI message. Do this instead */ 1609 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { 1610 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1611 msleep(10); 1612 spin_lock_irqsave(&pl022->queue_lock, flags); 1613 } 1614 1615 if (!list_empty(&pl022->queue) || pl022->busy) 1616 status = -EBUSY; 1617 else 1618 pl022->running = false; 1619 1620 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1621 1622 return status; 1623 } 1624 1625 static int destroy_queue(struct pl022 *pl022) 1626 { 1627 int status; 1628 1629 status = stop_queue(pl022); 1630 /* we are unloading the module or failing to load (only two calls 1631 * to this routine), and neither call can handle a return value. 1632 * However, destroy_workqueue calls flush_workqueue, and that will 1633 * block until all work is done. If the reason that stop_queue 1634 * timed out is that the work will never finish, then it does no 1635 * good to call destroy_workqueue, so return anyway. */ 1636 if (status != 0) 1637 return status; 1638 1639 destroy_workqueue(pl022->workqueue); 1640 1641 return 0; 1642 } 1643 1644 static int verify_controller_parameters(struct pl022 *pl022, 1645 struct pl022_config_chip const *chip_info) 1646 { 1647 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1648 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1649 dev_err(&pl022->adev->dev, 1650 "interface is configured incorrectly\n"); 1651 return -EINVAL; 1652 } 1653 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1654 (!pl022->vendor->unidir)) { 1655 dev_err(&pl022->adev->dev, 1656 "unidirectional mode not supported in this " 1657 "hardware version\n"); 1658 return -EINVAL; 1659 } 1660 if ((chip_info->hierarchy != SSP_MASTER) 1661 && (chip_info->hierarchy != SSP_SLAVE)) { 1662 dev_err(&pl022->adev->dev, 1663 "hierarchy is configured incorrectly\n"); 1664 return -EINVAL; 1665 } 1666 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1667 && (chip_info->com_mode != DMA_TRANSFER) 1668 && (chip_info->com_mode != POLLING_TRANSFER)) { 1669 dev_err(&pl022->adev->dev, 1670 "Communication mode is configured incorrectly\n"); 1671 return -EINVAL; 1672 } 1673 switch (chip_info->rx_lev_trig) { 1674 case SSP_RX_1_OR_MORE_ELEM: 1675 case SSP_RX_4_OR_MORE_ELEM: 1676 case SSP_RX_8_OR_MORE_ELEM: 1677 /* These are always OK, all variants can handle this */ 1678 break; 1679 case SSP_RX_16_OR_MORE_ELEM: 1680 if (pl022->vendor->fifodepth < 16) { 1681 dev_err(&pl022->adev->dev, 1682 "RX FIFO Trigger Level is configured incorrectly\n"); 1683 return -EINVAL; 1684 } 1685 break; 1686 case SSP_RX_32_OR_MORE_ELEM: 1687 if (pl022->vendor->fifodepth < 32) { 1688 dev_err(&pl022->adev->dev, 1689 "RX FIFO Trigger Level is configured incorrectly\n"); 1690 return -EINVAL; 1691 } 1692 break; 1693 default: 1694 dev_err(&pl022->adev->dev, 1695 "RX FIFO Trigger Level is configured incorrectly\n"); 1696 return -EINVAL; 1697 break; 1698 } 1699 switch (chip_info->tx_lev_trig) { 1700 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1701 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1702 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1703 /* These are always OK, all variants can handle this */ 1704 break; 1705 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1706 if (pl022->vendor->fifodepth < 16) { 1707 dev_err(&pl022->adev->dev, 1708 "TX FIFO Trigger Level is configured incorrectly\n"); 1709 return -EINVAL; 1710 } 1711 break; 1712 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1713 if (pl022->vendor->fifodepth < 32) { 1714 dev_err(&pl022->adev->dev, 1715 "TX FIFO Trigger Level is configured incorrectly\n"); 1716 return -EINVAL; 1717 } 1718 break; 1719 default: 1720 dev_err(&pl022->adev->dev, 1721 "TX FIFO Trigger Level is configured incorrectly\n"); 1722 return -EINVAL; 1723 break; 1724 } 1725 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1726 if ((chip_info->ctrl_len < SSP_BITS_4) 1727 || (chip_info->ctrl_len > SSP_BITS_32)) { 1728 dev_err(&pl022->adev->dev, 1729 "CTRL LEN is configured incorrectly\n"); 1730 return -EINVAL; 1731 } 1732 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1733 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1734 dev_err(&pl022->adev->dev, 1735 "Wait State is configured incorrectly\n"); 1736 return -EINVAL; 1737 } 1738 /* Half duplex is only available in the ST Micro version */ 1739 if (pl022->vendor->extended_cr) { 1740 if ((chip_info->duplex != 1741 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1742 && (chip_info->duplex != 1743 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1744 dev_err(&pl022->adev->dev, 1745 "Microwire duplex mode is configured incorrectly\n"); 1746 return -EINVAL; 1747 } 1748 } else { 1749 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1750 dev_err(&pl022->adev->dev, 1751 "Microwire half duplex mode requested," 1752 " but this is only available in the" 1753 " ST version of PL022\n"); 1754 return -EINVAL; 1755 } 1756 } 1757 return 0; 1758 } 1759 1760 /** 1761 * pl022_transfer - transfer function registered to SPI master framework 1762 * @spi: spi device which is requesting transfer 1763 * @msg: spi message which is to handled is queued to driver queue 1764 * 1765 * This function is registered to the SPI framework for this SPI master 1766 * controller. It will queue the spi_message in the queue of driver if 1767 * the queue is not stopped and return. 1768 */ 1769 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) 1770 { 1771 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1772 unsigned long flags; 1773 1774 spin_lock_irqsave(&pl022->queue_lock, flags); 1775 1776 if (!pl022->running) { 1777 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1778 return -ESHUTDOWN; 1779 } 1780 msg->actual_length = 0; 1781 msg->status = -EINPROGRESS; 1782 msg->state = STATE_START; 1783 1784 list_add_tail(&msg->queue, &pl022->queue); 1785 if (pl022->running && !pl022->busy) 1786 queue_work(pl022->workqueue, &pl022->pump_messages); 1787 1788 spin_unlock_irqrestore(&pl022->queue_lock, flags); 1789 return 0; 1790 } 1791 1792 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1793 { 1794 return rate / (cpsdvsr * (1 + scr)); 1795 } 1796 1797 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1798 ssp_clock_params * clk_freq) 1799 { 1800 /* Lets calculate the frequency parameters */ 1801 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1802 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1803 best_scr = 0, tmp, found = 0; 1804 1805 rate = clk_get_rate(pl022->clk); 1806 /* cpsdvscr = 2 & scr 0 */ 1807 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1808 /* cpsdvsr = 254 & scr = 255 */ 1809 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1810 1811 if (!((freq <= max_tclk) && (freq >= min_tclk))) { 1812 dev_err(&pl022->adev->dev, 1813 "controller data is incorrect: out of range frequency"); 1814 return -EINVAL; 1815 } 1816 1817 /* 1818 * best_freq will give closest possible available rate (<= requested 1819 * freq) for all values of scr & cpsdvsr. 1820 */ 1821 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1822 while (scr <= SCR_MAX) { 1823 tmp = spi_rate(rate, cpsdvsr, scr); 1824 1825 if (tmp > freq) 1826 scr++; 1827 /* 1828 * If found exact value, update and break. 1829 * If found more closer value, update and continue. 1830 */ 1831 else if ((tmp == freq) || (tmp > best_freq)) { 1832 best_freq = tmp; 1833 best_cpsdvsr = cpsdvsr; 1834 best_scr = scr; 1835 1836 if (tmp == freq) 1837 break; 1838 } 1839 scr++; 1840 } 1841 cpsdvsr += 2; 1842 scr = SCR_MIN; 1843 } 1844 1845 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1846 clk_freq->scr = (u8) (best_scr & 0xFF); 1847 dev_dbg(&pl022->adev->dev, 1848 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1849 freq, best_freq); 1850 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1851 clk_freq->cpsdvsr, clk_freq->scr); 1852 1853 return 0; 1854 } 1855 1856 /* 1857 * A piece of default chip info unless the platform 1858 * supplies it. 1859 */ 1860 static const struct pl022_config_chip pl022_default_chip_info = { 1861 .com_mode = POLLING_TRANSFER, 1862 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1863 .hierarchy = SSP_SLAVE, 1864 .slave_tx_disable = DO_NOT_DRIVE_TX, 1865 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1866 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1867 .ctrl_len = SSP_BITS_8, 1868 .wait_state = SSP_MWIRE_WAIT_ZERO, 1869 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1870 .cs_control = null_cs_control, 1871 }; 1872 1873 /** 1874 * pl022_setup - setup function registered to SPI master framework 1875 * @spi: spi device which is requesting setup 1876 * 1877 * This function is registered to the SPI framework for this SPI master 1878 * controller. If it is the first time when setup is called by this device, 1879 * this function will initialize the runtime state for this chip and save 1880 * the same in the device structure. Else it will update the runtime info 1881 * with the updated chip info. Nothing is really being written to the 1882 * controller hardware here, that is not done until the actual transfer 1883 * commence. 1884 */ 1885 static int pl022_setup(struct spi_device *spi) 1886 { 1887 struct pl022_config_chip const *chip_info; 1888 struct chip_data *chip; 1889 struct ssp_clock_params clk_freq = {0, }; 1890 int status = 0; 1891 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1892 unsigned int bits = spi->bits_per_word; 1893 u32 tmp; 1894 1895 if (!spi->max_speed_hz) 1896 return -EINVAL; 1897 1898 /* Get controller_state if one is supplied */ 1899 chip = spi_get_ctldata(spi); 1900 1901 if (chip == NULL) { 1902 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1903 if (!chip) { 1904 dev_err(&spi->dev, 1905 "cannot allocate controller state\n"); 1906 return -ENOMEM; 1907 } 1908 dev_dbg(&spi->dev, 1909 "allocated memory for controller's runtime state\n"); 1910 } 1911 1912 /* Get controller data if one is supplied */ 1913 chip_info = spi->controller_data; 1914 1915 if (chip_info == NULL) { 1916 chip_info = &pl022_default_chip_info; 1917 /* spi_board_info.controller_data not is supplied */ 1918 dev_dbg(&spi->dev, 1919 "using default controller_data settings\n"); 1920 } else 1921 dev_dbg(&spi->dev, 1922 "using user supplied controller_data settings\n"); 1923 1924 /* 1925 * We can override with custom divisors, else we use the board 1926 * frequency setting 1927 */ 1928 if ((0 == chip_info->clk_freq.cpsdvsr) 1929 && (0 == chip_info->clk_freq.scr)) { 1930 status = calculate_effective_freq(pl022, 1931 spi->max_speed_hz, 1932 &clk_freq); 1933 if (status < 0) 1934 goto err_config_params; 1935 } else { 1936 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1937 if ((clk_freq.cpsdvsr % 2) != 0) 1938 clk_freq.cpsdvsr = 1939 clk_freq.cpsdvsr - 1; 1940 } 1941 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1942 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1943 status = -EINVAL; 1944 dev_err(&spi->dev, 1945 "cpsdvsr is configured incorrectly\n"); 1946 goto err_config_params; 1947 } 1948 1949 status = verify_controller_parameters(pl022, chip_info); 1950 if (status) { 1951 dev_err(&spi->dev, "controller data is incorrect"); 1952 goto err_config_params; 1953 } 1954 1955 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1956 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1957 1958 /* Now set controller state based on controller data */ 1959 chip->xfer_type = chip_info->com_mode; 1960 if (!chip_info->cs_control) { 1961 chip->cs_control = null_cs_control; 1962 dev_warn(&spi->dev, 1963 "chip select function is NULL for this chip\n"); 1964 } else 1965 chip->cs_control = chip_info->cs_control; 1966 1967 if (bits <= 3) { 1968 /* PL022 doesn't support less than 4-bits */ 1969 status = -ENOTSUPP; 1970 goto err_config_params; 1971 } else if (bits <= 8) { 1972 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1973 chip->n_bytes = 1; 1974 chip->read = READING_U8; 1975 chip->write = WRITING_U8; 1976 } else if (bits <= 16) { 1977 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1978 chip->n_bytes = 2; 1979 chip->read = READING_U16; 1980 chip->write = WRITING_U16; 1981 } else { 1982 if (pl022->vendor->max_bpw >= 32) { 1983 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1984 chip->n_bytes = 4; 1985 chip->read = READING_U32; 1986 chip->write = WRITING_U32; 1987 } else { 1988 dev_err(&spi->dev, 1989 "illegal data size for this controller!\n"); 1990 dev_err(&spi->dev, 1991 "a standard pl022 can only handle " 1992 "1 <= n <= 16 bit words\n"); 1993 status = -ENOTSUPP; 1994 goto err_config_params; 1995 } 1996 } 1997 1998 /* Now Initialize all register settings required for this chip */ 1999 chip->cr0 = 0; 2000 chip->cr1 = 0; 2001 chip->dmacr = 0; 2002 chip->cpsr = 0; 2003 if ((chip_info->com_mode == DMA_TRANSFER) 2004 && ((pl022->master_info)->enable_dma)) { 2005 chip->enable_dma = true; 2006 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 2007 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2008 SSP_DMACR_MASK_RXDMAE, 0); 2009 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 2010 SSP_DMACR_MASK_TXDMAE, 1); 2011 } else { 2012 chip->enable_dma = false; 2013 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 2014 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2015 SSP_DMACR_MASK_RXDMAE, 0); 2016 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 2017 SSP_DMACR_MASK_TXDMAE, 1); 2018 } 2019 2020 chip->cpsr = clk_freq.cpsdvsr; 2021 2022 /* Special setup for the ST micro extended control registers */ 2023 if (pl022->vendor->extended_cr) { 2024 u32 etx; 2025 2026 if (pl022->vendor->pl023) { 2027 /* These bits are only in the PL023 */ 2028 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 2029 SSP_CR1_MASK_FBCLKDEL_ST, 13); 2030 } else { 2031 /* These bits are in the PL022 but not PL023 */ 2032 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 2033 SSP_CR0_MASK_HALFDUP_ST, 5); 2034 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 2035 SSP_CR0_MASK_CSS_ST, 16); 2036 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2037 SSP_CR0_MASK_FRF_ST, 21); 2038 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 2039 SSP_CR1_MASK_MWAIT_ST, 6); 2040 } 2041 SSP_WRITE_BITS(chip->cr0, bits - 1, 2042 SSP_CR0_MASK_DSS_ST, 0); 2043 2044 if (spi->mode & SPI_LSB_FIRST) { 2045 tmp = SSP_RX_LSB; 2046 etx = SSP_TX_LSB; 2047 } else { 2048 tmp = SSP_RX_MSB; 2049 etx = SSP_TX_MSB; 2050 } 2051 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2052 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2053 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2054 SSP_CR1_MASK_RXIFLSEL_ST, 7); 2055 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2056 SSP_CR1_MASK_TXIFLSEL_ST, 10); 2057 } else { 2058 SSP_WRITE_BITS(chip->cr0, bits - 1, 2059 SSP_CR0_MASK_DSS, 0); 2060 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2061 SSP_CR0_MASK_FRF, 4); 2062 } 2063 2064 /* Stuff that is common for all versions */ 2065 if (spi->mode & SPI_CPOL) 2066 tmp = SSP_CLK_POL_IDLE_HIGH; 2067 else 2068 tmp = SSP_CLK_POL_IDLE_LOW; 2069 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2070 2071 if (spi->mode & SPI_CPHA) 2072 tmp = SSP_CLK_SECOND_EDGE; 2073 else 2074 tmp = SSP_CLK_FIRST_EDGE; 2075 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2076 2077 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2078 /* Loopback is available on all versions except PL023 */ 2079 if (pl022->vendor->loopback) { 2080 if (spi->mode & SPI_LOOP) 2081 tmp = LOOPBACK_ENABLED; 2082 else 2083 tmp = LOOPBACK_DISABLED; 2084 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2085 } 2086 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2087 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2088 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2089 3); 2090 2091 /* Save controller_state */ 2092 spi_set_ctldata(spi, chip); 2093 return status; 2094 err_config_params: 2095 spi_set_ctldata(spi, NULL); 2096 kfree(chip); 2097 return status; 2098 } 2099 2100 /** 2101 * pl022_cleanup - cleanup function registered to SPI master framework 2102 * @spi: spi device which is requesting cleanup 2103 * 2104 * This function is registered to the SPI framework for this SPI master 2105 * controller. It will free the runtime state of chip. 2106 */ 2107 static void pl022_cleanup(struct spi_device *spi) 2108 { 2109 struct chip_data *chip = spi_get_ctldata(spi); 2110 2111 spi_set_ctldata(spi, NULL); 2112 kfree(chip); 2113 } 2114 2115 static int __devinit 2116 pl022_probe(struct amba_device *adev, const struct amba_id *id) 2117 { 2118 struct device *dev = &adev->dev; 2119 struct pl022_ssp_controller *platform_info = adev->dev.platform_data; 2120 struct spi_master *master; 2121 struct pl022 *pl022 = NULL; /*Data for this driver */ 2122 int status = 0; 2123 2124 dev_info(&adev->dev, 2125 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2126 if (platform_info == NULL) { 2127 dev_err(&adev->dev, "probe - no platform data supplied\n"); 2128 status = -ENODEV; 2129 goto err_no_pdata; 2130 } 2131 2132 /* Allocate master with space for data */ 2133 master = spi_alloc_master(dev, sizeof(struct pl022)); 2134 if (master == NULL) { 2135 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2136 status = -ENOMEM; 2137 goto err_no_master; 2138 } 2139 2140 pl022 = spi_master_get_devdata(master); 2141 pl022->master = master; 2142 pl022->master_info = platform_info; 2143 pl022->adev = adev; 2144 pl022->vendor = id->data; 2145 2146 /* 2147 * Bus Number Which has been Assigned to this SSP controller 2148 * on this board 2149 */ 2150 master->bus_num = platform_info->bus_id; 2151 master->num_chipselect = platform_info->num_chipselect; 2152 master->cleanup = pl022_cleanup; 2153 master->setup = pl022_setup; 2154 master->transfer = pl022_transfer; 2155 2156 /* 2157 * Supports mode 0-3, loopback, and active low CS. Transfers are 2158 * always MS bit first on the original pl022. 2159 */ 2160 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2161 if (pl022->vendor->extended_cr) 2162 master->mode_bits |= SPI_LSB_FIRST; 2163 2164 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2165 2166 status = amba_request_regions(adev, NULL); 2167 if (status) 2168 goto err_no_ioregion; 2169 2170 pl022->phybase = adev->res.start; 2171 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 2172 if (pl022->virtbase == NULL) { 2173 status = -ENOMEM; 2174 goto err_no_ioremap; 2175 } 2176 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", 2177 adev->res.start, pl022->virtbase); 2178 2179 pl022->clk = clk_get(&adev->dev, NULL); 2180 if (IS_ERR(pl022->clk)) { 2181 status = PTR_ERR(pl022->clk); 2182 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2183 goto err_no_clk; 2184 } 2185 2186 status = clk_prepare(pl022->clk); 2187 if (status) { 2188 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); 2189 goto err_clk_prep; 2190 } 2191 2192 status = clk_enable(pl022->clk); 2193 if (status) { 2194 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2195 goto err_no_clk_en; 2196 } 2197 2198 /* Disable SSP */ 2199 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2200 SSP_CR1(pl022->virtbase)); 2201 load_ssp_default_config(pl022); 2202 2203 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", 2204 pl022); 2205 if (status < 0) { 2206 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2207 goto err_no_irq; 2208 } 2209 2210 /* Get DMA channels */ 2211 if (platform_info->enable_dma) { 2212 status = pl022_dma_probe(pl022); 2213 if (status != 0) 2214 platform_info->enable_dma = 0; 2215 } 2216 2217 /* Initialize and start queue */ 2218 status = init_queue(pl022); 2219 if (status != 0) { 2220 dev_err(&adev->dev, "probe - problem initializing queue\n"); 2221 goto err_init_queue; 2222 } 2223 status = start_queue(pl022); 2224 if (status != 0) { 2225 dev_err(&adev->dev, "probe - problem starting queue\n"); 2226 goto err_start_queue; 2227 } 2228 /* Register with the SPI framework */ 2229 amba_set_drvdata(adev, pl022); 2230 status = spi_register_master(master); 2231 if (status != 0) { 2232 dev_err(&adev->dev, 2233 "probe - problem registering spi master\n"); 2234 goto err_spi_register; 2235 } 2236 dev_dbg(dev, "probe succeeded\n"); 2237 2238 /* let runtime pm put suspend */ 2239 pm_runtime_put(dev); 2240 return 0; 2241 2242 err_spi_register: 2243 err_start_queue: 2244 err_init_queue: 2245 destroy_queue(pl022); 2246 if (platform_info->enable_dma) 2247 pl022_dma_remove(pl022); 2248 2249 free_irq(adev->irq[0], pl022); 2250 err_no_irq: 2251 clk_disable(pl022->clk); 2252 err_no_clk_en: 2253 clk_unprepare(pl022->clk); 2254 err_clk_prep: 2255 clk_put(pl022->clk); 2256 err_no_clk: 2257 iounmap(pl022->virtbase); 2258 err_no_ioremap: 2259 amba_release_regions(adev); 2260 err_no_ioregion: 2261 spi_master_put(master); 2262 err_no_master: 2263 err_no_pdata: 2264 return status; 2265 } 2266 2267 static int __devexit 2268 pl022_remove(struct amba_device *adev) 2269 { 2270 struct pl022 *pl022 = amba_get_drvdata(adev); 2271 2272 if (!pl022) 2273 return 0; 2274 2275 /* 2276 * undo pm_runtime_put() in probe. I assume that we're not 2277 * accessing the primecell here. 2278 */ 2279 pm_runtime_get_noresume(&adev->dev); 2280 2281 /* Remove the queue */ 2282 if (destroy_queue(pl022) != 0) 2283 dev_err(&adev->dev, "queue remove failed\n"); 2284 load_ssp_default_config(pl022); 2285 if (pl022->master_info->enable_dma) 2286 pl022_dma_remove(pl022); 2287 2288 free_irq(adev->irq[0], pl022); 2289 clk_disable(pl022->clk); 2290 clk_unprepare(pl022->clk); 2291 clk_put(pl022->clk); 2292 iounmap(pl022->virtbase); 2293 amba_release_regions(adev); 2294 tasklet_disable(&pl022->pump_transfers); 2295 spi_unregister_master(pl022->master); 2296 spi_master_put(pl022->master); 2297 amba_set_drvdata(adev, NULL); 2298 return 0; 2299 } 2300 2301 #ifdef CONFIG_SUSPEND 2302 static int pl022_suspend(struct device *dev) 2303 { 2304 struct pl022 *pl022 = dev_get_drvdata(dev); 2305 int status = 0; 2306 2307 status = stop_queue(pl022); 2308 if (status) { 2309 dev_warn(dev, "suspend cannot stop queue\n"); 2310 return status; 2311 } 2312 2313 amba_vcore_enable(pl022->adev); 2314 amba_pclk_enable(pl022->adev); 2315 load_ssp_default_config(pl022); 2316 amba_pclk_disable(pl022->adev); 2317 amba_vcore_disable(pl022->adev); 2318 dev_dbg(dev, "suspended\n"); 2319 return 0; 2320 } 2321 2322 static int pl022_resume(struct device *dev) 2323 { 2324 struct pl022 *pl022 = dev_get_drvdata(dev); 2325 int status = 0; 2326 2327 /* Start the queue running */ 2328 status = start_queue(pl022); 2329 if (status) 2330 dev_err(dev, "problem starting queue (%d)\n", status); 2331 else 2332 dev_dbg(dev, "resumed\n"); 2333 2334 return status; 2335 } 2336 #endif /* CONFIG_PM */ 2337 2338 #ifdef CONFIG_PM_RUNTIME 2339 static int pl022_runtime_suspend(struct device *dev) 2340 { 2341 struct pl022 *pl022 = dev_get_drvdata(dev); 2342 2343 clk_disable(pl022->clk); 2344 amba_vcore_disable(pl022->adev); 2345 2346 return 0; 2347 } 2348 2349 static int pl022_runtime_resume(struct device *dev) 2350 { 2351 struct pl022 *pl022 = dev_get_drvdata(dev); 2352 2353 amba_vcore_enable(pl022->adev); 2354 clk_enable(pl022->clk); 2355 2356 return 0; 2357 } 2358 #endif 2359 2360 static const struct dev_pm_ops pl022_dev_pm_ops = { 2361 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2362 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2363 }; 2364 2365 static struct vendor_data vendor_arm = { 2366 .fifodepth = 8, 2367 .max_bpw = 16, 2368 .unidir = false, 2369 .extended_cr = false, 2370 .pl023 = false, 2371 .loopback = true, 2372 }; 2373 2374 static struct vendor_data vendor_st = { 2375 .fifodepth = 32, 2376 .max_bpw = 32, 2377 .unidir = false, 2378 .extended_cr = true, 2379 .pl023 = false, 2380 .loopback = true, 2381 }; 2382 2383 static struct vendor_data vendor_st_pl023 = { 2384 .fifodepth = 32, 2385 .max_bpw = 32, 2386 .unidir = false, 2387 .extended_cr = true, 2388 .pl023 = true, 2389 .loopback = false, 2390 }; 2391 2392 static struct vendor_data vendor_db5500_pl023 = { 2393 .fifodepth = 32, 2394 .max_bpw = 32, 2395 .unidir = false, 2396 .extended_cr = true, 2397 .pl023 = true, 2398 .loopback = true, 2399 }; 2400 2401 static struct amba_id pl022_ids[] = { 2402 { 2403 /* 2404 * ARM PL022 variant, this has a 16bit wide 2405 * and 8 locations deep TX/RX FIFO 2406 */ 2407 .id = 0x00041022, 2408 .mask = 0x000fffff, 2409 .data = &vendor_arm, 2410 }, 2411 { 2412 /* 2413 * ST Micro derivative, this has 32bit wide 2414 * and 32 locations deep TX/RX FIFO 2415 */ 2416 .id = 0x01080022, 2417 .mask = 0xffffffff, 2418 .data = &vendor_st, 2419 }, 2420 { 2421 /* 2422 * ST-Ericsson derivative "PL023" (this is not 2423 * an official ARM number), this is a PL022 SSP block 2424 * stripped to SPI mode only, it has 32bit wide 2425 * and 32 locations deep TX/RX FIFO but no extended 2426 * CR0/CR1 register 2427 */ 2428 .id = 0x00080023, 2429 .mask = 0xffffffff, 2430 .data = &vendor_st_pl023, 2431 }, 2432 { 2433 .id = 0x10080023, 2434 .mask = 0xffffffff, 2435 .data = &vendor_db5500_pl023, 2436 }, 2437 { 0, 0 }, 2438 }; 2439 2440 static struct amba_driver pl022_driver = { 2441 .drv = { 2442 .name = "ssp-pl022", 2443 .pm = &pl022_dev_pm_ops, 2444 }, 2445 .id_table = pl022_ids, 2446 .probe = pl022_probe, 2447 .remove = __devexit_p(pl022_remove), 2448 }; 2449 2450 static int __init pl022_init(void) 2451 { 2452 return amba_driver_register(&pl022_driver); 2453 } 2454 subsys_initcall(pl022_init); 2455 2456 static void __exit pl022_exit(void) 2457 { 2458 amba_driver_unregister(&pl022_driver); 2459 } 2460 module_exit(pl022_exit); 2461 2462 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2463 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2464 MODULE_LICENSE("GPL"); 2465