1 /* 2 * PIC32 Quad SPI controller driver. 3 * 4 * Purna Chandra Mandal <purna.mandal@microchip.com> 5 * Copyright (c) 2016, Microchip Technology Inc. 6 * 7 * This program is free software; you can distribute it and/or modify it 8 * under the terms of the GNU General Public License (Version 2) as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/platform_device.h> 25 #include <linux/slab.h> 26 #include <linux/spi/spi.h> 27 28 /* SQI registers */ 29 #define PESQI_XIP_CONF1_REG 0x00 30 #define PESQI_XIP_CONF2_REG 0x04 31 #define PESQI_CONF_REG 0x08 32 #define PESQI_CTRL_REG 0x0C 33 #define PESQI_CLK_CTRL_REG 0x10 34 #define PESQI_CMD_THRES_REG 0x14 35 #define PESQI_INT_THRES_REG 0x18 36 #define PESQI_INT_ENABLE_REG 0x1C 37 #define PESQI_INT_STAT_REG 0x20 38 #define PESQI_TX_DATA_REG 0x24 39 #define PESQI_RX_DATA_REG 0x28 40 #define PESQI_STAT1_REG 0x2C 41 #define PESQI_STAT2_REG 0x30 42 #define PESQI_BD_CTRL_REG 0x34 43 #define PESQI_BD_CUR_ADDR_REG 0x38 44 #define PESQI_BD_BASE_ADDR_REG 0x40 45 #define PESQI_BD_STAT_REG 0x44 46 #define PESQI_BD_POLL_CTRL_REG 0x48 47 #define PESQI_BD_TX_DMA_STAT_REG 0x4C 48 #define PESQI_BD_RX_DMA_STAT_REG 0x50 49 #define PESQI_THRES_REG 0x54 50 #define PESQI_INT_SIGEN_REG 0x58 51 52 /* PESQI_CONF_REG fields */ 53 #define PESQI_MODE 0x7 54 #define PESQI_MODE_BOOT 0 55 #define PESQI_MODE_PIO 1 56 #define PESQI_MODE_DMA 2 57 #define PESQI_MODE_XIP 3 58 #define PESQI_MODE_SHIFT 0 59 #define PESQI_CPHA BIT(3) 60 #define PESQI_CPOL BIT(4) 61 #define PESQI_LSBF BIT(5) 62 #define PESQI_RXLATCH BIT(7) 63 #define PESQI_SERMODE BIT(8) 64 #define PESQI_WP_EN BIT(9) 65 #define PESQI_HOLD_EN BIT(10) 66 #define PESQI_BURST_EN BIT(12) 67 #define PESQI_CS_CTRL_HW BIT(15) 68 #define PESQI_SOFT_RESET BIT(16) 69 #define PESQI_LANES_SHIFT 20 70 #define PESQI_SINGLE_LANE 0 71 #define PESQI_DUAL_LANE 1 72 #define PESQI_QUAD_LANE 2 73 #define PESQI_CSEN_SHIFT 24 74 #define PESQI_EN BIT(23) 75 76 /* PESQI_CLK_CTRL_REG fields */ 77 #define PESQI_CLK_EN BIT(0) 78 #define PESQI_CLK_STABLE BIT(1) 79 #define PESQI_CLKDIV_SHIFT 8 80 #define PESQI_CLKDIV 0xff 81 82 /* PESQI_INT_THR/CMD_THR_REG */ 83 #define PESQI_TXTHR_MASK 0x1f 84 #define PESQI_TXTHR_SHIFT 8 85 #define PESQI_RXTHR_MASK 0x1f 86 #define PESQI_RXTHR_SHIFT 0 87 88 /* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */ 89 #define PESQI_TXEMPTY BIT(0) 90 #define PESQI_TXFULL BIT(1) 91 #define PESQI_TXTHR BIT(2) 92 #define PESQI_RXEMPTY BIT(3) 93 #define PESQI_RXFULL BIT(4) 94 #define PESQI_RXTHR BIT(5) 95 #define PESQI_BDDONE BIT(9) /* BD processing complete */ 96 #define PESQI_PKTCOMP BIT(10) /* packet processing complete */ 97 #define PESQI_DMAERR BIT(11) /* error */ 98 99 /* PESQI_BD_CTRL_REG */ 100 #define PESQI_DMA_EN BIT(0) /* enable DMA engine */ 101 #define PESQI_POLL_EN BIT(1) /* enable polling */ 102 #define PESQI_BDP_START BIT(2) /* start BD processor */ 103 104 /* PESQI controller buffer descriptor */ 105 struct buf_desc { 106 u32 bd_ctrl; /* control */ 107 u32 bd_status; /* reserved */ 108 u32 bd_addr; /* DMA buffer addr */ 109 u32 bd_nextp; /* next item in chain */ 110 }; 111 112 /* bd_ctrl */ 113 #define BD_BUFLEN 0x1ff 114 #define BD_CBD_INT_EN BIT(16) /* Current BD is processed */ 115 #define BD_PKT_INT_EN BIT(17) /* All BDs of PKT processed */ 116 #define BD_LIFM BIT(18) /* last data of pkt */ 117 #define BD_LAST BIT(19) /* end of list */ 118 #define BD_DATA_RECV BIT(20) /* receive data */ 119 #define BD_DDR BIT(21) /* DDR mode */ 120 #define BD_DUAL BIT(22) /* Dual SPI */ 121 #define BD_QUAD BIT(23) /* Quad SPI */ 122 #define BD_LSBF BIT(25) /* LSB First */ 123 #define BD_STAT_CHECK BIT(27) /* Status poll */ 124 #define BD_DEVSEL_SHIFT 28 /* CS */ 125 #define BD_CS_DEASSERT BIT(30) /* de-assert CS after current BD */ 126 #define BD_EN BIT(31) /* BD owned by H/W */ 127 128 /** 129 * struct ring_desc - Representation of SQI ring descriptor 130 * @list: list element to add to free or used list. 131 * @bd: PESQI controller buffer descriptor 132 * @bd_dma: DMA address of PESQI controller buffer descriptor 133 * @xfer_len: transfer length 134 */ 135 struct ring_desc { 136 struct list_head list; 137 struct buf_desc *bd; 138 dma_addr_t bd_dma; 139 u32 xfer_len; 140 }; 141 142 /* Global constants */ 143 #define PESQI_BD_BUF_LEN_MAX 256 144 #define PESQI_BD_COUNT 256 /* max 64KB data per spi message */ 145 146 struct pic32_sqi { 147 void __iomem *regs; 148 struct clk *sys_clk; 149 struct clk *base_clk; /* drives spi clock */ 150 struct spi_master *master; 151 int irq; 152 struct completion xfer_done; 153 struct ring_desc *ring; 154 void *bd; 155 dma_addr_t bd_dma; 156 struct list_head bd_list_free; /* free */ 157 struct list_head bd_list_used; /* allocated */ 158 struct spi_device *cur_spi; 159 u32 cur_speed; 160 u8 cur_mode; 161 }; 162 163 static inline void pic32_setbits(void __iomem *reg, u32 set) 164 { 165 writel(readl(reg) | set, reg); 166 } 167 168 static inline void pic32_clrbits(void __iomem *reg, u32 clr) 169 { 170 writel(readl(reg) & ~clr, reg); 171 } 172 173 static int pic32_sqi_set_clk_rate(struct pic32_sqi *sqi, u32 sck) 174 { 175 u32 val, div; 176 177 /* div = base_clk / (2 * spi_clk) */ 178 div = clk_get_rate(sqi->base_clk) / (2 * sck); 179 div &= PESQI_CLKDIV; 180 181 val = readl(sqi->regs + PESQI_CLK_CTRL_REG); 182 /* apply new divider */ 183 val &= ~(PESQI_CLK_STABLE | (PESQI_CLKDIV << PESQI_CLKDIV_SHIFT)); 184 val |= div << PESQI_CLKDIV_SHIFT; 185 writel(val, sqi->regs + PESQI_CLK_CTRL_REG); 186 187 /* wait for stability */ 188 return readl_poll_timeout(sqi->regs + PESQI_CLK_CTRL_REG, val, 189 val & PESQI_CLK_STABLE, 1, 5000); 190 } 191 192 static inline void pic32_sqi_enable_int(struct pic32_sqi *sqi) 193 { 194 u32 mask = PESQI_DMAERR | PESQI_BDDONE | PESQI_PKTCOMP; 195 196 writel(mask, sqi->regs + PESQI_INT_ENABLE_REG); 197 /* INT_SIGEN works as interrupt-gate to INTR line */ 198 writel(mask, sqi->regs + PESQI_INT_SIGEN_REG); 199 } 200 201 static inline void pic32_sqi_disable_int(struct pic32_sqi *sqi) 202 { 203 writel(0, sqi->regs + PESQI_INT_ENABLE_REG); 204 writel(0, sqi->regs + PESQI_INT_SIGEN_REG); 205 } 206 207 static irqreturn_t pic32_sqi_isr(int irq, void *dev_id) 208 { 209 struct pic32_sqi *sqi = dev_id; 210 u32 enable, status; 211 212 enable = readl(sqi->regs + PESQI_INT_ENABLE_REG); 213 status = readl(sqi->regs + PESQI_INT_STAT_REG); 214 215 /* check spurious interrupt */ 216 if (!status) 217 return IRQ_NONE; 218 219 if (status & PESQI_DMAERR) { 220 enable = 0; 221 goto irq_done; 222 } 223 224 if (status & PESQI_TXTHR) 225 enable &= ~(PESQI_TXTHR | PESQI_TXFULL | PESQI_TXEMPTY); 226 227 if (status & PESQI_RXTHR) 228 enable &= ~(PESQI_RXTHR | PESQI_RXFULL | PESQI_RXEMPTY); 229 230 if (status & PESQI_BDDONE) 231 enable &= ~PESQI_BDDONE; 232 233 /* packet processing completed */ 234 if (status & PESQI_PKTCOMP) { 235 /* mask all interrupts */ 236 enable = 0; 237 /* complete trasaction */ 238 complete(&sqi->xfer_done); 239 } 240 241 irq_done: 242 /* interrupts are sticky, so mask when handled */ 243 writel(enable, sqi->regs + PESQI_INT_ENABLE_REG); 244 245 return IRQ_HANDLED; 246 } 247 248 static struct ring_desc *ring_desc_get(struct pic32_sqi *sqi) 249 { 250 struct ring_desc *rdesc; 251 252 if (list_empty(&sqi->bd_list_free)) 253 return NULL; 254 255 rdesc = list_first_entry(&sqi->bd_list_free, struct ring_desc, list); 256 list_move_tail(&rdesc->list, &sqi->bd_list_used); 257 return rdesc; 258 } 259 260 static void ring_desc_put(struct pic32_sqi *sqi, struct ring_desc *rdesc) 261 { 262 list_move(&rdesc->list, &sqi->bd_list_free); 263 } 264 265 static int pic32_sqi_one_transfer(struct pic32_sqi *sqi, 266 struct spi_message *mesg, 267 struct spi_transfer *xfer) 268 { 269 struct spi_device *spi = mesg->spi; 270 struct scatterlist *sg, *sgl; 271 struct ring_desc *rdesc; 272 struct buf_desc *bd; 273 int nents, i; 274 u32 bd_ctrl; 275 u32 nbits; 276 277 /* Device selection */ 278 bd_ctrl = spi->chip_select << BD_DEVSEL_SHIFT; 279 280 /* half-duplex: select transfer buffer, direction and lane */ 281 if (xfer->rx_buf) { 282 bd_ctrl |= BD_DATA_RECV; 283 nbits = xfer->rx_nbits; 284 sgl = xfer->rx_sg.sgl; 285 nents = xfer->rx_sg.nents; 286 } else { 287 nbits = xfer->tx_nbits; 288 sgl = xfer->tx_sg.sgl; 289 nents = xfer->tx_sg.nents; 290 } 291 292 if (nbits & SPI_NBITS_QUAD) 293 bd_ctrl |= BD_QUAD; 294 else if (nbits & SPI_NBITS_DUAL) 295 bd_ctrl |= BD_DUAL; 296 297 /* LSB first */ 298 if (spi->mode & SPI_LSB_FIRST) 299 bd_ctrl |= BD_LSBF; 300 301 /* ownership to hardware */ 302 bd_ctrl |= BD_EN; 303 304 for_each_sg(sgl, sg, nents, i) { 305 /* get ring descriptor */ 306 rdesc = ring_desc_get(sqi); 307 if (!rdesc) 308 break; 309 310 bd = rdesc->bd; 311 312 /* BD CTRL: length */ 313 rdesc->xfer_len = sg_dma_len(sg); 314 bd->bd_ctrl = bd_ctrl; 315 bd->bd_ctrl |= rdesc->xfer_len; 316 317 /* BD STAT */ 318 bd->bd_status = 0; 319 320 /* BD BUFFER ADDRESS */ 321 bd->bd_addr = sg->dma_address; 322 } 323 324 return 0; 325 } 326 327 static int pic32_sqi_prepare_hardware(struct spi_master *master) 328 { 329 struct pic32_sqi *sqi = spi_master_get_devdata(master); 330 331 /* enable spi interface */ 332 pic32_setbits(sqi->regs + PESQI_CONF_REG, PESQI_EN); 333 /* enable spi clk */ 334 pic32_setbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN); 335 336 return 0; 337 } 338 339 static bool pic32_sqi_can_dma(struct spi_master *master, 340 struct spi_device *spi, 341 struct spi_transfer *x) 342 { 343 /* Do DMA irrespective of transfer size */ 344 return true; 345 } 346 347 static int pic32_sqi_one_message(struct spi_master *master, 348 struct spi_message *msg) 349 { 350 struct spi_device *spi = msg->spi; 351 struct ring_desc *rdesc, *next; 352 struct spi_transfer *xfer; 353 struct pic32_sqi *sqi; 354 int ret = 0, mode; 355 unsigned long timeout; 356 u32 val; 357 358 sqi = spi_master_get_devdata(master); 359 360 reinit_completion(&sqi->xfer_done); 361 msg->actual_length = 0; 362 363 /* We can't handle spi_transfer specific "speed_hz", "bits_per_word" 364 * and "delay_usecs". But spi_device specific speed and mode change 365 * can be handled at best during spi chip-select switch. 366 */ 367 if (sqi->cur_spi != spi) { 368 /* set spi speed */ 369 if (sqi->cur_speed != spi->max_speed_hz) { 370 sqi->cur_speed = spi->max_speed_hz; 371 ret = pic32_sqi_set_clk_rate(sqi, spi->max_speed_hz); 372 if (ret) 373 dev_warn(&spi->dev, "set_clk, %d\n", ret); 374 } 375 376 /* set spi mode */ 377 mode = spi->mode & (SPI_MODE_3 | SPI_LSB_FIRST); 378 if (sqi->cur_mode != mode) { 379 val = readl(sqi->regs + PESQI_CONF_REG); 380 val &= ~(PESQI_CPOL | PESQI_CPHA | PESQI_LSBF); 381 if (mode & SPI_CPOL) 382 val |= PESQI_CPOL; 383 if (mode & SPI_LSB_FIRST) 384 val |= PESQI_LSBF; 385 val |= PESQI_CPHA; 386 writel(val, sqi->regs + PESQI_CONF_REG); 387 388 sqi->cur_mode = mode; 389 } 390 sqi->cur_spi = spi; 391 } 392 393 /* prepare hardware desc-list(BD) for transfer(s) */ 394 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 395 ret = pic32_sqi_one_transfer(sqi, msg, xfer); 396 if (ret) { 397 dev_err(&spi->dev, "xfer %p err\n", xfer); 398 goto xfer_out; 399 } 400 } 401 402 /* BDs are prepared and chained. Now mark LAST_BD, CS_DEASSERT at last 403 * element of the list. 404 */ 405 rdesc = list_last_entry(&sqi->bd_list_used, struct ring_desc, list); 406 rdesc->bd->bd_ctrl |= BD_LAST | BD_CS_DEASSERT | 407 BD_LIFM | BD_PKT_INT_EN; 408 409 /* set base address BD list for DMA engine */ 410 rdesc = list_first_entry(&sqi->bd_list_used, struct ring_desc, list); 411 writel(rdesc->bd_dma, sqi->regs + PESQI_BD_BASE_ADDR_REG); 412 413 /* enable interrupt */ 414 pic32_sqi_enable_int(sqi); 415 416 /* enable DMA engine */ 417 val = PESQI_DMA_EN | PESQI_POLL_EN | PESQI_BDP_START; 418 writel(val, sqi->regs + PESQI_BD_CTRL_REG); 419 420 /* wait for xfer completion */ 421 timeout = wait_for_completion_timeout(&sqi->xfer_done, 5 * HZ); 422 if (timeout == 0) { 423 dev_err(&sqi->master->dev, "wait timedout/interrupted\n"); 424 ret = -ETIMEDOUT; 425 msg->status = ret; 426 } else { 427 /* success */ 428 msg->status = 0; 429 ret = 0; 430 } 431 432 /* disable DMA */ 433 writel(0, sqi->regs + PESQI_BD_CTRL_REG); 434 435 pic32_sqi_disable_int(sqi); 436 437 xfer_out: 438 list_for_each_entry_safe_reverse(rdesc, next, 439 &sqi->bd_list_used, list) { 440 /* Update total byte transferred */ 441 msg->actual_length += rdesc->xfer_len; 442 /* release ring descr */ 443 ring_desc_put(sqi, rdesc); 444 } 445 spi_finalize_current_message(spi->master); 446 447 return ret; 448 } 449 450 static int pic32_sqi_unprepare_hardware(struct spi_master *master) 451 { 452 struct pic32_sqi *sqi = spi_master_get_devdata(master); 453 454 /* disable clk */ 455 pic32_clrbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN); 456 /* disable spi */ 457 pic32_clrbits(sqi->regs + PESQI_CONF_REG, PESQI_EN); 458 459 return 0; 460 } 461 462 static int ring_desc_ring_alloc(struct pic32_sqi *sqi) 463 { 464 struct ring_desc *rdesc; 465 struct buf_desc *bd; 466 int i; 467 468 /* allocate coherent DMAable memory for hardware buffer descriptors. */ 469 sqi->bd = dma_zalloc_coherent(&sqi->master->dev, 470 sizeof(*bd) * PESQI_BD_COUNT, 471 &sqi->bd_dma, GFP_DMA32); 472 if (!sqi->bd) { 473 dev_err(&sqi->master->dev, "failed allocating dma buffer\n"); 474 return -ENOMEM; 475 } 476 477 /* allocate software ring descriptors */ 478 sqi->ring = kcalloc(PESQI_BD_COUNT, sizeof(*rdesc), GFP_KERNEL); 479 if (!sqi->ring) { 480 dma_free_coherent(&sqi->master->dev, 481 sizeof(*bd) * PESQI_BD_COUNT, 482 sqi->bd, sqi->bd_dma); 483 return -ENOMEM; 484 } 485 486 bd = (struct buf_desc *)sqi->bd; 487 488 INIT_LIST_HEAD(&sqi->bd_list_free); 489 INIT_LIST_HEAD(&sqi->bd_list_used); 490 491 /* initialize ring-desc */ 492 for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT; i++, rdesc++) { 493 INIT_LIST_HEAD(&rdesc->list); 494 rdesc->bd = &bd[i]; 495 rdesc->bd_dma = sqi->bd_dma + (void *)&bd[i] - (void *)bd; 496 list_add_tail(&rdesc->list, &sqi->bd_list_free); 497 } 498 499 /* Prepare BD: chain to next BD(s) */ 500 for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT - 1; i++) 501 bd[i].bd_nextp = rdesc[i + 1].bd_dma; 502 bd[PESQI_BD_COUNT - 1].bd_nextp = 0; 503 504 return 0; 505 } 506 507 static void ring_desc_ring_free(struct pic32_sqi *sqi) 508 { 509 dma_free_coherent(&sqi->master->dev, 510 sizeof(struct buf_desc) * PESQI_BD_COUNT, 511 sqi->bd, sqi->bd_dma); 512 kfree(sqi->ring); 513 } 514 515 static void pic32_sqi_hw_init(struct pic32_sqi *sqi) 516 { 517 unsigned long flags; 518 u32 val; 519 520 /* Soft-reset of PESQI controller triggers interrupt. 521 * We are not yet ready to handle them so disable CPU 522 * interrupt for the time being. 523 */ 524 local_irq_save(flags); 525 526 /* assert soft-reset */ 527 writel(PESQI_SOFT_RESET, sqi->regs + PESQI_CONF_REG); 528 529 /* wait until clear */ 530 readl_poll_timeout_atomic(sqi->regs + PESQI_CONF_REG, val, 531 !(val & PESQI_SOFT_RESET), 1, 5000); 532 533 /* disable all interrupts */ 534 pic32_sqi_disable_int(sqi); 535 536 /* Now it is safe to enable back CPU interrupt */ 537 local_irq_restore(flags); 538 539 /* tx and rx fifo interrupt threshold */ 540 val = readl(sqi->regs + PESQI_CMD_THRES_REG); 541 val &= ~(PESQI_TXTHR_MASK << PESQI_TXTHR_SHIFT); 542 val &= ~(PESQI_RXTHR_MASK << PESQI_RXTHR_SHIFT); 543 val |= (1U << PESQI_TXTHR_SHIFT) | (1U << PESQI_RXTHR_SHIFT); 544 writel(val, sqi->regs + PESQI_CMD_THRES_REG); 545 546 val = readl(sqi->regs + PESQI_INT_THRES_REG); 547 val &= ~(PESQI_TXTHR_MASK << PESQI_TXTHR_SHIFT); 548 val &= ~(PESQI_RXTHR_MASK << PESQI_RXTHR_SHIFT); 549 val |= (1U << PESQI_TXTHR_SHIFT) | (1U << PESQI_RXTHR_SHIFT); 550 writel(val, sqi->regs + PESQI_INT_THRES_REG); 551 552 /* default configuration */ 553 val = readl(sqi->regs + PESQI_CONF_REG); 554 555 /* set mode: DMA */ 556 val &= ~PESQI_MODE; 557 val |= PESQI_MODE_DMA << PESQI_MODE_SHIFT; 558 writel(val, sqi->regs + PESQI_CONF_REG); 559 560 /* DATAEN - SQIID0-ID3 */ 561 val |= PESQI_QUAD_LANE << PESQI_LANES_SHIFT; 562 563 /* burst/INCR4 enable */ 564 val |= PESQI_BURST_EN; 565 566 /* CSEN - all CS */ 567 val |= 3U << PESQI_CSEN_SHIFT; 568 writel(val, sqi->regs + PESQI_CONF_REG); 569 570 /* write poll count */ 571 writel(0, sqi->regs + PESQI_BD_POLL_CTRL_REG); 572 573 sqi->cur_speed = 0; 574 sqi->cur_mode = -1; 575 } 576 577 static int pic32_sqi_probe(struct platform_device *pdev) 578 { 579 struct spi_master *master; 580 struct pic32_sqi *sqi; 581 struct resource *reg; 582 int ret; 583 584 master = spi_alloc_master(&pdev->dev, sizeof(*sqi)); 585 if (!master) 586 return -ENOMEM; 587 588 sqi = spi_master_get_devdata(master); 589 sqi->master = master; 590 591 reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 592 sqi->regs = devm_ioremap_resource(&pdev->dev, reg); 593 if (IS_ERR(sqi->regs)) { 594 ret = PTR_ERR(sqi->regs); 595 goto err_free_master; 596 } 597 598 /* irq */ 599 sqi->irq = platform_get_irq(pdev, 0); 600 if (sqi->irq < 0) { 601 dev_err(&pdev->dev, "no irq found\n"); 602 ret = sqi->irq; 603 goto err_free_master; 604 } 605 606 /* clocks */ 607 sqi->sys_clk = devm_clk_get(&pdev->dev, "reg_ck"); 608 if (IS_ERR(sqi->sys_clk)) { 609 ret = PTR_ERR(sqi->sys_clk); 610 dev_err(&pdev->dev, "no sys_clk ?\n"); 611 goto err_free_master; 612 } 613 614 sqi->base_clk = devm_clk_get(&pdev->dev, "spi_ck"); 615 if (IS_ERR(sqi->base_clk)) { 616 ret = PTR_ERR(sqi->base_clk); 617 dev_err(&pdev->dev, "no base clk ?\n"); 618 goto err_free_master; 619 } 620 621 ret = clk_prepare_enable(sqi->sys_clk); 622 if (ret) { 623 dev_err(&pdev->dev, "sys clk enable failed\n"); 624 goto err_free_master; 625 } 626 627 ret = clk_prepare_enable(sqi->base_clk); 628 if (ret) { 629 dev_err(&pdev->dev, "base clk enable failed\n"); 630 clk_disable_unprepare(sqi->sys_clk); 631 goto err_free_master; 632 } 633 634 init_completion(&sqi->xfer_done); 635 636 /* initialize hardware */ 637 pic32_sqi_hw_init(sqi); 638 639 /* allocate buffers & descriptors */ 640 ret = ring_desc_ring_alloc(sqi); 641 if (ret) { 642 dev_err(&pdev->dev, "ring alloc failed\n"); 643 goto err_disable_clk; 644 } 645 646 /* install irq handlers */ 647 ret = request_irq(sqi->irq, pic32_sqi_isr, 0, 648 dev_name(&pdev->dev), sqi); 649 if (ret < 0) { 650 dev_err(&pdev->dev, "request_irq(%d), failed\n", sqi->irq); 651 goto err_free_ring; 652 } 653 654 /* register master */ 655 master->num_chipselect = 2; 656 master->max_speed_hz = clk_get_rate(sqi->base_clk); 657 master->dma_alignment = 32; 658 master->max_dma_len = PESQI_BD_BUF_LEN_MAX; 659 master->dev.of_node = of_node_get(pdev->dev.of_node); 660 master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_TX_DUAL | 661 SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD; 662 master->flags = SPI_MASTER_HALF_DUPLEX; 663 master->can_dma = pic32_sqi_can_dma; 664 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 665 master->transfer_one_message = pic32_sqi_one_message; 666 master->prepare_transfer_hardware = pic32_sqi_prepare_hardware; 667 master->unprepare_transfer_hardware = pic32_sqi_unprepare_hardware; 668 669 ret = devm_spi_register_master(&pdev->dev, master); 670 if (ret) { 671 dev_err(&master->dev, "failed registering spi master\n"); 672 free_irq(sqi->irq, sqi); 673 goto err_free_ring; 674 } 675 676 platform_set_drvdata(pdev, sqi); 677 678 return 0; 679 680 err_free_ring: 681 ring_desc_ring_free(sqi); 682 683 err_disable_clk: 684 clk_disable_unprepare(sqi->base_clk); 685 clk_disable_unprepare(sqi->sys_clk); 686 687 err_free_master: 688 spi_master_put(master); 689 return ret; 690 } 691 692 static int pic32_sqi_remove(struct platform_device *pdev) 693 { 694 struct pic32_sqi *sqi = platform_get_drvdata(pdev); 695 696 /* release resources */ 697 free_irq(sqi->irq, sqi); 698 ring_desc_ring_free(sqi); 699 700 /* disable clk */ 701 clk_disable_unprepare(sqi->base_clk); 702 clk_disable_unprepare(sqi->sys_clk); 703 704 return 0; 705 } 706 707 static const struct of_device_id pic32_sqi_of_ids[] = { 708 {.compatible = "microchip,pic32mzda-sqi",}, 709 {}, 710 }; 711 MODULE_DEVICE_TABLE(of, pic32_sqi_of_ids); 712 713 static struct platform_driver pic32_sqi_driver = { 714 .driver = { 715 .name = "sqi-pic32", 716 .of_match_table = of_match_ptr(pic32_sqi_of_ids), 717 }, 718 .probe = pic32_sqi_probe, 719 .remove = pic32_sqi_remove, 720 }; 721 722 module_platform_driver(pic32_sqi_driver); 723 724 MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>"); 725 MODULE_DESCRIPTION("Microchip SPI driver for PIC32 SQI controller."); 726 MODULE_LICENSE("GPL v2"); 727