xref: /openbmc/linux/drivers/spi/spi-orion.c (revision f97769fd)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Marvell Orion SPI controller driver
4  *
5  * Author: Shadi Ammouri <shadi@marvell.com>
6  * Copyright (C) 2007-2008 Marvell Ltd.
7  */
8 
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/platform_device.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/spi/spi.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/clk.h>
21 #include <linux/sizes.h>
22 #include <asm/unaligned.h>
23 
24 #define DRIVER_NAME			"orion_spi"
25 
26 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
27 #define SPI_AUTOSUSPEND_TIMEOUT		200
28 
29 /* Some SoCs using this driver support up to 8 chip selects.
30  * It is up to the implementer to only use the chip selects
31  * that are available.
32  */
33 #define ORION_NUM_CHIPSELECTS		8
34 
35 #define ORION_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */
36 
37 #define ORION_SPI_IF_CTRL_REG		0x00
38 #define ORION_SPI_IF_CONFIG_REG		0x04
39 #define ORION_SPI_IF_RXLSBF		BIT(14)
40 #define ORION_SPI_IF_TXLSBF		BIT(13)
41 #define ORION_SPI_DATA_OUT_REG		0x08
42 #define ORION_SPI_DATA_IN_REG		0x0c
43 #define ORION_SPI_INT_CAUSE_REG		0x10
44 #define ORION_SPI_TIMING_PARAMS_REG	0x18
45 
46 /* Register for the "Direct Mode" */
47 #define SPI_DIRECT_WRITE_CONFIG_REG	0x20
48 
49 #define ORION_SPI_TMISO_SAMPLE_MASK	(0x3 << 6)
50 #define ORION_SPI_TMISO_SAMPLE_1	(1 << 6)
51 #define ORION_SPI_TMISO_SAMPLE_2	(2 << 6)
52 
53 #define ORION_SPI_MODE_CPOL		(1 << 11)
54 #define ORION_SPI_MODE_CPHA		(1 << 12)
55 #define ORION_SPI_IF_8_16_BIT_MODE	(1 << 5)
56 #define ORION_SPI_CLK_PRESCALE_MASK	0x1F
57 #define ARMADA_SPI_CLK_PRESCALE_MASK	0xDF
58 #define ORION_SPI_MODE_MASK		(ORION_SPI_MODE_CPOL | \
59 					 ORION_SPI_MODE_CPHA)
60 #define ORION_SPI_CS_MASK	0x1C
61 #define ORION_SPI_CS_SHIFT	2
62 #define ORION_SPI_CS(cs)	((cs << ORION_SPI_CS_SHIFT) & \
63 					ORION_SPI_CS_MASK)
64 
65 enum orion_spi_type {
66 	ORION_SPI,
67 	ARMADA_SPI,
68 };
69 
70 struct orion_spi_dev {
71 	enum orion_spi_type	typ;
72 	/*
73 	 * min_divisor and max_hz should be exclusive, the only we can
74 	 * have both is for managing the armada-370-spi case with old
75 	 * device tree
76 	 */
77 	unsigned long		max_hz;
78 	unsigned int		min_divisor;
79 	unsigned int		max_divisor;
80 	u32			prescale_mask;
81 	bool			is_errata_50mhz_ac;
82 };
83 
84 struct orion_direct_acc {
85 	void __iomem		*vaddr;
86 	u32			size;
87 };
88 
89 struct orion_child_options {
90 	struct orion_direct_acc direct_access;
91 };
92 
93 struct orion_spi {
94 	struct spi_master	*master;
95 	void __iomem		*base;
96 	struct clk              *clk;
97 	struct clk              *axi_clk;
98 	const struct orion_spi_dev *devdata;
99 
100 	struct orion_child_options	child[ORION_NUM_CHIPSELECTS];
101 };
102 
103 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
104 {
105 	return orion_spi->base + reg;
106 }
107 
108 static inline void
109 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
110 {
111 	void __iomem *reg_addr = spi_reg(orion_spi, reg);
112 	u32 val;
113 
114 	val = readl(reg_addr);
115 	val |= mask;
116 	writel(val, reg_addr);
117 }
118 
119 static inline void
120 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
121 {
122 	void __iomem *reg_addr = spi_reg(orion_spi, reg);
123 	u32 val;
124 
125 	val = readl(reg_addr);
126 	val &= ~mask;
127 	writel(val, reg_addr);
128 }
129 
130 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
131 {
132 	u32 tclk_hz;
133 	u32 rate;
134 	u32 prescale;
135 	u32 reg;
136 	struct orion_spi *orion_spi;
137 	const struct orion_spi_dev *devdata;
138 
139 	orion_spi = spi_master_get_devdata(spi->master);
140 	devdata = orion_spi->devdata;
141 
142 	tclk_hz = clk_get_rate(orion_spi->clk);
143 
144 	if (devdata->typ == ARMADA_SPI) {
145 		/*
146 		 * Given the core_clk (tclk_hz) and the target rate (speed) we
147 		 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
148 		 * [0..7]) such that
149 		 *
150 		 * 	core_clk / (SPR * 2 ** SPPR)
151 		 *
152 		 * is as big as possible but not bigger than speed.
153 		 */
154 
155 		/* best integer divider: */
156 		unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
157 		unsigned spr, sppr;
158 
159 		if (divider < 16) {
160 			/* This is the easy case, divider is less than 16 */
161 			spr = divider;
162 			sppr = 0;
163 
164 		} else {
165 			unsigned two_pow_sppr;
166 			/*
167 			 * Find the highest bit set in divider. This and the
168 			 * three next bits define SPR (apart from rounding).
169 			 * SPPR is then the number of zero bits that must be
170 			 * appended:
171 			 */
172 			sppr = fls(divider) - 4;
173 
174 			/*
175 			 * As SPR only has 4 bits, we have to round divider up
176 			 * to the next multiple of 2 ** sppr.
177 			 */
178 			two_pow_sppr = 1 << sppr;
179 			divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
180 
181 			/*
182 			 * recalculate sppr as rounding up divider might have
183 			 * increased it enough to change the position of the
184 			 * highest set bit. In this case the bit that now
185 			 * doesn't make it into SPR is 0, so there is no need to
186 			 * round again.
187 			 */
188 			sppr = fls(divider) - 4;
189 			spr = divider >> sppr;
190 
191 			/*
192 			 * Now do range checking. SPR is constructed to have a
193 			 * width of 4 bits, so this is fine for sure. So we
194 			 * still need to check for sppr to fit into 3 bits:
195 			 */
196 			if (sppr > 7)
197 				return -EINVAL;
198 		}
199 
200 		prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
201 	} else {
202 		/*
203 		 * the supported rates are: 4,6,8...30
204 		 * round up as we look for equal or less speed
205 		 */
206 		rate = DIV_ROUND_UP(tclk_hz, speed);
207 		rate = roundup(rate, 2);
208 
209 		/* check if requested speed is too small */
210 		if (rate > 30)
211 			return -EINVAL;
212 
213 		if (rate < 4)
214 			rate = 4;
215 
216 		/* Convert the rate to SPI clock divisor value.	*/
217 		prescale = 0x10 + rate/2;
218 	}
219 
220 	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
221 	reg = ((reg & ~devdata->prescale_mask) | prescale);
222 	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
223 
224 	return 0;
225 }
226 
227 static void
228 orion_spi_mode_set(struct spi_device *spi)
229 {
230 	u32 reg;
231 	struct orion_spi *orion_spi;
232 
233 	orion_spi = spi_master_get_devdata(spi->master);
234 
235 	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
236 	reg &= ~ORION_SPI_MODE_MASK;
237 	if (spi->mode & SPI_CPOL)
238 		reg |= ORION_SPI_MODE_CPOL;
239 	if (spi->mode & SPI_CPHA)
240 		reg |= ORION_SPI_MODE_CPHA;
241 	if (spi->mode & SPI_LSB_FIRST)
242 		reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
243 	else
244 		reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
245 
246 	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
247 }
248 
249 static void
250 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
251 {
252 	u32 reg;
253 	struct orion_spi *orion_spi;
254 
255 	orion_spi = spi_master_get_devdata(spi->master);
256 
257 	/*
258 	 * Erratum description: (Erratum NO. FE-9144572) The device
259 	 * SPI interface supports frequencies of up to 50 MHz.
260 	 * However, due to this erratum, when the device core clock is
261 	 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
262 	 * clock and CPOL=CPHA=1 there might occur data corruption on
263 	 * reads from the SPI device.
264 	 * Erratum Workaround:
265 	 * Work in one of the following configurations:
266 	 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
267 	 * Register".
268 	 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
269 	 * Register" before setting the interface.
270 	 */
271 	reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
272 	reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
273 
274 	if (clk_get_rate(orion_spi->clk) == 250000000 &&
275 			speed == 50000000 && spi->mode & SPI_CPOL &&
276 			spi->mode & SPI_CPHA)
277 		reg |= ORION_SPI_TMISO_SAMPLE_2;
278 	else
279 		reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
280 
281 	writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
282 }
283 
284 /*
285  * called only when no transfer is active on the bus
286  */
287 static int
288 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
289 {
290 	struct orion_spi *orion_spi;
291 	unsigned int speed = spi->max_speed_hz;
292 	unsigned int bits_per_word = spi->bits_per_word;
293 	int	rc;
294 
295 	orion_spi = spi_master_get_devdata(spi->master);
296 
297 	if ((t != NULL) && t->speed_hz)
298 		speed = t->speed_hz;
299 
300 	if ((t != NULL) && t->bits_per_word)
301 		bits_per_word = t->bits_per_word;
302 
303 	orion_spi_mode_set(spi);
304 
305 	if (orion_spi->devdata->is_errata_50mhz_ac)
306 		orion_spi_50mhz_ac_timing_erratum(spi, speed);
307 
308 	rc = orion_spi_baudrate_set(spi, speed);
309 	if (rc)
310 		return rc;
311 
312 	if (bits_per_word == 16)
313 		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
314 				  ORION_SPI_IF_8_16_BIT_MODE);
315 	else
316 		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
317 				  ORION_SPI_IF_8_16_BIT_MODE);
318 
319 	return 0;
320 }
321 
322 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
323 {
324 	struct orion_spi *orion_spi;
325 
326 	orion_spi = spi_master_get_devdata(spi->master);
327 
328 	/*
329 	 * If this line is using a GPIO to control chip select, this internal
330 	 * .set_cs() function will still be called, so we clear any previous
331 	 * chip select. The CS we activate will not have any elecrical effect,
332 	 * as it is handled by a GPIO, but that doesn't matter. What we need
333 	 * is to deassert the old chip select and assert some other chip select.
334 	 */
335 	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
336 	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
337 			  ORION_SPI_CS(spi->chip_select));
338 
339 	/*
340 	 * Chip select logic is inverted from spi_set_cs(). For lines using a
341 	 * GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens
342 	 * in the GPIO library, but we don't care about that, because in those
343 	 * cases we are dealing with an unused native CS anyways so the polarity
344 	 * doesn't matter.
345 	 */
346 	if (!enable)
347 		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
348 	else
349 		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
350 }
351 
352 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
353 {
354 	int i;
355 
356 	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
357 		if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
358 			return 1;
359 
360 		udelay(1);
361 	}
362 
363 	return -1;
364 }
365 
366 static inline int
367 orion_spi_write_read_8bit(struct spi_device *spi,
368 			  const u8 **tx_buf, u8 **rx_buf)
369 {
370 	void __iomem *tx_reg, *rx_reg, *int_reg;
371 	struct orion_spi *orion_spi;
372 
373 	orion_spi = spi_master_get_devdata(spi->master);
374 	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
375 	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
376 	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
377 
378 	/* clear the interrupt cause register */
379 	writel(0x0, int_reg);
380 
381 	if (tx_buf && *tx_buf)
382 		writel(*(*tx_buf)++, tx_reg);
383 	else
384 		writel(0, tx_reg);
385 
386 	if (orion_spi_wait_till_ready(orion_spi) < 0) {
387 		dev_err(&spi->dev, "TXS timed out\n");
388 		return -1;
389 	}
390 
391 	if (rx_buf && *rx_buf)
392 		*(*rx_buf)++ = readl(rx_reg);
393 
394 	return 1;
395 }
396 
397 static inline int
398 orion_spi_write_read_16bit(struct spi_device *spi,
399 			   const u16 **tx_buf, u16 **rx_buf)
400 {
401 	void __iomem *tx_reg, *rx_reg, *int_reg;
402 	struct orion_spi *orion_spi;
403 
404 	orion_spi = spi_master_get_devdata(spi->master);
405 	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
406 	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
407 	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
408 
409 	/* clear the interrupt cause register */
410 	writel(0x0, int_reg);
411 
412 	if (tx_buf && *tx_buf)
413 		writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
414 	else
415 		writel(0, tx_reg);
416 
417 	if (orion_spi_wait_till_ready(orion_spi) < 0) {
418 		dev_err(&spi->dev, "TXS timed out\n");
419 		return -1;
420 	}
421 
422 	if (rx_buf && *rx_buf)
423 		put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
424 
425 	return 1;
426 }
427 
428 static unsigned int
429 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
430 {
431 	unsigned int count;
432 	int word_len;
433 	struct orion_spi *orion_spi;
434 	int cs = spi->chip_select;
435 	void __iomem *vaddr;
436 
437 	word_len = spi->bits_per_word;
438 	count = xfer->len;
439 
440 	orion_spi = spi_master_get_devdata(spi->master);
441 
442 	/*
443 	 * Use SPI direct write mode if base address is available. Otherwise
444 	 * fall back to PIO mode for this transfer.
445 	 */
446 	vaddr = orion_spi->child[cs].direct_access.vaddr;
447 
448 	if (vaddr && xfer->tx_buf && word_len == 8) {
449 		unsigned int cnt = count / 4;
450 		unsigned int rem = count % 4;
451 
452 		/*
453 		 * Send the TX-data to the SPI device via the direct
454 		 * mapped address window
455 		 */
456 		iowrite32_rep(vaddr, xfer->tx_buf, cnt);
457 		if (rem) {
458 			u32 *buf = (u32 *)xfer->tx_buf;
459 
460 			iowrite8_rep(vaddr, &buf[cnt], rem);
461 		}
462 
463 		return count;
464 	}
465 
466 	if (word_len == 8) {
467 		const u8 *tx = xfer->tx_buf;
468 		u8 *rx = xfer->rx_buf;
469 
470 		do {
471 			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
472 				goto out;
473 			count--;
474 			spi_delay_exec(&xfer->word_delay, xfer);
475 		} while (count);
476 	} else if (word_len == 16) {
477 		const u16 *tx = xfer->tx_buf;
478 		u16 *rx = xfer->rx_buf;
479 
480 		do {
481 			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
482 				goto out;
483 			count -= 2;
484 			spi_delay_exec(&xfer->word_delay, xfer);
485 		} while (count);
486 	}
487 
488 out:
489 	return xfer->len - count;
490 }
491 
492 static int orion_spi_transfer_one(struct spi_master *master,
493 					struct spi_device *spi,
494 					struct spi_transfer *t)
495 {
496 	int status = 0;
497 
498 	status = orion_spi_setup_transfer(spi, t);
499 	if (status < 0)
500 		return status;
501 
502 	if (t->len)
503 		orion_spi_write_read(spi, t);
504 
505 	return status;
506 }
507 
508 static int orion_spi_setup(struct spi_device *spi)
509 {
510 	return orion_spi_setup_transfer(spi, NULL);
511 }
512 
513 static int orion_spi_reset(struct orion_spi *orion_spi)
514 {
515 	/* Verify that the CS is deasserted */
516 	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
517 
518 	/* Don't deassert CS between the direct mapped SPI transfers */
519 	writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
520 
521 	return 0;
522 }
523 
524 static const struct orion_spi_dev orion_spi_dev_data = {
525 	.typ = ORION_SPI,
526 	.min_divisor = 4,
527 	.max_divisor = 30,
528 	.prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
529 };
530 
531 static const struct orion_spi_dev armada_370_spi_dev_data = {
532 	.typ = ARMADA_SPI,
533 	.min_divisor = 4,
534 	.max_divisor = 1920,
535 	.max_hz = 50000000,
536 	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
537 };
538 
539 static const struct orion_spi_dev armada_xp_spi_dev_data = {
540 	.typ = ARMADA_SPI,
541 	.max_hz = 50000000,
542 	.max_divisor = 1920,
543 	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
544 };
545 
546 static const struct orion_spi_dev armada_375_spi_dev_data = {
547 	.typ = ARMADA_SPI,
548 	.min_divisor = 15,
549 	.max_divisor = 1920,
550 	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
551 };
552 
553 static const struct orion_spi_dev armada_380_spi_dev_data = {
554 	.typ = ARMADA_SPI,
555 	.max_hz = 50000000,
556 	.max_divisor = 1920,
557 	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
558 	.is_errata_50mhz_ac = true,
559 };
560 
561 static const struct of_device_id orion_spi_of_match_table[] = {
562 	{
563 		.compatible = "marvell,orion-spi",
564 		.data = &orion_spi_dev_data,
565 	},
566 	{
567 		.compatible = "marvell,armada-370-spi",
568 		.data = &armada_370_spi_dev_data,
569 	},
570 	{
571 		.compatible = "marvell,armada-375-spi",
572 		.data = &armada_375_spi_dev_data,
573 	},
574 	{
575 		.compatible = "marvell,armada-380-spi",
576 		.data = &armada_380_spi_dev_data,
577 	},
578 	{
579 		.compatible = "marvell,armada-390-spi",
580 		.data = &armada_xp_spi_dev_data,
581 	},
582 	{
583 		.compatible = "marvell,armada-xp-spi",
584 		.data = &armada_xp_spi_dev_data,
585 	},
586 
587 	{}
588 };
589 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
590 
591 static int orion_spi_probe(struct platform_device *pdev)
592 {
593 	const struct of_device_id *of_id;
594 	const struct orion_spi_dev *devdata;
595 	struct spi_master *master;
596 	struct orion_spi *spi;
597 	struct resource *r;
598 	unsigned long tclk_hz;
599 	int status = 0;
600 	struct device_node *np;
601 
602 	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
603 	if (master == NULL) {
604 		dev_dbg(&pdev->dev, "master allocation failed\n");
605 		return -ENOMEM;
606 	}
607 
608 	if (pdev->id != -1)
609 		master->bus_num = pdev->id;
610 	if (pdev->dev.of_node) {
611 		u32 cell_index;
612 
613 		if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
614 					  &cell_index))
615 			master->bus_num = cell_index;
616 	}
617 
618 	/* we support all 4 SPI modes and LSB first option */
619 	master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
620 	master->set_cs = orion_spi_set_cs;
621 	master->transfer_one = orion_spi_transfer_one;
622 	master->num_chipselect = ORION_NUM_CHIPSELECTS;
623 	master->setup = orion_spi_setup;
624 	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
625 	master->auto_runtime_pm = true;
626 	master->use_gpio_descriptors = true;
627 	master->flags = SPI_MASTER_GPIO_SS;
628 
629 	platform_set_drvdata(pdev, master);
630 
631 	spi = spi_master_get_devdata(master);
632 	spi->master = master;
633 
634 	of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
635 	devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
636 	spi->devdata = devdata;
637 
638 	spi->clk = devm_clk_get(&pdev->dev, NULL);
639 	if (IS_ERR(spi->clk)) {
640 		status = PTR_ERR(spi->clk);
641 		goto out;
642 	}
643 
644 	status = clk_prepare_enable(spi->clk);
645 	if (status)
646 		goto out;
647 
648 	/* The following clock is only used by some SoCs */
649 	spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
650 	if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
651 		status = -EPROBE_DEFER;
652 		goto out_rel_clk;
653 	}
654 	if (!IS_ERR(spi->axi_clk))
655 		clk_prepare_enable(spi->axi_clk);
656 
657 	tclk_hz = clk_get_rate(spi->clk);
658 
659 	/*
660 	 * With old device tree, armada-370-spi could be used with
661 	 * Armada XP, however for this SoC the maximum frequency is
662 	 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
663 	 * higher than 200MHz. So, in order to be able to handle both
664 	 * SoCs, we can take the minimum of 50MHz and tclk/4.
665 	 */
666 	if (of_device_is_compatible(pdev->dev.of_node,
667 					"marvell,armada-370-spi"))
668 		master->max_speed_hz = min(devdata->max_hz,
669 				DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
670 	else if (devdata->min_divisor)
671 		master->max_speed_hz =
672 			DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
673 	else
674 		master->max_speed_hz = devdata->max_hz;
675 	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
676 
677 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
678 	spi->base = devm_ioremap_resource(&pdev->dev, r);
679 	if (IS_ERR(spi->base)) {
680 		status = PTR_ERR(spi->base);
681 		goto out_rel_axi_clk;
682 	}
683 
684 	for_each_available_child_of_node(pdev->dev.of_node, np) {
685 		struct orion_direct_acc *dir_acc;
686 		u32 cs;
687 
688 		/* Get chip-select number from the "reg" property */
689 		status = of_property_read_u32(np, "reg", &cs);
690 		if (status) {
691 			dev_err(&pdev->dev,
692 				"%pOF has no valid 'reg' property (%d)\n",
693 				np, status);
694 			continue;
695 		}
696 
697 		/*
698 		 * Check if an address is configured for this SPI device. If
699 		 * not, the MBus mapping via the 'ranges' property in the 'soc'
700 		 * node is not configured and this device should not use the
701 		 * direct mode. In this case, just continue with the next
702 		 * device.
703 		 */
704 		status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
705 		if (status)
706 			continue;
707 
708 		/*
709 		 * Only map one page for direct access. This is enough for the
710 		 * simple TX transfer which only writes to the first word.
711 		 * This needs to get extended for the direct SPI NOR / SPI NAND
712 		 * support, once this gets implemented.
713 		 */
714 		dir_acc = &spi->child[cs].direct_access;
715 		dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
716 		if (!dir_acc->vaddr) {
717 			status = -ENOMEM;
718 			goto out_rel_axi_clk;
719 		}
720 		dir_acc->size = PAGE_SIZE;
721 
722 		dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
723 	}
724 
725 	pm_runtime_set_active(&pdev->dev);
726 	pm_runtime_use_autosuspend(&pdev->dev);
727 	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
728 	pm_runtime_enable(&pdev->dev);
729 
730 	status = orion_spi_reset(spi);
731 	if (status < 0)
732 		goto out_rel_pm;
733 
734 	master->dev.of_node = pdev->dev.of_node;
735 	status = spi_register_master(master);
736 	if (status < 0)
737 		goto out_rel_pm;
738 
739 	return status;
740 
741 out_rel_pm:
742 	pm_runtime_disable(&pdev->dev);
743 out_rel_axi_clk:
744 	clk_disable_unprepare(spi->axi_clk);
745 out_rel_clk:
746 	clk_disable_unprepare(spi->clk);
747 out:
748 	spi_master_put(master);
749 	return status;
750 }
751 
752 
753 static int orion_spi_remove(struct platform_device *pdev)
754 {
755 	struct spi_master *master = platform_get_drvdata(pdev);
756 	struct orion_spi *spi = spi_master_get_devdata(master);
757 
758 	pm_runtime_get_sync(&pdev->dev);
759 	clk_disable_unprepare(spi->axi_clk);
760 	clk_disable_unprepare(spi->clk);
761 
762 	spi_unregister_master(master);
763 	pm_runtime_disable(&pdev->dev);
764 
765 	return 0;
766 }
767 
768 MODULE_ALIAS("platform:" DRIVER_NAME);
769 
770 #ifdef CONFIG_PM
771 static int orion_spi_runtime_suspend(struct device *dev)
772 {
773 	struct spi_master *master = dev_get_drvdata(dev);
774 	struct orion_spi *spi = spi_master_get_devdata(master);
775 
776 	clk_disable_unprepare(spi->axi_clk);
777 	clk_disable_unprepare(spi->clk);
778 	return 0;
779 }
780 
781 static int orion_spi_runtime_resume(struct device *dev)
782 {
783 	struct spi_master *master = dev_get_drvdata(dev);
784 	struct orion_spi *spi = spi_master_get_devdata(master);
785 
786 	if (!IS_ERR(spi->axi_clk))
787 		clk_prepare_enable(spi->axi_clk);
788 	return clk_prepare_enable(spi->clk);
789 }
790 #endif
791 
792 static const struct dev_pm_ops orion_spi_pm_ops = {
793 	SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
794 			   orion_spi_runtime_resume,
795 			   NULL)
796 };
797 
798 static struct platform_driver orion_spi_driver = {
799 	.driver = {
800 		.name	= DRIVER_NAME,
801 		.pm	= &orion_spi_pm_ops,
802 		.of_match_table = of_match_ptr(orion_spi_of_match_table),
803 	},
804 	.probe		= orion_spi_probe,
805 	.remove		= orion_spi_remove,
806 };
807 
808 module_platform_driver(orion_spi_driver);
809 
810 MODULE_DESCRIPTION("Orion SPI driver");
811 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
812 MODULE_LICENSE("GPL");
813