1 /* 2 * Marvell Orion SPI controller driver 3 * 4 * Author: Shadi Ammouri <shadi@marvell.com> 5 * Copyright (C) 2007-2008 Marvell Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/spi/spi.h> 18 #include <linux/module.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/clk.h> 24 #include <linux/sizes.h> 25 #include <linux/gpio.h> 26 #include <asm/unaligned.h> 27 28 #define DRIVER_NAME "orion_spi" 29 30 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */ 31 #define SPI_AUTOSUSPEND_TIMEOUT 200 32 33 /* Some SoCs using this driver support up to 8 chip selects. 34 * It is up to the implementer to only use the chip selects 35 * that are available. 36 */ 37 #define ORION_NUM_CHIPSELECTS 8 38 39 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ 40 41 #define ORION_SPI_IF_CTRL_REG 0x00 42 #define ORION_SPI_IF_CONFIG_REG 0x04 43 #define ORION_SPI_IF_RXLSBF BIT(14) 44 #define ORION_SPI_IF_TXLSBF BIT(13) 45 #define ORION_SPI_DATA_OUT_REG 0x08 46 #define ORION_SPI_DATA_IN_REG 0x0c 47 #define ORION_SPI_INT_CAUSE_REG 0x10 48 #define ORION_SPI_TIMING_PARAMS_REG 0x18 49 50 /* Register for the "Direct Mode" */ 51 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20 52 53 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6) 54 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6) 55 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6) 56 57 #define ORION_SPI_MODE_CPOL (1 << 11) 58 #define ORION_SPI_MODE_CPHA (1 << 12) 59 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) 60 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F 61 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF 62 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ 63 ORION_SPI_MODE_CPHA) 64 #define ORION_SPI_CS_MASK 0x1C 65 #define ORION_SPI_CS_SHIFT 2 66 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ 67 ORION_SPI_CS_MASK) 68 69 enum orion_spi_type { 70 ORION_SPI, 71 ARMADA_SPI, 72 }; 73 74 struct orion_spi_dev { 75 enum orion_spi_type typ; 76 /* 77 * min_divisor and max_hz should be exclusive, the only we can 78 * have both is for managing the armada-370-spi case with old 79 * device tree 80 */ 81 unsigned long max_hz; 82 unsigned int min_divisor; 83 unsigned int max_divisor; 84 u32 prescale_mask; 85 bool is_errata_50mhz_ac; 86 }; 87 88 struct orion_direct_acc { 89 void __iomem *vaddr; 90 u32 size; 91 }; 92 93 struct orion_child_options { 94 struct orion_direct_acc direct_access; 95 }; 96 97 struct orion_spi { 98 struct spi_master *master; 99 void __iomem *base; 100 struct clk *clk; 101 struct clk *axi_clk; 102 const struct orion_spi_dev *devdata; 103 int unused_hw_gpio; 104 105 struct orion_child_options child[ORION_NUM_CHIPSELECTS]; 106 }; 107 108 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) 109 { 110 return orion_spi->base + reg; 111 } 112 113 static inline void 114 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 115 { 116 void __iomem *reg_addr = spi_reg(orion_spi, reg); 117 u32 val; 118 119 val = readl(reg_addr); 120 val |= mask; 121 writel(val, reg_addr); 122 } 123 124 static inline void 125 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 126 { 127 void __iomem *reg_addr = spi_reg(orion_spi, reg); 128 u32 val; 129 130 val = readl(reg_addr); 131 val &= ~mask; 132 writel(val, reg_addr); 133 } 134 135 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 136 { 137 u32 tclk_hz; 138 u32 rate; 139 u32 prescale; 140 u32 reg; 141 struct orion_spi *orion_spi; 142 const struct orion_spi_dev *devdata; 143 144 orion_spi = spi_master_get_devdata(spi->master); 145 devdata = orion_spi->devdata; 146 147 tclk_hz = clk_get_rate(orion_spi->clk); 148 149 if (devdata->typ == ARMADA_SPI) { 150 /* 151 * Given the core_clk (tclk_hz) and the target rate (speed) we 152 * determine the best values for SPR (in [0 .. 15]) and SPPR (in 153 * [0..7]) such that 154 * 155 * core_clk / (SPR * 2 ** SPPR) 156 * 157 * is as big as possible but not bigger than speed. 158 */ 159 160 /* best integer divider: */ 161 unsigned divider = DIV_ROUND_UP(tclk_hz, speed); 162 unsigned spr, sppr; 163 164 if (divider < 16) { 165 /* This is the easy case, divider is less than 16 */ 166 spr = divider; 167 sppr = 0; 168 169 } else { 170 unsigned two_pow_sppr; 171 /* 172 * Find the highest bit set in divider. This and the 173 * three next bits define SPR (apart from rounding). 174 * SPPR is then the number of zero bits that must be 175 * appended: 176 */ 177 sppr = fls(divider) - 4; 178 179 /* 180 * As SPR only has 4 bits, we have to round divider up 181 * to the next multiple of 2 ** sppr. 182 */ 183 two_pow_sppr = 1 << sppr; 184 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; 185 186 /* 187 * recalculate sppr as rounding up divider might have 188 * increased it enough to change the position of the 189 * highest set bit. In this case the bit that now 190 * doesn't make it into SPR is 0, so there is no need to 191 * round again. 192 */ 193 sppr = fls(divider) - 4; 194 spr = divider >> sppr; 195 196 /* 197 * Now do range checking. SPR is constructed to have a 198 * width of 4 bits, so this is fine for sure. So we 199 * still need to check for sppr to fit into 3 bits: 200 */ 201 if (sppr > 7) 202 return -EINVAL; 203 } 204 205 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; 206 } else { 207 /* 208 * the supported rates are: 4,6,8...30 209 * round up as we look for equal or less speed 210 */ 211 rate = DIV_ROUND_UP(tclk_hz, speed); 212 rate = roundup(rate, 2); 213 214 /* check if requested speed is too small */ 215 if (rate > 30) 216 return -EINVAL; 217 218 if (rate < 4) 219 rate = 4; 220 221 /* Convert the rate to SPI clock divisor value. */ 222 prescale = 0x10 + rate/2; 223 } 224 225 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 226 reg = ((reg & ~devdata->prescale_mask) | prescale); 227 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 228 229 return 0; 230 } 231 232 static void 233 orion_spi_mode_set(struct spi_device *spi) 234 { 235 u32 reg; 236 struct orion_spi *orion_spi; 237 238 orion_spi = spi_master_get_devdata(spi->master); 239 240 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 241 reg &= ~ORION_SPI_MODE_MASK; 242 if (spi->mode & SPI_CPOL) 243 reg |= ORION_SPI_MODE_CPOL; 244 if (spi->mode & SPI_CPHA) 245 reg |= ORION_SPI_MODE_CPHA; 246 if (spi->mode & SPI_LSB_FIRST) 247 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF; 248 else 249 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF); 250 251 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 252 } 253 254 static void 255 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed) 256 { 257 u32 reg; 258 struct orion_spi *orion_spi; 259 260 orion_spi = spi_master_get_devdata(spi->master); 261 262 /* 263 * Erratum description: (Erratum NO. FE-9144572) The device 264 * SPI interface supports frequencies of up to 50 MHz. 265 * However, due to this erratum, when the device core clock is 266 * 250 MHz and the SPI interfaces is configured for 50MHz SPI 267 * clock and CPOL=CPHA=1 there might occur data corruption on 268 * reads from the SPI device. 269 * Erratum Workaround: 270 * Work in one of the following configurations: 271 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration 272 * Register". 273 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1 274 * Register" before setting the interface. 275 */ 276 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 277 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK; 278 279 if (clk_get_rate(orion_spi->clk) == 250000000 && 280 speed == 50000000 && spi->mode & SPI_CPOL && 281 spi->mode & SPI_CPHA) 282 reg |= ORION_SPI_TMISO_SAMPLE_2; 283 else 284 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */ 285 286 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 287 } 288 289 /* 290 * called only when no transfer is active on the bus 291 */ 292 static int 293 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 294 { 295 struct orion_spi *orion_spi; 296 unsigned int speed = spi->max_speed_hz; 297 unsigned int bits_per_word = spi->bits_per_word; 298 int rc; 299 300 orion_spi = spi_master_get_devdata(spi->master); 301 302 if ((t != NULL) && t->speed_hz) 303 speed = t->speed_hz; 304 305 if ((t != NULL) && t->bits_per_word) 306 bits_per_word = t->bits_per_word; 307 308 orion_spi_mode_set(spi); 309 310 if (orion_spi->devdata->is_errata_50mhz_ac) 311 orion_spi_50mhz_ac_timing_erratum(spi, speed); 312 313 rc = orion_spi_baudrate_set(spi, speed); 314 if (rc) 315 return rc; 316 317 if (bits_per_word == 16) 318 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 319 ORION_SPI_IF_8_16_BIT_MODE); 320 else 321 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 322 ORION_SPI_IF_8_16_BIT_MODE); 323 324 return 0; 325 } 326 327 static void orion_spi_set_cs(struct spi_device *spi, bool enable) 328 { 329 struct orion_spi *orion_spi; 330 int cs; 331 332 orion_spi = spi_master_get_devdata(spi->master); 333 334 if (gpio_is_valid(spi->cs_gpio)) 335 cs = orion_spi->unused_hw_gpio; 336 else 337 cs = spi->chip_select; 338 339 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); 340 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 341 ORION_SPI_CS(cs)); 342 343 /* Chip select logic is inverted from spi_set_cs */ 344 if (!enable) 345 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 346 else 347 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 348 } 349 350 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) 351 { 352 int i; 353 354 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { 355 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) 356 return 1; 357 358 udelay(1); 359 } 360 361 return -1; 362 } 363 364 static inline int 365 orion_spi_write_read_8bit(struct spi_device *spi, 366 const u8 **tx_buf, u8 **rx_buf) 367 { 368 void __iomem *tx_reg, *rx_reg, *int_reg; 369 struct orion_spi *orion_spi; 370 371 orion_spi = spi_master_get_devdata(spi->master); 372 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 373 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 374 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 375 376 /* clear the interrupt cause register */ 377 writel(0x0, int_reg); 378 379 if (tx_buf && *tx_buf) 380 writel(*(*tx_buf)++, tx_reg); 381 else 382 writel(0, tx_reg); 383 384 if (orion_spi_wait_till_ready(orion_spi) < 0) { 385 dev_err(&spi->dev, "TXS timed out\n"); 386 return -1; 387 } 388 389 if (rx_buf && *rx_buf) 390 *(*rx_buf)++ = readl(rx_reg); 391 392 return 1; 393 } 394 395 static inline int 396 orion_spi_write_read_16bit(struct spi_device *spi, 397 const u16 **tx_buf, u16 **rx_buf) 398 { 399 void __iomem *tx_reg, *rx_reg, *int_reg; 400 struct orion_spi *orion_spi; 401 402 orion_spi = spi_master_get_devdata(spi->master); 403 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 404 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 405 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 406 407 /* clear the interrupt cause register */ 408 writel(0x0, int_reg); 409 410 if (tx_buf && *tx_buf) 411 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); 412 else 413 writel(0, tx_reg); 414 415 if (orion_spi_wait_till_ready(orion_spi) < 0) { 416 dev_err(&spi->dev, "TXS timed out\n"); 417 return -1; 418 } 419 420 if (rx_buf && *rx_buf) 421 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); 422 423 return 1; 424 } 425 426 static unsigned int 427 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 428 { 429 unsigned int count; 430 int word_len; 431 struct orion_spi *orion_spi; 432 int cs = spi->chip_select; 433 434 word_len = spi->bits_per_word; 435 count = xfer->len; 436 437 orion_spi = spi_master_get_devdata(spi->master); 438 439 /* 440 * Use SPI direct write mode if base address is available. Otherwise 441 * fall back to PIO mode for this transfer. 442 */ 443 if ((orion_spi->child[cs].direct_access.vaddr) && (xfer->tx_buf) && 444 (word_len == 8)) { 445 unsigned int cnt = count / 4; 446 unsigned int rem = count % 4; 447 448 /* 449 * Send the TX-data to the SPI device via the direct 450 * mapped address window 451 */ 452 iowrite32_rep(orion_spi->child[cs].direct_access.vaddr, 453 xfer->tx_buf, cnt); 454 if (rem) { 455 u32 *buf = (u32 *)xfer->tx_buf; 456 457 iowrite8_rep(orion_spi->child[cs].direct_access.vaddr, 458 &buf[cnt], rem); 459 } 460 461 return count; 462 } 463 464 if (word_len == 8) { 465 const u8 *tx = xfer->tx_buf; 466 u8 *rx = xfer->rx_buf; 467 468 do { 469 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) 470 goto out; 471 count--; 472 } while (count); 473 } else if (word_len == 16) { 474 const u16 *tx = xfer->tx_buf; 475 u16 *rx = xfer->rx_buf; 476 477 do { 478 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) 479 goto out; 480 count -= 2; 481 } while (count); 482 } 483 484 out: 485 return xfer->len - count; 486 } 487 488 static int orion_spi_transfer_one(struct spi_master *master, 489 struct spi_device *spi, 490 struct spi_transfer *t) 491 { 492 int status = 0; 493 494 status = orion_spi_setup_transfer(spi, t); 495 if (status < 0) 496 return status; 497 498 if (t->len) 499 orion_spi_write_read(spi, t); 500 501 return status; 502 } 503 504 static int orion_spi_setup(struct spi_device *spi) 505 { 506 if (gpio_is_valid(spi->cs_gpio)) { 507 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 508 } 509 return orion_spi_setup_transfer(spi, NULL); 510 } 511 512 static int orion_spi_reset(struct orion_spi *orion_spi) 513 { 514 /* Verify that the CS is deasserted */ 515 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 516 517 /* Don't deassert CS between the direct mapped SPI transfers */ 518 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG)); 519 520 return 0; 521 } 522 523 static const struct orion_spi_dev orion_spi_dev_data = { 524 .typ = ORION_SPI, 525 .min_divisor = 4, 526 .max_divisor = 30, 527 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, 528 }; 529 530 static const struct orion_spi_dev armada_370_spi_dev_data = { 531 .typ = ARMADA_SPI, 532 .min_divisor = 4, 533 .max_divisor = 1920, 534 .max_hz = 50000000, 535 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 536 }; 537 538 static const struct orion_spi_dev armada_xp_spi_dev_data = { 539 .typ = ARMADA_SPI, 540 .max_hz = 50000000, 541 .max_divisor = 1920, 542 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 543 }; 544 545 static const struct orion_spi_dev armada_375_spi_dev_data = { 546 .typ = ARMADA_SPI, 547 .min_divisor = 15, 548 .max_divisor = 1920, 549 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 550 }; 551 552 static const struct orion_spi_dev armada_380_spi_dev_data = { 553 .typ = ARMADA_SPI, 554 .max_hz = 50000000, 555 .max_divisor = 1920, 556 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 557 .is_errata_50mhz_ac = true, 558 }; 559 560 static const struct of_device_id orion_spi_of_match_table[] = { 561 { 562 .compatible = "marvell,orion-spi", 563 .data = &orion_spi_dev_data, 564 }, 565 { 566 .compatible = "marvell,armada-370-spi", 567 .data = &armada_370_spi_dev_data, 568 }, 569 { 570 .compatible = "marvell,armada-375-spi", 571 .data = &armada_375_spi_dev_data, 572 }, 573 { 574 .compatible = "marvell,armada-380-spi", 575 .data = &armada_380_spi_dev_data, 576 }, 577 { 578 .compatible = "marvell,armada-390-spi", 579 .data = &armada_xp_spi_dev_data, 580 }, 581 { 582 .compatible = "marvell,armada-xp-spi", 583 .data = &armada_xp_spi_dev_data, 584 }, 585 586 {} 587 }; 588 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); 589 590 static int orion_spi_probe(struct platform_device *pdev) 591 { 592 const struct of_device_id *of_id; 593 const struct orion_spi_dev *devdata; 594 struct spi_master *master; 595 struct orion_spi *spi; 596 struct resource *r; 597 unsigned long tclk_hz; 598 int status = 0; 599 struct device_node *np; 600 601 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); 602 if (master == NULL) { 603 dev_dbg(&pdev->dev, "master allocation failed\n"); 604 return -ENOMEM; 605 } 606 607 if (pdev->id != -1) 608 master->bus_num = pdev->id; 609 if (pdev->dev.of_node) { 610 u32 cell_index; 611 612 if (!of_property_read_u32(pdev->dev.of_node, "cell-index", 613 &cell_index)) 614 master->bus_num = cell_index; 615 } 616 617 /* we support all 4 SPI modes and LSB first option */ 618 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; 619 master->set_cs = orion_spi_set_cs; 620 master->transfer_one = orion_spi_transfer_one; 621 master->num_chipselect = ORION_NUM_CHIPSELECTS; 622 master->setup = orion_spi_setup; 623 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 624 master->auto_runtime_pm = true; 625 master->flags = SPI_MASTER_GPIO_SS; 626 627 platform_set_drvdata(pdev, master); 628 629 spi = spi_master_get_devdata(master); 630 spi->master = master; 631 spi->unused_hw_gpio = -1; 632 633 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); 634 devdata = (of_id) ? of_id->data : &orion_spi_dev_data; 635 spi->devdata = devdata; 636 637 spi->clk = devm_clk_get(&pdev->dev, NULL); 638 if (IS_ERR(spi->clk)) { 639 status = PTR_ERR(spi->clk); 640 goto out; 641 } 642 643 status = clk_prepare_enable(spi->clk); 644 if (status) 645 goto out; 646 647 /* The following clock is only used by some SoCs */ 648 spi->axi_clk = devm_clk_get(&pdev->dev, "axi"); 649 if (IS_ERR(spi->axi_clk) && 650 PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) { 651 status = -EPROBE_DEFER; 652 goto out_rel_clk; 653 } 654 if (!IS_ERR(spi->axi_clk)) 655 clk_prepare_enable(spi->axi_clk); 656 657 tclk_hz = clk_get_rate(spi->clk); 658 659 /* 660 * With old device tree, armada-370-spi could be used with 661 * Armada XP, however for this SoC the maximum frequency is 662 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be 663 * higher than 200MHz. So, in order to be able to handle both 664 * SoCs, we can take the minimum of 50MHz and tclk/4. 665 */ 666 if (of_device_is_compatible(pdev->dev.of_node, 667 "marvell,armada-370-spi")) 668 master->max_speed_hz = min(devdata->max_hz, 669 DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); 670 else if (devdata->min_divisor) 671 master->max_speed_hz = 672 DIV_ROUND_UP(tclk_hz, devdata->min_divisor); 673 else 674 master->max_speed_hz = devdata->max_hz; 675 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); 676 677 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 678 spi->base = devm_ioremap_resource(&pdev->dev, r); 679 if (IS_ERR(spi->base)) { 680 status = PTR_ERR(spi->base); 681 goto out_rel_axi_clk; 682 } 683 684 /* Scan all SPI devices of this controller for direct mapped devices */ 685 for_each_available_child_of_node(pdev->dev.of_node, np) { 686 u32 cs; 687 688 /* Get chip-select number from the "reg" property */ 689 status = of_property_read_u32(np, "reg", &cs); 690 if (status) { 691 dev_err(&pdev->dev, 692 "%pOF has no valid 'reg' property (%d)\n", 693 np, status); 694 continue; 695 } 696 697 /* 698 * Check if an address is configured for this SPI device. If 699 * not, the MBus mapping via the 'ranges' property in the 'soc' 700 * node is not configured and this device should not use the 701 * direct mode. In this case, just continue with the next 702 * device. 703 */ 704 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r); 705 if (status) 706 continue; 707 708 /* 709 * Only map one page for direct access. This is enough for the 710 * simple TX transfer which only writes to the first word. 711 * This needs to get extended for the direct SPI-NOR / SPI-NAND 712 * support, once this gets implemented. 713 */ 714 spi->child[cs].direct_access.vaddr = devm_ioremap(&pdev->dev, 715 r->start, 716 PAGE_SIZE); 717 if (!spi->child[cs].direct_access.vaddr) { 718 status = -ENOMEM; 719 goto out_rel_axi_clk; 720 } 721 spi->child[cs].direct_access.size = PAGE_SIZE; 722 723 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs); 724 } 725 726 pm_runtime_set_active(&pdev->dev); 727 pm_runtime_use_autosuspend(&pdev->dev); 728 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 729 pm_runtime_enable(&pdev->dev); 730 731 status = orion_spi_reset(spi); 732 if (status < 0) 733 goto out_rel_pm; 734 735 pm_runtime_mark_last_busy(&pdev->dev); 736 pm_runtime_put_autosuspend(&pdev->dev); 737 738 master->dev.of_node = pdev->dev.of_node; 739 status = spi_register_master(master); 740 if (status < 0) 741 goto out_rel_pm; 742 743 if (master->cs_gpios) { 744 int i; 745 for (i = 0; i < master->num_chipselect; ++i) { 746 char *gpio_name; 747 748 if (!gpio_is_valid(master->cs_gpios[i])) { 749 continue; 750 } 751 752 gpio_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, 753 "%s-CS%d", dev_name(&pdev->dev), i); 754 if (!gpio_name) { 755 status = -ENOMEM; 756 goto out_rel_master; 757 } 758 759 status = devm_gpio_request(&pdev->dev, 760 master->cs_gpios[i], gpio_name); 761 if (status) { 762 dev_err(&pdev->dev, 763 "Can't request GPIO for CS %d\n", 764 master->cs_gpios[i]); 765 goto out_rel_master; 766 } 767 if (spi->unused_hw_gpio == -1) { 768 dev_info(&pdev->dev, 769 "Selected unused HW CS#%d for any GPIO CSes\n", 770 i); 771 spi->unused_hw_gpio = i; 772 } 773 } 774 } 775 776 777 return status; 778 779 out_rel_master: 780 spi_unregister_master(master); 781 out_rel_pm: 782 pm_runtime_disable(&pdev->dev); 783 out_rel_axi_clk: 784 clk_disable_unprepare(spi->axi_clk); 785 out_rel_clk: 786 clk_disable_unprepare(spi->clk); 787 out: 788 spi_master_put(master); 789 return status; 790 } 791 792 793 static int orion_spi_remove(struct platform_device *pdev) 794 { 795 struct spi_master *master = platform_get_drvdata(pdev); 796 struct orion_spi *spi = spi_master_get_devdata(master); 797 798 pm_runtime_get_sync(&pdev->dev); 799 clk_disable_unprepare(spi->axi_clk); 800 clk_disable_unprepare(spi->clk); 801 802 spi_unregister_master(master); 803 pm_runtime_disable(&pdev->dev); 804 805 return 0; 806 } 807 808 MODULE_ALIAS("platform:" DRIVER_NAME); 809 810 #ifdef CONFIG_PM 811 static int orion_spi_runtime_suspend(struct device *dev) 812 { 813 struct spi_master *master = dev_get_drvdata(dev); 814 struct orion_spi *spi = spi_master_get_devdata(master); 815 816 clk_disable_unprepare(spi->axi_clk); 817 clk_disable_unprepare(spi->clk); 818 return 0; 819 } 820 821 static int orion_spi_runtime_resume(struct device *dev) 822 { 823 struct spi_master *master = dev_get_drvdata(dev); 824 struct orion_spi *spi = spi_master_get_devdata(master); 825 826 if (!IS_ERR(spi->axi_clk)) 827 clk_prepare_enable(spi->axi_clk); 828 return clk_prepare_enable(spi->clk); 829 } 830 #endif 831 832 static const struct dev_pm_ops orion_spi_pm_ops = { 833 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, 834 orion_spi_runtime_resume, 835 NULL) 836 }; 837 838 static struct platform_driver orion_spi_driver = { 839 .driver = { 840 .name = DRIVER_NAME, 841 .pm = &orion_spi_pm_ops, 842 .of_match_table = of_match_ptr(orion_spi_of_match_table), 843 }, 844 .probe = orion_spi_probe, 845 .remove = orion_spi_remove, 846 }; 847 848 module_platform_driver(orion_spi_driver); 849 850 MODULE_DESCRIPTION("Orion SPI driver"); 851 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); 852 MODULE_LICENSE("GPL"); 853