1 /* 2 * Marvell Orion SPI controller driver 3 * 4 * Author: Shadi Ammouri <shadi@marvell.com> 5 * Copyright (C) 2007-2008 Marvell Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/spi/spi.h> 18 #include <linux/module.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/clk.h> 24 #include <linux/sizes.h> 25 #include <asm/unaligned.h> 26 27 #define DRIVER_NAME "orion_spi" 28 29 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */ 30 #define SPI_AUTOSUSPEND_TIMEOUT 200 31 32 /* Some SoCs using this driver support up to 8 chip selects. 33 * It is up to the implementer to only use the chip selects 34 * that are available. 35 */ 36 #define ORION_NUM_CHIPSELECTS 8 37 38 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ 39 40 #define ORION_SPI_IF_CTRL_REG 0x00 41 #define ORION_SPI_IF_CONFIG_REG 0x04 42 #define ORION_SPI_IF_RXLSBF BIT(14) 43 #define ORION_SPI_IF_TXLSBF BIT(13) 44 #define ORION_SPI_DATA_OUT_REG 0x08 45 #define ORION_SPI_DATA_IN_REG 0x0c 46 #define ORION_SPI_INT_CAUSE_REG 0x10 47 #define ORION_SPI_TIMING_PARAMS_REG 0x18 48 49 /* Register for the "Direct Mode" */ 50 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20 51 52 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6) 53 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6) 54 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6) 55 56 #define ORION_SPI_MODE_CPOL (1 << 11) 57 #define ORION_SPI_MODE_CPHA (1 << 12) 58 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) 59 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F 60 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF 61 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ 62 ORION_SPI_MODE_CPHA) 63 #define ORION_SPI_CS_MASK 0x1C 64 #define ORION_SPI_CS_SHIFT 2 65 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ 66 ORION_SPI_CS_MASK) 67 68 enum orion_spi_type { 69 ORION_SPI, 70 ARMADA_SPI, 71 }; 72 73 struct orion_spi_dev { 74 enum orion_spi_type typ; 75 /* 76 * min_divisor and max_hz should be exclusive, the only we can 77 * have both is for managing the armada-370-spi case with old 78 * device tree 79 */ 80 unsigned long max_hz; 81 unsigned int min_divisor; 82 unsigned int max_divisor; 83 u32 prescale_mask; 84 bool is_errata_50mhz_ac; 85 }; 86 87 struct orion_direct_acc { 88 void __iomem *vaddr; 89 u32 size; 90 }; 91 92 struct orion_spi { 93 struct spi_master *master; 94 void __iomem *base; 95 struct clk *clk; 96 const struct orion_spi_dev *devdata; 97 98 struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS]; 99 }; 100 101 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) 102 { 103 return orion_spi->base + reg; 104 } 105 106 static inline void 107 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 108 { 109 void __iomem *reg_addr = spi_reg(orion_spi, reg); 110 u32 val; 111 112 val = readl(reg_addr); 113 val |= mask; 114 writel(val, reg_addr); 115 } 116 117 static inline void 118 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 119 { 120 void __iomem *reg_addr = spi_reg(orion_spi, reg); 121 u32 val; 122 123 val = readl(reg_addr); 124 val &= ~mask; 125 writel(val, reg_addr); 126 } 127 128 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 129 { 130 u32 tclk_hz; 131 u32 rate; 132 u32 prescale; 133 u32 reg; 134 struct orion_spi *orion_spi; 135 const struct orion_spi_dev *devdata; 136 137 orion_spi = spi_master_get_devdata(spi->master); 138 devdata = orion_spi->devdata; 139 140 tclk_hz = clk_get_rate(orion_spi->clk); 141 142 if (devdata->typ == ARMADA_SPI) { 143 /* 144 * Given the core_clk (tclk_hz) and the target rate (speed) we 145 * determine the best values for SPR (in [0 .. 15]) and SPPR (in 146 * [0..7]) such that 147 * 148 * core_clk / (SPR * 2 ** SPPR) 149 * 150 * is as big as possible but not bigger than speed. 151 */ 152 153 /* best integer divider: */ 154 unsigned divider = DIV_ROUND_UP(tclk_hz, speed); 155 unsigned spr, sppr; 156 157 if (divider < 16) { 158 /* This is the easy case, divider is less than 16 */ 159 spr = divider; 160 sppr = 0; 161 162 } else { 163 unsigned two_pow_sppr; 164 /* 165 * Find the highest bit set in divider. This and the 166 * three next bits define SPR (apart from rounding). 167 * SPPR is then the number of zero bits that must be 168 * appended: 169 */ 170 sppr = fls(divider) - 4; 171 172 /* 173 * As SPR only has 4 bits, we have to round divider up 174 * to the next multiple of 2 ** sppr. 175 */ 176 two_pow_sppr = 1 << sppr; 177 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; 178 179 /* 180 * recalculate sppr as rounding up divider might have 181 * increased it enough to change the position of the 182 * highest set bit. In this case the bit that now 183 * doesn't make it into SPR is 0, so there is no need to 184 * round again. 185 */ 186 sppr = fls(divider) - 4; 187 spr = divider >> sppr; 188 189 /* 190 * Now do range checking. SPR is constructed to have a 191 * width of 4 bits, so this is fine for sure. So we 192 * still need to check for sppr to fit into 3 bits: 193 */ 194 if (sppr > 7) 195 return -EINVAL; 196 } 197 198 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; 199 } else { 200 /* 201 * the supported rates are: 4,6,8...30 202 * round up as we look for equal or less speed 203 */ 204 rate = DIV_ROUND_UP(tclk_hz, speed); 205 rate = roundup(rate, 2); 206 207 /* check if requested speed is too small */ 208 if (rate > 30) 209 return -EINVAL; 210 211 if (rate < 4) 212 rate = 4; 213 214 /* Convert the rate to SPI clock divisor value. */ 215 prescale = 0x10 + rate/2; 216 } 217 218 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 219 reg = ((reg & ~devdata->prescale_mask) | prescale); 220 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 221 222 return 0; 223 } 224 225 static void 226 orion_spi_mode_set(struct spi_device *spi) 227 { 228 u32 reg; 229 struct orion_spi *orion_spi; 230 231 orion_spi = spi_master_get_devdata(spi->master); 232 233 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 234 reg &= ~ORION_SPI_MODE_MASK; 235 if (spi->mode & SPI_CPOL) 236 reg |= ORION_SPI_MODE_CPOL; 237 if (spi->mode & SPI_CPHA) 238 reg |= ORION_SPI_MODE_CPHA; 239 if (spi->mode & SPI_LSB_FIRST) 240 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF; 241 else 242 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF); 243 244 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 245 } 246 247 static void 248 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed) 249 { 250 u32 reg; 251 struct orion_spi *orion_spi; 252 253 orion_spi = spi_master_get_devdata(spi->master); 254 255 /* 256 * Erratum description: (Erratum NO. FE-9144572) The device 257 * SPI interface supports frequencies of up to 50 MHz. 258 * However, due to this erratum, when the device core clock is 259 * 250 MHz and the SPI interfaces is configured for 50MHz SPI 260 * clock and CPOL=CPHA=1 there might occur data corruption on 261 * reads from the SPI device. 262 * Erratum Workaround: 263 * Work in one of the following configurations: 264 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration 265 * Register". 266 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1 267 * Register" before setting the interface. 268 */ 269 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 270 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK; 271 272 if (clk_get_rate(orion_spi->clk) == 250000000 && 273 speed == 50000000 && spi->mode & SPI_CPOL && 274 spi->mode & SPI_CPHA) 275 reg |= ORION_SPI_TMISO_SAMPLE_2; 276 else 277 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */ 278 279 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 280 } 281 282 /* 283 * called only when no transfer is active on the bus 284 */ 285 static int 286 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 287 { 288 struct orion_spi *orion_spi; 289 unsigned int speed = spi->max_speed_hz; 290 unsigned int bits_per_word = spi->bits_per_word; 291 int rc; 292 293 orion_spi = spi_master_get_devdata(spi->master); 294 295 if ((t != NULL) && t->speed_hz) 296 speed = t->speed_hz; 297 298 if ((t != NULL) && t->bits_per_word) 299 bits_per_word = t->bits_per_word; 300 301 orion_spi_mode_set(spi); 302 303 if (orion_spi->devdata->is_errata_50mhz_ac) 304 orion_spi_50mhz_ac_timing_erratum(spi, speed); 305 306 rc = orion_spi_baudrate_set(spi, speed); 307 if (rc) 308 return rc; 309 310 if (bits_per_word == 16) 311 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 312 ORION_SPI_IF_8_16_BIT_MODE); 313 else 314 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 315 ORION_SPI_IF_8_16_BIT_MODE); 316 317 return 0; 318 } 319 320 static void orion_spi_set_cs(struct spi_device *spi, bool enable) 321 { 322 struct orion_spi *orion_spi; 323 324 orion_spi = spi_master_get_devdata(spi->master); 325 326 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); 327 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 328 ORION_SPI_CS(spi->chip_select)); 329 330 /* Chip select logic is inverted from spi_set_cs */ 331 if (!enable) 332 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 333 else 334 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 335 } 336 337 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) 338 { 339 int i; 340 341 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { 342 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) 343 return 1; 344 345 udelay(1); 346 } 347 348 return -1; 349 } 350 351 static inline int 352 orion_spi_write_read_8bit(struct spi_device *spi, 353 const u8 **tx_buf, u8 **rx_buf) 354 { 355 void __iomem *tx_reg, *rx_reg, *int_reg; 356 struct orion_spi *orion_spi; 357 358 orion_spi = spi_master_get_devdata(spi->master); 359 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 360 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 361 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 362 363 /* clear the interrupt cause register */ 364 writel(0x0, int_reg); 365 366 if (tx_buf && *tx_buf) 367 writel(*(*tx_buf)++, tx_reg); 368 else 369 writel(0, tx_reg); 370 371 if (orion_spi_wait_till_ready(orion_spi) < 0) { 372 dev_err(&spi->dev, "TXS timed out\n"); 373 return -1; 374 } 375 376 if (rx_buf && *rx_buf) 377 *(*rx_buf)++ = readl(rx_reg); 378 379 return 1; 380 } 381 382 static inline int 383 orion_spi_write_read_16bit(struct spi_device *spi, 384 const u16 **tx_buf, u16 **rx_buf) 385 { 386 void __iomem *tx_reg, *rx_reg, *int_reg; 387 struct orion_spi *orion_spi; 388 389 orion_spi = spi_master_get_devdata(spi->master); 390 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 391 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 392 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 393 394 /* clear the interrupt cause register */ 395 writel(0x0, int_reg); 396 397 if (tx_buf && *tx_buf) 398 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); 399 else 400 writel(0, tx_reg); 401 402 if (orion_spi_wait_till_ready(orion_spi) < 0) { 403 dev_err(&spi->dev, "TXS timed out\n"); 404 return -1; 405 } 406 407 if (rx_buf && *rx_buf) 408 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); 409 410 return 1; 411 } 412 413 static unsigned int 414 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 415 { 416 unsigned int count; 417 int word_len; 418 struct orion_spi *orion_spi; 419 int cs = spi->chip_select; 420 421 word_len = spi->bits_per_word; 422 count = xfer->len; 423 424 orion_spi = spi_master_get_devdata(spi->master); 425 426 /* 427 * Use SPI direct write mode if base address is available. Otherwise 428 * fall back to PIO mode for this transfer. 429 */ 430 if ((orion_spi->direct_access[cs].vaddr) && (xfer->tx_buf) && 431 (word_len == 8)) { 432 unsigned int cnt = count / 4; 433 unsigned int rem = count % 4; 434 435 /* 436 * Send the TX-data to the SPI device via the direct 437 * mapped address window 438 */ 439 iowrite32_rep(orion_spi->direct_access[cs].vaddr, 440 xfer->tx_buf, cnt); 441 if (rem) { 442 u32 *buf = (u32 *)xfer->tx_buf; 443 444 iowrite8_rep(orion_spi->direct_access[cs].vaddr, 445 &buf[cnt], rem); 446 } 447 448 return count; 449 } 450 451 if (word_len == 8) { 452 const u8 *tx = xfer->tx_buf; 453 u8 *rx = xfer->rx_buf; 454 455 do { 456 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) 457 goto out; 458 count--; 459 } while (count); 460 } else if (word_len == 16) { 461 const u16 *tx = xfer->tx_buf; 462 u16 *rx = xfer->rx_buf; 463 464 do { 465 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) 466 goto out; 467 count -= 2; 468 } while (count); 469 } 470 471 out: 472 return xfer->len - count; 473 } 474 475 static int orion_spi_transfer_one(struct spi_master *master, 476 struct spi_device *spi, 477 struct spi_transfer *t) 478 { 479 int status = 0; 480 481 status = orion_spi_setup_transfer(spi, t); 482 if (status < 0) 483 return status; 484 485 if (t->len) 486 orion_spi_write_read(spi, t); 487 488 return status; 489 } 490 491 static int orion_spi_setup(struct spi_device *spi) 492 { 493 return orion_spi_setup_transfer(spi, NULL); 494 } 495 496 static int orion_spi_reset(struct orion_spi *orion_spi) 497 { 498 /* Verify that the CS is deasserted */ 499 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 500 501 /* Don't deassert CS between the direct mapped SPI transfers */ 502 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG)); 503 504 return 0; 505 } 506 507 static const struct orion_spi_dev orion_spi_dev_data = { 508 .typ = ORION_SPI, 509 .min_divisor = 4, 510 .max_divisor = 30, 511 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, 512 }; 513 514 static const struct orion_spi_dev armada_370_spi_dev_data = { 515 .typ = ARMADA_SPI, 516 .min_divisor = 4, 517 .max_divisor = 1920, 518 .max_hz = 50000000, 519 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 520 }; 521 522 static const struct orion_spi_dev armada_xp_spi_dev_data = { 523 .typ = ARMADA_SPI, 524 .max_hz = 50000000, 525 .max_divisor = 1920, 526 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 527 }; 528 529 static const struct orion_spi_dev armada_375_spi_dev_data = { 530 .typ = ARMADA_SPI, 531 .min_divisor = 15, 532 .max_divisor = 1920, 533 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 534 }; 535 536 static const struct orion_spi_dev armada_380_spi_dev_data = { 537 .typ = ARMADA_SPI, 538 .max_hz = 50000000, 539 .max_divisor = 1920, 540 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 541 .is_errata_50mhz_ac = true, 542 }; 543 544 static const struct of_device_id orion_spi_of_match_table[] = { 545 { 546 .compatible = "marvell,orion-spi", 547 .data = &orion_spi_dev_data, 548 }, 549 { 550 .compatible = "marvell,armada-370-spi", 551 .data = &armada_370_spi_dev_data, 552 }, 553 { 554 .compatible = "marvell,armada-375-spi", 555 .data = &armada_375_spi_dev_data, 556 }, 557 { 558 .compatible = "marvell,armada-380-spi", 559 .data = &armada_380_spi_dev_data, 560 }, 561 { 562 .compatible = "marvell,armada-390-spi", 563 .data = &armada_xp_spi_dev_data, 564 }, 565 { 566 .compatible = "marvell,armada-xp-spi", 567 .data = &armada_xp_spi_dev_data, 568 }, 569 570 {} 571 }; 572 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); 573 574 static int orion_spi_probe(struct platform_device *pdev) 575 { 576 const struct of_device_id *of_id; 577 const struct orion_spi_dev *devdata; 578 struct spi_master *master; 579 struct orion_spi *spi; 580 struct resource *r; 581 unsigned long tclk_hz; 582 int status = 0; 583 struct device_node *np; 584 585 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); 586 if (master == NULL) { 587 dev_dbg(&pdev->dev, "master allocation failed\n"); 588 return -ENOMEM; 589 } 590 591 if (pdev->id != -1) 592 master->bus_num = pdev->id; 593 if (pdev->dev.of_node) { 594 u32 cell_index; 595 596 if (!of_property_read_u32(pdev->dev.of_node, "cell-index", 597 &cell_index)) 598 master->bus_num = cell_index; 599 } 600 601 /* we support all 4 SPI modes and LSB first option */ 602 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; 603 master->set_cs = orion_spi_set_cs; 604 master->transfer_one = orion_spi_transfer_one; 605 master->num_chipselect = ORION_NUM_CHIPSELECTS; 606 master->setup = orion_spi_setup; 607 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 608 master->auto_runtime_pm = true; 609 610 platform_set_drvdata(pdev, master); 611 612 spi = spi_master_get_devdata(master); 613 spi->master = master; 614 615 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); 616 devdata = (of_id) ? of_id->data : &orion_spi_dev_data; 617 spi->devdata = devdata; 618 619 spi->clk = devm_clk_get(&pdev->dev, NULL); 620 if (IS_ERR(spi->clk)) { 621 status = PTR_ERR(spi->clk); 622 goto out; 623 } 624 625 status = clk_prepare_enable(spi->clk); 626 if (status) 627 goto out; 628 629 tclk_hz = clk_get_rate(spi->clk); 630 631 /* 632 * With old device tree, armada-370-spi could be used with 633 * Armada XP, however for this SoC the maximum frequency is 634 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be 635 * higher than 200MHz. So, in order to be able to handle both 636 * SoCs, we can take the minimum of 50MHz and tclk/4. 637 */ 638 if (of_device_is_compatible(pdev->dev.of_node, 639 "marvell,armada-370-spi")) 640 master->max_speed_hz = min(devdata->max_hz, 641 DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); 642 else if (devdata->min_divisor) 643 master->max_speed_hz = 644 DIV_ROUND_UP(tclk_hz, devdata->min_divisor); 645 else 646 master->max_speed_hz = devdata->max_hz; 647 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); 648 649 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 650 spi->base = devm_ioremap_resource(&pdev->dev, r); 651 if (IS_ERR(spi->base)) { 652 status = PTR_ERR(spi->base); 653 goto out_rel_clk; 654 } 655 656 /* Scan all SPI devices of this controller for direct mapped devices */ 657 for_each_available_child_of_node(pdev->dev.of_node, np) { 658 u32 cs; 659 660 /* Get chip-select number from the "reg" property */ 661 status = of_property_read_u32(np, "reg", &cs); 662 if (status) { 663 dev_err(&pdev->dev, 664 "%s has no valid 'reg' property (%d)\n", 665 np->full_name, status); 666 status = 0; 667 continue; 668 } 669 670 /* 671 * Check if an address is configured for this SPI device. If 672 * not, the MBus mapping via the 'ranges' property in the 'soc' 673 * node is not configured and this device should not use the 674 * direct mode. In this case, just continue with the next 675 * device. 676 */ 677 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r); 678 if (status) 679 continue; 680 681 /* 682 * Only map one page for direct access. This is enough for the 683 * simple TX transfer which only writes to the first word. 684 * This needs to get extended for the direct SPI-NOR / SPI-NAND 685 * support, once this gets implemented. 686 */ 687 spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev, 688 r->start, 689 PAGE_SIZE); 690 if (!spi->direct_access[cs].vaddr) { 691 status = -ENOMEM; 692 goto out_rel_clk; 693 } 694 spi->direct_access[cs].size = PAGE_SIZE; 695 696 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs); 697 } 698 699 pm_runtime_set_active(&pdev->dev); 700 pm_runtime_use_autosuspend(&pdev->dev); 701 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 702 pm_runtime_enable(&pdev->dev); 703 704 status = orion_spi_reset(spi); 705 if (status < 0) 706 goto out_rel_pm; 707 708 pm_runtime_mark_last_busy(&pdev->dev); 709 pm_runtime_put_autosuspend(&pdev->dev); 710 711 master->dev.of_node = pdev->dev.of_node; 712 status = spi_register_master(master); 713 if (status < 0) 714 goto out_rel_pm; 715 716 return status; 717 718 out_rel_pm: 719 pm_runtime_disable(&pdev->dev); 720 out_rel_clk: 721 clk_disable_unprepare(spi->clk); 722 out: 723 spi_master_put(master); 724 return status; 725 } 726 727 728 static int orion_spi_remove(struct platform_device *pdev) 729 { 730 struct spi_master *master = platform_get_drvdata(pdev); 731 struct orion_spi *spi = spi_master_get_devdata(master); 732 733 pm_runtime_get_sync(&pdev->dev); 734 clk_disable_unprepare(spi->clk); 735 736 spi_unregister_master(master); 737 pm_runtime_disable(&pdev->dev); 738 739 return 0; 740 } 741 742 MODULE_ALIAS("platform:" DRIVER_NAME); 743 744 #ifdef CONFIG_PM 745 static int orion_spi_runtime_suspend(struct device *dev) 746 { 747 struct spi_master *master = dev_get_drvdata(dev); 748 struct orion_spi *spi = spi_master_get_devdata(master); 749 750 clk_disable_unprepare(spi->clk); 751 return 0; 752 } 753 754 static int orion_spi_runtime_resume(struct device *dev) 755 { 756 struct spi_master *master = dev_get_drvdata(dev); 757 struct orion_spi *spi = spi_master_get_devdata(master); 758 759 return clk_prepare_enable(spi->clk); 760 } 761 #endif 762 763 static const struct dev_pm_ops orion_spi_pm_ops = { 764 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, 765 orion_spi_runtime_resume, 766 NULL) 767 }; 768 769 static struct platform_driver orion_spi_driver = { 770 .driver = { 771 .name = DRIVER_NAME, 772 .pm = &orion_spi_pm_ops, 773 .of_match_table = of_match_ptr(orion_spi_of_match_table), 774 }, 775 .probe = orion_spi_probe, 776 .remove = orion_spi_remove, 777 }; 778 779 module_platform_driver(orion_spi_driver); 780 781 MODULE_DESCRIPTION("Orion SPI driver"); 782 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); 783 MODULE_LICENSE("GPL"); 784