1 /* 2 * Marvell Orion SPI controller driver 3 * 4 * Author: Shadi Ammouri <shadi@marvell.com> 5 * Copyright (C) 2007-2008 Marvell Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/spi/spi.h> 18 #include <linux/module.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/clk.h> 23 #include <linux/sizes.h> 24 #include <asm/unaligned.h> 25 26 #define DRIVER_NAME "orion_spi" 27 28 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */ 29 #define SPI_AUTOSUSPEND_TIMEOUT 200 30 31 #define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/ 32 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ 33 34 #define ORION_SPI_IF_CTRL_REG 0x00 35 #define ORION_SPI_IF_CONFIG_REG 0x04 36 #define ORION_SPI_DATA_OUT_REG 0x08 37 #define ORION_SPI_DATA_IN_REG 0x0c 38 #define ORION_SPI_INT_CAUSE_REG 0x10 39 40 #define ORION_SPI_MODE_CPOL (1 << 11) 41 #define ORION_SPI_MODE_CPHA (1 << 12) 42 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) 43 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F 44 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF 45 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ 46 ORION_SPI_MODE_CPHA) 47 48 enum orion_spi_type { 49 ORION_SPI, 50 ARMADA_SPI, 51 }; 52 53 struct orion_spi_dev { 54 enum orion_spi_type typ; 55 unsigned int min_divisor; 56 unsigned int max_divisor; 57 u32 prescale_mask; 58 }; 59 60 struct orion_spi { 61 struct spi_master *master; 62 void __iomem *base; 63 struct clk *clk; 64 const struct orion_spi_dev *devdata; 65 }; 66 67 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) 68 { 69 return orion_spi->base + reg; 70 } 71 72 static inline void 73 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 74 { 75 void __iomem *reg_addr = spi_reg(orion_spi, reg); 76 u32 val; 77 78 val = readl(reg_addr); 79 val |= mask; 80 writel(val, reg_addr); 81 } 82 83 static inline void 84 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 85 { 86 void __iomem *reg_addr = spi_reg(orion_spi, reg); 87 u32 val; 88 89 val = readl(reg_addr); 90 val &= ~mask; 91 writel(val, reg_addr); 92 } 93 94 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 95 { 96 u32 tclk_hz; 97 u32 rate; 98 u32 prescale; 99 u32 reg; 100 struct orion_spi *orion_spi; 101 const struct orion_spi_dev *devdata; 102 103 orion_spi = spi_master_get_devdata(spi->master); 104 devdata = orion_spi->devdata; 105 106 tclk_hz = clk_get_rate(orion_spi->clk); 107 108 if (devdata->typ == ARMADA_SPI) { 109 unsigned int clk, spr, sppr, sppr2, err; 110 unsigned int best_spr, best_sppr, best_err; 111 112 best_err = speed; 113 best_spr = 0; 114 best_sppr = 0; 115 116 /* Iterate over the valid range looking for best fit */ 117 for (sppr = 0; sppr < 8; sppr++) { 118 sppr2 = 0x1 << sppr; 119 120 spr = tclk_hz / sppr2; 121 spr = DIV_ROUND_UP(spr, speed); 122 if ((spr == 0) || (spr > 15)) 123 continue; 124 125 clk = tclk_hz / (spr * sppr2); 126 err = speed - clk; 127 128 if (err < best_err) { 129 best_spr = spr; 130 best_sppr = sppr; 131 best_err = err; 132 } 133 } 134 135 if ((best_sppr == 0) && (best_spr == 0)) 136 return -EINVAL; 137 138 prescale = ((best_sppr & 0x6) << 5) | 139 ((best_sppr & 0x1) << 4) | best_spr; 140 } else { 141 /* 142 * the supported rates are: 4,6,8...30 143 * round up as we look for equal or less speed 144 */ 145 rate = DIV_ROUND_UP(tclk_hz, speed); 146 rate = roundup(rate, 2); 147 148 /* check if requested speed is too small */ 149 if (rate > 30) 150 return -EINVAL; 151 152 if (rate < 4) 153 rate = 4; 154 155 /* Convert the rate to SPI clock divisor value. */ 156 prescale = 0x10 + rate/2; 157 } 158 159 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 160 reg = ((reg & ~devdata->prescale_mask) | prescale); 161 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 162 163 return 0; 164 } 165 166 static void 167 orion_spi_mode_set(struct spi_device *spi) 168 { 169 u32 reg; 170 struct orion_spi *orion_spi; 171 172 orion_spi = spi_master_get_devdata(spi->master); 173 174 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 175 reg &= ~ORION_SPI_MODE_MASK; 176 if (spi->mode & SPI_CPOL) 177 reg |= ORION_SPI_MODE_CPOL; 178 if (spi->mode & SPI_CPHA) 179 reg |= ORION_SPI_MODE_CPHA; 180 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 181 } 182 183 /* 184 * called only when no transfer is active on the bus 185 */ 186 static int 187 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 188 { 189 struct orion_spi *orion_spi; 190 unsigned int speed = spi->max_speed_hz; 191 unsigned int bits_per_word = spi->bits_per_word; 192 int rc; 193 194 orion_spi = spi_master_get_devdata(spi->master); 195 196 if ((t != NULL) && t->speed_hz) 197 speed = t->speed_hz; 198 199 if ((t != NULL) && t->bits_per_word) 200 bits_per_word = t->bits_per_word; 201 202 orion_spi_mode_set(spi); 203 204 rc = orion_spi_baudrate_set(spi, speed); 205 if (rc) 206 return rc; 207 208 if (bits_per_word == 16) 209 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 210 ORION_SPI_IF_8_16_BIT_MODE); 211 else 212 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 213 ORION_SPI_IF_8_16_BIT_MODE); 214 215 return 0; 216 } 217 218 static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable) 219 { 220 if (enable) 221 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 222 else 223 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 224 } 225 226 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) 227 { 228 int i; 229 230 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { 231 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) 232 return 1; 233 234 udelay(1); 235 } 236 237 return -1; 238 } 239 240 static inline int 241 orion_spi_write_read_8bit(struct spi_device *spi, 242 const u8 **tx_buf, u8 **rx_buf) 243 { 244 void __iomem *tx_reg, *rx_reg, *int_reg; 245 struct orion_spi *orion_spi; 246 247 orion_spi = spi_master_get_devdata(spi->master); 248 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 249 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 250 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 251 252 /* clear the interrupt cause register */ 253 writel(0x0, int_reg); 254 255 if (tx_buf && *tx_buf) 256 writel(*(*tx_buf)++, tx_reg); 257 else 258 writel(0, tx_reg); 259 260 if (orion_spi_wait_till_ready(orion_spi) < 0) { 261 dev_err(&spi->dev, "TXS timed out\n"); 262 return -1; 263 } 264 265 if (rx_buf && *rx_buf) 266 *(*rx_buf)++ = readl(rx_reg); 267 268 return 1; 269 } 270 271 static inline int 272 orion_spi_write_read_16bit(struct spi_device *spi, 273 const u16 **tx_buf, u16 **rx_buf) 274 { 275 void __iomem *tx_reg, *rx_reg, *int_reg; 276 struct orion_spi *orion_spi; 277 278 orion_spi = spi_master_get_devdata(spi->master); 279 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 280 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 281 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 282 283 /* clear the interrupt cause register */ 284 writel(0x0, int_reg); 285 286 if (tx_buf && *tx_buf) 287 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); 288 else 289 writel(0, tx_reg); 290 291 if (orion_spi_wait_till_ready(orion_spi) < 0) { 292 dev_err(&spi->dev, "TXS timed out\n"); 293 return -1; 294 } 295 296 if (rx_buf && *rx_buf) 297 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); 298 299 return 1; 300 } 301 302 static unsigned int 303 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 304 { 305 unsigned int count; 306 int word_len; 307 308 word_len = spi->bits_per_word; 309 count = xfer->len; 310 311 if (word_len == 8) { 312 const u8 *tx = xfer->tx_buf; 313 u8 *rx = xfer->rx_buf; 314 315 do { 316 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) 317 goto out; 318 count--; 319 } while (count); 320 } else if (word_len == 16) { 321 const u16 *tx = xfer->tx_buf; 322 u16 *rx = xfer->rx_buf; 323 324 do { 325 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) 326 goto out; 327 count -= 2; 328 } while (count); 329 } 330 331 out: 332 return xfer->len - count; 333 } 334 335 static int orion_spi_transfer_one_message(struct spi_master *master, 336 struct spi_message *m) 337 { 338 struct orion_spi *orion_spi = spi_master_get_devdata(master); 339 struct spi_device *spi = m->spi; 340 struct spi_transfer *t = NULL; 341 int par_override = 0; 342 int status = 0; 343 int cs_active = 0; 344 345 /* Load defaults */ 346 status = orion_spi_setup_transfer(spi, NULL); 347 348 if (status < 0) 349 goto msg_done; 350 351 list_for_each_entry(t, &m->transfers, transfer_list) { 352 if (par_override || t->speed_hz || t->bits_per_word) { 353 par_override = 1; 354 status = orion_spi_setup_transfer(spi, t); 355 if (status < 0) 356 break; 357 if (!t->speed_hz && !t->bits_per_word) 358 par_override = 0; 359 } 360 361 if (!cs_active) { 362 orion_spi_set_cs(orion_spi, 1); 363 cs_active = 1; 364 } 365 366 if (t->len) 367 m->actual_length += orion_spi_write_read(spi, t); 368 369 if (t->delay_usecs) 370 udelay(t->delay_usecs); 371 372 if (t->cs_change) { 373 orion_spi_set_cs(orion_spi, 0); 374 cs_active = 0; 375 } 376 } 377 378 msg_done: 379 if (cs_active) 380 orion_spi_set_cs(orion_spi, 0); 381 382 m->status = status; 383 spi_finalize_current_message(master); 384 385 return 0; 386 } 387 388 static int orion_spi_reset(struct orion_spi *orion_spi) 389 { 390 /* Verify that the CS is deasserted */ 391 orion_spi_set_cs(orion_spi, 0); 392 393 return 0; 394 } 395 396 static const struct orion_spi_dev orion_spi_dev_data = { 397 .typ = ORION_SPI, 398 .min_divisor = 4, 399 .max_divisor = 30, 400 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, 401 }; 402 403 static const struct orion_spi_dev armada_spi_dev_data = { 404 .typ = ARMADA_SPI, 405 .min_divisor = 1, 406 .max_divisor = 1920, 407 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 408 }; 409 410 static const struct of_device_id orion_spi_of_match_table[] = { 411 { .compatible = "marvell,orion-spi", .data = &orion_spi_dev_data, }, 412 { .compatible = "marvell,armada-370-spi", .data = &armada_spi_dev_data, }, 413 {} 414 }; 415 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); 416 417 static int orion_spi_probe(struct platform_device *pdev) 418 { 419 const struct of_device_id *of_id; 420 const struct orion_spi_dev *devdata; 421 struct spi_master *master; 422 struct orion_spi *spi; 423 struct resource *r; 424 unsigned long tclk_hz; 425 int status = 0; 426 427 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); 428 if (master == NULL) { 429 dev_dbg(&pdev->dev, "master allocation failed\n"); 430 return -ENOMEM; 431 } 432 433 if (pdev->id != -1) 434 master->bus_num = pdev->id; 435 if (pdev->dev.of_node) { 436 u32 cell_index; 437 438 if (!of_property_read_u32(pdev->dev.of_node, "cell-index", 439 &cell_index)) 440 master->bus_num = cell_index; 441 } 442 443 /* we support only mode 0, and no options */ 444 master->mode_bits = SPI_CPHA | SPI_CPOL; 445 446 master->transfer_one_message = orion_spi_transfer_one_message; 447 master->num_chipselect = ORION_NUM_CHIPSELECTS; 448 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 449 master->auto_runtime_pm = true; 450 451 platform_set_drvdata(pdev, master); 452 453 spi = spi_master_get_devdata(master); 454 spi->master = master; 455 456 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); 457 devdata = (of_id) ? of_id->data : &orion_spi_dev_data; 458 spi->devdata = devdata; 459 460 spi->clk = devm_clk_get(&pdev->dev, NULL); 461 if (IS_ERR(spi->clk)) { 462 status = PTR_ERR(spi->clk); 463 goto out; 464 } 465 466 status = clk_prepare_enable(spi->clk); 467 if (status) 468 goto out; 469 470 tclk_hz = clk_get_rate(spi->clk); 471 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->min_divisor); 472 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); 473 474 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 475 spi->base = devm_ioremap_resource(&pdev->dev, r); 476 if (IS_ERR(spi->base)) { 477 status = PTR_ERR(spi->base); 478 goto out_rel_clk; 479 } 480 481 pm_runtime_set_active(&pdev->dev); 482 pm_runtime_use_autosuspend(&pdev->dev); 483 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 484 pm_runtime_enable(&pdev->dev); 485 486 status = orion_spi_reset(spi); 487 if (status < 0) 488 goto out_rel_pm; 489 490 pm_runtime_mark_last_busy(&pdev->dev); 491 pm_runtime_put_autosuspend(&pdev->dev); 492 493 master->dev.of_node = pdev->dev.of_node; 494 status = spi_register_master(master); 495 if (status < 0) 496 goto out_rel_pm; 497 498 return status; 499 500 out_rel_pm: 501 pm_runtime_disable(&pdev->dev); 502 out_rel_clk: 503 clk_disable_unprepare(spi->clk); 504 out: 505 spi_master_put(master); 506 return status; 507 } 508 509 510 static int orion_spi_remove(struct platform_device *pdev) 511 { 512 struct spi_master *master = platform_get_drvdata(pdev); 513 struct orion_spi *spi = spi_master_get_devdata(master); 514 515 pm_runtime_get_sync(&pdev->dev); 516 clk_disable_unprepare(spi->clk); 517 518 spi_unregister_master(master); 519 pm_runtime_disable(&pdev->dev); 520 521 return 0; 522 } 523 524 MODULE_ALIAS("platform:" DRIVER_NAME); 525 526 #ifdef CONFIG_PM 527 static int orion_spi_runtime_suspend(struct device *dev) 528 { 529 struct spi_master *master = dev_get_drvdata(dev); 530 struct orion_spi *spi = spi_master_get_devdata(master); 531 532 clk_disable_unprepare(spi->clk); 533 return 0; 534 } 535 536 static int orion_spi_runtime_resume(struct device *dev) 537 { 538 struct spi_master *master = dev_get_drvdata(dev); 539 struct orion_spi *spi = spi_master_get_devdata(master); 540 541 return clk_prepare_enable(spi->clk); 542 } 543 #endif 544 545 static const struct dev_pm_ops orion_spi_pm_ops = { 546 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, 547 orion_spi_runtime_resume, 548 NULL) 549 }; 550 551 static struct platform_driver orion_spi_driver = { 552 .driver = { 553 .name = DRIVER_NAME, 554 .pm = &orion_spi_pm_ops, 555 .of_match_table = of_match_ptr(orion_spi_of_match_table), 556 }, 557 .probe = orion_spi_probe, 558 .remove = orion_spi_remove, 559 }; 560 561 module_platform_driver(orion_spi_driver); 562 563 MODULE_DESCRIPTION("Orion SPI driver"); 564 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); 565 MODULE_LICENSE("GPL"); 566