xref: /openbmc/linux/drivers/spi/spi-orion.c (revision be709d48)
1 /*
2  * Marvell Orion SPI controller driver
3  *
4  * Author: Shadi Ammouri <shadi@marvell.com>
5  * Copyright (C) 2007-2008 Marvell Ltd.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/spi/spi.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/clk.h>
25 #include <linux/sizes.h>
26 #include <linux/gpio.h>
27 #include <asm/unaligned.h>
28 
29 #define DRIVER_NAME			"orion_spi"
30 
31 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
32 #define SPI_AUTOSUSPEND_TIMEOUT		200
33 
34 /* Some SoCs using this driver support up to 8 chip selects.
35  * It is up to the implementer to only use the chip selects
36  * that are available.
37  */
38 #define ORION_NUM_CHIPSELECTS		8
39 
40 #define ORION_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */
41 
42 #define ORION_SPI_IF_CTRL_REG		0x00
43 #define ORION_SPI_IF_CONFIG_REG		0x04
44 #define ORION_SPI_IF_RXLSBF		BIT(14)
45 #define ORION_SPI_IF_TXLSBF		BIT(13)
46 #define ORION_SPI_DATA_OUT_REG		0x08
47 #define ORION_SPI_DATA_IN_REG		0x0c
48 #define ORION_SPI_INT_CAUSE_REG		0x10
49 #define ORION_SPI_TIMING_PARAMS_REG	0x18
50 
51 /* Register for the "Direct Mode" */
52 #define SPI_DIRECT_WRITE_CONFIG_REG	0x20
53 
54 #define ORION_SPI_TMISO_SAMPLE_MASK	(0x3 << 6)
55 #define ORION_SPI_TMISO_SAMPLE_1	(1 << 6)
56 #define ORION_SPI_TMISO_SAMPLE_2	(2 << 6)
57 
58 #define ORION_SPI_MODE_CPOL		(1 << 11)
59 #define ORION_SPI_MODE_CPHA		(1 << 12)
60 #define ORION_SPI_IF_8_16_BIT_MODE	(1 << 5)
61 #define ORION_SPI_CLK_PRESCALE_MASK	0x1F
62 #define ARMADA_SPI_CLK_PRESCALE_MASK	0xDF
63 #define ORION_SPI_MODE_MASK		(ORION_SPI_MODE_CPOL | \
64 					 ORION_SPI_MODE_CPHA)
65 #define ORION_SPI_CS_MASK	0x1C
66 #define ORION_SPI_CS_SHIFT	2
67 #define ORION_SPI_CS(cs)	((cs << ORION_SPI_CS_SHIFT) & \
68 					ORION_SPI_CS_MASK)
69 
70 enum orion_spi_type {
71 	ORION_SPI,
72 	ARMADA_SPI,
73 };
74 
75 struct orion_spi_dev {
76 	enum orion_spi_type	typ;
77 	/*
78 	 * min_divisor and max_hz should be exclusive, the only we can
79 	 * have both is for managing the armada-370-spi case with old
80 	 * device tree
81 	 */
82 	unsigned long		max_hz;
83 	unsigned int		min_divisor;
84 	unsigned int		max_divisor;
85 	u32			prescale_mask;
86 	bool			is_errata_50mhz_ac;
87 };
88 
89 struct orion_direct_acc {
90 	void __iomem		*vaddr;
91 	u32			size;
92 };
93 
94 struct orion_child_options {
95 	struct orion_direct_acc direct_access;
96 };
97 
98 struct orion_spi {
99 	struct spi_master	*master;
100 	void __iomem		*base;
101 	struct clk              *clk;
102 	struct clk              *axi_clk;
103 	const struct orion_spi_dev *devdata;
104 	int			unused_hw_gpio;
105 
106 	struct orion_child_options	child[ORION_NUM_CHIPSELECTS];
107 };
108 
109 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
110 {
111 	return orion_spi->base + reg;
112 }
113 
114 static inline void
115 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
116 {
117 	void __iomem *reg_addr = spi_reg(orion_spi, reg);
118 	u32 val;
119 
120 	val = readl(reg_addr);
121 	val |= mask;
122 	writel(val, reg_addr);
123 }
124 
125 static inline void
126 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
127 {
128 	void __iomem *reg_addr = spi_reg(orion_spi, reg);
129 	u32 val;
130 
131 	val = readl(reg_addr);
132 	val &= ~mask;
133 	writel(val, reg_addr);
134 }
135 
136 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
137 {
138 	u32 tclk_hz;
139 	u32 rate;
140 	u32 prescale;
141 	u32 reg;
142 	struct orion_spi *orion_spi;
143 	const struct orion_spi_dev *devdata;
144 
145 	orion_spi = spi_master_get_devdata(spi->master);
146 	devdata = orion_spi->devdata;
147 
148 	tclk_hz = clk_get_rate(orion_spi->clk);
149 
150 	if (devdata->typ == ARMADA_SPI) {
151 		/*
152 		 * Given the core_clk (tclk_hz) and the target rate (speed) we
153 		 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
154 		 * [0..7]) such that
155 		 *
156 		 * 	core_clk / (SPR * 2 ** SPPR)
157 		 *
158 		 * is as big as possible but not bigger than speed.
159 		 */
160 
161 		/* best integer divider: */
162 		unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
163 		unsigned spr, sppr;
164 
165 		if (divider < 16) {
166 			/* This is the easy case, divider is less than 16 */
167 			spr = divider;
168 			sppr = 0;
169 
170 		} else {
171 			unsigned two_pow_sppr;
172 			/*
173 			 * Find the highest bit set in divider. This and the
174 			 * three next bits define SPR (apart from rounding).
175 			 * SPPR is then the number of zero bits that must be
176 			 * appended:
177 			 */
178 			sppr = fls(divider) - 4;
179 
180 			/*
181 			 * As SPR only has 4 bits, we have to round divider up
182 			 * to the next multiple of 2 ** sppr.
183 			 */
184 			two_pow_sppr = 1 << sppr;
185 			divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
186 
187 			/*
188 			 * recalculate sppr as rounding up divider might have
189 			 * increased it enough to change the position of the
190 			 * highest set bit. In this case the bit that now
191 			 * doesn't make it into SPR is 0, so there is no need to
192 			 * round again.
193 			 */
194 			sppr = fls(divider) - 4;
195 			spr = divider >> sppr;
196 
197 			/*
198 			 * Now do range checking. SPR is constructed to have a
199 			 * width of 4 bits, so this is fine for sure. So we
200 			 * still need to check for sppr to fit into 3 bits:
201 			 */
202 			if (sppr > 7)
203 				return -EINVAL;
204 		}
205 
206 		prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
207 	} else {
208 		/*
209 		 * the supported rates are: 4,6,8...30
210 		 * round up as we look for equal or less speed
211 		 */
212 		rate = DIV_ROUND_UP(tclk_hz, speed);
213 		rate = roundup(rate, 2);
214 
215 		/* check if requested speed is too small */
216 		if (rate > 30)
217 			return -EINVAL;
218 
219 		if (rate < 4)
220 			rate = 4;
221 
222 		/* Convert the rate to SPI clock divisor value.	*/
223 		prescale = 0x10 + rate/2;
224 	}
225 
226 	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
227 	reg = ((reg & ~devdata->prescale_mask) | prescale);
228 	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
229 
230 	return 0;
231 }
232 
233 static void
234 orion_spi_mode_set(struct spi_device *spi)
235 {
236 	u32 reg;
237 	struct orion_spi *orion_spi;
238 
239 	orion_spi = spi_master_get_devdata(spi->master);
240 
241 	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
242 	reg &= ~ORION_SPI_MODE_MASK;
243 	if (spi->mode & SPI_CPOL)
244 		reg |= ORION_SPI_MODE_CPOL;
245 	if (spi->mode & SPI_CPHA)
246 		reg |= ORION_SPI_MODE_CPHA;
247 	if (spi->mode & SPI_LSB_FIRST)
248 		reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
249 	else
250 		reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
251 
252 	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
253 }
254 
255 static void
256 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
257 {
258 	u32 reg;
259 	struct orion_spi *orion_spi;
260 
261 	orion_spi = spi_master_get_devdata(spi->master);
262 
263 	/*
264 	 * Erratum description: (Erratum NO. FE-9144572) The device
265 	 * SPI interface supports frequencies of up to 50 MHz.
266 	 * However, due to this erratum, when the device core clock is
267 	 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
268 	 * clock and CPOL=CPHA=1 there might occur data corruption on
269 	 * reads from the SPI device.
270 	 * Erratum Workaround:
271 	 * Work in one of the following configurations:
272 	 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
273 	 * Register".
274 	 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
275 	 * Register" before setting the interface.
276 	 */
277 	reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
278 	reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
279 
280 	if (clk_get_rate(orion_spi->clk) == 250000000 &&
281 			speed == 50000000 && spi->mode & SPI_CPOL &&
282 			spi->mode & SPI_CPHA)
283 		reg |= ORION_SPI_TMISO_SAMPLE_2;
284 	else
285 		reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
286 
287 	writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
288 }
289 
290 /*
291  * called only when no transfer is active on the bus
292  */
293 static int
294 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
295 {
296 	struct orion_spi *orion_spi;
297 	unsigned int speed = spi->max_speed_hz;
298 	unsigned int bits_per_word = spi->bits_per_word;
299 	int	rc;
300 
301 	orion_spi = spi_master_get_devdata(spi->master);
302 
303 	if ((t != NULL) && t->speed_hz)
304 		speed = t->speed_hz;
305 
306 	if ((t != NULL) && t->bits_per_word)
307 		bits_per_word = t->bits_per_word;
308 
309 	orion_spi_mode_set(spi);
310 
311 	if (orion_spi->devdata->is_errata_50mhz_ac)
312 		orion_spi_50mhz_ac_timing_erratum(spi, speed);
313 
314 	rc = orion_spi_baudrate_set(spi, speed);
315 	if (rc)
316 		return rc;
317 
318 	if (bits_per_word == 16)
319 		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
320 				  ORION_SPI_IF_8_16_BIT_MODE);
321 	else
322 		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
323 				  ORION_SPI_IF_8_16_BIT_MODE);
324 
325 	return 0;
326 }
327 
328 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
329 {
330 	struct orion_spi *orion_spi;
331 	int cs;
332 
333 	orion_spi = spi_master_get_devdata(spi->master);
334 
335 	if (gpio_is_valid(spi->cs_gpio))
336 		cs = orion_spi->unused_hw_gpio;
337 	else
338 		cs = spi->chip_select;
339 
340 	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
341 	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
342 				ORION_SPI_CS(cs));
343 
344 	/* Chip select logic is inverted from spi_set_cs */
345 	if (!enable)
346 		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
347 	else
348 		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
349 }
350 
351 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
352 {
353 	int i;
354 
355 	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
356 		if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
357 			return 1;
358 
359 		udelay(1);
360 	}
361 
362 	return -1;
363 }
364 
365 static inline int
366 orion_spi_write_read_8bit(struct spi_device *spi,
367 			  const u8 **tx_buf, u8 **rx_buf)
368 {
369 	void __iomem *tx_reg, *rx_reg, *int_reg;
370 	struct orion_spi *orion_spi;
371 
372 	orion_spi = spi_master_get_devdata(spi->master);
373 	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
374 	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
375 	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
376 
377 	/* clear the interrupt cause register */
378 	writel(0x0, int_reg);
379 
380 	if (tx_buf && *tx_buf)
381 		writel(*(*tx_buf)++, tx_reg);
382 	else
383 		writel(0, tx_reg);
384 
385 	if (orion_spi_wait_till_ready(orion_spi) < 0) {
386 		dev_err(&spi->dev, "TXS timed out\n");
387 		return -1;
388 	}
389 
390 	if (rx_buf && *rx_buf)
391 		*(*rx_buf)++ = readl(rx_reg);
392 
393 	return 1;
394 }
395 
396 static inline int
397 orion_spi_write_read_16bit(struct spi_device *spi,
398 			   const u16 **tx_buf, u16 **rx_buf)
399 {
400 	void __iomem *tx_reg, *rx_reg, *int_reg;
401 	struct orion_spi *orion_spi;
402 
403 	orion_spi = spi_master_get_devdata(spi->master);
404 	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
405 	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
406 	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
407 
408 	/* clear the interrupt cause register */
409 	writel(0x0, int_reg);
410 
411 	if (tx_buf && *tx_buf)
412 		writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
413 	else
414 		writel(0, tx_reg);
415 
416 	if (orion_spi_wait_till_ready(orion_spi) < 0) {
417 		dev_err(&spi->dev, "TXS timed out\n");
418 		return -1;
419 	}
420 
421 	if (rx_buf && *rx_buf)
422 		put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
423 
424 	return 1;
425 }
426 
427 static unsigned int
428 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
429 {
430 	unsigned int count;
431 	int word_len;
432 	struct orion_spi *orion_spi;
433 	int cs = spi->chip_select;
434 	void __iomem *vaddr;
435 
436 	word_len = spi->bits_per_word;
437 	count = xfer->len;
438 
439 	orion_spi = spi_master_get_devdata(spi->master);
440 
441 	/*
442 	 * Use SPI direct write mode if base address is available. Otherwise
443 	 * fall back to PIO mode for this transfer.
444 	 */
445 	vaddr = orion_spi->child[cs].direct_access.vaddr;
446 
447 	if (vaddr && xfer->tx_buf && word_len == 8) {
448 		unsigned int cnt = count / 4;
449 		unsigned int rem = count % 4;
450 
451 		/*
452 		 * Send the TX-data to the SPI device via the direct
453 		 * mapped address window
454 		 */
455 		iowrite32_rep(vaddr, xfer->tx_buf, cnt);
456 		if (rem) {
457 			u32 *buf = (u32 *)xfer->tx_buf;
458 
459 			iowrite8_rep(vaddr, &buf[cnt], rem);
460 		}
461 
462 		return count;
463 	}
464 
465 	if (word_len == 8) {
466 		const u8 *tx = xfer->tx_buf;
467 		u8 *rx = xfer->rx_buf;
468 
469 		do {
470 			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
471 				goto out;
472 			count--;
473 		} while (count);
474 	} else if (word_len == 16) {
475 		const u16 *tx = xfer->tx_buf;
476 		u16 *rx = xfer->rx_buf;
477 
478 		do {
479 			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
480 				goto out;
481 			count -= 2;
482 		} while (count);
483 	}
484 
485 out:
486 	return xfer->len - count;
487 }
488 
489 static int orion_spi_transfer_one(struct spi_master *master,
490 					struct spi_device *spi,
491 					struct spi_transfer *t)
492 {
493 	int status = 0;
494 
495 	status = orion_spi_setup_transfer(spi, t);
496 	if (status < 0)
497 		return status;
498 
499 	if (t->len)
500 		orion_spi_write_read(spi, t);
501 
502 	return status;
503 }
504 
505 static int orion_spi_setup(struct spi_device *spi)
506 {
507 	if (gpio_is_valid(spi->cs_gpio)) {
508 		gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
509 	}
510 	return orion_spi_setup_transfer(spi, NULL);
511 }
512 
513 static int orion_spi_reset(struct orion_spi *orion_spi)
514 {
515 	/* Verify that the CS is deasserted */
516 	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
517 
518 	/* Don't deassert CS between the direct mapped SPI transfers */
519 	writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
520 
521 	return 0;
522 }
523 
524 static const struct orion_spi_dev orion_spi_dev_data = {
525 	.typ = ORION_SPI,
526 	.min_divisor = 4,
527 	.max_divisor = 30,
528 	.prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
529 };
530 
531 static const struct orion_spi_dev armada_370_spi_dev_data = {
532 	.typ = ARMADA_SPI,
533 	.min_divisor = 4,
534 	.max_divisor = 1920,
535 	.max_hz = 50000000,
536 	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
537 };
538 
539 static const struct orion_spi_dev armada_xp_spi_dev_data = {
540 	.typ = ARMADA_SPI,
541 	.max_hz = 50000000,
542 	.max_divisor = 1920,
543 	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
544 };
545 
546 static const struct orion_spi_dev armada_375_spi_dev_data = {
547 	.typ = ARMADA_SPI,
548 	.min_divisor = 15,
549 	.max_divisor = 1920,
550 	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
551 };
552 
553 static const struct orion_spi_dev armada_380_spi_dev_data = {
554 	.typ = ARMADA_SPI,
555 	.max_hz = 50000000,
556 	.max_divisor = 1920,
557 	.prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
558 	.is_errata_50mhz_ac = true,
559 };
560 
561 static const struct of_device_id orion_spi_of_match_table[] = {
562 	{
563 		.compatible = "marvell,orion-spi",
564 		.data = &orion_spi_dev_data,
565 	},
566 	{
567 		.compatible = "marvell,armada-370-spi",
568 		.data = &armada_370_spi_dev_data,
569 	},
570 	{
571 		.compatible = "marvell,armada-375-spi",
572 		.data = &armada_375_spi_dev_data,
573 	},
574 	{
575 		.compatible = "marvell,armada-380-spi",
576 		.data = &armada_380_spi_dev_data,
577 	},
578 	{
579 		.compatible = "marvell,armada-390-spi",
580 		.data = &armada_xp_spi_dev_data,
581 	},
582 	{
583 		.compatible = "marvell,armada-xp-spi",
584 		.data = &armada_xp_spi_dev_data,
585 	},
586 
587 	{}
588 };
589 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
590 
591 static int orion_spi_probe(struct platform_device *pdev)
592 {
593 	const struct of_device_id *of_id;
594 	const struct orion_spi_dev *devdata;
595 	struct spi_master *master;
596 	struct orion_spi *spi;
597 	struct resource *r;
598 	unsigned long tclk_hz;
599 	int status = 0;
600 	struct device_node *np;
601 
602 	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
603 	if (master == NULL) {
604 		dev_dbg(&pdev->dev, "master allocation failed\n");
605 		return -ENOMEM;
606 	}
607 
608 	if (pdev->id != -1)
609 		master->bus_num = pdev->id;
610 	if (pdev->dev.of_node) {
611 		u32 cell_index;
612 
613 		if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
614 					  &cell_index))
615 			master->bus_num = cell_index;
616 	}
617 
618 	/* we support all 4 SPI modes and LSB first option */
619 	master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
620 	master->set_cs = orion_spi_set_cs;
621 	master->transfer_one = orion_spi_transfer_one;
622 	master->num_chipselect = ORION_NUM_CHIPSELECTS;
623 	master->setup = orion_spi_setup;
624 	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
625 	master->auto_runtime_pm = true;
626 	master->flags = SPI_MASTER_GPIO_SS;
627 
628 	platform_set_drvdata(pdev, master);
629 
630 	spi = spi_master_get_devdata(master);
631 	spi->master = master;
632 	spi->unused_hw_gpio = -1;
633 
634 	of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
635 	devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
636 	spi->devdata = devdata;
637 
638 	spi->clk = devm_clk_get(&pdev->dev, NULL);
639 	if (IS_ERR(spi->clk)) {
640 		status = PTR_ERR(spi->clk);
641 		goto out;
642 	}
643 
644 	status = clk_prepare_enable(spi->clk);
645 	if (status)
646 		goto out;
647 
648 	/* The following clock is only used by some SoCs */
649 	spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
650 	if (IS_ERR(spi->axi_clk) &&
651 	    PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
652 		status = -EPROBE_DEFER;
653 		goto out_rel_clk;
654 	}
655 	if (!IS_ERR(spi->axi_clk))
656 		clk_prepare_enable(spi->axi_clk);
657 
658 	tclk_hz = clk_get_rate(spi->clk);
659 
660 	/*
661 	 * With old device tree, armada-370-spi could be used with
662 	 * Armada XP, however for this SoC the maximum frequency is
663 	 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
664 	 * higher than 200MHz. So, in order to be able to handle both
665 	 * SoCs, we can take the minimum of 50MHz and tclk/4.
666 	 */
667 	if (of_device_is_compatible(pdev->dev.of_node,
668 					"marvell,armada-370-spi"))
669 		master->max_speed_hz = min(devdata->max_hz,
670 				DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
671 	else if (devdata->min_divisor)
672 		master->max_speed_hz =
673 			DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
674 	else
675 		master->max_speed_hz = devdata->max_hz;
676 	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
677 
678 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
679 	spi->base = devm_ioremap_resource(&pdev->dev, r);
680 	if (IS_ERR(spi->base)) {
681 		status = PTR_ERR(spi->base);
682 		goto out_rel_axi_clk;
683 	}
684 
685 	for_each_available_child_of_node(pdev->dev.of_node, np) {
686 		struct orion_direct_acc *dir_acc;
687 		u32 cs;
688 		int cs_gpio;
689 
690 		/* Get chip-select number from the "reg" property */
691 		status = of_property_read_u32(np, "reg", &cs);
692 		if (status) {
693 			dev_err(&pdev->dev,
694 				"%pOF has no valid 'reg' property (%d)\n",
695 				np, status);
696 			continue;
697 		}
698 
699 		/*
700 		 * Initialize the CS GPIO:
701 		 * - properly request the actual GPIO signal
702 		 * - de-assert the logical signal so that all GPIO CS lines
703 		 *   are inactive when probing for slaves
704 		 * - find an unused physical CS which will be driven for any
705 		 *   slave which uses a CS GPIO
706 		 */
707 		cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", cs);
708 		if (cs_gpio > 0) {
709 			char *gpio_name;
710 			int cs_flags;
711 
712 			if (spi->unused_hw_gpio == -1) {
713 				dev_info(&pdev->dev,
714 					"Selected unused HW CS#%d for any GPIO CSes\n",
715 					cs);
716 				spi->unused_hw_gpio = cs;
717 			}
718 
719 			gpio_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
720 					"%s-CS%d", dev_name(&pdev->dev), cs);
721 			if (!gpio_name) {
722 				status = -ENOMEM;
723 				goto out_rel_axi_clk;
724 			}
725 
726 			cs_flags = of_property_read_bool(np, "spi-cs-high") ?
727 				GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
728 			status = devm_gpio_request_one(&pdev->dev, cs_gpio,
729 					cs_flags, gpio_name);
730 			if (status) {
731 				dev_err(&pdev->dev,
732 					"Can't request GPIO for CS %d\n", cs);
733 				goto out_rel_axi_clk;
734 			}
735 		}
736 
737 		/*
738 		 * Check if an address is configured for this SPI device. If
739 		 * not, the MBus mapping via the 'ranges' property in the 'soc'
740 		 * node is not configured and this device should not use the
741 		 * direct mode. In this case, just continue with the next
742 		 * device.
743 		 */
744 		status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
745 		if (status)
746 			continue;
747 
748 		/*
749 		 * Only map one page for direct access. This is enough for the
750 		 * simple TX transfer which only writes to the first word.
751 		 * This needs to get extended for the direct SPI-NOR / SPI-NAND
752 		 * support, once this gets implemented.
753 		 */
754 		dir_acc = &spi->child[cs].direct_access;
755 		dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
756 		if (!dir_acc->vaddr) {
757 			status = -ENOMEM;
758 			goto out_rel_axi_clk;
759 		}
760 		dir_acc->size = PAGE_SIZE;
761 
762 		dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
763 	}
764 
765 	pm_runtime_set_active(&pdev->dev);
766 	pm_runtime_use_autosuspend(&pdev->dev);
767 	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
768 	pm_runtime_enable(&pdev->dev);
769 
770 	status = orion_spi_reset(spi);
771 	if (status < 0)
772 		goto out_rel_pm;
773 
774 	pm_runtime_mark_last_busy(&pdev->dev);
775 	pm_runtime_put_autosuspend(&pdev->dev);
776 
777 	master->dev.of_node = pdev->dev.of_node;
778 	status = spi_register_master(master);
779 	if (status < 0)
780 		goto out_rel_pm;
781 
782 	return status;
783 
784 out_rel_pm:
785 	pm_runtime_disable(&pdev->dev);
786 out_rel_axi_clk:
787 	clk_disable_unprepare(spi->axi_clk);
788 out_rel_clk:
789 	clk_disable_unprepare(spi->clk);
790 out:
791 	spi_master_put(master);
792 	return status;
793 }
794 
795 
796 static int orion_spi_remove(struct platform_device *pdev)
797 {
798 	struct spi_master *master = platform_get_drvdata(pdev);
799 	struct orion_spi *spi = spi_master_get_devdata(master);
800 
801 	pm_runtime_get_sync(&pdev->dev);
802 	clk_disable_unprepare(spi->axi_clk);
803 	clk_disable_unprepare(spi->clk);
804 
805 	spi_unregister_master(master);
806 	pm_runtime_disable(&pdev->dev);
807 
808 	return 0;
809 }
810 
811 MODULE_ALIAS("platform:" DRIVER_NAME);
812 
813 #ifdef CONFIG_PM
814 static int orion_spi_runtime_suspend(struct device *dev)
815 {
816 	struct spi_master *master = dev_get_drvdata(dev);
817 	struct orion_spi *spi = spi_master_get_devdata(master);
818 
819 	clk_disable_unprepare(spi->axi_clk);
820 	clk_disable_unprepare(spi->clk);
821 	return 0;
822 }
823 
824 static int orion_spi_runtime_resume(struct device *dev)
825 {
826 	struct spi_master *master = dev_get_drvdata(dev);
827 	struct orion_spi *spi = spi_master_get_devdata(master);
828 
829 	if (!IS_ERR(spi->axi_clk))
830 		clk_prepare_enable(spi->axi_clk);
831 	return clk_prepare_enable(spi->clk);
832 }
833 #endif
834 
835 static const struct dev_pm_ops orion_spi_pm_ops = {
836 	SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
837 			   orion_spi_runtime_resume,
838 			   NULL)
839 };
840 
841 static struct platform_driver orion_spi_driver = {
842 	.driver = {
843 		.name	= DRIVER_NAME,
844 		.pm	= &orion_spi_pm_ops,
845 		.of_match_table = of_match_ptr(orion_spi_of_match_table),
846 	},
847 	.probe		= orion_spi_probe,
848 	.remove		= orion_spi_remove,
849 };
850 
851 module_platform_driver(orion_spi_driver);
852 
853 MODULE_DESCRIPTION("Orion SPI driver");
854 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
855 MODULE_LICENSE("GPL");
856