1 /* 2 * Marvell Orion SPI controller driver 3 * 4 * Author: Shadi Ammouri <shadi@marvell.com> 5 * Copyright (C) 2007-2008 Marvell Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/spi/spi.h> 18 #include <linux/module.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/clk.h> 25 #include <linux/sizes.h> 26 #include <linux/gpio.h> 27 #include <asm/unaligned.h> 28 29 #define DRIVER_NAME "orion_spi" 30 31 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */ 32 #define SPI_AUTOSUSPEND_TIMEOUT 200 33 34 /* Some SoCs using this driver support up to 8 chip selects. 35 * It is up to the implementer to only use the chip selects 36 * that are available. 37 */ 38 #define ORION_NUM_CHIPSELECTS 8 39 40 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ 41 42 #define ORION_SPI_IF_CTRL_REG 0x00 43 #define ORION_SPI_IF_CONFIG_REG 0x04 44 #define ORION_SPI_IF_RXLSBF BIT(14) 45 #define ORION_SPI_IF_TXLSBF BIT(13) 46 #define ORION_SPI_DATA_OUT_REG 0x08 47 #define ORION_SPI_DATA_IN_REG 0x0c 48 #define ORION_SPI_INT_CAUSE_REG 0x10 49 #define ORION_SPI_TIMING_PARAMS_REG 0x18 50 51 /* Register for the "Direct Mode" */ 52 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20 53 54 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6) 55 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6) 56 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6) 57 58 #define ORION_SPI_MODE_CPOL (1 << 11) 59 #define ORION_SPI_MODE_CPHA (1 << 12) 60 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) 61 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F 62 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF 63 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ 64 ORION_SPI_MODE_CPHA) 65 #define ORION_SPI_CS_MASK 0x1C 66 #define ORION_SPI_CS_SHIFT 2 67 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ 68 ORION_SPI_CS_MASK) 69 70 enum orion_spi_type { 71 ORION_SPI, 72 ARMADA_SPI, 73 }; 74 75 struct orion_spi_dev { 76 enum orion_spi_type typ; 77 /* 78 * min_divisor and max_hz should be exclusive, the only we can 79 * have both is for managing the armada-370-spi case with old 80 * device tree 81 */ 82 unsigned long max_hz; 83 unsigned int min_divisor; 84 unsigned int max_divisor; 85 u32 prescale_mask; 86 bool is_errata_50mhz_ac; 87 }; 88 89 struct orion_direct_acc { 90 void __iomem *vaddr; 91 u32 size; 92 }; 93 94 struct orion_child_options { 95 struct orion_direct_acc direct_access; 96 }; 97 98 struct orion_spi { 99 struct spi_master *master; 100 void __iomem *base; 101 struct clk *clk; 102 struct clk *axi_clk; 103 const struct orion_spi_dev *devdata; 104 int unused_hw_gpio; 105 106 struct orion_child_options child[ORION_NUM_CHIPSELECTS]; 107 }; 108 109 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) 110 { 111 return orion_spi->base + reg; 112 } 113 114 static inline void 115 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 116 { 117 void __iomem *reg_addr = spi_reg(orion_spi, reg); 118 u32 val; 119 120 val = readl(reg_addr); 121 val |= mask; 122 writel(val, reg_addr); 123 } 124 125 static inline void 126 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 127 { 128 void __iomem *reg_addr = spi_reg(orion_spi, reg); 129 u32 val; 130 131 val = readl(reg_addr); 132 val &= ~mask; 133 writel(val, reg_addr); 134 } 135 136 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 137 { 138 u32 tclk_hz; 139 u32 rate; 140 u32 prescale; 141 u32 reg; 142 struct orion_spi *orion_spi; 143 const struct orion_spi_dev *devdata; 144 145 orion_spi = spi_master_get_devdata(spi->master); 146 devdata = orion_spi->devdata; 147 148 tclk_hz = clk_get_rate(orion_spi->clk); 149 150 if (devdata->typ == ARMADA_SPI) { 151 /* 152 * Given the core_clk (tclk_hz) and the target rate (speed) we 153 * determine the best values for SPR (in [0 .. 15]) and SPPR (in 154 * [0..7]) such that 155 * 156 * core_clk / (SPR * 2 ** SPPR) 157 * 158 * is as big as possible but not bigger than speed. 159 */ 160 161 /* best integer divider: */ 162 unsigned divider = DIV_ROUND_UP(tclk_hz, speed); 163 unsigned spr, sppr; 164 165 if (divider < 16) { 166 /* This is the easy case, divider is less than 16 */ 167 spr = divider; 168 sppr = 0; 169 170 } else { 171 unsigned two_pow_sppr; 172 /* 173 * Find the highest bit set in divider. This and the 174 * three next bits define SPR (apart from rounding). 175 * SPPR is then the number of zero bits that must be 176 * appended: 177 */ 178 sppr = fls(divider) - 4; 179 180 /* 181 * As SPR only has 4 bits, we have to round divider up 182 * to the next multiple of 2 ** sppr. 183 */ 184 two_pow_sppr = 1 << sppr; 185 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; 186 187 /* 188 * recalculate sppr as rounding up divider might have 189 * increased it enough to change the position of the 190 * highest set bit. In this case the bit that now 191 * doesn't make it into SPR is 0, so there is no need to 192 * round again. 193 */ 194 sppr = fls(divider) - 4; 195 spr = divider >> sppr; 196 197 /* 198 * Now do range checking. SPR is constructed to have a 199 * width of 4 bits, so this is fine for sure. So we 200 * still need to check for sppr to fit into 3 bits: 201 */ 202 if (sppr > 7) 203 return -EINVAL; 204 } 205 206 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; 207 } else { 208 /* 209 * the supported rates are: 4,6,8...30 210 * round up as we look for equal or less speed 211 */ 212 rate = DIV_ROUND_UP(tclk_hz, speed); 213 rate = roundup(rate, 2); 214 215 /* check if requested speed is too small */ 216 if (rate > 30) 217 return -EINVAL; 218 219 if (rate < 4) 220 rate = 4; 221 222 /* Convert the rate to SPI clock divisor value. */ 223 prescale = 0x10 + rate/2; 224 } 225 226 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 227 reg = ((reg & ~devdata->prescale_mask) | prescale); 228 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 229 230 return 0; 231 } 232 233 static void 234 orion_spi_mode_set(struct spi_device *spi) 235 { 236 u32 reg; 237 struct orion_spi *orion_spi; 238 239 orion_spi = spi_master_get_devdata(spi->master); 240 241 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 242 reg &= ~ORION_SPI_MODE_MASK; 243 if (spi->mode & SPI_CPOL) 244 reg |= ORION_SPI_MODE_CPOL; 245 if (spi->mode & SPI_CPHA) 246 reg |= ORION_SPI_MODE_CPHA; 247 if (spi->mode & SPI_LSB_FIRST) 248 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF; 249 else 250 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF); 251 252 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 253 } 254 255 static void 256 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed) 257 { 258 u32 reg; 259 struct orion_spi *orion_spi; 260 261 orion_spi = spi_master_get_devdata(spi->master); 262 263 /* 264 * Erratum description: (Erratum NO. FE-9144572) The device 265 * SPI interface supports frequencies of up to 50 MHz. 266 * However, due to this erratum, when the device core clock is 267 * 250 MHz and the SPI interfaces is configured for 50MHz SPI 268 * clock and CPOL=CPHA=1 there might occur data corruption on 269 * reads from the SPI device. 270 * Erratum Workaround: 271 * Work in one of the following configurations: 272 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration 273 * Register". 274 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1 275 * Register" before setting the interface. 276 */ 277 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 278 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK; 279 280 if (clk_get_rate(orion_spi->clk) == 250000000 && 281 speed == 50000000 && spi->mode & SPI_CPOL && 282 spi->mode & SPI_CPHA) 283 reg |= ORION_SPI_TMISO_SAMPLE_2; 284 else 285 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */ 286 287 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 288 } 289 290 /* 291 * called only when no transfer is active on the bus 292 */ 293 static int 294 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 295 { 296 struct orion_spi *orion_spi; 297 unsigned int speed = spi->max_speed_hz; 298 unsigned int bits_per_word = spi->bits_per_word; 299 int rc; 300 301 orion_spi = spi_master_get_devdata(spi->master); 302 303 if ((t != NULL) && t->speed_hz) 304 speed = t->speed_hz; 305 306 if ((t != NULL) && t->bits_per_word) 307 bits_per_word = t->bits_per_word; 308 309 orion_spi_mode_set(spi); 310 311 if (orion_spi->devdata->is_errata_50mhz_ac) 312 orion_spi_50mhz_ac_timing_erratum(spi, speed); 313 314 rc = orion_spi_baudrate_set(spi, speed); 315 if (rc) 316 return rc; 317 318 if (bits_per_word == 16) 319 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 320 ORION_SPI_IF_8_16_BIT_MODE); 321 else 322 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 323 ORION_SPI_IF_8_16_BIT_MODE); 324 325 return 0; 326 } 327 328 static void orion_spi_set_cs(struct spi_device *spi, bool enable) 329 { 330 struct orion_spi *orion_spi; 331 int cs; 332 333 orion_spi = spi_master_get_devdata(spi->master); 334 335 if (gpio_is_valid(spi->cs_gpio)) 336 cs = orion_spi->unused_hw_gpio; 337 else 338 cs = spi->chip_select; 339 340 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); 341 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 342 ORION_SPI_CS(cs)); 343 344 /* Chip select logic is inverted from spi_set_cs */ 345 if (!enable) 346 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 347 else 348 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 349 } 350 351 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) 352 { 353 int i; 354 355 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { 356 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) 357 return 1; 358 359 udelay(1); 360 } 361 362 return -1; 363 } 364 365 static inline int 366 orion_spi_write_read_8bit(struct spi_device *spi, 367 const u8 **tx_buf, u8 **rx_buf) 368 { 369 void __iomem *tx_reg, *rx_reg, *int_reg; 370 struct orion_spi *orion_spi; 371 372 orion_spi = spi_master_get_devdata(spi->master); 373 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 374 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 375 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 376 377 /* clear the interrupt cause register */ 378 writel(0x0, int_reg); 379 380 if (tx_buf && *tx_buf) 381 writel(*(*tx_buf)++, tx_reg); 382 else 383 writel(0, tx_reg); 384 385 if (orion_spi_wait_till_ready(orion_spi) < 0) { 386 dev_err(&spi->dev, "TXS timed out\n"); 387 return -1; 388 } 389 390 if (rx_buf && *rx_buf) 391 *(*rx_buf)++ = readl(rx_reg); 392 393 return 1; 394 } 395 396 static inline int 397 orion_spi_write_read_16bit(struct spi_device *spi, 398 const u16 **tx_buf, u16 **rx_buf) 399 { 400 void __iomem *tx_reg, *rx_reg, *int_reg; 401 struct orion_spi *orion_spi; 402 403 orion_spi = spi_master_get_devdata(spi->master); 404 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 405 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 406 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 407 408 /* clear the interrupt cause register */ 409 writel(0x0, int_reg); 410 411 if (tx_buf && *tx_buf) 412 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); 413 else 414 writel(0, tx_reg); 415 416 if (orion_spi_wait_till_ready(orion_spi) < 0) { 417 dev_err(&spi->dev, "TXS timed out\n"); 418 return -1; 419 } 420 421 if (rx_buf && *rx_buf) 422 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); 423 424 return 1; 425 } 426 427 static unsigned int 428 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 429 { 430 unsigned int count; 431 int word_len; 432 struct orion_spi *orion_spi; 433 int cs = spi->chip_select; 434 void __iomem *vaddr; 435 436 word_len = spi->bits_per_word; 437 count = xfer->len; 438 439 orion_spi = spi_master_get_devdata(spi->master); 440 441 /* 442 * Use SPI direct write mode if base address is available. Otherwise 443 * fall back to PIO mode for this transfer. 444 */ 445 vaddr = orion_spi->child[cs].direct_access.vaddr; 446 447 if (vaddr && xfer->tx_buf && word_len == 8) { 448 unsigned int cnt = count / 4; 449 unsigned int rem = count % 4; 450 451 /* 452 * Send the TX-data to the SPI device via the direct 453 * mapped address window 454 */ 455 iowrite32_rep(vaddr, xfer->tx_buf, cnt); 456 if (rem) { 457 u32 *buf = (u32 *)xfer->tx_buf; 458 459 iowrite8_rep(vaddr, &buf[cnt], rem); 460 } 461 462 return count; 463 } 464 465 if (word_len == 8) { 466 const u8 *tx = xfer->tx_buf; 467 u8 *rx = xfer->rx_buf; 468 469 do { 470 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) 471 goto out; 472 count--; 473 if (xfer->word_delay_usecs) 474 udelay(xfer->word_delay_usecs); 475 } while (count); 476 } else if (word_len == 16) { 477 const u16 *tx = xfer->tx_buf; 478 u16 *rx = xfer->rx_buf; 479 480 do { 481 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) 482 goto out; 483 count -= 2; 484 if (xfer->word_delay_usecs) 485 udelay(xfer->word_delay_usecs); 486 } while (count); 487 } 488 489 out: 490 return xfer->len - count; 491 } 492 493 static int orion_spi_transfer_one(struct spi_master *master, 494 struct spi_device *spi, 495 struct spi_transfer *t) 496 { 497 int status = 0; 498 499 status = orion_spi_setup_transfer(spi, t); 500 if (status < 0) 501 return status; 502 503 if (t->len) 504 orion_spi_write_read(spi, t); 505 506 return status; 507 } 508 509 static int orion_spi_setup(struct spi_device *spi) 510 { 511 if (gpio_is_valid(spi->cs_gpio)) { 512 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 513 } 514 return orion_spi_setup_transfer(spi, NULL); 515 } 516 517 static int orion_spi_reset(struct orion_spi *orion_spi) 518 { 519 /* Verify that the CS is deasserted */ 520 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 521 522 /* Don't deassert CS between the direct mapped SPI transfers */ 523 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG)); 524 525 return 0; 526 } 527 528 static const struct orion_spi_dev orion_spi_dev_data = { 529 .typ = ORION_SPI, 530 .min_divisor = 4, 531 .max_divisor = 30, 532 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, 533 }; 534 535 static const struct orion_spi_dev armada_370_spi_dev_data = { 536 .typ = ARMADA_SPI, 537 .min_divisor = 4, 538 .max_divisor = 1920, 539 .max_hz = 50000000, 540 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 541 }; 542 543 static const struct orion_spi_dev armada_xp_spi_dev_data = { 544 .typ = ARMADA_SPI, 545 .max_hz = 50000000, 546 .max_divisor = 1920, 547 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 548 }; 549 550 static const struct orion_spi_dev armada_375_spi_dev_data = { 551 .typ = ARMADA_SPI, 552 .min_divisor = 15, 553 .max_divisor = 1920, 554 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 555 }; 556 557 static const struct orion_spi_dev armada_380_spi_dev_data = { 558 .typ = ARMADA_SPI, 559 .max_hz = 50000000, 560 .max_divisor = 1920, 561 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 562 .is_errata_50mhz_ac = true, 563 }; 564 565 static const struct of_device_id orion_spi_of_match_table[] = { 566 { 567 .compatible = "marvell,orion-spi", 568 .data = &orion_spi_dev_data, 569 }, 570 { 571 .compatible = "marvell,armada-370-spi", 572 .data = &armada_370_spi_dev_data, 573 }, 574 { 575 .compatible = "marvell,armada-375-spi", 576 .data = &armada_375_spi_dev_data, 577 }, 578 { 579 .compatible = "marvell,armada-380-spi", 580 .data = &armada_380_spi_dev_data, 581 }, 582 { 583 .compatible = "marvell,armada-390-spi", 584 .data = &armada_xp_spi_dev_data, 585 }, 586 { 587 .compatible = "marvell,armada-xp-spi", 588 .data = &armada_xp_spi_dev_data, 589 }, 590 591 {} 592 }; 593 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); 594 595 static int orion_spi_probe(struct platform_device *pdev) 596 { 597 const struct of_device_id *of_id; 598 const struct orion_spi_dev *devdata; 599 struct spi_master *master; 600 struct orion_spi *spi; 601 struct resource *r; 602 unsigned long tclk_hz; 603 int status = 0; 604 struct device_node *np; 605 606 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); 607 if (master == NULL) { 608 dev_dbg(&pdev->dev, "master allocation failed\n"); 609 return -ENOMEM; 610 } 611 612 if (pdev->id != -1) 613 master->bus_num = pdev->id; 614 if (pdev->dev.of_node) { 615 u32 cell_index; 616 617 if (!of_property_read_u32(pdev->dev.of_node, "cell-index", 618 &cell_index)) 619 master->bus_num = cell_index; 620 } 621 622 /* we support all 4 SPI modes and LSB first option */ 623 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; 624 master->set_cs = orion_spi_set_cs; 625 master->transfer_one = orion_spi_transfer_one; 626 master->num_chipselect = ORION_NUM_CHIPSELECTS; 627 master->setup = orion_spi_setup; 628 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 629 master->auto_runtime_pm = true; 630 master->flags = SPI_MASTER_GPIO_SS; 631 632 platform_set_drvdata(pdev, master); 633 634 spi = spi_master_get_devdata(master); 635 spi->master = master; 636 spi->unused_hw_gpio = -1; 637 638 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); 639 devdata = (of_id) ? of_id->data : &orion_spi_dev_data; 640 spi->devdata = devdata; 641 642 spi->clk = devm_clk_get(&pdev->dev, NULL); 643 if (IS_ERR(spi->clk)) { 644 status = PTR_ERR(spi->clk); 645 goto out; 646 } 647 648 status = clk_prepare_enable(spi->clk); 649 if (status) 650 goto out; 651 652 /* The following clock is only used by some SoCs */ 653 spi->axi_clk = devm_clk_get(&pdev->dev, "axi"); 654 if (IS_ERR(spi->axi_clk) && 655 PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) { 656 status = -EPROBE_DEFER; 657 goto out_rel_clk; 658 } 659 if (!IS_ERR(spi->axi_clk)) 660 clk_prepare_enable(spi->axi_clk); 661 662 tclk_hz = clk_get_rate(spi->clk); 663 664 /* 665 * With old device tree, armada-370-spi could be used with 666 * Armada XP, however for this SoC the maximum frequency is 667 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be 668 * higher than 200MHz. So, in order to be able to handle both 669 * SoCs, we can take the minimum of 50MHz and tclk/4. 670 */ 671 if (of_device_is_compatible(pdev->dev.of_node, 672 "marvell,armada-370-spi")) 673 master->max_speed_hz = min(devdata->max_hz, 674 DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); 675 else if (devdata->min_divisor) 676 master->max_speed_hz = 677 DIV_ROUND_UP(tclk_hz, devdata->min_divisor); 678 else 679 master->max_speed_hz = devdata->max_hz; 680 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); 681 682 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 683 spi->base = devm_ioremap_resource(&pdev->dev, r); 684 if (IS_ERR(spi->base)) { 685 status = PTR_ERR(spi->base); 686 goto out_rel_axi_clk; 687 } 688 689 for_each_available_child_of_node(pdev->dev.of_node, np) { 690 struct orion_direct_acc *dir_acc; 691 u32 cs; 692 int cs_gpio; 693 694 /* Get chip-select number from the "reg" property */ 695 status = of_property_read_u32(np, "reg", &cs); 696 if (status) { 697 dev_err(&pdev->dev, 698 "%pOF has no valid 'reg' property (%d)\n", 699 np, status); 700 continue; 701 } 702 703 /* 704 * Initialize the CS GPIO: 705 * - properly request the actual GPIO signal 706 * - de-assert the logical signal so that all GPIO CS lines 707 * are inactive when probing for slaves 708 * - find an unused physical CS which will be driven for any 709 * slave which uses a CS GPIO 710 */ 711 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", cs); 712 if (cs_gpio > 0) { 713 char *gpio_name; 714 int cs_flags; 715 716 if (spi->unused_hw_gpio == -1) { 717 dev_info(&pdev->dev, 718 "Selected unused HW CS#%d for any GPIO CSes\n", 719 cs); 720 spi->unused_hw_gpio = cs; 721 } 722 723 gpio_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, 724 "%s-CS%d", dev_name(&pdev->dev), cs); 725 if (!gpio_name) { 726 status = -ENOMEM; 727 goto out_rel_axi_clk; 728 } 729 730 cs_flags = of_property_read_bool(np, "spi-cs-high") ? 731 GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH; 732 status = devm_gpio_request_one(&pdev->dev, cs_gpio, 733 cs_flags, gpio_name); 734 if (status) { 735 dev_err(&pdev->dev, 736 "Can't request GPIO for CS %d\n", cs); 737 goto out_rel_axi_clk; 738 } 739 } 740 741 /* 742 * Check if an address is configured for this SPI device. If 743 * not, the MBus mapping via the 'ranges' property in the 'soc' 744 * node is not configured and this device should not use the 745 * direct mode. In this case, just continue with the next 746 * device. 747 */ 748 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r); 749 if (status) 750 continue; 751 752 /* 753 * Only map one page for direct access. This is enough for the 754 * simple TX transfer which only writes to the first word. 755 * This needs to get extended for the direct SPI-NOR / SPI-NAND 756 * support, once this gets implemented. 757 */ 758 dir_acc = &spi->child[cs].direct_access; 759 dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE); 760 if (!dir_acc->vaddr) { 761 status = -ENOMEM; 762 goto out_rel_axi_clk; 763 } 764 dir_acc->size = PAGE_SIZE; 765 766 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs); 767 } 768 769 pm_runtime_set_active(&pdev->dev); 770 pm_runtime_use_autosuspend(&pdev->dev); 771 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 772 pm_runtime_enable(&pdev->dev); 773 774 status = orion_spi_reset(spi); 775 if (status < 0) 776 goto out_rel_pm; 777 778 pm_runtime_mark_last_busy(&pdev->dev); 779 pm_runtime_put_autosuspend(&pdev->dev); 780 781 master->dev.of_node = pdev->dev.of_node; 782 status = spi_register_master(master); 783 if (status < 0) 784 goto out_rel_pm; 785 786 return status; 787 788 out_rel_pm: 789 pm_runtime_disable(&pdev->dev); 790 out_rel_axi_clk: 791 clk_disable_unprepare(spi->axi_clk); 792 out_rel_clk: 793 clk_disable_unprepare(spi->clk); 794 out: 795 spi_master_put(master); 796 return status; 797 } 798 799 800 static int orion_spi_remove(struct platform_device *pdev) 801 { 802 struct spi_master *master = platform_get_drvdata(pdev); 803 struct orion_spi *spi = spi_master_get_devdata(master); 804 805 pm_runtime_get_sync(&pdev->dev); 806 clk_disable_unprepare(spi->axi_clk); 807 clk_disable_unprepare(spi->clk); 808 809 spi_unregister_master(master); 810 pm_runtime_disable(&pdev->dev); 811 812 return 0; 813 } 814 815 MODULE_ALIAS("platform:" DRIVER_NAME); 816 817 #ifdef CONFIG_PM 818 static int orion_spi_runtime_suspend(struct device *dev) 819 { 820 struct spi_master *master = dev_get_drvdata(dev); 821 struct orion_spi *spi = spi_master_get_devdata(master); 822 823 clk_disable_unprepare(spi->axi_clk); 824 clk_disable_unprepare(spi->clk); 825 return 0; 826 } 827 828 static int orion_spi_runtime_resume(struct device *dev) 829 { 830 struct spi_master *master = dev_get_drvdata(dev); 831 struct orion_spi *spi = spi_master_get_devdata(master); 832 833 if (!IS_ERR(spi->axi_clk)) 834 clk_prepare_enable(spi->axi_clk); 835 return clk_prepare_enable(spi->clk); 836 } 837 #endif 838 839 static const struct dev_pm_ops orion_spi_pm_ops = { 840 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, 841 orion_spi_runtime_resume, 842 NULL) 843 }; 844 845 static struct platform_driver orion_spi_driver = { 846 .driver = { 847 .name = DRIVER_NAME, 848 .pm = &orion_spi_pm_ops, 849 .of_match_table = of_match_ptr(orion_spi_of_match_table), 850 }, 851 .probe = orion_spi_probe, 852 .remove = orion_spi_remove, 853 }; 854 855 module_platform_driver(orion_spi_driver); 856 857 MODULE_DESCRIPTION("Orion SPI driver"); 858 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); 859 MODULE_LICENSE("GPL"); 860